A service score counter circuit

Abstract

The utility model relates to service examination technical field, proposes a kind of service scoring counter circuit, including trigger circuit, latching circuit, encoding decoding circuit and counting display circuit connected in turn, latching circuit includes multiple groups of latching branch, the connection mode of each group of latching branch is same, wherein one latching branch includes or gate U1 and latch U5, the setting end of latch U5 receives the first count signal of the scoring grade corresponding that trigger circuit outputs, the output end of latch U5 exports the second count signal of the scoring grade corresponding, the input end of or gate U1 receives the second count signal of other scoring grade corresponding, and the output end is connected the reset end of latch U5. Through the above technical scheme, the uniqueness latching and anti-collision of signal are realized by pure hardware circuit, fundamentally eliminate the repeated counting and data error caused by key dithering or simultaneous error touch, significantly improve the reliability, accuracy and anti-interference ability of scoring operation.

Description

Technical Field

[0001] This utility model relates to the field of service assessment technology, specifically to a service scoring counter circuit. Background Technology

[0002] Currently, the service industry mostly uses software-based evaluation systems (such as QR code evaluation or touch screens). These systems suffer from cumbersome operation steps, low customer participation, high equipment costs, and are prone to slow response or failure due to software crashes. Although some hardware counters are used, their simple circuit structure often lacks effective interlocking and signal holding mechanisms, leading to signal jitter or false triggering when the button is activated, resulting in inaccurate counting results and poor reliability. Utility Model Content

[0003] This invention proposes a service scoring counter circuit, which solves the problem of unreliability in existing service scoring systems.

[0004] The technical solution of this utility model is as follows: A service scoring counter circuit includes a trigger circuit, a latch circuit, an encoding / decoding circuit, and a counting display circuit connected in sequence. The latch circuit includes multiple latch branches of the same number as the scoring levels. Each latch branch is connected in the same way. One latch branch includes an OR gate U1 and a latch U5. The setting terminal of the latch U5 receives a first counting signal corresponding to the scoring level output by the trigger circuit. The output terminal of the latch U5 outputs a second counting signal corresponding to the scoring level. The input terminal of the OR gate U1 receives the second counting signal corresponding to other scoring levels. The output terminal of the OR gate U1 is connected to the reset terminal of the latch U5.

[0005] Furthermore, the scoring levels include four levels.

[0006] Furthermore, the trigger circuit includes multiple sets of trigger branches, the same number as the scoring level. Each set of trigger branches has the same connection method. One of the trigger branches includes a switch button K1, a resistor R1, and a capacitor C1. The first end of the switch button K1 is connected to a 3.3V power supply, and the second end is grounded through the resistor R1. The far-ground end of the resistor R1 outputs the first counting signal corresponding to the scoring level. The far-ground end of the resistor R1 is also grounded through the capacitor C1.

[0007] Furthermore, the encoding and decoding circuit includes an encoder U9, a decoder U11, and an OR gate U10. The input of the OR gate U10 receives the second counting signals corresponding to all scoring levels, and the output of the OR gate U10 outputs a counting enable signal Y1. The input of the encoder U9 sequentially receives all the second counting signals from low to high scoring levels. The output of the encoder U9 is sequentially connected to the input of the decoder U11, and the output of the decoder U1 sequentially outputs all the third counting signals from low to high scoring levels.

[0008] Furthermore, the counting display circuit includes multiple sets of counting display branches, the same number as the scoring levels. Each set of counting display branches is connected in the same way. One of the counting display branches includes an AND gate U19, a counter U12, and a display tube DS1. The first input terminal of the AND gate U19 receives a counting enable signal Y1, the second input terminal receives a third counting signal corresponding to the scoring level, and the output terminal is connected to the clock input terminal of the counter U12. The output terminal of the counter U12 is connected to the input terminal of the display tube DS1.

[0009] The working principle and beneficial effects of this utility model are as follows: In this invention, the circuit implements the scoring function through an interlocked latch structure. When the trigger signal of any level is valid, its corresponding latch branch is set and outputs a valid signal. Simultaneously, this signal forces the remaining latches to reset through an OR gate in other branches, ensuring that only one scoring level is validly latched at any given time. After subsequent encoding and decoding, this interlocked signal drives the counting and display circuit to accurately count the corresponding level. The unique latching and anti-collision of the signal are achieved through a purely hardware circuit, fundamentally eliminating duplicate counting and data errors caused by key bounce or simultaneous accidental touches, significantly improving the reliability, accuracy, and anti-interference capability of the scoring operation.

[0010] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0011] Figure 1 This is a circuit diagram of the latching circuit in this utility model; Figure 2 This is a circuit diagram of the trigger circuit in this utility model; Figure 3 This is a circuit diagram of the encoding and decoding circuit in this utility model; Figure 4 This is a circuit diagram of the counting display circuit in this utility model. Detailed Implementation

[0012] The technical solutions of this utility model will be clearly and completely described below with reference to the embodiments of this utility model. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this utility model. Example

[0013] This embodiment proposes a service scoring counter circuit, which includes a trigger circuit, a latch circuit, an encoding / decoding circuit, and a counting display circuit connected in sequence.

[0014] In one specific implementation plan, the scoring system proposed in this embodiment includes four levels, representing unsatisfactory, average, satisfactory, and very satisfactory, respectively.

[0015] like Figure 1 As shown, the latching circuit includes multiple latching branches with the same number as the scoring levels. The first latching branch includes an OR gate U1 and a latch U5. The setting terminal of latch U5 receives the first counting signal A1 corresponding to the scoring level output by the trigger circuit, and the output terminal of latch U5 outputs the second counting signal B1 corresponding to the scoring level. The input terminal of OR gate U1 receives the second counting signals corresponding to other scoring levels, and the output terminal of OR gate U1 is connected to the reset terminal of latch U5. The second latching branch includes an OR gate U2 and a latch U6. The setting terminal of latch U6 receives the first counting signal A2 corresponding to the scoring level output by the trigger circuit, and the output terminal of latch U6 outputs the second counting signal B2 corresponding to the scoring level. The input terminal of OR gate U2 receives the second counting signals corresponding to other scoring levels, and the output terminal of OR gate U2 is connected to the reset terminal of latch U5. The first latch branch includes an OR gate U3 and a latch U7. The setting terminal of latch U7 receives the first counting signal A3 corresponding to the scoring level output by the trigger circuit, and the output terminal of latch U7 outputs the second counting signal B3 corresponding to the scoring level. The input terminal of OR gate U3 receives the second counting signal corresponding to other scoring levels, and the output terminal of OR gate U3 is connected to the reset terminal of latch U7. The second latch branch includes an OR gate U4 and a latch U8. The setting terminal of latch U8 receives the first counting signal A4 corresponding to the scoring level output by the trigger circuit, and the output terminal of latch U8 outputs the second counting signal B4 corresponding to the scoring level. The input terminal of OR gate U4 receives the second counting signal corresponding to other scoring levels, and the output terminal of OR gate U4 is connected to the reset terminal of latch U8.

[0016] In this embodiment, the circuit implements the service scoring function through an interlocked latch structure. When the trigger signal of any level is valid, its corresponding latch branch is set and outputs a valid signal. Simultaneously, this signal forces the remaining latches to reset through an OR gate in other branches, ensuring that only one scoring level is validly latched at any given time. After subsequent encoding and decoding, this interlocked signal drives the counting and display circuit to accurately count the corresponding level. The unique latching and anti-collision of the signal are achieved through pure hardware circuitry, fundamentally eliminating duplicate counting and data errors caused by key bounce or simultaneous accidental touches, significantly improving the reliability, accuracy, and anti-interference capability of the scoring operation.

[0017] Furthermore, such as Figure 2 As shown.

[0018] The trigger circuit includes multiple trigger branches, the same number as the scoring levels. The first trigger branch includes a switch button K1, a resistor R1, and a capacitor C1. The first terminal of switch button K1 is connected to a 3.3V power supply, and the second terminal is grounded through resistor R1. The far-ground terminal of resistor R1 outputs the first counting signal A1 corresponding to the scoring level. The far-ground terminal of resistor R1 is also grounded through capacitor C1. The second trigger branch includes a switch button K2, a resistor R2, and a capacitor C2. The first terminal of switch button K2 is connected to a 3.3V power supply, and the second terminal is grounded through resistor R2. The far-ground terminal of resistor R2 outputs the first counting signal A2 corresponding to the scoring level. The far-ground terminal of resistor R2 is also grounded through capacitor C1. The ground terminal is also grounded through capacitor C2; the third trigger branch includes switch button K3, resistor R3 and capacitor C3. The first end of switch button K3 is connected to a 3.3V power supply, and the second end is grounded through resistor R3. The far end of resistor R3 outputs the first counting signal A3 corresponding to the scoring level. The far end of resistor R3 is also grounded through capacitor C3; the fourth trigger branch includes switch button K4, resistor R4 and capacitor C4. The first end of switch button K4 is connected to a 3.3V power supply, and the second end is grounded through resistor R4. The far end of resistor R4 outputs the first counting signal A4 corresponding to the scoring level. The far end of resistor R4 is also grounded through capacitor C4.

[0019] In this embodiment, the trigger circuit provides independent pull-down resistors (R1-R4) and capacitors (C1-C4) for each scoring level, forming an RC debouncing network. When the buttons (K1-K4) are not pressed, a stable low level is output; when pressed, a clean high-level pulse is generated as the first counting signal (A1-A4). This signal is sent to the subsequent interlocked latch circuit: after any latch branch is set, its output second counting signal (B1-B4) will force the remaining latches to reset through the OR gate (U1-U4) of other branches, thereby ensuring that only one scoring signal is effectively latched at any given time. This interlocked signal, after being encoded and decoded, drives the counting display circuit to perform accurate accumulation. Through the trigger design of pull-down resistors and RC debouncing, combined with the pure hardware interlocked latch structure, not only are false triggers caused by mechanical button bounce effectively eliminated, but signal conflicts and counting errors caused by multiple buttons being pressed simultaneously are also logically prevented, giving the entire system extremely high reliability, anti-interference capability, and operational determinism.

[0020] Furthermore, such as Figure 3 As shown.

[0021] The encoding and decoding circuit includes an encoder U9, a decoder U11, and an OR gate U10. The input of the OR gate U10 receives the second count signal corresponding to all scoring levels, and the output of the OR gate U10 outputs the count enable signal Y1. The input of the encoder U9 receives all the second count signals of scoring levels from low to high in sequence. The output of the encoder U9 is connected to the input of the decoder U11 in sequence. The output of the decoder U11 outputs all the third count signals of scoring levels from low to high in sequence.

[0022] In this embodiment, the encoder-decoder circuit summarizes and distributes the second counting signals (B1-B4), the OR gate U10 generates a unified counting enable signal Y1, and the encoder U9 and decoder U11 work together to compile and route the unique latch signal to the corresponding output channel (the third counting signal D1-D4).

[0023] Furthermore, such as Figure 4 As shown.

[0024] The counting display circuit includes multiple counting display branches, the same number as the scoring levels. The first counting display branch includes an AND gate U19, a counter U12, and a display tube DS1. The first input of AND gate U19 receives a counting enable signal Y1, the second input receives a third counting signal D1 corresponding to the scoring level, and its output is connected to the clock input of counter U12. The output of counter U12 is connected to the input of display tube DS1. The second counting display branch includes an AND gate U13, a counter U14, and a display tube DS2. The first input of AND gate U13 receives a counting enable signal Y1, the second input receives a third counting signal D2 corresponding to the scoring level, and its output is connected to the clock input of counter U14. The output of counter U14... The first input terminal is connected to the input terminal of the display tube DS2; the third counting display branch includes AND gate U15, counter U16 and display tube DS3. The first input terminal of AND gate U15 receives the counting enable signal Y1, the second input terminal receives the third counting signal D3 corresponding to the scoring level, and the output terminal is connected to the clock input terminal of counter U16. The output terminal of counter U16 is connected to the input terminal of display tube DS3; the fourth counting display branch includes AND gate U17, counter U18 and display tube DS4. The first input terminal of AND gate U17 receives the counting enable signal Y1, the second input terminal receives the third counting signal D4 corresponding to the scoring level, and the output terminal is connected to the clock input terminal of counter U18. The output terminal of counter U18 is connected to the input terminal of display tube DS4.

[0025] In this embodiment, each counting and display branch includes an AND gate, a counter, and a display tube. The common counting enable signal Y1 and the channel-specific third counting signal are logically operated at the AND gate. Only when both are at a high level at the same time will the AND gate output a rising edge clock pulse to the clock input of the counter, driving the channel counter to increment precisely by one and update the display tube value in real time.

[0026] Based on all the above technical solutions, the trigger circuit converts physical button actions into stable high-level pulses (first counting signals A1-A4) through pull-down resistors and an RC debouncing network. This signal is input to the core interlocking latch circuit, which, through the logic of latches and OR gates, ensures that once any button action is latched, other channels are immediately blocked, and a unique second counting signal (B1-B4) is output. Subsequently, the encoder-decoder circuit summarizes and distributes the latched signals: OR gate U10 generates a unified counting enable clock Y1, while encoder U9 and decoder U11 work together to compile and route the unique latched signal to the corresponding output channel (third counting signals D1-D4). Finally, in the counting display circuit, each channel's AND gate (e.g., U19) only generates a rising-edge clock to drive the counter (e.g., U12) to increment precisely by one and update the value of the display tube (e.g., DS1) in real time when it simultaneously receives the common enable signal Y1 and its own channel's strobe signal (e.g., D1).

[0027] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. A service rating counter circuit, characterized in that, The circuit includes a trigger circuit, a latch circuit, an encoder / decoder circuit, and a counting display circuit connected in sequence. The latch circuit includes multiple latch branches with the same number of branches as the scoring levels. Each latch branch is connected in the same way. One latch branch includes an OR gate U1 and a latch U5. The setting terminal of the latch U5 receives the first counting signal corresponding to the scoring level output by the trigger circuit. The output terminal of the latch U5 outputs the second counting signal corresponding to the scoring level. The input terminal of the OR gate U1 receives the second counting signal corresponding to other scoring levels. The output terminal of the OR gate U1 is connected to the reset terminal of the latch U5.

2. The service scoring counter circuit according to claim 1, characterized in that, The scoring system includes four levels.

3. The service scoring counter circuit according to claim 1, characterized in that, The trigger circuit includes multiple sets of trigger branches, the same number as the scoring level. Each set of trigger branches is connected in the same way. One of the trigger branches includes a switch button K1, a resistor R1, and a capacitor C1. The first end of the switch button K1 is connected to a 3.3V power supply, and the second end is grounded through the resistor R1. The far end of the resistor R1 outputs the first counting signal corresponding to the scoring level. The far end of the resistor R1 is also grounded through the capacitor C1.

4. The service rating counter circuit according to claim 1, characterized in that, The encoding and decoding circuit includes an encoder U9, a decoder U11, and an OR gate U10. The input of the OR gate U10 receives the second counting signals corresponding to all scoring levels, and the output of the OR gate U10 outputs a counting enable signal Y1. The input of the encoder U9 sequentially receives all the second counting signals of scoring levels from low to high. The output of the encoder U9 is sequentially connected to the input of the decoder U11, and the output of the decoder U11 sequentially outputs all the third counting signals of scoring levels from low to high.

5. A service scoring counter circuit according to claim 4, characterized in that, The counting display circuit includes multiple sets of counting display branches, the same number as the scoring levels. Each set of counting display branches is connected in the same way. One of the counting display branches includes an AND gate U19, a counter U12, and a display tube DS1. The first input terminal of the AND gate U19 receives a counting enable signal Y1, the second input terminal receives a third counting signal corresponding to the scoring level, and the output terminal is connected to the clock input terminal of the counter U12. The output terminal of the counter U12 is connected to the input terminal of the display tube DS1.

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