Pin arrangements, packages, chips and chip test sockets suitable for DDR interfaces
Patent Information
- Application Number
- CN202522059690.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-23
- Publication Date
- 2026-11-03
- Estimated Expiration
- 2035-09-23
AI Technical Summary
The existing DDR interface has an unreasonable pin arrangement structure, which leads to increased packaging costs, reduced electrical performance, and inability to adapt to irregular areas.
The array arrangement structure employs pin combinations, including multiple first pin pairs and second pin pairs. First and second VSS pins are arranged between the pin pairs to ensure the isolation and electrical performance of the DQ pins and DQS pins, adapting to different packaging scenarios.
It reduces the vertical dimensions of the package, lowers the packaging cost, improves the isolation of data pins, enhances electrical performance, and is suitable for a variety of packaging scenarios.
Smart Images
Figure CN224936087U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of packaging technology, and in particular to a pin arrangement structure, package, chip and chip test socket suitable for DDR (Double Data Rate) interface. Background Technology
[0002] As chip integration increases, the interconnection between chip packages and printed circuit boards (PCBs) also becomes more complex, leading to a denser pin distribution on chip packages. This is especially true for DDR interfaces in high-performance CPUs or artificial intelligence (AI) chips, where the number of DDR signals and their associated pins on a single chip can reach hundreds or even thousands. To meet the ever-increasing electrical performance requirements of DDR interfaces within limited package pin resources, large chips with a vast number of DDR signals typically employ pin arrangement strategies to optimize the use of package pin resources.
[0003] However, the existing pin arrangement still has the following drawbacks: 1) An unreasonable horizontal pin arrangement structure requires more vertical pin resources, thereby increasing packaging costs; 2) The data pin layout is unreasonable and the isolation is poor, which affects the electrical performance of the chip; 3) It has limited applicability and cannot be used in areas with irregular pin arrangements.
[0004] Therefore, there is an urgent need for a pin arrangement structure to overcome the above-mentioned defects. Utility Model Content
[0005] The purpose of this invention is to provide a pin arrangement structure, package, chip, and chip test socket suitable for DDR interfaces, thereby solving at least one of the aforementioned technical problems to a certain extent.
[0006] To achieve the above objectives, a first aspect of this utility model provides a pin arrangement structure suitable for a DDR interface. The pin arrangement structure includes multiple pin combinations arranged in an array, wherein each pin combination includes: multiple first pin pairs for providing a data transmission channel to perform data read / write operations, wherein each first pin pair includes data pins arranged in pairs of adjacent data pins, and the pairs of adjacent data pins in the multiple first pin pairs are arranged in the same oblique direction; a second pin pair for providing a timing reference for the data read / write operations performed by the first pin pairs, and adapted to the first pin pairs, wherein the second pin pair includes pairs of adjacent data strobe pins, and wherein the first pin pairs are arranged on both sides of the second pin pairs; a first ground pin for providing a reference potential for the first pin pairs and the second pin pairs, and arranged between the first pin pairs located on the same side of the second pin pairs; wherein for a data pin in a first pin pair that is close to its adapted second pin pair, the distance between it and the first data strobe pin and the second data strobe pin in the adapted second pin pair is equal; wherein in adjacent pin combinations, a second ground pin is arranged between the data pins closest to each other.
[0007] According to one embodiment of the present invention, the two adjacent data pins are arranged in a first oblique direction, wherein the first oblique direction refers to a clockwise tilt with the longitudinal direction as a reference.
[0008] According to one embodiment of the present invention, the two adjacent data pins are arranged in a second oblique direction, wherein the second oblique direction refers to a counterclockwise tilt with the longitudinal direction as the reference.
[0009] According to one embodiment of the present invention, for pin combinations arranged in an array, pin combinations arranged in the same horizontal direction are arranged at the same horizontal position or are arranged adjacent to each other in an alternating vertical arrangement, and / or pin combinations arranged in the same vertical direction are arranged at the same vertical position or are arranged adjacent to each other in an alternating horizontal arrangement.
[0010] According to one embodiment of the present invention, for pin combinations arranged in an array, there is one or more columns of second ground pins between horizontally adjacent pin combinations, and / or one or more rows of second ground pins between vertically adjacent pin combinations.
[0011] According to one embodiment of the present invention, for each pin combination, the first ground pin is arranged between corresponding data pins in two first pin pairs located on the same side.
[0012] According to one embodiment of the present invention, each pin combination includes four first pin pairs and two second pin pairs, wherein the two second pin pairs are arranged on the same line, the four first pin pairs are symmetrically arranged on both sides of the second pin pairs, and the distance between the first ground pin and the corresponding data pin in the two first pin pairs located on the same side is equal to that between them.
[0013] To achieve the above objectives, a second aspect of the present invention provides a package including a plurality of pins, wherein the plurality of pins adopt the pin arrangement structure described in the first aspect.
[0014] To achieve the above objectives, a third aspect of this utility model provides a chip, the chip comprising the package described in the second aspect.
[0015] To achieve the above objectives, a fourth aspect of this utility model provides a chip test socket, which is adapted to the chip described in the third aspect, wherein the pins of the chip test socket adopt a pin arrangement structure consistent with that of the chip described in the third aspect.
[0016] It is evident that this utility model has the following advantages compared to the prior art: 1) Effectively reduces the vertical dimension of the package, thereby lowering packaging costs; 2) Enhanced isolation between data pins ensures positive improvements in the chip's electrical performance. 3) It can be flexibly applied to various packaging scenarios, especially suitable for areas with irregular pin array arrangements, thereby making the most rational use of pin resources.
[0017] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0018] The above and / or additional aspects and advantages of this utility model will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic diagram of an existing pin arrangement structure; Figure 2 yes Figure 1 The diagram shows the distribution of adjacent pin combinations, where no front-isolated ground pins are arranged on the straight path between the data pins closest to each other in adjacent pin combinations. Figure 3 This is a schematic diagram of another existing pin arrangement structure; Figure 4 This is a schematic diagram of a pin arrangement structure according to an exemplary embodiment of the present invention; Figure 5 This is a schematic diagram of the pin arrangement of a pin combination according to an exemplary embodiment of the present invention; Figure 6 This is a schematic diagram illustrating the distribution of adjacent pin combinations according to an exemplary embodiment of the present invention; Figure 7 This is a schematic diagram of a pin arrangement structure according to an exemplary embodiment of the present invention; Figure 8 This is a schematic diagram illustrating an applicable scenario for a pin arrangement structure according to an exemplary embodiment of the present invention; Figure 9 This is a schematic diagram illustrating an applicable scenario for a pin arrangement structure according to an exemplary embodiment of the present invention; Figure 10 This is a schematic diagram of a pin arrangement structure according to an exemplary embodiment of the present invention; Figure 11 This is a schematic diagram of a pin arrangement structure according to an exemplary embodiment of the present invention; Figure 12 This is a schematic diagram of the pin arrangement of a pin combination according to an exemplary embodiment of the present invention; and Figure 13 This is a schematic diagram of the pin arrangement of a pin combination according to an exemplary embodiment of the present invention. Detailed Implementation
[0019] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this utility model, and should not be construed as limiting this utility model.
[0020] DDR (Double Data Rate) interface is a high-speed data transmission technology based on the rising and falling edges of a clock, and it is widely used in computer systems, mobile devices and embedded systems.
[0021] The pin types of a DDR interface typically include address and command, data channels, clock and timing control, power and ground, and other special auxiliary functions. This invention mainly describes the pin arrangement structure of a DDR interface for the ground pin (hereinafter referred to as the VSS pin) in the power and ground type, and the data pin (hereinafter referred to as the DQ pin) and data strobe pin (hereinafter referred to as the DQS pin) in the data channel type.
[0022] In practical applications, the arrangement of package pins has a certain impact on the overall pin resource utilization and the electrical performance of the chip. When the arrangement of package pins is not reasonable or does not adapt to the current pin resource distribution, it will lead to an increase in packaging cost and a decrease in electrical performance.
[0023] For example, Figure 1 It is an existing pin arrangement structure scheme, such as Figure 1 As shown, Figure 1 The pin arrangement shown adopts a "diamond" pattern. Figure 1 As can be seen, while ensuring consistency in the design of different pin combinations, it can ensure that there are at most two DQ pin crosstalk sources among the pins adjacent to each DQ pin. Since DQS is a differential signal, the crosstalk between the DQ pin and the adjacent DQS_P pin, and between the adjacent DQS_N pin, can cancel each other out. However, in this layout scheme, the different pin combinations arranged horizontally adopt a staggered arrangement of three rows, resulting in more pin resources being required vertically to meet the pin requirements of the DDR interface. In addition, VSS pins are arranged between adjacent DQ pins in the horizontally arranged adjacent pin combinations for isolation. However, although a row of VSS pins is arranged between the pin combinations in the vertical arrangement, the VSS pins are not on the straight path of the adjacent DQ pins in the adjacent pin combinations, that is, the isolation between adjacent DQ pins between different pin combinations is poor. Furthermore, Figure 2 It shows Figure 1 The isolation structure between two adjacent pin combinations in the scheme, such as Figure 2 As shown, there is no VSS pin with front isolation on the straight path (dashed arrow) between the DQ pins that are close to each other in the two adjacent pin combinations, which results in poor isolation between the adjacent pin combinations and thus affects the electrical performance.
[0024] Figure 3 It is another pin arrangement scheme for the DDR interface, from Figure 3 As can be seen, the scheme uses an "arrow-shaped" pattern arrangement, which is consistent with... Figure 1 The layout shown is slightly different. Figure 3 In the scheme shown, the number of adjacent DQ pins next to each DQ pin is reduced from two to one, but the vertically arranged pin combination also requires more pin resources, and the isolation between DQ pins that are close to each other in the vertically adjacent pin combination is also poor.
[0025] In view of this, the present invention proposes a package pin arrangement structure suitable for DDR interfaces. Specifically, the package pin structure includes multiple pin combinations arranged in an array, wherein each pin combination includes: multiple first pin pairs for providing data transmission channels to perform data read and write operations, wherein each first pin pair includes DQ pins arranged in pairs, and the pairs of adjacent DQ pins in the multiple first pin pairs are arranged in the same direction; a second pin pair for providing a timing reference for the data read and write operations performed by the first pin pairs, and adapted to the first pin pairs, wherein the second pin pair includes pairs of adjacent DQS pins, and wherein the first pin pairs are arranged on both sides of the second pin pairs; a first VSS pin for providing a reference potential for the first pin pairs and the second pin pairs, and arranged between the first pin pairs located on the same side of the second pin pairs; wherein, for the DQ pin of the first pin pair that is close to the adapted second pin pair, the distance between it and the two DQS pins in the adapted second pin pair is equal; in two adjacent pin combinations, a second VSS pin is arranged between the DQ pins closest to each other.
[0026] For example, in this invention, each pin combination includes multiple DQ pins, DQS pins, and VSS pins. The DQ pins provide a bidirectional data transmission channel, carrying read and write data signals. For instance, the DRAM chip outputs data to the memory controller via the DQ pins, or the memory controller inputs data to the DRAM chip via the DQ pins. The signal output by the DQS pins is a bidirectional differential signal, providing a timing reference for data sampling. When the DQ pins perform data input / output, the signal emitted by the DQS pins is strictly synchronized to ensure the accuracy of data input / output. The VSS pins are used to provide a stable zero-potential reference point to form a current loop. Additionally, the VSS pins are used to provide isolation between different types of pins to reduce crosstalk between high-speed signals.
[0027] In this invention, the DQ pin, DQS pin, and VSS pin are divided into multiple pin combinations, and the package pin arrangement of different combinations of DDR signals remains consistent. Furthermore, the multiple pin combinations are arranged in an array. Since DDR memory data transmission is grouped in bytes, the pins in each pin combination belong to the same byte group. For example, a byte group may include eight DQ signals and two pairs of DQS differential signals.
[0028] In this embodiment, for each pin combination, the DQ pins are arranged in pairs to form multiple first pin pairs, and the arrangement of each pair of adjacent DQ pins is in the same oblique direction. It should be noted that "same oblique direction" here refers to the consistent tilt direction of the DQ pin arrangement; the tilt angle can be the same or different, and this embodiment does not impose excessive limitations on this. The second pin pairs provide the DQS differential signal to the first pin pairs. Therefore, the second pin pairs are adapted to the arrangement of the first pin pairs. For example, each second pin pair can be adapted to the first pin pairs distributed on both sides of it. Each second pin pair includes two DQS pins, namely DQS_P pin and DQS_N pin, which together provide the differential signal.
[0029] This invention also includes VSS pins, which can be divided into first VSS pins and second VSS pins based on their arrangement. First VSS pins refer to those arranged within the same Byte Group, while second VSS pins refer to those arranged between different Byte Groups. Specifically, multiple first VSS pins can be arranged between first pin pairs on the same side. For example, the arrangement of first VSS pins on the same side can be consistent with or inconsistent with the tilt orientation of the first pin pairs. Multiple second VSS pins are arranged between adjacent pin combinations, with one or more of them arranged on a straight path between the closest DQ pins of each adjacent pin combination. This effectively isolates the DQ pins of different pin combinations, thereby improving the isolation between adjacent pin combinations.
[0030] In addition, as mentioned above, since DQS is a differential signal, in order to avoid crosstalk, the distance between the DQ pin closest to the DQS pin and the two DQS pins is equal, so that the crosstalk between the two DQS pins and the DQ pin can be completely canceled out.
[0031] As can be seen, in this invention, the DQ pins are arranged adjacent to each other in pairs, at an angle, and facing the same direction. This ensures that the DQ pins of different pin combinations are staggered vertically, effectively enhancing the isolation between different pin combinations. Furthermore, since the adjacent DQ pins are arranged with the same angle, they can be arranged according to the same angle, effectively saving pin resources and thus making rational use of pin resources. In addition, at least one second VSS pin is arranged between the DQ pins that are close to each other in any adjacent pin combination, further strengthening the isolation between pin combinations.
[0032] It should be noted that although there may be adjacent DQS pins with different pin combinations in this invention, since DQS is a differential signal, it has strong anti-interference ability. Therefore, from the perspective of overall layout, its electrical performance is positively improved.
[0033] Other preferred embodiments of this utility model will be further described in detail below with reference to the accompanying drawings.
[0034] Example 1 The two adjacent data pins are arranged in a first oblique direction, wherein the first oblique direction refers to a clockwise tilt with the longitudinal direction as the reference.
[0035] like Figure 4 As shown, Figure 4 It includes multiple pin combinations arranged in an array, for example... Figure 4 The pin combination 1 is arranged in a 4*4 (row*column) array. Since the pin arrangement of each pin combination in this invention is the same, the following description will use one pin combination as an example. Figure 5 A schematic diagram of the pin arrangement for one of the pin combinations is shown, such as... Figure 5 As shown, each pin combination 1 includes multiple first pin pairs 10, second pin pairs 20, and first VSS pins 30. Specifically, for any two DQ pins 101 and 102 of any first pin pair 10, this invention defines the DQ pin closer to the second pin pair 20 as the first DQ pin, and the DQ pin farther from the second pin pair 20 as the second DQ pin. Figure 5 As can be seen, the arrangement of adjacent DQ pins forms the first oblique direction. Specifically, with Figure 4 or Figure 5 Using the Cartesian coordinate system shown in the plane as a reference, the arrangement of the first and second DQ pins is tilted clockwise relative to the vertical axis (y-axis) of the Cartesian coordinate system. This can be understood as the orientation from the lower left region of the pins to the upper right region of the pins, i.e., a "lower left-upper right" orientation (e.g., ...). Figure 5 (As shown by the middle arrow). Figure 5 As shown, the second pin pair 20 is adapted to the two first pin pairs 10 arranged on its two sides. Figure 5For any second pin pair 20 (located on the top and bottom sides), it may include two adjacent DQS pins 201 and 202, which together provide differential signals to the first pin pairs 10 arranged on both sides of it. In the first pin pair 10, the first DQ pin 101, relatively close to the second pin pair 20, is adjacent to both DQS pins 201 and 202, and is arranged on the center vertical line connecting these two DQS pins. This arrangement ensures that the distance between the first DQ pin 101 and the two DQS pins is equal, thereby canceling out crosstalk between the first DQ pin 101 and the two DQS pins. A first VSS pin 30 is arranged between the first pin pairs 10 located on the same side of the second pin pair 20. For example, as... Figure 5 As shown, a first VSS pin 30 is arranged between the two left and right first pin pairs 10 located above the second pin pair 20 to provide a reference potential for these two first pin pairs. Similarly, a first VSS pin 30 is also arranged between the two left and right first pin pairs 10 located below the second pin pair 20 to provide a reference potential.
[0036] For a clearer understanding of the arrangement of the second VSS pin, please refer to [further details]. Figure 6 , Figure 6 for Figure 4 The diagram shows the arrangement of two adjacent pins in a vertically distributed configuration. Figure 6 The diagram shows two adjacent pin combinations labeled 1A and 1B. The two lowest second DQ pins 102a and 102b in the upper pin combination 1A, and the two highest second DQ pins 102c and 102d in the lower pin combination 1B, are close to each other. If the second VSS pins of the two pin combinations are not properly arranged, the isolation between the upper and lower pin combinations will inevitably be poor. Therefore, in this invention, the second VSS pins 40 are respectively arranged on the line connecting second DQ pins 102a and 102c, on the line connecting second DQ pins 102b and 102c, and on the straight path between second DQ pins 102b and 102d. Thus, because the DQ pins of adjacent pin combinations are staggered in this embodiment, front-facing second VSS pins are arranged on the straight paths of the close second DQ pins for isolation.
[0037] This embodiment one and Figure 1 and Figure 3Compared to the scheme shown, the pin combinations in the same horizontal direction do not need to be arranged in three staggered rows, thus saving pin resources. Furthermore, although there is only one row of VSS pins for isolation between different pin combinations in the vertical direction, the DQ pins of adjacent pin combinations in the vertical direction are staggered, and the DQ pins that are close to each other are isolated by VSS pins, thereby further enhancing the isolation between different pin combinations.
[0038] Example 2 The two adjacent data pins are arranged in a second oblique direction, wherein the second direction refers to a counterclockwise tilt with the longitudinal direction as the reference.
[0039] like Figure 7 As shown, Figure 7 It includes multiple pin combinations 2 arranged in an array, for example Figure 7 The pin combination 2 is arranged in a 4*4 (row*column) array.
[0040] The only difference between this embodiment and embodiment one is that the orientation of adjacent DQ pins in embodiment two is different. For example... Figure 7 As shown, the line connecting any two adjacent DQ pins is tilted counterclockwise relative to the vertical axis (y-axis) of the Cartesian coordinate system. This can be understood as the direction from the lower right region of the entire pin to the upper left region of the pin, i.e., a "lower right-upper left" orientation (as shown in the image). Figure 7 (As indicated by the middle arrow).
[0041] Based on the above embodiments one and two, it can be understood that although the two embodiments are consistent in terms of pin arrangement rules, differing only in orientation, they can be flexibly adapted to more packaging scenarios. For example, in actual design, the four corners of the chip package may be missing due to process requirements, resulting in irregular pin distribution at the four corners. However, based on the arrangement scheme of this utility model, the arrangement scheme of embodiment one or embodiment two can be flexibly selected based on the actual irregular area, thereby further making reasonable use of the entire pin resource.
[0042] Specifically, such as Figure 8 and Figure 9 As shown, where Figure 8 The scene in the top left corner is missing. Figure 8 The scene in the bottom left corner is missing. (Due to...) Figure 8 The top left corner is missing. To address this, this invention can adopt the "bottom left-top right" orientation arrangement of Embodiment 1, thereby making more efficient use of the pin resources near the top left corner area. Similarly, due to... Figure 9 Since the lower left corner is missing, the "lower right-upper left" orientation arrangement of Embodiment 2 can make more reasonable use of the pin resources near the lower left corner area.
[0043] It should be noted that, Figure 8 and Figure 9 This is merely an illustrative example. For other scenarios, those skilled in the art can flexibly choose different arrangement schemes of the embodiments, or combine different embodiments, to adopt a reasonable arrangement scheme for various missing scenarios, thereby maximizing the utilization of pin resources. For example, for scenarios where the upper edge is missing, this utility model can consider a staggered arrangement scheme to make reasonable use of the pin resources near the missing upper edge. This staggered arrangement scheme will be described in the following embodiments and will not be elaborated on here.
[0044] Example 3 For pin combinations arranged in an array, pin combinations arranged in the same horizontal direction are arranged at the same horizontal position or are arranged adjacent to each other in an alternating vertical arrangement, and / or pin combinations arranged in the same vertical direction are arranged at the same vertical position or are arranged adjacent to each other in an alternating horizontal arrangement.
[0045] Specifically, pin combinations arranged in an array can be arranged according to certain rules. For example, pin combinations in the same row are all at the same horizontal position, meaning that the center lines connecting them form a straight line. (Refer to the above.) Figure 4 and Figure 7 The illustrated arrangement shows pin combinations in the same horizontal row arranged horizontally at the same horizontal position. Alternatively, pin combinations in the same horizontal row can be arranged vertically, alternating between each other. Specifically, for a given horizontal row, if the first pin combination from the left is at the first horizontal position, then the second pin combination to the right can be shifted down or up one row, and so on. This arrangement ensures that adjacent pin combinations in the same horizontal row are staggered. For example... Figure 10As shown, the pin combinations in the top row are arranged from left to right as pin combination 1a, pin combination 1b, pin combination 1c, and pin combination 1d. Pin combination 1a and pin combination 1c are at the same horizontal level, while pin combination 1b and pin combination 1d are at the same horizontal level but staggered one row below pin combination 1a and pin combination 1c, creating a staggered arrangement. The rows below follow this pattern. It should be noted that the number of rows staggered is not limited to one; those skilled in the art can choose flexibly according to the actual situation. This staggered arrangement can also be implemented by pairing two pin combinations. For example, pin combination 1a and pin combination 1b are a pair at the same horizontal level, while pin combination 1c and pin combination 1d are a pair at the same horizontal level, but their horizontal positions are staggered one or more rows above or below the horizontal positions of pin combination 1a and pin combination 1b.
[0046] One advantage of this staggered arrangement scheme is that, for example, if the upper edge of pin combination 1b is missing, pin combination 1b can be staggered down a certain number of rows, compared to... Figure 4 or Figure 7 When pin combinations in the same horizontal row are positioned at the same horizontal level, pin resources near the missing portion can be better utilized.
[0047] Figure 11 The layout and Figure 10 Similarly, except that the orientation of adjacent DQ pins is different, and their staggered arrangement follows the same pattern. Figure 11 The same applies, so I won't go into too much detail here.
[0048] Similarly, for pin combinations in the same column, they can be arranged in the same vertical position or staggered left and right. The arrangement principle is similar to the arrangement rules in the same horizontal row, and will not be elaborated further here.
[0049] It should be noted that for this staggered arrangement scheme, the isolation between adjacent DQ pins must be ensured. Depending on the actual staggered arrangement, a second VSS pin (row or column) can be appropriately arranged between adjacent pin combinations to both enhance the isolation between pin combinations and make reasonable use of pin resources.
[0050] Example 4 For pin combinations arranged in an array, adjacent pin combinations laterally are separated by one or more columns of second VSS pins, and / or adjacent pin combinations vertically are separated by one or more rows of second VSS pins.
[0051] Specifically, in some layout examples, in order to adapt to certain specific layout rules, one or more rows or columns of second VSS pins can be added between adjacent pin combinations. Although this layout method will occupy more pin resources, from an overall perspective, on the one hand, it can adapt to the special characteristics of certain packaging processes and make reasonable allocation of pin resources as a whole; on the other hand, it can effectively strengthen the isolation between DQ pins between different pin combinations and ensure that the overall electrical performance of the chip reaches the best.
[0052] refer to Figure 10 and Figure 11 First refer to Figure 10 , Figure 10 The layout scheme shown is the same as Figure 4 Compared to the layout shown, pin combinations in the same horizontal row are arranged in a staggered manner, while pin combinations in the same vertical column are arranged identically, all in the same vertical position. Furthermore... Figure 10 In the middle, the comparison between horizontally adjacent pin combinations Figure 4 To enhance isolation, a second column of VSS pins has been added. Taking the top row as an example, two columns of second VSS pins are arranged between pin combinations 1a and 1b, between pin combinations 1b and 1c, and between pin combinations 1c and 1d (see [link to documentation]). Figure 10 The VSS pin is shown in the dashed box. Similarly, Figure 11 The layout scheme shown is relative to Figure 7 In the illustrated arrangement, pin combinations in the same horizontal row are staggered vertically, while pin combinations in the same vertical column remain unchanged, all in the same vertical position. Furthermore... Figure 11 In the middle, compared to the horizontally adjacent pin combinations 2a, 2b, 2c, and 2d Figure 7 To add a second VSS pin (refer to...) Figure 11 The VSS pin (shown in the dashed box) is used to enhance isolation between pin combinations.
[0053] Similarly, for pin combinations in the same column, one or more rows of second VSS pins can be added horizontally to further enhance the isolation between vertically adjacent pin combinations. Since the arrangement rules are similar to the horizontal arrangement, they will not be elaborated upon here.
[0054] Example 5 For each pin combination, the first VSS pin is positioned between the corresponding DQ pins in two first pin pairs located on the same side.
[0055] Specifically, such as Figure 12As shown, two first pin pairs, denoted as first pin pair 10e and first pin pair 10f, are arranged on the upper side of the DQS pin. First pin pair 10e includes a first DQ pin 101e and a second DQ pin 102e, and first pin pair 10f includes a first DQ pin 101f and a second DQ pin 102f. First DQ pins 101e and 101f are adjacent to the DQS pin, while second DQ pins 102e and 102f are relatively far from the DQS pin. Figure 12 The first VSS pins 30a and 30b are respectively arranged on the straight path between the first DQ pin 101e and the first DQ pin 101f, and on the straight path between the second DQ pin 102e and the second DQ pin 102f. This arrangement enhances the isolation between the first DQ pin 101e in the first pin pair 10e and the first DQ pin 101f in the second pin pair 10f, as well as the isolation between the second DQ pin 102e in the first pin pair 10e and the second DQ pin 102f in the second pin pair 10f. Similarly, the first VSS pin 30 is also arranged between the two first pin pairs located below the DQS pin, as per the above rule, and will not be elaborated further here.
[0056] Example 6 Each pin combination includes four first pin pairs and two second pin pairs, wherein the two second pin pairs are arranged on the same line, and the four first pin pairs are arranged symmetrically on both sides of the second pin pairs. The distance between the first VSS pin and the corresponding DQ pin of the two first pin pairs on the same side is equal to that between them.
[0057] Specifically, such as Figure 13 As shown, Figure 13The pin configuration includes four first pin pairs 10g, 10h, 10j, and 10k, and two second pin pairs 20a and 20b. The center line connecting the two second pin pairs 20a and 20b forms a horizontal straight line. The first pin pairs 10g and 10j are arranged in a matching configuration with the second pin pair 20a, and the first pin pairs 10h and 10k are arranged in a matching configuration with the second pin pair 20b. The first pin pairs 10g and 10j are arranged symmetrically with the second pin pair 20a as the horizontal center, and the first pin pairs 10h and 10k are arranged symmetrically with the second pin pair 20b as the horizontal center. Simultaneously, the first VSS pin 30c is located at the center between the second DQ pin 102g of the first pin pair 10g and the second DQ pin 102h of the first pin pair 10h; the first VSS pin 30d is located at the center between the first DQ pin 101g of the first pin pair 10g and the first DQ pin 101h of the first pin pair 10h; the first VSS pin 30e is located at the center between the second DQ pin 102j of the first pin pair 10j and the second DQ pin 102k of the first pin pair 10k; and the first VSS pin 30f is located at the center between the first DQ pin 101j of the first pin pair 10j and the first DQ pin 102k of the first pin pair 10k. Furthermore... Figure 12 In this design, all adjacent pins in the pin group are equidistant from each other. This regular, equidistant, and symmetrical distribution is more conducive to the packaging process design, allowing for cross-referencing and even direct copying during the design process, significantly improving design efficiency.
[0058] Based on the same concept, this utility model also provides a package that includes multiple pins, wherein the multiple pins adopt the pin arrangement structure described in the above embodiments.
[0059] Accordingly, this utility model also provides a chip, which includes the packaging described above.
[0060] Accordingly, this utility model also provides a chip test socket, which is compatible with the chip described above, wherein the pins of the chip test socket adopt the same pin arrangement structure as the chip.
[0061] Specifically, the arrangement scheme of this utility model is also suitable for components that are compatible with the package. For example, when the package is an LGA package, the corresponding socket pins need to adopt the same arrangement scheme as the package pins.
[0062] For more advantages and details regarding the above package, chip, and chip test socket, please refer to the embodiment of the pin arrangement structure described above, which will not be elaborated upon here.
[0063] The above description is merely a preferred embodiment of this utility model and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure involved in this utility model is not limited to the technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this utility model.
[0064] Furthermore, although the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. Multitasking and parallel processing may be advantageous in certain environments. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this invention. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.
[0065] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.
Claims
1. A pin arrangement structure suitable for a DDR interface, characterized in that, The pin arrangement structure includes multiple pin combinations arranged in an array, wherein each pin combination includes: Multiple first pin pairs are provided to provide data transmission channels for performing data input / output, wherein each first pin pair includes data pins arranged in pairs of adjacent data pins, and the pairs of adjacent data pins in the multiple first pin pairs are arranged in the same diagonal direction; The second pin pair is used to provide a timing reference for the data input / output performed by the first pin pair and is adapted to the arrangement of the first pin pair, wherein the second pin pair includes two adjacent data strobe pins, and wherein the first pin pair is arranged on both sides of the second pin pair; A first ground pin is used to provide a reference potential for the first pin pair and the second pin pair, and is arranged between the first pin pair located on the same side of the second pin pair; Wherein, for the data pin of the first pin pair that is close to the second pin pair that is adapted to it, the distance between it and the two data strobe pins in the second pin pair that are adapted to it is equal; In two adjacent pin combinations, a second ground pin is placed between the data pins closest to each other.
2. The pin arrangement structure according to claim 1, characterized in that, The two adjacent data pins are arranged in a first oblique direction, wherein the first oblique direction refers to a clockwise tilt with the longitudinal direction as the reference.
3. The pin arrangement structure according to claim 1, characterized in that, The two adjacent data pins are arranged in a second oblique direction, wherein the second oblique direction refers to a counterclockwise tilt relative to the longitudinal direction.
4. The pin arrangement structure according to claim 1, characterized in that, For pin combinations arranged in an array, pin combinations arranged in the same horizontal direction are arranged at the same horizontal position or are arranged adjacent to each other in an alternating vertical arrangement, and / or pin combinations arranged in the same vertical direction are arranged at the same vertical position or are arranged adjacent to each other in an alternating horizontal arrangement.
5. The pin arrangement structure according to claim 1, characterized in that, For pin combinations arranged in an array, adjacent pin combinations laterally are separated by one or more columns of second ground pins, and / or adjacent pin combinations vertically are separated by one or more rows of second ground pins.
6. The pin arrangement structure according to claim 1, characterized in that, For each pin combination, the first ground pin is positioned between the corresponding data pins in two first pin pairs located on the same side.
7. The pin arrangement structure according to claim 1, characterized in that, Each pin combination includes four first pin pairs and two second pin pairs, wherein the two second pin pairs are arranged on the same line, and the four first pin pairs are arranged symmetrically on both sides of the second pin pairs. The distance between the first ground pin and the corresponding data pin in the two first pin pairs on the same side is equal to that between them.
8. A package, characterized in that, The package includes a plurality of pins, wherein the plurality of pins adopt the pin arrangement structure of any one of claims 1-7.
9. A chip, characterized in that, The chip comprises the package of claim 8.
10. A chip test socket, characterized in that, The chip test socket is adapted to the chip of claim 9, wherein the pins of the chip test socket adopt the same pin arrangement structure as the chip.