ELECTRONIC COMPONENT AND COATED SEMICONDUCER SUBSTRATE

Abstract

Coated semiconductor substrate (2,3), comprising: a semiconductor substrate (2); and a layer system (3) arranged on the semiconductor substrate (2); wherein the layer system (3) comprises: an electrical contact layer (3.1) which is arranged directly on the semiconductor substrate (2), wherein the electrical contact layer (3.1) is a single-element layer of Al; a functional layer (3.2) arranged directly on the electrical contact layer (3.1), wherein the functional layer (3.2) comprises Ti or an alloy comprising Ti; an adhesive layer (3.3) which is arranged directly on the functional layer (3.2), wherein the adhesive layer (3.3) comprises Ni; a solder layer (3.4) which is arranged directly on the adhesive layer (3.3), wherein the solder layer (3.4) is a single-element layer of Sn; a protective layer (43.5) that is arranged directly on the solder layer (3.4).

Description

TECHNICAL AREA

[0001] The present invention relates to an electronic component and a coated semiconductor substrate. BACKGROUND

[0002] For the production of electronic components, semiconductor chips, semiconductor dies, semiconductor substrates, or semiconductor wafers are very often deposited onto carriers such as leadframes. Currently, the only available highly conductive die mounting material for power semiconductor chips with high temperature cycling resistance and high heat storage reliability is AuSn diffusion solder die mounting. This die mounting material is an AuSn alloy with an Au content of approximately 80%. Due to the high cost, this AuSn solution is limited to a thin solder layer, which usually results in a challenging die mounting process.

[0003] DE 196 03 654 C1 relates to a method for soldering a semiconductor body onto a substrate. A disadvantage is that when a nickel layer is soldered with tin, the nickel dissolves in the tin. DE 101 24 141 A1 shows a layer stack between a semiconductor chip and a substrate, designed to absorb thermomechanical stresses between the chip and the substrate, thereby increasing the reliability of the attachment. The substrate is a copper conductor frame. A thick aluminum layer connects to the chip as a buffer layer. DE 10 2005 029 246 A1 shows a semiconductor chip that is soldered to a conductor track applied to a substrate via a sequence of layers. The layer sequence includes barrier layers on both sides of a solder layer. The barrier layers can be made of titanium, vanadium, chromium, or niobium. DE 195 32 250 A1 relates to diffusion soldering in a multilayer structure.A variety of possible material combinations suitable for diffusion brazing are listed, along with their respective melting temperatures. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The accompanying drawings are provided to offer a more detailed understanding of the embodiments. The drawings illustrate embodiments and, together with the description, serve to explain the principles of their design. Other embodiments and many of the intended advantages of the embodiments readily gain in value when better understood with reference to the following detailed description. The elements in the drawings are not necessarily to scale with each other. The same reference numerals denote corresponding similar parts. Fig. Figure 1 shows a schematic cross-sectional side view of an electronic component according to the invention; Fig. 2a and Fig. Figure 2b shows schematic cross-sectional side view representations to illustrate essential mechanisms of the bonding process; Fig. Figure 3 shows a flowchart to illustrate a method for manufacturing an electronic component according to the invention; and Fig. Figure 4 shows a schematic cross-sectional side view of a support and a semiconductor substrate together with a layer stack to illustrate a method for manufacturing an electronic component according to the invention. DETAILED DESCRIPTION OF ILLUSTRATIVE FORM OF EXECUTION

[0005] The aspects and embodiments are now described with reference to the drawings, in which the same reference numerals are always used to refer generally to the same elements. For explanatory purposes, numerous specific details are listed in order to provide a thorough understanding of one or more aspects of the embodiments. However, it may be obvious to a person skilled in the art that one or more aspects of the embodiments can also be implemented with fewer specific details. In other cases, known structures and elements are shown schematically to facilitate the description of one or more aspects of the embodiments. It is understood that other embodiments may be used and structural or logical modifications may occur without deviating from the scope of protection of the present invention.Please note that the drawings are not, or not necessarily, to scale.

[0006] Even if a particular feature or aspect of an embodiment is disclosed only with reference to one of several implementations, such a feature or aspect may additionally be combined with one or more other features or aspects of the other implementations if this may be desirable and advantageous in a particular application. Furthermore, when the terms "contain," "have," "with," or other variations thereof are used in the detailed description or the claims, such terms shall be considered inclusive, similar to the term "comprise." The terms "coupled" and "connected," along with derivatives, may also be used.It is understood that these terms can be used to indicate that two elements cooperate or interact with each other, whether they are in direct physical or electrical contact or not. The term "exemplary" is to be understood merely as an example and not as the best or optimal case. Thus, the following detailed description should not be interpreted in a limiting sense, and the scope of protection of the present invention is defined by the attached claims.

[0007] In the embodiments of an electronic component and a method for manufacturing an electronic component, various types of semiconductor chips or circuits integrated in semiconductor chips may be used, including logic integrated circuits, analog integrated circuits, integrated mixed-signal circuits, MEMS (microelectromechanical systems), integrated power circuits, chips with integrated passives, etc.In the embodiments, semiconductor chips can also be used that have MOS transistor structures or vertical transistor structures such as IGBT structures (IGBT - bipolar transistor with insulated gate electrode) or, more generally, transistor structures in which at least one electrical contact terminal is located on a first main surface of the semiconductor chip and at least one other electrical contact terminal is located on a second main surface of the semiconductor chip opposite the first main surface of the semiconductor chip.

[0008] In several embodiments, layers or layer stacks are applied one upon another, or materials are applied to or deposited onto layers. It is understood that all such terms as "applied" or "deposited" are intended to include literally all types and techniques for applying layers. In particular, they are intended to include techniques in which layers are applied as a whole in one step, such as lamination techniques, as well as techniques in which layers are deposited sequentially, such as sputtering, electroplating, encapsulation, chemical vapor deposition (CVD), etc.

[0009] Fig. Figure 1 shows a schematic cross-sectional side view of an electronic component according to the invention. The electronic component 10 of Fig. 1 comprises a carrier 1 with a metallic surface, a semiconductor substrate 2 and a layer system 3 arranged between the semiconductor substrate 2 and the carrier 1. The layer system 3 comprises an electrical contact layer 3.1 arranged on the semiconductor substrate 2, a functional layer 3.2 arranged on the electrical contact layer 3.1, an adhesive layer 3.3 arranged on the functional layer 3.2, and a solder layer 3.4 arranged between the adhesive layer 3.3 and the carrier 1.

[0010] According to one embodiment of the electronic component 10, the semiconductor substrate 2 consists of a silicon-based semiconductor material, e.g., a substrate of Si, SiC, or another silicon-based material, or a compound semiconductor material such as a III-V material like GaN. The semiconductor substrate may have an electrical contact terminal on its lower surface, which is formed by a highly doped n + - or p +-area of ​​training, encompass.

[0011] According to the invention, the electrical contact layer 3.1 is a single-element layer made of Al.

[0012] According to the invention, the functional layer 3.2 consists of a barrier layer. The functional layer comprises Ti or a Ti-containing alloy.

[0013] According to the invention, the adhesive layer comprises 3.3 Ni.

[0014] According to the invention, the solder layer 3.4 is a single-element layer made of Sn.

[0015] According to the invention, the solder layer 3.4 comprises a single-element solder material that does not tend to form phases during deposition. Additionally, the solder material itself can be free of precious metals and therefore significantly cheaper. Due to the lower cost, it can be applied in a much thicker layer than AuSn, thus simplifying the die fastening process. Depending on the solder material, the soldering temperature can also be significantly reduced, resulting in higher durability because the isothermal solidification of the solder material places less stress on the solder joint.

[0016] According to one embodiment of the electronic component 10, the carrier 1 has a metal carrier, which in particular comprises Cu or Ni.

[0017] According to one embodiment of the electronic component 10, the support 1 is coated with one or more metal layers. In this case, the support 1 itself can consist of a non-metallic support, such as a ceramic material like aluminum oxide. In particular, the uppermost metal layer consists of Ag or Cu, or of an alloy of one or more of these elements.

[0018] According to the embodiment of the electronic component 10 according to the invention, intermetallic phases are formed between the carrier 1 and the solder layer 3.4 or between a metal layer arranged on the carrier 1 and the solder layer 3.4.

[0019] According to the embodiment of the electronic component 10 according to the invention, intermetallic phases are formed between the adhesive layer 3.3 and the solder layer 3.4.

[0020] According to one embodiment of the electronic component 10, the adhesive layer 3.3 and the surface of the carrier 1 or the surface of a metal layer with which the carrier surface is coated are formed from the same base material, namely Ni or NiNiP.

[0021] According to one embodiment of the electronic component 10, the carrier 1 has a leadframe.

[0022] According to one embodiment of the electronic component 10, the layer system 3 is free of Au.

[0023] According to one embodiment of the electronic component 10, the semiconductor substrate 2 has a thickness in the range of 5 µm to 500 µm.

[0024] According to one embodiment of the electronic component 10, the electrical contact layer 3.1 has a thickness in the range of 100 nm to 1 µm.

[0025] According to one embodiment of the electronic component 10, the functional layer 3.2 has a thickness in the range of 50 nm to 200 nm.

[0026] According to one embodiment of the electronic component 10, the adhesive layer 3.3 has a thickness in the range of 200 nm to 2 µm.

[0027] According to one embodiment of the electronic component 10, the solder layer 3.4 has a thickness in the range of 1 µm to 5 µm.

[0028] Note that the thickness ranges mentioned above also include all incremental values.

[0029] It has been found that good results can be achieved when the adhesive layer 3.3 and the surface of the substrate 1, i.e., the base material of the substrate 1 or a top metal layer with which the substrate 1 is coated, consist of the same base material, e.g., Cu / Cu, Ag / Ag, NiV / Ni, or NiV / NiNiP, which creates a binary or quasi-binary alloy system that forms a characteristic layer structure in the solder joint. The layer structure essentially represents the phase fractions shown in a phase diagram of a binary alloy, with the structure being comparable to a two-sided diffusion pair of, in this case, Cu / Sn.

[0030] Fig. 2a and Fig. Figure 2b shows schematic cross-sectional side view representations to illustrate a layer structure according to an embodiment to illustrate the bonding mechanism. Fig. 2a shows the carrier 1 and from the layer stack 3 only the adhesive layer 3.3 and the solder layer 3.4 are shown before the bonding process. Fig. Figure 2b shows the layer structure after the bonding process. It is evident that intermetallic phase layers have formed on both sides of the solder layer 3.4. Fig. 2b A first intermetallic phase layer 3.5 is formed between the adhesive layer 3.3 and the solder layer 3.4, and a second intermetallic phase layer 3.6 is formed between the solder layer 3.4 and the substrate 1. The first intermetallic phase layer 3.5 is rich in the metal of the adhesive layer 3.3, and the second intermetallic phase layer 3.6 is rich in the metal of the substrate 1 surface. The remaining intermediate solder layer 3.4 is still rich in the metal of the initial solder layer 3.4. If the materials of the substrate 1 and the adhesive layer 3.3 are identical, and depending on the layer thickness, only a homogeneous layer of an alloy phase may form instead of the solder layer 3.4, the first intermetallic phase layer 3.5, and the second intermetallic phase layer 3.6. Depending on the material combination used, more than two different layers may also form at the joint.

[0031] Fig. Figure 3 shows a flowchart illustrating a method for manufacturing an electronic component according to the invention. The method 30 comprises providing a semiconductor substrate (31), depositing an electrical contact layer on the semiconductor substrate (32), depositing a functional layer on the electrical contact layer (33), depositing an adhesive layer on the functional layer (34), depositing a solder layer on the adhesive layer (35), depositing a protective layer on the solder layer (36), and attaching the semiconductor substrate to a support (37).

[0032] According to one embodiment of method 30, the method further comprises the deposition of one or more of the following layers: the electrical contact layer, the functional layer, the adhesive layer, the solder layer and the protective layer by means of physical vapor deposition or sputtering, in particular within the same processing apparatus.

[0033] According to one embodiment of method 30, the electrical contact layer consists of an Al or Ti layer, the functional layer of a Ti, TiW or W layer, the adhesive layer of a Cu or Ag layer, the solder layer of a Sn layer and the protective layer of an Ag or Au layer.

[0034] Further embodiments of method 30 can be achieved by incorporating a feature described above in conjunction with the embodiments of Fig. 1 and Fig. 2 was described in Fig. 3 will be formed.

[0035] Fig. Figure 4 shows a schematic cross-sectional side view of a support and a semiconductor substrate together with a layer stack to illustrate a method for manufacturing an electronic component according to the invention. Fig. Figure 4 essentially shows a support 41, in particular a leadframe, and a semiconductor substrate 42, which is to be bonded to the support 41. For this purpose, a layer stack 43 is deposited onto the lower surface of the semiconductor substrate 42. In a first step, an electrical contact layer 43.1 is deposited onto the lower surface of the semiconductor substrate 42. In a second step, a functional layer 43.2 is deposited onto the electrical contact layer 43.1. In a third step, an adhesive layer 43.3 is deposited onto the functional layer 43.2. In a fourth step, a solder layer 43.4 is deposited onto the adhesive layer 43.3. In a fifth step, a protective layer 43.5 is deposited onto the solder layer 43.4. The deposition processes can be carried out by physical vapor deposition or sputtering.

[0036] According to one embodiment, the protective layer 43.5 has a thickness in the range of 50 nm to 300 nm. Thus, the protective layer 43.5 can be manufactured so thinly that it is present in the final product, such as the one described in Fig. The layer shown in Figure 1 practically disappears. The protective layer 43.5 prevents oxidation of the solder layer 43.4.

[0037] In the embodiment of Fig. 4. One or more metal layers 41.1 are deposited on the support 41. The metal layer 41.1, or the uppermost metal layer if two or more metal layers are present, consists of Au, Ag, Cu, Pd or Pt, or of an alloy of one or more of these elements.

[0038] Finally, after the production of the layer stack 43, the semiconductor substrate 42 is bonded together with the layer stack 43 to the upper surface of the support 41 or the upper surface of the top metal layer 41.1.

[0039] Additionally, it should be noted that the system consisting of the semiconductor substrate 42 and the layer stack 43 can be soldered at a die attachment temperature of 300°C, resulting in a lower die attachment stress compared to the 350°C at which the AuSn solder layer is currently attached.

Claims

[1] Coated semiconductor substrate (2,3), comprising: a semiconductor substrate (2); and a layer system (3) arranged on the semiconductor substrate (2); wherein the layer system (3) comprises: an electrical contact layer (3.1) which is arranged directly on the semiconductor substrate (2), wherein the electrical contact layer (3.1) is a single-element layer of Al; a functional layer (3.2) arranged directly on the electrical contact layer (3.1), wherein the functional layer (3.2) comprises Ti or an alloy comprising Ti; an adhesive layer (3.3) which is arranged directly on the functional layer (3.2), wherein the adhesive layer (3.3) comprises Ni; a solder layer (3.4) which is arranged directly on the adhesive layer (3.3), wherein the solder layer (3.4) is a single-element layer of Sn; a protective layer (43.5) that is arranged directly on the solder layer (3.4). [2] Coated semiconductor substrate (2,3) according to claim 1, wherein the protective layer (43.5) comprises an Ag layer or an Au layer. [3] Coated semiconductor substrate (2, 3) according to claim 1 or 2, wherein the semiconductor substrate (2) has a lower surface comprising an electrical contact terminal formed by a highly doped n + - or p + -area is formed, and the layer system (3) is arranged on the lower surface of the semiconductor substrate (2). [4] Coated semiconductor substrate (2,3) according to any of the preceding claims, wherein the semiconductor substrate (2) comprises a vertical transistor structure. [5] Coated semiconductor substrate (2,3) according to one of the preceding claims, wherein the solder layer (3.4) has a thickness in the range of 1 µm to 5 µm. [6] Coated semiconductor substrate (2,3) according to one of the preceding claims, wherein the protective layer (43.5) has a thickness in the range of 50 nm to 300 nm. [7] Coated semiconductor substrate (2,3) according to any of the preceding claims, wherein the adhesive layer (3.3) comprises NiV. [8] Coated semiconductor substrate (2,3) according to one of the preceding claims, wherein the adhesive layer (3,3) has a thickness in the range of 200 nm to 1 µm. [9] Coated semiconductor substrate (2,3) according to one of the preceding claims, wherein the electrical contact layer (3.1) has a thickness in the range of 100 nm to 1 µm. [10] Coated semiconductor substrate (2,3) according to one of the preceding claims, wherein the functional layer (3.2) has a thickness in the range of 50 nm to 200 nm. [11] Electronic component (10), comprising: a support (1, 41) wherein the surface of the support (1, 41) comprises Cu in a first alternative and Ag in a second alternative; a semiconductor substrate (2) attached to the support (1) by: an electrical contact layer (3.1) which is arranged directly on the semiconductor substrate (2), wherein the electrical contact layer (3.1) is a single-element layer of Al; a functional layer (3.2) arranged directly on the electrical contact layer (3.1), wherein the functional layer (3.2) comprises Ti or an alloy comprising Ti; an adhesive layer (3.3) which is arranged directly on the functional layer (3.2), wherein the adhesive layer (3.3) comprises Ni; a first intermetallic phase layer (3.5) arranged directly on the adhesive layer (3.3), wherein the first intermetallic phase layer (3.5) comprises Ni and Sn; and a second intermetallic phase layer (3.6) between the first intermetallic phase layer (3.5) and the surface of the support (1, 41), comprising Cu and Sn in the first alternative and Ag and Sn in the second alternative, wherein a single-element layer of Sn is arranged between the first intermetallic phase layer (3.5) and the second intermetallic phase layer (3.6). [12] Electronic component (10) according to claim 11, wherein the second intermetallic phase layer (3.6) has traces of Au or Ag. [13] Electronic component according to one of claims 11 or 12, wherein the semiconductor substrate (2) has a lower surface comprising an electrical contact terminal formed by a highly doped n + - or p + -area is formed, and the layer system (3) is arranged on the lower surface of the semiconductor substrate (2). [14] Electronic component according to one of claims 11 to 13, wherein the semiconductor substrate (2) comprises a vertical transistor structure. [15] Electronic component according to any one of claims 11 to 14, wherein the adhesive layer (3.3) comprises NiV. [16] Coated semiconductor substrate (2,3) according to any one of claims 11 to 15, wherein the adhesive layer (3,3) has a thickness in the range of 200 nm to 1 µm. [17] Electronic component according to any one of claims 11 to 16, wherein the electrical contact layer (3.1) has a thickness in the range of 100 nm to 1 µm. [18] Electronic component according to any one of claims 11 to 17, wherein the functional layer (3.2) has a thickness in the range of 50 nm to 200 nm.

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