Method for refreshing a memory element, refresh address generator and memory element

Abstract

A method for refreshing a memory element, comprising: - generating a refresh address with a refresh period, - performing each refresh at a weak cell with a first address when the refresh address is a second address, instead of a first strong cell with the second address, and - performing each refresh at a first strong cell or a second strong cell with a third address when the refresh address is the third address, - wherein address information is stored for only one of the first, second, and third addresses, and / or wherein the third address is selected from a pool of addresses with a range defined by at least two least significant bits of one of the first and second addresses.

Description

The invention relates to a method for refreshing a memory element, an associated refresh address generator, and a memory element equipped with such a refresh address generator. More specifically, the invention relates to refresh leveraging, which uses several high-capacity memory cells for one low-capacity memory cell. A volatile memory device, such as dynamic random access memory (DRAM), performs a refresh operation to retain data stored in memory cells. If a memory cell has a retention time shorter than the refresh period of the refresh operation, a row of memory cells containing such a cell must be replaced by a row of redundant cells. As the size of the memory cell decreases, the number of memory cells with retention times shorter than the refresh period increases. Accordingly, the number of rows of redundant cells in a conventional volatile memory device should be increased. However, such a high number of redundant cells increases the size and complexity of the volatile memory device. US patent 2007 / 0033338A1 discloses a memory with address-dependent differentiated refresh rate to accommodate memory rows with low data retention capacity. The invention is based on the technical problem of providing a memory element refresh method, an associated refresh address generator and a memory element equipped therewith, which are able to reduce or avoid difficulties encountered in prior art systems. The invention solves this problem by providing a refresh method with the features of claim 1, a refresh address generator with the features of claim 16, and a memory element with the features of claim 33. Advantageous embodiments of the invention are specified in the dependent claims. The invention enables more frequent refreshes for weak memory cells in order to reduce the number of redundant memory cells. The invention can be implemented with a memory element as claimed, which operates within a memory module, a mobile system or a computer system. Advantageous embodiments of the invention are described below and are shown in the drawings, in which: Fig. 1 is a flowchart of steps for refreshing a volatile memory device with refresh leveraging, Fig. 2 is a graphical representation of an exemplary distribution of a number of memory cell rows with minimum retention times for a volatile memory device, Fig. 3 is a timing diagram of exemplary refreshes of memory cell rows performed according to a refresh method of Fig. 1, Fig. 4 is a block diagram of a volatile memory device for performing refresh operations with refresh leveraging, Fig. 5 is a block diagram of a refresh address generator suitable for use in the volatile memory device of Fig. 4, Fig. 6 is another flowchart of steps for refreshing a volatile memory device with refresh leveraging, Fig.Figure 7 is a timing diagram of exemplary refreshes of a row with weak cells and first and second rows with strong cells, performed according to Figure 6; Figure 8 shows an exemplary memory cell array with a row of weak cells and first and second rows with strong cells; Figure 9 is a block diagram of a refresh address generator suitable for performing the refresh procedure of Figure 6; Figure 10 is a timing diagram of exemplary refreshes performed in a burst mode; Figure 11 is another flowchart of steps for refreshing a volatile memory device with refresh leveraging; Figure 12 shows another exemplary memory cell array with a row of weak cells and first and second rows with strong cells; Figure 13 is a block diagram of a refresh address generator for performing the refresh procedure of Figure 11.Figure 14 is another flowchart of steps for refreshing a volatile memory device using refresh leveraging; Figure 15 is another exemplary memory cell array with one row of weak cells and first and second rows of strong cells; Figure 16 is a block diagram of a refresh generator suitable for performing the refresh procedure of Figure 14; Figure 17 is another exemplary memory cell array with one row of weak cells and first and second rows of strong cells; Figure 18 is a block diagram of another refresh address generator suitable for performing the refresh procedure of Figure 14; Figure 19 is a flowchart of steps for refreshing a volatile memory device depending on a flag of strong cells; Figure 20 is a timing diagram of exemplary refreshes of one row of weak cells and first and second rows of strong cells, as shown in Figure 14.Fig. 19 is carried out, Fig. 21 is a block diagram of a refresh address generator suitable for performing the refresh procedure of Fig. 19, Fig. 22 shows another exemplary memory cell array with one row of weak cells and first and second rows of strong cells, Fig. 23 is a block diagram of another refresh address generator suitable for performing the refresh procedure of Fig. 19, Fig. 24 is a flowchart of steps for refreshing a volatile memory device according to a selected memory bank, Fig. 25 is a block diagram of a refresh address generator suitable for performing the refresh procedure of Fig. 24, Fig. 26 is a block diagram of another refresh address generator suitable for performing the refresh procedure of Fig. 24, Fig.Figure 27 is a flowchart of steps for refreshing a volatile memory device using refresh leveraging, employing a plurality of strong cell rows; Figure 28 is a timing diagram of exemplary refreshes of one weak cell row and several first and second strong cell rows performed according to the refresh procedure of Figure 27; Figure 29 shows another exemplary memory cell array with one weak cell row and several first and second strong cell rows; Figure 30 is a block diagram of a refresh address generator suitable for performing the refresh procedure of Figure 27; Figure 31 is a timing diagram of exemplary refreshes of one weak cell row, several strong first cell rows, and one strong second cell row performed according to the refresh procedure of Figure 27.Figure 32 is a timing diagram showing exemplary refreshes performed in a burst mode for each quarter of rows of a memory cell array; Figure 33 is a block diagram of a refresh address generator suitable for use in the volatile memory device of Figure 4 with multiple comparators; Figure 34 is a block diagram of another exemplary refresh address generator with multiple comparators; Figure 35 is a block diagram of another exemplary refresh address generator with multiple comparators; Figure 36 is a block diagram of another exemplary refresh address generator with multiple comparators; Figure 37 is a block diagram of another exemplary refresh address generator with multiple comparators.Figure 38 is a block diagram of a memory module comprising a memory element with refresh leveraging implemented according to the invention, Figure 39 is a block diagram of a mobile system comprising a memory element with refresh leveraging implemented according to the invention, and Figure 40 is a block diagram of a computer system comprising a memory element with refresh leveraging implemented according to the invention. The figures referenced herein are drawn for clarity of illustration and are not necessarily drawn to scale. Elements with the same reference numerals throughout the figures refer to elements with identical or similar structure and / or function, unless otherwise indicated. Exemplary embodiments of the invention are described in more detail below with reference to the accompanying figures. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. Fig. 1 illustrates steps for refreshing a volatile memory device using refresh leveraging according to an exemplary embodiment of the invention. Referring to Fig. 1, a refresh operation is initiated (S110) when a volatile memory device is turned on. For example, the refresh operation is initiated after completion of a turn-on sequence or after completion of a turn-off mode. In one exemplary embodiment, the refresh operation is an auto-refresh operation that, in response to a periodic refresh instruction (REF), generates a refresh row address to refresh a memory cell row containing that refresh row address. In another exemplary embodiment, the refresh operation is a self-refresh operation for periodically refreshing memory cell rows with a built-in clock in a self-refresh mode of the volatile memory device in response to a self-refresh entry instruction (SRE). In yet another exemplary embodiment, the refresh operation serves a distributed refresh scheme, wherein the refresh cycles are distributed such that they are clocked at predetermined periodic refresh intervals (tREFI).In another exemplary embodiment, the refresh operation serves a burst refresh scheme, whereby a series of refresh cycles are performed sequentially. Upon initiation of the refresh operation, at least one row of weak cells is refreshed with a first period shorter than the refresh period (S130), and at least two rows of strong cells associated with the row of weak cells are refreshed with a second period longer than the refresh period (S170). The row of weak cells is a row of memory cells that includes at least one memory cell with a first retention time shorter than the refresh period. Each row of strong cells is a row of memory cells with retention times longer than the refresh period. The refresh period is defined as a standard value for the volatile memory device. For example, the refresh period is 32 ms, 64 ms, etc. According to one aspect of the invention, the first retention period is shorter than the refresh period and longer than or equal to half the refresh period. Furthermore, the second retention period is longer than or equal to twice the refresh period. For example, the first period for refreshing each row of weak cells is half the refresh period, and the second period for refreshing each row of strong cells is twice the refresh period. Each row of weak cells is related to at least two rows of strong cells and is refreshed during one refresh period instead of at least one of the associated rows of strong cells. Refreshing a row of weak cells instead of a row of strong cells is also referred to herein as "refresh leveraging." In an exemplary embodiment of the invention, a row of weak cells corresponds to a first and second row of strong cells, and the row of weak cells is refreshed instead of the first row of strong cells each time a refresh row address for the first row of strong cells is generated by a refresh counter. Furthermore, the first and second rows of strong cells are refreshed alternately each time a refresh row address for the second row of strong cells is generated by the refresh counter. Accordingly, the row with weak cells is refreshed when the refresh row address for the first row with strong cells is generated, and also when the refresh row address for the row with weak cells is generated. Thus, the row with weak cells is refreshed with the first period, which is half the refresh period. Furthermore, each of the first and second rows with strong cells is refreshed with the second period, which is twice the refresh period. In an exemplary embodiment of the invention, the row with weak cells is refreshed in odd-numbered refresh periods instead of the first row with strong cells, and in even-numbered refresh periods instead of the second row with strong cells. Accordingly, the row with weak cells is refreshed twice per refresh period, and each of the first and second rows with strong cells is refreshed once every two refresh periods. Memory cell rows other than the weak cell row and the first and second strong cell rows are refreshed at the refresh period (S150). That is, normal memory cell rows are refreshed at the refresh period defined in the volatile memory device standard. The invention is described for rows of memory cells, each of which is coupled to a word line. However, the invention can be applied to any group of memory cells comprising a weak memory cell with a retention time shorter than the refresh period and a first and second group of memory cells with retention times longer than the refresh period. For example, the invention can be applied to a weak memory cell with a retention time shorter than the refresh period and a first and second strong memory cell with retention times longer than the refresh period. As described above, in each refresh period, each row of weak cells is refreshed instead of a row of strong cells, such that the total number of refreshes performed per refresh period does not increase. Accordingly, the refresh period of the weak cell row decreases without an increase in auto-refresh current or refresh power consumption. Furthermore, the weak cell row does not need to be replaced by a row of redundant cells, since the refresh period of the weak cell row decreases below its retention time. Consequently, the size of a redundant cell array and a redundant volatile memory circuit can be reduced. Fig. 2 shows a graphical representation of the distribution of a number of memory cell rows with minimum retention times of memory cells in a memory cell row. Fig. 3 shows a timing diagram of exemplary refreshes performed according to a refresh procedure from Fig. 1. Referring to Fig. 2 and Fig. 3, a memory cell row with a minimum retention time shorter than a refresh period RP defined in the standard of the volatile memory device is a row 201 with weak cells. Here, the minimum retention time of a memory cell row is the shortest retention time of the respective retention times of memory cells in the memory cell row. A refresh 210 for the row 201 with weak cells is performed with a first period P1 that is shorter than or equal to the minimum retention time of the row with weak cells.Since row 201 is refreshed with weak cells with the first period P1, which is shorter than its minimum retention time, the memory cell row does not need to be replaced by a row of redundancy cells. At least two rows, 202 and 203, containing strong cells are selected for each row, 201, containing weak cells. Memory cell rows with minimum retention times longer than or equal to a second period, P2, are selected as the strong cells, 202 and 203. The strong cells in rows 202 and 203 retain data even if they are refreshed with a second period, P2, that is longer than the refresh period, RP. Thus, some refreshes, 230, are performed on the strong cells in rows 202 and 203, while any remaining refreshes intended for the strong cells in rows 202 and 203 are instead performed on the weak cells in row 201. As shown in Fig. 2, most memory cell rows exhibit minimum retention times that are longer than or equal to the second period P2 (e.g., approximately twice the refresh period RP). Accordingly, if row 201 with weak cells is found during a test procedure as part of a manufacturing process, rows 202 and 203 with strong cells, which are associated with row 201 with weak cells, will be selected in one of numerous ways. Apart from rows 202 and 203 containing strong cells, memory cell rows with minimum retention times longer than or equal to the refresh period RP are refreshed using the refresh period RP. A refresh counter generates a refresh row address for each memory cell row using the refresh period RP, ensuring that a refresh 220 is performed for such a memory cell row using the refresh period RP. In one exemplary embodiment of the invention, a memory cell row with a minimum retention time shorter than the first period P1 is replaced by a row of redundant cells. In another exemplary embodiment of the present invention, the volatile memory element reduces the refresh period for such a memory cell row by relating the memory cell row to at least three rows of strong cells, as described below with reference to Figures 27, 28, 29, 30, 31 to 32. Accordingly, such a memory cell row retains data even if the memory cell row is not replaced by a row of redundant cells. Fig. 4 shows a volatile memory element 300 for performing refresh leveraging according to an exemplary embodiment of the invention. The volatile memory element 300 includes a control logic 310, an address register 320, a bank control logic 330, a row address multiplexer 340, a column address buffer 350, row decoders 360a to 360d, column decoders 370a to 370d, memory cell arrays 380a to 380d, sampling amplifiers 385a to 385d, an input / output gate control circuit 390, a data input / output buffer 395, and a refresh address generator 400.The volatile memory element 300 can be a dynamic random access memory (DRAM), such as a synchronous dynamic dual data rate random access memory (DDR-SDRAM), a synchronous dynamic dual data rate low-performance random access memory (LPDDR-SDRAM), a graphical synchronous dynamic dual data rate random access memory (GDDR-SDRAM), a dynamic Rambus random access memory (RDRAM), or other volatile memory elements with a refresh operation. The memory cell array includes a first, second, third, and fourth bank array 380a, 380b, 380c, and 380d, respectively. The row decoder includes a first, second, third, and fourth bank row decoder 360a, 360b, 360c, and 360d, which are coupled to the first, second, third, and fourth bank arrays 380a, 380b, 380c, and 380d, respectively. The column decoder includes a first, second, third, and fourth bank column decoder 370a, 370b, 370c, and 370d, which are coupled to the first, second, third, and fourth bank arrays 380a, 380b, 380c, and 380d, respectively. The sampling amplifier includes a first, second, third, and fourth bank sampling amplifier 385a, 385b, 385c, and 385d, which are coupled to the first, second, third, and fourth bank arrays 380a, 380b, 380c, and 380d, respectively. The four bank arrays 380a, 380b, 380c, and 380d, the four bank row decoders 360a, 360b, 360c, and 360d, the four bank column decoders 370a, 370b, 370c, and 370d, and the four bank sampling amplifiers 385a, 385b, 385c, and 385d can form a first, second, third, and fourth bank, respectively. Although the volatile memory element 300 in Fig. 4 is shown to contain four banks, the invention can be carried out with the volatile memory element 300 containing any number of banks. Address register 320 receives an address ADDR, containing a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR, from a memory control unit (not shown). Address register 320 transfers the received bank address BANK_ADDR to the bank control logic 330, the received row address ROW_ADDR to the row address multiplexer 340, and the received column address COL_ADDR to the column address buffer 350. The bank control logic 330 generates bank control signals in response to the bank address BANK_ADDR. One of the bank line decoders 360a, 360b, 360c and 360d corresponding to the bank address BANK_ADDR is activated in response to the bank control signals, and one of the bank column decoders 370a, 370b, 370c and 370d corresponding to the bank address BANK_ADDR is activated in response to the bank control signals. The line address multiplexer 340 receives the line address ROW_ADDR from the address register 320 and a final refresh line address CREF_ADDR from the refresh address generator 400. The line address multiplexer 340 selectively outputs either the line address ROW_ADDR or the final refresh line address CREF_ADDR for use on the bank line decoders 360a, 360b, 360c and 360d. The activated bank line decoders 360a, 360b, 360c, and 360d decode the line address from the line address multiplexer 340 and activate a word line corresponding to the line address. For example, the activated bank line decoder applies a word line driver voltage to the word line corresponding to the line address. The column address buffer 350 receives the column address COL_ADDR from the address register 320 and temporarily stores it. In a burst mode according to an exemplary embodiment of the present invention, the column address buffer 350 generates incremented column addresses from the received column address COL_ADDR. The column address buffer 350 applies such a column address to the bank column decoders 370a, 370b, 370c, and 370d. An activated bank column decoder 370a, 370b, 370c, and 370d decodes the column address COL_ADDR from the column address buffer 350 in order to control the input / output gate control circuit 390 to output data corresponding to the column address COL_ADDR. The input / output gate control circuit 390 includes a circuit structure for gate control of input / output data, an input data mask logic, read data buffers for storing data from the bank fields 380a, 380b, 380c and 380d, and write drivers for writing data to the bank fields 380a, 380b, 380c and 380d. Data DQ to be read from one of the bank fields 380a, 380b, 380c and 380d is sampled by means of a respective sampling amplifier coupled to that bank field and stored in the read data buffers, and such data DQ is supplied to the memory control unit via the data input / output buffer 395. Data DQ to be written to one of the bank fields 380a, 380b, 380c and 380d are supplied to the data input / output buffer 395 by the memory control unit, and such data DQ are written to that bank field via the write drivers. The control logic 310 controls the operation of the volatile memory element 300 by generating control signals to perform a read or write operation. The control logic 310 includes an instruction decoder 311, which decodes a CMD instruction received from the memory control unit, and a mode register 312, which defines an operating mode of the volatile memory element 300. For example, the instruction decoder 311 generates the control signals corresponding to the CMD instruction by decoding a write enable signal ( / WE), a row address sample signal ( / RAS), a column address sample signal ( / CAS), and a chip select signal ( / CS). The instruction decoder 311 also receives a clock signal (CLK) and a clock enable signal ( / CKE) to operate the volatile memory element 300 synchronously. In an exemplary embodiment of the invention, the control logic 310 controls the refresh address generator 400 to perform an auto-refresh operation in response to a refresh instruction (REF) or to perform a self-refresh operation in response to a self-refresh entry instruction (SRE). The refresh address generator 400 generates a refresh row address and compares it to a row address of strong cells. If the refresh row address matches the row address of strong cells, it changes it to a row address of weak cells. Accordingly, the row address of weak cells, instead of the row address of strong cells, is applied to the bank row decoders 360a, 360b, 360c, and 360d, such that a row of weak cells corresponding to the row address of weak cells is refreshed in bank fields 380a, 380b, 380c, and 380d, instead of a row of strong cells corresponding to the row address of strong cells. Thus, the row with weak cells is refreshed when the row address of strong cells is generated, and also when the row address of weak cells is generated. That is, the row with weak cells is refreshed twice per refresh period. In an alternative embodiment of the invention, the row address of weak cells is only applied to a selected bank when the row address of strong cells is generated, while the row address of strong cells is applied to other banks. In this case, the row with weak cells is only refreshed in the selected bank instead of the row with strong cells, and the row with strong cells is refreshed in the other banks. In this way, the volatile memory element 300 reduces the refresh period of the row with weak cells without increasing the refresh current or refresh power consumption. Furthermore, the dimensions of a redundant cell array and a redundant circuit within the volatile memory element 300 can be reduced. Fig. 5 shows the refresh address generator 400 in the volatile memory element 300 of Fig. 4 according to an exemplary embodiment of the invention. Referring to Fig. 5, the refresh address generator 400 in this example includes an address storage unit 410, a refresh counter 430, a comparison unit 450, and an address change unit 470. The address storage unit 410 stores address information ADDR_INFO for at least one row of weak cells. The amount of address information ADDR_INFO stored in the address storage unit 410 corresponds to the number of rows of weak cells in the memory cell array. For each row of weak cells, the address storage unit 410 stores address information ADDR_INFO for at least one row address of weak cells for that row and at least two row addresses of strong cells that are related to the row address of weak cells. In an exemplary embodiment of the invention, the address storage unit 410 stores address information ADDR_INFO for only one of the row addresses of weak cells and one of the row addresses of strong cells.The other row address of weak cells and the row addresses of strong cells can be determined from predefined bit relationships between the row address of weak cells and the row addresses of strong cells. In an exemplary embodiment of the invention, the address information ADDR_INFO is stored in the address storage unit 410 before the volatile memory element is packed. Alternatively, the address information ADDR_INFO is stored in the address storage unit 410 after the volatile memory element has been packed. In an exemplary embodiment of the invention, the address storage unit 410 can be implemented with an electrically programmable fuse memory, a laser-programmable fuse memory, an anti-fuse memory, a one-time programmable memory, flash memory, or other types of non-volatile memory. In a further embodiment of the invention, the address information ADDR_INFO includes the result of a predefined operation (e.g., an XOR operation) performed on the row address of weak cells, the first row address of strong cells, and / or the second row address of strong cells. For example, the predefined operation is performed by means of a test element while rows with weak cells are being searched for during a test procedure, and the result of the predefined operation is written to the address memory unit 410 by means of the test element. The refresh counter 430 counts to generate an initial refresh line address REF_ADDR, which has N bits, where N is an integer greater than 1. For example, the refresh counter 430 increments the refresh line address REF_ADDR and initializes the refresh line address REF_ADDR to a minimum line address (e.g., "0") when the refresh line address REF_ADDR exceeds a maximum line address. The refresh counter 430 further generates a strong cell flag STR_FLAG to control the refreshes of rows containing strong cells. In an exemplary embodiment of the invention, the refresh counter 430 inverts the strong cell flag STR_FLAG each time the refresh row address REF_ADDR is initialized. For example, the refresh counter 430 is implemented as an N+M bit counter, where M is an integer greater than 0. In this case, the lower N bits generated by the counter 430 are used as the initial refresh row address REF_ADDR, and the upper M bits from the counter 430 are used as the strong cell flag STR_FLAG. In an exemplary embodiment of the invention, the refresh counter 430 is implemented with an N+1 bit counter. In this case, the lower N bits of the N+1 bit counter 430 are used as the initial refresh row address REF_ADDR, and the most significant bit (MSB) of the counter 430 is used as the strong cell flag STR_FLAG. The comparator unit 450 compares the initial refresh row address REF_ADDR from the refresh counter 430 with the address information ADDR_INFO from the address storage unit 410 to generate a match signal MATCH from the comparison and / or the flag STR_FLAG of strong cells. For example, the comparator unit 450 generates an initial match signal from comparing the refresh row address REF_ADDR with the first row address of strong cells. The comparator 450 also generates a second match signal by comparing the refresh row address REF_ADDR with the second row address of strong cells and the flag STR_FLAG of strong cells. For example, if the refresh row address REF_ADDR matches the second row address of strong cells and the flag STR_FLAG of strong cells is at a high logic level, the comparator 450 generates the second match signal at a high logic level. The address change unit 470 modifies the initial refresh row address REF_ADDR in response to the MATCH signal from the comparator unit 450 to generate a final refresh row address CREF_ADDR. For example, the address change unit 470 modifies the initial refresh row address REF_ADDR in response to the first match signal to the row address of weak cells, or it modifies the initial refresh row address REF_ADDR in response to the second match signal to the first row address of strong cells. In an exemplary embodiment of the invention, the address change unit 470 changes the initial refresh line address REF_ADDR based on the address information ADDR_INFO from the address storage unit 410. Alternatively, the address change unit 470 changes the initial refresh line address REF_ADDR using logic gates that perform a predefined operation. The final refresh line address CREF_ADDR is fed to the bank line decoders 360a, 360b, 360c, and 360d via the line address multiplexer 340 shown in Fig. 4. Accordingly, a memory cell line corresponding to the final refresh line address CREF_ADDR is refreshed in the bank fields 380a, 380b, 380c, and 380d. In this way, the refresh address generator 400 allows a row with weak cells to be refreshed instead of a row with strong cells by supplying the row address of weak cells when the refresh counter 430 generates one of the first and second row addresses of strong cells. Accordingly, the refresh period for the row with weak cells is reduced without increasing the refresh current or refresh power consumption. Figure 6 illustrates steps for a method of refreshing a volatile memory device using refresh leveraging according to a further exemplary embodiment of the invention. In Figure 6, when a memory cell row is identified as a row with weak cells, a first row address STR_ADDR_1 of strong cells is determined by inverting a most significant bit (MSB) of a row address WEAK_ADDR of weak cells for the row with weak cells. Furthermore, a second row address STR_ADDR_2 of strong cells is determined by inverting a least significant bit (LSB) of the first row address STR_ADDR_1 of strong cells. Referring to Fig. 6, when a refresh operation is initiated, a refresh counter (S510) is initialized, for example to "0". In that case, the STR_FLAG flag of strong cells is initialized to a low logic level. According to an exemplary embodiment of the invention, the refresh row address REF_ADDR has N bits, where N is an integer greater than 1. In that case, the upper N-1 bits of the refresh row address REF_ADDR are compared with the upper N-1 bits of the first row address STR_ADDR_1 of strong cells (S520). If the upper N-1 bits of the refresh row address REF_ADDR do not match the upper N-1 bits of the first row address STR_ADDR_1 of strong cells (S520: NO), a memory cell row corresponding to the initial refresh row address REF_ADDR is refreshed (S540), and thereafter the refresh counter increments the refresh row address REF_ADDR by 1 (S570). If the upper N-1 bits of the refresh line address REF_ADDR match the upper N-1 bits of the first line address STR_ADDR_1 of strong cells (S520: YES), an LSB of the refresh line address REF_ADDR is compared with an LSB of the first line address STR_ADDR_1 of strong cells (S525). Such comparisons (S520) and (S525) can be performed essentially simultaneously in an exemplary embodiment of the invention. If the N bits of the initial refresh row address REF_ADDR match the N bits of the first row address STR_ADDR_1 of strong cells (S520: YES, S525: YES), the row address WEAK_ADDR of weak cells is generated as the final refresh row address CREF_ADDR by inverting the MSB of the initial refresh row address REF_ADDR (S550). In that case, the row containing weak cells, which has the row address WEAK_ADDR of weak cells, is refreshed (S555), and then the refresh counter increments the refresh row address REF_ADDR by 1 (S570). If the upper N-1 bits of the refresh row address REF_ADDR match the upper N-1 bits of the first row address STR_ADDR_1 of strong cells (S520: YES), and the LSB of the refresh row address REF_ADDR does not match the LSB of the first row address STR_ADDR_1 of strong cells (S525: NO), then the refresh row address REF_ADDR matches the second row address STR_ADDR_2 of strong cells. In that case, one of the first and second rows of strong cells, which have the first or second row address STR_ADDR_1 or STR_ADDR_2 of strong cells, is selectively refreshed according to the flag STR_FLAG of strong cells. For example, if the refresh row address REF_ADDR matches the second row address STR_ADDR_2 of strong cells (S520: YES, S525: NO), the logic level of the strong cells' flag STR_FLAG is checked (S530). If the strong cells' flag STR_FLAG has a first logic level (e.g., a low logic level) (S530: YES), the second row of strong cells corresponding to the refresh row address REF_ADDR (i.e., the second row address STR_ADDR_2 of strong cells) is refreshed (S540). Afterward, the refresh counter increments the refresh row address REF_ADDR by 1 (S570). After each increment of the refresh row address REF_ADDR (S570), the refresh row address REF_ADDR is compared to a maximum row address MAX_ADDR, which is the maximum value of row addresses for memory cell rows contained in a memory cell array. If the refresh row address REF_ADDR exceeds the maximum row address MAX_ADDR (S580: YES), the refresh row address REF_ADDR is reinitialized, and the STR_FLAG flag of strong cells is inverted (S585), so that the memory cell rows of the memory cell array are refreshed sequentially again. In this way, the STR_FLAG flag of strong cells is inverted at each refresh period RP. If the refresh row address REF_ADDR matches the second row address STR_ADDR_2 of strong cells (S520: YES, S525: NO) and the flag STR_FLAG of strong cells has a second logic level (i.e., a high logic level), the first row address STR_ADDR_1 of strong cells is created by inverting the LSB of the refresh row address REF_ADDR (S560). Accordingly, the first row of strong cells, which has the first row address STR_ADDR_1 of strong cells, is refreshed (S565). Thereafter, the refresh row address REF_ADDR is incremented by 1 each time one of the memory cell rows is refreshed (S570). These refresh operation steps are repeated until the volatile memory device is switched off. As shown in Fig. 2, most memory cell rows exhibit minimum retention times that are longer than or equal to twice the refresh period RP. Thus, if a memory cell row is identified as having weak cells, a first memory cell row with a row address determined by inverting the MSB of a row address from the weak cell row will very likely have a minimum retention time that is longer than or equal to twice the refresh period RP, so that this first memory cell row can be used as having strong cells. Furthermore, a second memory cell row with a row address determined by inverting the LSB of the first memory cell row's row address will most likely have a minimum retention time that is longer than or equal to approximately twice the refresh period RP, allowing this second memory cell row to be used as another row of strong cells. In this way, the row of weak cells is refreshed instead of the first row of strong cells when the first row address STR_ADDR_1 is generated by strong cells. Consequently, the refresh period of the row of weak cells is reduced without increasing the refresh current or power consumption. Fig. 7 shows a timing diagram of exemplary refreshes of a row with weak cells, a first row with strong cells, and a second row with strong cells, performed according to the refresh procedure of Fig. 6. Referring to Fig. 7, the row with weak cells is refreshed with a first period (RP / 2), which is half a refresh period RP. For example, a refresh 510 is performed for the row with weak cells when the row address for the row with weak cells is generated, and another refresh 515 for the row with weak cells is performed instead of the one for the first row with strong cells when the row address for the first row with strong cells is generated. Thus, the row with weak cells is refreshed twice in each refresh period RP. Each of the first and second rows of strong cells is refreshed with a second period (2RP) that is twice the refresh period RP. The first and second rows of strong cells are refreshed alternately in each refresh period RP. For example, a refresh 530 is performed for the second row of strong cells in every odd-numbered refresh period, and a refresh 525 is performed for the first row of strong cells in every even-numbered refresh period, so that each of the first and second rows of strong cells is refreshed once every two refresh periods RP. Fig. 8 shows an exemplary memory cell array according to the invention with one row of weak cells and a first and second row of strong cells. Fig. 8 shows a bank 600a of the memory cell array. In Fig. 8, the MSB of a row address defines an upper and a lower part of the bank 600a, and the LSB of the row address defines two adjacent memory cell rows. Referring to Fig. 8, after the line address WEAK_ADDR of weak cells for line 610a containing weak cells has been determined by examining the memory cell array, the first line address STR_ADDR_1 of strong cells is determined by inverting the MSB of the line address WEAK_ADDR of weak cells. Thus, memory cell line 620a, corresponding to the first line address STR_ADDR_1 of strong cells, is designated as the first line containing strong cells. The second line address STR_ADDR_2 of strong cells is determined by inverting the LSB of the first line address STR_AADR_1 of strong cells. Thus, memory cell line 630a, corresponding to the second line address STR_ADDR_2 of strong cells, is designated as the second line containing strong cells. As shown in Fig. 2, most memory cell rows exhibit minimum retention times that are longer than or equal to twice the refresh period RP. Although the first and second row addresses STR_ADDR_1 and STR_ADDR_2 are determined by strong cells without checking the memory cell rows, accordingly, memory cell rows 620a and 630a will very likely exhibit minimum retention times that are longer than or equal to twice the refresh period RP. Fig. 9 shows a refresh address generator 400a for performing the refresh method of Fig. 6 according to a further exemplary embodiment of the invention. The refresh address generator 400a in this example includes an address storage unit 410a, a refresh counter 430a, a comparison unit 450a, and an address modification unit 470a. The address storage unit 410a includes a first memory area 411a that stores a first row address STR_ADDR_1 of strong cells. Alternatively, the address storage unit 410a stores a row address WEAK_ADDR of weak cells or a second row address STR_ADDR_2 of strong cells instead of the first row address STR_ADDR_1 of strong cells. The address storage unit 410a supplies the comparator unit 450a with N bits SA11, SA12, and SA1N of the first row address STR_ADDR_1 of strong cells. In an exemplary embodiment of the invention, the address storage unit 410a is implemented with an electrically programmable fuse memory, a laser-programmable fuse memory, an anti-fuse memory, a one-time programmable memory, flash memory, or other types of non-volatile memory. Although Fig. 9 shows the address storage unit 410a storing a first row address STR_ADDR_1 of strong cells that corresponds to a row address WEAK_ADDR of weak cells, the address storage unit 410a can store more first row addresses of strong cells that correspond to more row addresses of weak cells. The refresh counter 430a generates an initial refresh line address REF_ADDR and a strong cell flag STR_FLAG by counting. In an exemplary embodiment of the present invention, the refresh counter 430a is an N+1 bit counter. In this case, the N+1th bit (i.e., the MSB) of the counter 430a is a strong cell flag STR_FLAG, and the lower N bits of the counter 430a form the initial refresh line address REF_ADDR. The comparator unit 450a compares the refresh line address REF_ADDR from the refresh counter 430a and the first line address STR_ADDR_1 of strong cells from the address storage unit 410a to generate a first match signal MATCH1 from this comparison. The comparator unit 450a generates a second match signal MATCH2 from a comparison of the refresh line address REF_ADDR with the second line address STR_ADDR_2 of strong cells and from the flag STR_FLAG of strong cells. The first match signal, MATCH1, is generated at a high logic level when the refresh row address REF_ADDR matches the first row address STR_ADDR_1 of strong cells. The second match signal, MATCH2, is generated at a high logic level when the refresh row address REF_ADDR matches the second row address STR_ADDR_2 of strong cells and the flag STR_FLAG of strong cells is at a high logic level. The comparator unit 450a contains a plurality of comparators 451a, 452a, and 453a and a plurality of logic gates 461a, 462a, 463a, and 464a. Each comparator compares a corresponding bit of the refresh row address REF_ADDR with a corresponding bit of the first row address STR_ADDR_1 of strong cells. For example, a first comparator 451a compares a first bit RA1 (i.e., the LSB) of the refresh row address REF_ADDR with the first bit SA11 (i.e., the LSB) of the first row address STR_ADDR_1 of strong cells. A second comparator 452a compares a second bit RA2 of the refresh row address REF_ADDR with the second bit SA12 of the first row address STR_ADDR_1 of strong cells. An nth comparator 453a compares an Nth bit RAN (i.e. the MSB) of the refresh row address REF_ADDR with the Nth bit SA1N (i.e. the MSB) of the first row address STR_ADDR_1 of strong cells. The first AND gate 461a generates the first match signal MATCH1 by performing an AND operation on the output signals of the first to Nth comparators 451a, 452a, and 453a. If the N bits RA1, RA2, and RAN of the refresh line address REF_ADDR each match the N bits SA11, SA12, and SA1N of the first line address STR_ADDR_1 of strong cells, the first AND gate 461a generates the first match signal MATCH1 with a high logic level. Inverter 462a inverts an output signal of the first comparator 451a. The second AND gate 463a performs an AND operation on an output signal of inverter 462a and the output signals of the second to Nth comparators 452a and 453a. If the first bit RA1 of the refresh line address REF_ADDR does not match the first bit SA11 of the first line address STR_ADDR_1 of strong cells, and the second to Nth bits RA2 and RAN of the refresh line address REF_ADDR match the second to Nth bits SA12 and SA1N of the first line address STR_ADDR_1 of strong cells, the second AND gate 463a produces an output signal with a high logic level. This means that if the refresh line address REF_ADDR matches a line address where only the LSB differs from the first line address STR_ADDR_1 of strong cells (i.e., if the refresh line address REF_ADDR matches the second line address STR_ADDR_2 of strong cells), the second AND gate 463a generates the output signal at a high logic level. The third AND gate 464a generates the second match signal MATCH2 by performing an AND operation on the flag STR_FLAG of strong cells and the output signal of the second AND gate 463a. If the refresh line address REF_ADDR matches the second line address STR_ADDR_2 of strong cells and the flag STR_FLAG of strong cells is at a high logic level, the third AND gate 464a generates the second match signal MATCH2 at a high logic level. Fig. 9 shows the comparator unit 450a with a set of comparators 451a, 452a and 453a and logic gates 461a, 462a, 463a and 464a for a row address WEAK_ADDR of weak cells. However, the invention can also be implemented with the comparator unit 450a with multiple sets of comparators and logic gates corresponding to multiple row addresses of weak cells. The address change unit 470a receives the initial refresh line address REF_ADDR from the refresh counter 430a and the first and second match signals MATCH1 and MATCH2 from the comparator unit 450a. If the first and second match signals MATCH1 and MATCH2 each have a low logic level, the address change unit 470a outputs the initial refresh line address REF_ADDR as the final refresh line address CREF_ADDR. If the first match signal MATCH1 is at a high logic level, the address change unit 470a outputs the row address WEAK_ADDR of weak cells as the final refresh row address CREF_ADDR instead of the initial refresh row address REF_ADDR. If the second match signal MATCH2 is at a high logic level, the address change unit 470a outputs the first row address STR_ADDR_1 of strong cells as the final refresh row address CREF_ADDR instead of the initial refresh row address REF_ADDR. The address change unit 470a includes a first inverter 471a and a first multiplexer 472a to generate the first bit CRA1 of the final refresh line address CREF_ADDR from the first bit RA1 of the refresh line address REF_ADDR and the second matching signal MATCH2. The address change unit 470a includes a second inverter 473a and a second multiplexer 474a to generate the Nth bit CRAN of the final refresh line address CREF_ADDR from the Nth bit RAN of the refresh line address REF_ADDR and the first matching signal MATCH1. The second inverter 473a inverts the Nth bit RAN of the refresh line address REF_ADDR. The second multiplexer 474a, in response to the first match signal MATCH1, selectively outputs the Nth bit RAN, or its inversion, as the Nth bit CRAN of the final refresh line address CREF_ADDR. For example, if the first match signal MATCH1 is at a high logic level, the refresh change unit 470a generates the line address WEAK_ADDR from weak cells by inverting the Nth bit RAN (i.e., the MSB) of the initial refresh line address REF_ADDR as the final refresh line address CREF_ADDR. The first inverter 471a inverts the first bit RA1 of the refresh line address REF_ADDR. The first multiplexer 472a, in response to the second match signal MATCH2, selectively outputs the first bit RA1, or its inversion, as the first bit CRA1 of the final refresh line address CREF_ADDR. For example, if the second match signal is at a high logic level, the refresh-modification unit 470a, by inverting the first bit RA1 (i.e., the LSB) of the initial refresh line address REF_ADDR, generates the first line address STR_ADDR_1 of strong cells as the final refresh line address CREF_ADDR. The address change unit 470a further includes a plurality of inverters 481a, 482a, 483a and 484a to generate the second to N-1 bits (CRA2 to CRAN-1) of the final refresh line address CREF_ADDR by delaying the second to N-1 bits (RA2 to RAN-1) of the initial refresh line address REF_ADDR. In this way, the refresh address generator 400a outputs the row address WEAK_ADDR from weak cells when the refresh counter 430 generates the first row address STR_ADDR_1 from strong cells. Furthermore, in each refresh period RP, the refresh address generator 400a alternately outputs one of the first and second row addresses STR_ADDR_1 and STR_ADDR_2 from strong cells when the refresh counter 430a generates the second row address STR_ADDR_2 from strong cells. Thus, a row with weak cells is refreshed instead of the first row with strong cells, thereby reducing the refresh period for the row with weak cells without increasing the refresh current and refresh power consumption. Furthermore, the first and second row addresses of strong cells STR_ADDR_1 and STR_ADDR_2 are determined from predefined bit relationships to the row address WEAK_ADDR of weak cells. For example, the first row address STR_ADDR_1 of strong cells is determined by inverting the MSB of the row address WEAK_ADDR of weak cells, and the second row address STR_ADDR_2 of strong cells is determined by inverting the LSB of the first row address STR_ADDR_1 of strong cells. Thus, the refresh address generator 400a can be reduced in size and complexity according to this aspect of the invention. Fig. 10 shows a timing diagram of exemplary refreshes according to an exemplary embodiment of the invention, performed in a burst refresh mode. For example, a first half of the memory cell rows in a memory cell array are refreshed sequentially in half a refresh period RP, and a second half of the memory cell rows are refreshed sequentially in half a refresh period RP after the first half of the memory cell rows have been refreshed. In this case, a first refresh 510 for a row with weak cells is performed when the first half of the memory cell rows have been refreshed, and a second refresh 515 for the row with weak cells is performed when the second half of the memory cell rows have been refreshed.Accordingly, even in a burst refresh mode, the row with weak cells is refreshed with a period (RP / 2) which is half the refresh period RP. Figure 11 illustrates steps for refreshing a volatile memory device using refresh leveraging according to a further exemplary embodiment of the invention. In Figure 11, a first row address STR_ADDR_1 of strong cells is set by inverting a most significant bit (MSB) of a row address WEAK_ADDR of weak cells. Furthermore, a second row address STR_ADDR_2 of strong cells is set by inverting an M-th bit of the first row address of strong cells STR_ADDR_1, where M is an integer greater than 0 and less than N. The refresh method of Fig. 11 is essentially similar to the refresh method of Fig. 6, except that the second row address STR_ADDR_2 of strong cells is set by inverting the M-th bit of the first row address STR_ADDR_1 of strong cells. Referring to Fig. 11, when a refresh operation is initiated, the refresh counter in an exemplary embodiment of the invention is initialized to “0” (S710), and a flag STR_FLAG of strong cells is also initialized to a low logic level. All bits except the M-th bits of the refresh line address REF_ADDR and the first line address STR_ADDR_1 of strong cells are compared (S720). Additionally, the M-th bits of the refresh line address REF_ADDR and the first line address STR_ADDR_1 of strong cells are compared (S725). In an exemplary embodiment of the invention, such comparisons (S720) and (S725) can be performed essentially simultaneously. If not all bits except the M-th bits of the refresh row address REF_ADDR and the first row address STR_ADDR_1 of strong cells match (S720: NO), a memory cell row corresponding to the initial refresh row address REF_ADDR is refreshed (S740). If all bits of the refresh row address REF_ADDR and the first row address STR_ADDR_1 of strong cells match (S720: YES), the row address WEAK_ADDR of weak cells is generated by inverting the MSB of the initial refresh row address REF_ADDR as the final refresh row address (S755). If the refresh row address REF_ADDR matches the second row address STR_ADDR_2 of strong cells (S720: YES and S725: NO), one of the first and second rows of strong cells corresponding to the first and second row addresses STR_ADDR_1 and STR_ADDR_2 of strong cells is selectively refreshed according to the strong cell flag STR_FLAG. If the strong cell flag STR_FLAG is at a low level (S730: YES), the second row of strong cells corresponding to the initial refresh row address REF_ADDR (i.e., the second row address STR_ADDR_2 of strong cells) is refreshed (S740). The refresh row address REF_ADDR is incremented by 1 each time a memory cell row is refreshed (S770). If the refresh row address REF_ADDR exceeds the maximum row address MAX_ADDR (S780: YES), the refresh row address REF_ADDR is reinitialized, and the STR_FLAG flag of strong cells is inverted (S785). That is, the STR_FLAG flag of strong cells is inverted in each refresh period RP. If the refresh row address REF_ADDR matches the second row address STR_ADDR_2 of strong cells (S720: YES, S725: NO) and the flag STR_FLAG of strong cells is at a high logic level (S730: NO), the first row address STR_ADDR_1 of strong cells is generated as the final refresh row address CREF_ADDR by inverting the M-th bit of the initial refresh row address REF_ADDR (S760). In this case, the first row containing strong cells, which has the first row address STR_ADDR_1 of strong cells, is refreshed (S765). In this way, when the first row address STR_ADDR_1 of strong cells is generated by the refresh counter, the row with weak cells is refreshed instead of the first row with strong cells. Accordingly, the refresh period for the row with weak cells is reduced without increasing the refresh current or refresh power consumption. Figure 12 shows an example of a first and second row of strong cells, selected according to the steps of Figure 11 for a row of weak cells in bank field 600b of a memory cell array. Referring to Figure 12, a row address WEAK_ADDR of weak cells for a row 610b with weak cells is determined by examining the memory cell array. A first row address STR_ADDR_1 of strong cells from a first row 620b with strong memory cells is set for the row 610b with weak cells by inverting one MSB of the row address WEAK_ADDR of weak cells. A second row address STR_ADDR_2 of strong cells from a second memory cell row 630b is set for the row 610b with weak cells by inverting one M-th bit of the first row address STR_ADDR_1 of strong cells. Fig. 13 shows a refresh address generator 400b for performing the refresh method of Fig. 11 according to a further exemplary embodiment of the invention. Referring to Fig. 13, the refresh address generator 400b includes an address storage unit 410b, a refresh counter 430b, a comparison unit 450b, and an address change unit 470b. The refresh address generator 400b of Fig. 13 is essentially similar to the refresh address generator 400a of Fig. 9, except that the first row address STR_ADDR_1 of strong cells in Fig. 13 is generated by inverting an M-th bit of the second row address STR_ADDR_2 of strong cells. The address storage unit 410b includes a first memory area 411b for storing the first row address STR_ADDR_1 of strong cells. The refresh counter 430b generates a refresh row address REF_ADDR and a flag STR_FLAG of strong cells by counting. The address storage unit 410b of Fig. 13 stores a first row address STR_ADDR_1 of strong cells, which corresponds to a row address WEAK_ADDR of weak cells. However, the invention can also be implemented such that the address storage unit 410b stores several first row addresses of strong cells, which correspond to several row addresses of weak cells. The comparator unit 450b generates a first match signal MATCH1 by comparing the refresh row address REF_ADDR with the first row address STR_ADDR_1 of strong cells. The comparator unit 450b also generates a second match signal MATCH2 based on the flag STR_FLAG of strong cells and by comparing the refresh row address REF_ADDR with the second row address STR_ADDR_2 of strong cells. The comparator unit 450b includes a plurality of comparators 451b, 452b, and 453b, as well as a plurality of logic gates 461b, 462b, 463b, and 464b. Fig. 13 shows the comparator unit 450b with a set of comparators 451b, 452b, and 453b and logic gates 461b, 462b, 463b, and 464b for comparing the refresh line address REF_ADDR with the first and second line addresses STR_ADDR_1 and STR_ADDR_2 of strong cells. However, the invention can also be implemented if the comparator unit 450b includes several sets of comparators and logic gates for comparing the refresh line address REF_ADDR with the respective first and second line addresses of strong cells for multiple line addresses of weak cells. If the first matching signal MATCH1 is at a high logic level, the address change unit 470b outputs the row address WEAK_ADDR of weak cells as the final refresh row address CREF_ADDR by inverting an Nth bit RAN of the initial refresh row address REF_ADDR. If the second matching signal MATCH2 is at a high logic level, the address change unit 470b outputs the first row address STR_ADDR_1 of strong cells as the final refresh row address CREF_ADDR by inverting an Mth bit RAM of the initial refresh row address REF_ADDR. The address change unit 470b includes a first inverter 471b and a first multiplexer 472b to change the M-th bit RAM of the initial refresh line address REF_ADDR. The address change unit 470b also includes a second inverter 473b and a second multiplexer 474b to change the N-th bit RAN of the initial refresh line address REF_ADDR. The address change unit 470b further includes a plurality of inverters 481b, 482b, 483b, and 484b to output the remaining bits CRA1 and CRAN-1 of the final refresh line address CREF_ADDR by delaying the corresponding bits RA1 and RAN-1 of the initial refresh line address REF_ADDR. In this way, the refresh address generator 400b outputs the row address WEAK_ADDR from weak cells when the refresh counter 430b generates the first row address STR_ADDR_1 from strong cells. Furthermore, during each refresh period RP, the refresh address generator 400b alternately outputs the first and second row addresses STR_ADDR_1 from strong cells when the refresh counter 430b generates the second row address STR_ADDR_2 from strong cells. Therefore, during each refresh period RP, the row with weak cells is refreshed instead of the first row with strong cells, thus reducing the refresh period for the row with weak cells without increasing the refresh current or power consumption. Fig. 14 illustrates steps for refreshing a volatile memory device using refresh leveraging according to a further exemplary embodiment of the invention. In Fig. 14, a row address WEAK_ADDR of weak cells is set according to a minimum retention time of a corresponding memory cell row, and any two other row addresses of the memory cell array are set as a first and second row address STR_ADDR_1 and STR_ADDR_2 of strong cells. In Fig. 14, when a refresh operation is initiated, a refresh counter is initialized to, for example, "0" (S810), and a flag STR_FLAG of strong cells is initialized to a low logic level. The refresh row address REF_ADDR is compared to the first row address STR_ADDR_1 of strong cells (S820) and to the second row address STR_ADDR_2 of strong cells (S825). The refresh row address REF_ADDR can be compared to the first and second row addresses STR_ADDR_1 and STR_ADDR_2 of strong cells (S820) and (S825) essentially simultaneously. If the refresh row address REF_ADDR does not match the first and second row addresses STR_ADDR_1 and STR_ADDR_2 of strong cells (S820: NO and S825: NO), a memory cell row corresponding to the refresh row address REF_ADDR is refreshed (S840). If the refresh row address REF_ADDR matches the first row address STR_ADDR_1 of strong cells (S820: YES), a row of weak cells corresponding to the row address WEAK_ADDR of weak cells is refreshed (S850). If the refresh row address REF_ADDR matches the second row address STR_ADDR_2 of strong cells (S825: YES), one of the first and second rows of strong cells corresponding to the first and second row addresses STR_ADDR_1 and STR_ADDR_2 of strong cells is selectively refreshed according to the strong cell flag STR_FLAG. For example, if the strong cell flag STR_FLAG is at a low logic level (S830: YES), the second row of strong cells is refreshed (S840). If the refresh row address REF_ADDR matches the second row address STR_ADDR_2 of strong cells (S825: YES) and the strong cell flag STR_FLAG is at a high logic level (S830: NO), the first row of strong cells corresponding to the first row address STR_ADDR_1 of strong cells is refreshed (S865). The refresh row address REF_ADDR is incremented by 1 each time a memory cell row is refreshed (S870). If the refresh row address REF_ADDR exceeds the maximum row address MAX_ADDR (S880: YES), the refresh row address REF_ADDR is initialized, and the STR_FLAG flag of strong cells is inverted (S885), as occurs at each refresh period RP. In this way, the row with weak cells is refreshed instead of the first row with strong cells when the first row address STR_ADDR_1 is generated by strong cells. Accordingly, the refresh period for the row with weak cells is reduced without increasing the refresh current or power consumption. Fig. 15 shows another exemplary bank field 600c of a memory cell array with one row of weak cells and a first and second row of strong cells according to the invention. Referring to Fig. 15, a row address WEAK_ADDR of weak cells for a row 610c with weak cells is determined from an examination of the memory cell array. A first row address STR_ADDR_1 is selected such that it is spaced from the row 610c with weak cells by at least a predetermined interval ITV. The specified interval ITV is determined according to a minimum retention time of row 610c containing weak cells. For example, if bank field 600c contains X memory cell rows and the minimum retention time of row 610c containing weak cells is three-quarters of a refresh period RP, then the first row address STR_ADDR_1 of strong cells and row 610c containing weak cells have an interval corresponding to a count through at least X / 4 memory cell rows. In this case, if the first row 620c with strong cells is separated from the row 610c with weak cells by X / 3 memory cell rows, the row 610c with weak cells will be refreshed at time intervals of one-third and two-thirds of the refresh period RP. That is, the maximum time interval between two consecutive refreshes for the row 610c with weak cells is two-thirds of the refresh period RP, which is shorter than the minimum retention time of the row 610c with weak cells, which is three-quarters of the refresh period RP. In this way, the first row 620c is selected such that it is spaced from the row 610c containing weak cells by the specified interval ITV, ensuring that the weak cell row 610c is repeatedly refreshed before the minimum retention time. Furthermore, in Fig. 15, any row address except the WEAK_ADDR row address of weak cells and the first STR_ADDR_1 row address of strong cells can be selected as the second STR_ADDR_2 row address of strong cells. Fig. 16 shows a refresh address generator 400c for performing a refresh process of Fig. 14 according to a further exemplary embodiment of the invention. Referring to Fig. 16, the refresh address generator 400c includes an address storage unit 410c, a refresh counter 430c, a comparison unit 450c, and an address change unit 470c. The address storage unit 410c comprises a first memory area 411c for storing a row address WEAK_ADDR of weak cells, a second memory area 412c for storing a first row address STR_ADDR_1 of strong cells, and a third memory area 413c for storing a second row address STR_ADDR_2 of strong cells. Fig. 16 shows the address storage unit 410c storing a row address WEAK_ADDR of weak cells, a first row address STR_ADDR_1 of strong cells, and a second row address STR_ADDR_2 of strong cells. However, the present invention can also be implemented such that the address storage unit 410c stores multiple row addresses of weak cells and multiple respective first and second row addresses of strong cells. The refresh counter 430c generates a refresh row address REF_ADDR and a flag STR_FLAG from strong cells by counting. The comparison unit 450c generates a first match signal MATCH1 by comparing the refresh row address REF_ADDR with the first row address STR_ADDR_1 of strong cells. The comparison unit 450c also generates a second match signal MATCH2 by comparing the refresh row address REF_ADDR with the second row address STR_ADDR_2 of strong cells and based on the flag STR_FLAG of strong cells. The comparator unit 450c includes a plurality of first comparators 451c and 452c, a plurality of second comparators 453c and 454c, and a plurality of logic gates 461c, 462c, and 463c. The first comparators 451c and 452c compare the initial refresh line address REF_ADDR with the first line address STR_ADDR_1 of strong cells. A first AND gate 461c generates the first match signal MATCH1 by performing an AND operation on the output signals of the first comparators 451c and 452c. If the refresh line address REF_ADDR matches the first line address STR_ADDR_1 of strong cells, the first AND gate 461c outputs the first match signal MATCH1 at a high logic level. The second comparators 453c and 454c compare the refresh line address REF_ADDR with the second line address STR_ADDR_2 of strong cells. A second AND gate 462c performs an AND operation on the output signals of the second comparators 453c and 454c. If the refresh line address REF_ADDR matches the second line address STR_ADDR_2 of strong cells, the second AND gate 462c produces an output signal with a high logic level. A third AND gate 463c generates the second match signal MATCH2 by performing an AND operation on the flag STR_FLAG of strong cells and the output signal of the second AND gate 462c. If the refresh row address REF_ADDR matches the second row address STR_ADDR_2 of strong cells and the flag STR_FLAG of strong cells is at a high logic level, the third AND gate 463c outputs the second match signal MATCH2 at a high logic level. Fig. 16 shows the comparator unit 450c with a set of first comparators 451c and 452c, second comparators 453c and 454c, and logic gates 461c, 462c, and 463c for comparing the refresh line address REF_ADDR with the first and second line addresses STR_ADDR_1 and STR_ADDR_2 of strong cells, which correspond to a line address WEAK_ADDR of weak cells. However, the invention can also be implemented with the comparator unit 450c with multiple sets of first comparators, second comparators, and logic gates for comparing the refresh line address REF_ADDR with the respective first and second line addresses of strong cells, which correspond to multiple line addresses of weak cells. The address change unit 470c outputs the row address WEAK_ADDR of weak cells as the final refresh row address CREF_ADDR if the first match signal MATCH1 is at a high logic level. Alternatively, the address change unit 470c outputs the first row address STR_ADDR_1 of strong cells as the final refresh row address CREF_ADDR if the second match signal MATCH2 is at a high logic level. The address change unit 470c includes a plurality of logic gates 471c, 472c, and 473c, a plurality of first multiplexers 481c and 483c, and a plurality of second multiplexers 482c and 484c. An inverter 471c inverts the first matching signal MATCH1, and a fourth AND gate 472c generates a first selection signal SEL1 by performing an AND operation on the second matching signal MATCH2 and inverting the first matching signal MATCH1. The fourth AND gate, 472c, outputs the first selection signal, SEL1, at a low logic level when the first match signal, MATCH1, is at a high logic level, and outputs the first selection signal, SEL1, at a high logic level when the second match signal, MATCH2, is at a high logic level, with the first match signal, MATCH1, at a low logic level. The first multiplexers, 481c and 483c, selectively output bits WA1 to WAN of the row address WEAK_ADDR from weak cells when the first match signal, MATCH1, is at a high logic level, and selectively output bits SA11 to SA1N of the first row address, STR_ADDR_1, from strong cells when the second match signal, MATCH2, is at a high logic level. An OR gate 473c generates a second selection signal SEL2 by performing an OR operation on the first matching signal MATCH1 and the second matching signal MATCH2. If either the first or the second matching signal MATCH1 or MATCH2 is at a high logic level, the OR gate 473c outputs the second selection signal SEL2 at a high logic level. The second multiplexers 482c and 484c selectively output the initial refresh line address REF_ADDR or a line address from the first multiplexers 481c and 483c in response to the second selection signal SEL2. If the first and second match signals MATCH1 and MATCH2 are at low logic levels, the second multiplexers 482c and 484c output the initial refresh line address REF_ADDR as the final refresh line address CREF_ADDR. The second multiplexers 482c and 484c output the row address WEAK_ADDR of weak cells as the final refresh row address CREF_ADDR when the first match signal MATCH1 is at a high logic level, and output the first row address STR_ADDR_1 of strong cells as the final refresh row address CREF_ADDR when the second match signal MATCH2 is at a high logic level. In this way, the refresh address generator 400c outputs the row address WEAK_ADDR from weak cells when the refresh counter 430c generates the first row address STR_ADDR_1 from strong cells. Additionally, during each refresh period RP, when the refresh counter 430c generates the second row address STR_ADDR_2 from strong cells, the refresh address generator 400c alternately outputs one of the first and second row addresses STR_ADDR_1 and STR_ADDR_2 from strong cells. Thus, the refresh address generator 400c allows the row with weak cells to be refreshed instead of the first row with strong cells, thereby reducing the refresh period for the row with weak cells without increasing the refresh current or power consumption. Fig. 17 shows a bank field 600d of a memory cell array according to an exemplary embodiment of the invention, comprising one row of weak cells and a first and second row of strong cells selected from a pool of possible strong memory cells. Referring to Fig. 17, a row address WEAK_ADDR of weak cells for a row 610d of weak cells is determined by examining the memory cell array. Furthermore, a pool of strong cells, from which the first and second row addresses STR_ADDR_1 and STR_ADDR_2 of strong cells are selected, is determined by inverting the MSB of the row address WEAK_ADDR of weak cells. The pool of strong cells contains 2M row addresses, of which M least significant bits differ from one another, where M is an integer greater than 1. For example, if each row address has N bits, the 2M row addresses that form the pool of strong cells have the same upper NM bits and different M least significant bits. Furthermore, in an exemplary embodiment of the invention, the upper NM bits, with the exception of the MSB (i.e., the M+1 to N-1 bits), of the 2M row addresses are the same as those of the row address WEAK_ADDR of weak cells. For example, in a case where a row address has 13 bits and the strong cell pool contains row addresses where the four least significant bits differ from each other, the strong cell pool will contain 16 row addresses. Each such row address in the strong cell pool will have a MSB that differs from that of the WEAK_ADDR row address of weak cells and will have bits five through twelve that are the same as those of the WEAK_ADDR row address of weak cells. Two memory cell rows with minimum retention times longer than or equal to approximately twice a refresh period (RP) are selected as the first and second strong cell rows, 620d and 630d, from among the 16 strong cell rows containing the 16 row addresses in the strong cell pool. Fig. 18 shows a refresh address generator 400d for performing the refresh method of Fig. 14 according to a further exemplary embodiment of the invention. Fig. 18 shows an example of the first and second row addresses STR_ADDR_1 and STR_ADDR_2 of strong cells, which are selected from 16 row addresses of a pool of strong cells shown in Fig. 17. Referring to Fig. 18, the refresh address generator 400d includes an address storage unit 410d, a refresh counter 430d, a comparison unit 450d, and an address change unit 470d. The address storage unit 410d includes a first memory area 411d for storing a first row address STR_ADDR_1 of strong cells and a second memory area 412d for storing the 4 least significant bits of a second row address STR_ADDR_2 of strong cells. The address memory unit 410d also includes a third memory area 413d for storing the result of a first XOR operation on the four least significant bits of the first row address STR_ADDR_1 of strong cells and a row address WEAK_ADDR of weak cells. The address memory unit 410d further includes a fourth memory area 414d for storing the result of a second XOR operation on the four least significant bits of the first row address STR_ADDR_1 of strong cells and the second row address STR_ADDR_2 of strong cells. Fig. 18 shows the address storage unit 410d, which stores the first row address STR_ADDR_1 of strong cells, the four least significant bits of the second row address STR_ADDR_2 of strong cells, and the results of the first and second XOR operations for a row address WEAK_ADDR of weak cells. However, the invention can also be implemented such that the address storage unit 410d stores similar address information corresponding to several row addresses of weak cells. The refresh counter 430d generates a refresh row address REF_ADDR and a flag STR_FLAG from strong cells by counting. The comparison unit 450d generates a first match signal MATCH1 by comparing the refresh row address REF_ADDR with the first row address STR_ADDR_1 of strong cells. The comparison unit 450d generates a second match signal MATCH2 by comparing the refresh row address REF_ADDR with the second row address STR_ADDR_2 of strong cells and based on the flag STR_FLAG of strong cells. The comparator unit 450d contains the first N comparators 451d, 452d, 453d, and 454d, the second four comparators 456d to 457d, and a plurality of logic gates 461d, 462d, and 463d. The first comparators 451d, 452d, 453d, and 454d compare the refresh row address REF_ADDR with the first row address STR_ADDR_1 of strong cells. A first AND gate 461d generates the first match signal MATCH1 by performing an AND operation on the output signals of the first comparators 451d, 452d, 453d, and 454d. If the initial refresh row address REF_ADDR matches the first row address STR_ADDR_1 of strong cells, the first AND gate 461d outputs the first match signal MATCH1 at a high logic level. The second comparators 456d to 457d compare the four least significant bits of the refresh row address REF_ADDR with the four least significant bits of the second row address STR_ADDR_2 of strong cells. A second AND gate 462d performs an AND operation on the output signals of the second comparators 456d to 457d and on the N-4 output signals of the N-4 comparators 453d and 454d, corresponding to the N-4 most significant bits (i.e., the fifth to Nth bits) of the refresh row address REF_ADDR. If the refresh line address REF_ADDR matches the second line address STR_ADDR_2 of strong cells, the second AND gate 462d generates a high-level output signal. A third AND gate 463d performs an AND operation on the flag STR_FLAG of strong cells and the output signal of the second AND gate 462d to generate the second match signal MATCH2. If the refresh line address REF_ADDR matches the second line address STR_ADDR_2 of strong cells and the flag STR_FLAG of strong cells is at a high logic level, the third AND gate 463d outputs the second match signal MATCH2 at a high logic level. Fig. 18 shows the comparator unit 450d, which includes a set of first comparators 451d, 452d, 453d, and 454d, second comparators 456d to 457d, and logic gates 461d, 462d, and 463d for comparing the refresh line address REF_ADDR with the first and second line addresses STR_ADDR_1 and STR_ADDR_2 of strong cells, which correspond to a line address WEAK_ADDR of weak cells. However, the invention can also be implemented such that the comparator unit 450d includes multiple sets of first comparators, second comparators, and logic gates for comparing the refresh line address REF_ADDR with the first and second line addresses of strong cells, which correspond to multiple line addresses of weak cells. The address change unit 470d outputs the row address WEAK_ADDR of weak cells as the final refresh row address CREF_ADDR if the first match signal MATCH1 is at a high logic level. Alternatively, the address change unit 470d outputs the first row address STR_ADDTR_1 of strong cells as the final refresh row address CREF_ADDR if the second match signal MATCH2 is at a high logic level. The address change unit 470d includes a first AND gate 471d or 476d, which performs an AND operation on the first matching signal MATCH1 and each of the bits stored in the third memory area 413d. The address change unit 470d also includes a second AND gate 472d or 477d, which performs an AND operation on the second matching signal MATCH2 and each of the bits stored in the fourth memory area 414d. The address change unit 470d further includes a respective OR gate 473d or 478d, which performs an OR operation on the outputs of respective AND gates that input bits of the same bit significance from the third and fourth memory areas 413d and 414d. Thus, the OR gates 473d and 478d output the bits stored in the third memory area 413d when the first matching signal MATCH1 is at a high logic level, and output the bits stored in the fourth memory area 414d when the second matching signal MATCH2 is at a high logic level. Each output of the OR gates 473d and 478d is applied to a control pin of a respective multiplexer 475d or 480d. A respective inverter 474d or 479d inverts one RA1 or RA4 of the four least significant bits of the initial refresh line address REF_ADDR. Inverter 481d inverts the Nth bit RAN of the refresh line address REF_ADDR. In response to the first match signal MATCH1, multiplexer 482d outputs one of the Nth bits RAN of the initial refresh line address REF_ADDR, or an inversion thereof, as one of the Nth bits CRAN of the final refresh line address CREF_ADDR. Each of multiplexers 475d and 480d, in response to a respective output signal from their respective OR gates 473d and 478d, selectively outputs one of the respective bits RA1 or RA4 of the initial refresh line address REF_ADDR, or an inversion thereof, as one of the respective bits CRA1 or CRA4 of the final refresh line address CREF_ADDR. The address change unit 470d also includes inverters 483d, 484d, 485d and 486d to delay the fifth to N-1th bits RA5 to RAN-1 of the initial refresh line address REF_ADDR in order to generate the final refresh line address CREF_ADDR. Accordingly, if the first matching signal MATCH1 is at a high logic level (i.e., if the initial refresh line address REF_ADDR matches the first line address STR_ADDR_1 of strong cells), the address change unit 470d inverts the Nth bit RAN of the initial refresh line address REF_ADDR. Furthermore, in that case, the address change unit 470d inverts any bit of the four least significant bits RA1 to RA4 of the initial refresh line address REF_ADDR that differs from corresponding bits of the line address WEAK_ADDR of weak cells. This means that the address change unit 470d outputs the row address WEAK_ADDR of weak cells as the final refresh row address CREF_ADDR if the refresh row address REF_ADDR matches the first row address STR_ADDR_1 of strong cells. Furthermore, if the second matching signal MATCH2 is at a high logic level (i.e., if the refresh row address REF_ADDR matches the second row address STR_ADDR_2 of strong cells and the flag STR_FLAG of strong cells is at a high logic level), the address change unit 470d inverts any bit of the four least significant bits RA1 to RA4 of the initial refresh row address REF_ADDR that differs from corresponding bits of the first row address STR_ADDR_1 of strong cells among the first to fourth bits RA1 to RA4 of the initial refresh row address REF_ADDR.Thus, the address change unit 470d outputs the first row address STR_ADDR_1 of strong cells as the final refresh row address CREF_ADDR if the refresh row address REF_ADDR matches the second row address STR_ADDR_2 of strong cells and the flag STR_FLAG of strong cells is at a high logic level. In this way, the refresh address generator 400d outputs the row address WEAK_ADDR of weak cells when the refresh counter 430d generates the first row address STR_ADDR_1 of strong cells. Furthermore, during each refresh period RP, the refresh address generator 400d alternately outputs the first and second row addresses STR_ADDR_1 and STR_ADDR_2 of strong cells when the refresh counter 430d generates the second row address STR_ADDR_2 of strong cells. Thus, the refresh address generator 400d allows the row with weak cells to be refreshed instead of the first row with strong cells, thereby reducing the refresh period for the weak cell row without increasing the refresh current or power consumption. Furthermore, the second row address STR_ADDR_2 of strong cells is selected from a pool of addresses with a range defined by at least two least significant bits of the row address WEAK_ADDR of weak cells and / or the first row address STR_ADDR_1 of strong cells. Fig. 19 illustrates steps for refreshing a volatile memory device depending on a flag of strong cells according to a further exemplary embodiment of the invention. In Fig. 19, a row of weak cells is refreshed in an odd-numbered refresh period instead of a first row of strong cells, and the row of weak cells is refreshed in an even-numbered refresh period instead of a second row of strong cells. In Fig. 19, when a refresh operation is initiated, a refresh counter is initialized, for example, to "0" (S910), and a flag STR_FLAG of strong cells is initialized to a low logic level. The initial refresh row address REF_ADDR is compared with a first row address STR_ADDR_1 of strong cells (S920) and with a second row address STR_ADDR_2 of strong cells (S930). In an exemplary embodiment of the present invention, comparisons of the refresh row address REF_ADDR with the first and second row addresses STR_ADDR_1 and STR_ADDR_2 (S920 and S930) are performed essentially simultaneously. If the refresh line address REF_ADDR does not match either the first or second line address STR_ADDR_1 and STR_ADDR_2 (S920: NO and S930: NO), a memory cell row corresponding to the initial refresh line address REF_ADDR is refreshed (S940). If the refresh row address REF_ADDR matches the first row address STR_ADDR_1 of strong cells (S920: YES), a first row of strong cells corresponding to the first row address STR_ADDR_1 of strong cells, or a row of weak cells corresponding to a row address WEAK_ADDR of weak cells, is selectively refreshed according to the strong cells' flag STR_FLAG (S925, S940, S950). For example, in this case, if the strong cells' flag STR_FLAG is at a first logic level (e.g., a high logic level) (S925: NO), the first row of strong cells corresponding to the first row address STR_ADDR_1 of strong cells is refreshed (S940). Alternatively, in this case, if the STR_FLAG flag of strong cells is on a second logic level (e.g., a low logic level) (S925: YES), the row with weak cells corresponding to the WEAK_ADDR row address of weak cells is refreshed (S950). If the refresh row address REF_ADDR matches the second row address STR_ADDR_2 of strong cells (S930: YES), a second row of strong cells corresponding to the second row address STR_ADDR_2 of strong cells, or the row of weak cells corresponding to the row address WEAK_ADDR of weak cells, is selectively refreshed according to the flag STR_FLAG of strong cells (S935, S940, S950). For example, in this case, if the flag STR_FLAG of strong cells has the second logic level (S935: NO), the second row of strong cells corresponding to the second row address STR_ADDR_2 of strong cells is refreshed (S940). Alternatively, in this case, if the flag STR_FLAG of strong cells has the first logic level (S935: YES), the row of weak cells corresponding to the row address WEAK_ADDR of weak cells is refreshed (S950). The refresh row address REF_ADDR is incremented by 1 each time a memory cell row is refreshed (S970). If the refresh row address REF_ADDR exceeds the maximum row address MAX_ADDR (S980: YES), the refresh row address REF_ADDR is initialized, and the strong cell flag STR_FLAG is inverted (S985), so that the strong cell flag STR_FLAG is inverted at each refresh period RP. In this way, the row with weak cells is refreshed instead of the second row with strong cells when the STR_FLAG flag of strong cells is at the first logic level. Furthermore, the row with weak cells is refreshed instead of the first row with strong cells when the STR_FLAG flag of strong cells is at the second logic level. Consequently, the refresh period for the row with weak cells is reduced without increasing the refresh current or refresh power consumption. Fig. 20 shows a timing diagram of exemplary refreshes of a row with weak cells and a first and second row with strong cells, performed according to Fig. 19, in an exemplary embodiment of the invention. Referring to Fig. 20, a row with weak cells is refreshed twice per refresh period RP. For example, during an odd-numbered refresh period, a refresh 910 is performed for the row with weak cells when a row address for the row with weak cells is generated, and an additional refresh 915 is performed for the row with weak cells when a row address for a first row with strong cells is generated. Alternatively, during an even-numbered refresh period, a refresh 910 is performed for the weak cell row when a row address is generated for the weak cell row, and an additional refresh 916 is performed for the weak cell row when a row address is generated for a second strong cell row. The weak cell row is repeatedly refreshed before the minimum retention time by selecting each of the first and second strong cell rows that are separated from the weak cell row by at least a predetermined interval. For example, the row address for the first strong cell row is determined by inverting the MSB of the weak cell row address, and the row address for the second strong cell row is determined by inverting the MSB and LSB of the weak cell row address.In this case, the refresh period of the row with weak cells is half the refresh period RP defined in the standard of the memory component. Each of the first and second rows containing strong cells is refreshed every 2RP period, which is twice the refresh period RP. For example, the first row of strong cells is refreshed in even-numbered refresh periods, and the second row of strong cells is refreshed in odd-numbered refresh periods. That is, each of the first and second rows containing strong cells is refreshed once every two refresh periods RP. Fig. 21 shows a refresh address generator 400e for performing the refresh method of Fig. 19 according to a further exemplary embodiment of the invention. Fig. 21 shows an example in which the first row address STR_ADDR_1 of strong cells is set by inverting the MSB of a row address WEAK_ADDR of weak cells, and a second row address STR_ADDR_2 of strong cells is set by inverting the LSB of the first row address STR_ADDR_1 of strong cells. Referring to Fig. 21, the refresh generator 400e includes an address storage unit 410e, a refresh counter 430e, a comparison unit 450e, and an address change unit 470e. The refresh address generator 400e is essentially similar to the refresh address generator 400a of Fig. 9, except that the refresh address generator 400e includes additional logic gates 462e, 463e and 473e. The address storage unit 410e includes a first memory area 411e for storing the first row address STR_ADDR_1 of strong cells. Fig. 21 shows the address storage unit 410e such that it stores a first row address STR_ADDR_1 of strong cells for a row address WEAK_ADDR of weak cells. However, the invention can also be implemented such that the address storage unit 410e stores several first row addresses of strong cells, corresponding to several row addresses of weak cells. The refresh counter 430e generates an initial refresh row address REF_ADDR and a flag STR_FLAG from strong cells by counting. The comparator unit 450e generates a first match signal MATCH1 from the flag STR_FLAG of strong cells and a comparison of the initial refresh row address REF_ADDR with the first row address STR_ADDR_1 of strong cells. The comparator unit 450e also generates a second match signal MATCH2 from the flag STR_FLAG of strong cells and a comparison of the initial refresh row address REF_ADDR with the second row address STR_ADDR_2 of strong cells. The comparator unit 450e contains N comparators 451e, 452e, and 453e and a plurality of logic gates 461e, 462e, 463e, 464e, 465e, and 466e. The N comparators 451e, 452e, and 453e compare respective bits of the initial refresh row address REF_ADDR and the first row address STR_ADDR_1 of strong cells. A first AND gate 461e performs an AND operation on the output signals of the N comparators 451e, 452e, and 453e. A first inverter 462e inverts the STR_FLAG flag of strong cells. The second AND gate 463e generates the first match signal MATCH1 by performing an AND operation on an output of the first AND gate 461e and inverting the STR_FLAG flag of strong cells. Similarly, the comparator 450e generates the first match signal MATCH1 at a high logic level when the refresh line address REF_ADDR matches the first line address STR_ADDR_1 of strong cells and the STR_FLAG flag of strong cells is at a low logic level. A second inverter 464e inverts the output of the first comparator 461e. A third AND gate 465e performs an AND operation on the outputs of the N-1 comparators 452e and 453e and one output of the second inverter 464e. The third AND gate 465e produces a high-level output signal when the refresh line address REF_ADDR is the same as the first line address STR_ADDR_1 of strong cells, except for the LSB (i.e., when the refresh line address REF_ADDR matches the second line address STR_ADDR_2 of strong cells). A fourth AND gate 466e produces the second match signal MATCH2 by performing an AND operation on the output signal of the third AND gate 465e and the flag STR_FLAG of strong cells.Accordingly, the comparator unit 450e generates the second match signal MATCH2 at a high logic level when the refresh row address REF_ADDR matches the second row address STR_ADDR_2 of strong cells and the flag STR_FLAG of strong cells is at a high logic level. Fig. 21 shows the comparator unit 450e, which includes a set of comparators 451e, 452e and 453e as well as logic gates 461e, 462e, 463e, 464e, 465e and 466e for a row address WEAK_ADDR of weak cells. However, the invention can also be implemented such that the comparator unit 450e has several sets of comparators and logic gates for several row addresses of weak cells. If the first match signal MATCH1 is at a high logic level, the address change unit 470e outputs the line address WEAK_ADDR of weak cells by inverting the Nth bit RAN of the initial refresh line address REF_ADDR as a final refresh line address CREF_ADDR. If the second match signal MATCH2 is at a high logic level, the address change unit 470e outputs the line address WEAK_ADDR of weak cells by inverting the first bit RA1 and the Nth bit RAN of the initial refresh line address REF_ADDR as the final refresh line address CREF_ADDR. The address change unit 470e includes a first inverter 471e and a first multiplexer 472e for changing the first bit RA1 of the refresh line address REF_ADDR. The address change unit 470e also includes an OR gate 473e, a second inverter 474e, and a second multiplexer 475e for changing the second bit RAN of the refresh line address REF_ADDR. The first inverter 471e and the first multiplexer 472e can, in response to the second matching signal MATCH2, invert the first bit RA1 of the initial refresh line address REF_ADDR to generate the first bit CRA1 of the final refresh line address CREF_ADDR. The OR gate 473e, the second inverter 474e, and a second multiplexer 475e can, in response to the first matching signal MATCH1 or the second matching signal MATCH2, invert the Nth bit RAN of the refresh line address REF_ADDR to generate the Nth bit CRAN of the final refresh line address CREF_ADDR. The address change unit 470e also includes inverters 481e, 482e, 483e and 484e for delaying the second to Nth bits RA2 and RAN-1 of the initial refresh line address REF_ADDR in order to generate corresponding bits CRA2 and CRAN-1 of the final refresh line address CREF_ADDR. In this way, the 400e refresh address generator outputs the row address WEAK_ADDR of weak cells in each refresh period RP instead of one of the first and second row addresses STR_ADDR_1 and STR_ADDR_2 of strong cells. Therefore, the 400e refresh address generator allows the row with weak cells to be refreshed instead of one of the first and second rows with strong cells, thus reducing the refresh period for the row with weak cells without increasing the refresh current or power consumption. Fig. 22 shows an exemplary bank field 600f of a memory element with one row of weak cells and a first and second row of strong cells according to a further embodiment of the invention. Referring to Fig. 22, a row address WEAK_ADDR of weak cells for a row 610f of weak cells is determined from a test of the memory element. A first row address STR_ADDR_1 of strong cells in a first row 620f containing strong cells is selected such that a counting time interval between the first row address STR_ADDR_1 of strong cells and the row address WEAK_ADDR of weak cells is at least a first predefined interval ITV1. Furthermore, a second row address STR_ADDR_2 of strong cells in a second row 630f containing strong cells is selected such that a counting time interval between the second row address STR_ADDR_2 of strong cells and the row address WEAK_ADDR of weak cells is at least a second predefined interval ITV2. The first and second predefined intervals ITV1 and ITV2 are determined according to a minimum retention time of row 610f with weak cells. For example, in a case where bank field 600f contains X memory cell rows and the minimum retention time of row 610f with weak cells is three-quarters of a refresh period RP, each of the first and second row addresses STR_ADDR_1 and STR_ADDR_2 of strong cells is selected such that the first and second predefined intervals ITV1 and ITV2 are at least X / 4 in each direction. For example, if each of the strong-cell rows 620f and 630f is separated from the weak-cell row 610f by an interval approximately equal to N / 3 memory cell rows, refreshes for the weak-cell row 610f can have time intervals approximately one-third or two-thirds of the refresh period RP. In that case, the maximum time interval between two consecutive refreshes for the weak-cell row 610f is two-thirds of the refresh period RP, which is shorter than the minimum retention time for the weak-cell row 610f, which is three-quarters of the refresh period RP. Fig. 23 shows a refresh address generator 400f for performing the refresh method of Fig. 19 according to a further exemplary embodiment of the invention. Fig. 23 shows an example in which a first and second row address STR_ADDR_1 and STR_ADDR_2 of strong cells are arbitrarily set. Referring to Fig. 23, the refresh address generator 400f includes an address storage unit 410f, a refresh counter 430f, a comparison unit 450f, and an address change unit 470f. The address storage unit 410f includes a first memory area 411f for storing a row address WEAK_ADDR of weak cells, a second memory area 412f for storing a first row address STR_ADDR_1 of strong cells, and a third memory area 413f for storing a second row address STR_ADDR_2 of strong cells. Fig. 23 shows the address storage unit 410f, which stores one row address WEAK_ADDR of weak cells, one first row address STR_ADDR_1 of strong cells, and one second row address STR_ADDR_2 of strong cells. However, the invention can also be implemented such that the address storage unit 410f stores multiple row addresses of weak cells, multiple first row addresses of strong cells, and multiple second row addresses of strong cells. The refresh counter 430e generates an initial refresh row address REF_ADDR and a flag STR_FLAG from strong cells by counting. Based on the flag STR_FLAG from strong cells and a comparison of the refresh row address REF_ADDR with the first row address STR_ADDR_1 of strong cells, the comparison unit 450f generates a first match signal MATCH1. The comparison unit 450f also generates a second match signal MATCH2 based on the flag STR_FLAG from strong cells and a comparison of the refresh row address REF_ADDR with the second row address STR_ADDR_2 of strong cells. The comparator unit 450f includes a plurality of N first comparators 451f and 452f, a plurality of N second comparators 453f and 454f, and a plurality of logic gates 461f, 462f, 463f, 464f, and 465f. The first comparators 451f and 452f, a first AND gate 461f, an inverter 462f, and a second AND gate 463f are configured to generate the first match signal MATCH1 at a high logic level when the refresh line address REF_ADDR matches the first line address STR_ADDR_1 of strong cells and the flag STR_FLAG of strong cells is at a low logic level.The second comparators 453f and 454f, a third AND gate 464f and a fourth AND gate 465f are configured to generate the second match signal MATCH2 at a high logic level when the refresh row address REF_ADDR matches the second row address STR_ADDR_2 of strong cells and the flag STR_FLAG of strong cells is at a high logic level. Fig. 23 shows the comparator unit 450f, which includes a set of first comparators 451f and 452f, second comparators 453f and 454f, and logic gates 461f, 462f, 463f, 464f, and 465f for a single row address WEAK_ADDR of weak cells. However, the invention can also be implemented such that the comparator unit 450f comprises multiple sets of first comparators, second comparators, and logic gates for multiple row addresses of weak cells. The address change unit 470f generates the row address WEAK_ADDR of weak cells as a final refresh row address CREF_ADDR when either of the first and second matching signals MATCH1 and MATCH2 is at a high logic level. The address change unit 470f includes an OR gate 471f and a plurality of multiplexers 472f, 473f, 474f, and 475f. The OR gate 471f generates a selection signal SEL by performing an OR operation on the first and second matching signals MATCH1 and MATCH2. Multiplexers 472f, 473fd, 474f, and 475f receive the refresh line address REF_ADDR from the refresh counter 430f and the line address WEAK_ADDR of weak cells from the address storage unit 410f. In response to the selection signal SEL, multiplexers 472f, 473f, 474f, and 475f selectively output either the refresh line address REF_ADDR or the line address WEAK_ADDR of weak cells as the final refresh line address CREF_ADDR. In this way, the 400f refresh address generator outputs the row address WEAK_ADDR of weak cells in each refresh period RP instead of one of the first and second row addresses STR_ADDR_1 and STR_ADDR_2 of strong cells. Therefore, the 400f refresh address generator allows the row with weak cells to be refreshed instead of one of the first and second rows with strong cells, thus reducing the refresh period for the row with weak cells without increasing the refresh current or power consumption. Fig. 24 illustrates steps for refreshing a volatile memory element according to a selected memory bank in a further exemplary embodiment of the invention. In Fig. 24, a row address WEAK_ADDR of weak cells, a first row address STR_ADDR_1 of strong cells, and a second row address STR_ADDR_2 of strong cells are defined on a memory bank basis such that refresh leveraging is performed on a memory bank basis. In Fig. 24, when a refresh operation is initiated, a refresh counter is initialized, for example, to "0" (S1010), and a flag STR_FLAG of strong cells is initialized to a low logic level. The refresh row address REF_ADDR is compared with the first and second row addresses STR_ADDR_1 and STR_ADDR_2 of strong cells (S1020 and S1025). In an exemplary embodiment of the invention, such comparisons (S1020 and S1025) are performed essentially simultaneously. If the refresh row address REF_ADDR does not match the first and second row addresses STR_ADDR_1 and STR_ADDR_2 of strong cells (S1020: NO and S1025: NO), the memory cell rows corresponding to the initial refresh row address REF_ADDR are refreshed in all banks (S1040). If the initial refresh row address REF_ADDR matches the first row address STR_ADDR_1 of strong cells (S1020: YES), a row of weak cells corresponding to the row address WEAK_ADDR of weak cells is refreshed in at least one bank indicated by bank information (i.e., a selected memory bank), and memory cell rows corresponding to the initial refresh row address REF_ADDR are refreshed in the other banks (i.e., unselected memory banks) (S1050). In an exemplary embodiment of the invention, the bank information includes a bank address stored in an address storage unit. Alternatively, the bank information includes bank flags for the respective banks stored in the address storage unit. If the refresh row address REF_ADDR matches the second row address STR_ADDR_2 of strong cells (S1025: YES) and the strong cell flag STR_FLAG is at a low logic level (S1030: YES), memory cell rows corresponding to the initial refresh row address REF_ADDR are refreshed in all banks (S1040). The refresh row address REF_ADDR is incremented by 1 each time a respective memory cell row is refreshed in the memory banks (S1070). If the refresh row address REF_ADDR exceeds the maximum row address MAX_ADDR (S1080: YES), the refresh row address REF_ADDR is initialized, and the strong cell flag STR_FLAG is inverted in each refresh period RP (S1085). If the refresh row address REF_ADDR matches the second row address STR_ADDR_2 of strong cells (S1025: YES) and the strong cell flag STR_FLAG is at a high logic level (S1030: NO), a first row of strong cells corresponding to the first row address STR_ADDR_1 of strong cells is refreshed in the bank that corresponds to the bank information, and memory cell rows corresponding to the initial refresh row address REF_ADDR are refreshed in the other banks (S1060). In this way, the weak cell row is refreshed only in the selected bank, as indicated by the bank information, instead of the first strong cell row. Fig. 25 shows a refresh address generator 400g for performing the refresh method of Fig. 24 according to a further exemplary embodiment of the invention. Fig. 25 includes refresh leveraging on a bank basis using a bank address BANK_ADDR. Furthermore, in Fig. 25, a first row address STR_ADDR_1 of strong cells is determined by inverting the MSB of a row address WEAK_ADDR of weak cells, and a second row address STR_ADDR_2 of strong cells is determined by inverting the LSB of the first row address STR_ADDR_1 of strong cells. Referring to Fig. 25, the refresh address generator 400g includes an address storage unit 410g, a refresh counter 430g, a comparison unit 450g, and an address change unit 470g. The address storage unit 410g includes a first memory area 411g for storing the first row address STR_ADDR_1 of strong cells and a second memory area 412g for storing the bank address BANK_ADDR. Fig. 25 shows the address storage unit 410g, which stores a first row address STR_ADDR_1 of strong cells and a bank address BANK_ADDR, which are related to a row address WEAK_ADDR of weak cells. However, the invention can also be implemented such that the address storage unit 410g stores multiple first row addresses of strong cells and multiple bank addresses, which are related to multiple row addresses of weak cells. The refresh counter 430g generates an initial refresh row address REF_ADDR and a flag STR_FLAG from strong cells by counting. The comparison unit 450g generates a first match signal MATCH1 by comparing the refresh row address REF_ADDR with the first row address STR_ADDR_1 of strong cells. The comparison unit 450g also generates a second match signal MATCH2 based on the flag STR_FLAG of strong cells and by comparing the refresh row address REF_ADDR with the second row address STR_ADDR_2 of strong cells. The comparator unit 450g feeds the first and second match signals MATCH1 and MATCH2 of a bank corresponding to the bank address BANK_ADDR to a plurality of banks 365a and 365h. Comparator unit 450g includes a plurality of comparators 451g, 452g, and 453g, a plurality of logic gates 461g, 462g, 463g, and 464g, a first demultiplexer 466g, and a second demultiplexer 467g. The comparators 451g, 452g, and 453g and the first AND gate 461g are configured to generate the first match signal MATCH1 at a high logic level when the refresh row address REF_ADDR matches the first row address STR_ADDR_1 of strong cells. The comparators 451g, 452g, and 453g, an inverter 462g, a second AND gate 463g, and a third AND gate 464g are configured to generate the second match signal MATCH2 at a high logic level when the refresh line address REF_ADDR matches the second line address STR_ADDR_2 of strong cells and the flag STR_FLAG of strong cells is at a high logic level. The first demultiplexer 466g transfers the first match signal MATCH1 in response to the bank address BANK_ADDR as one of a plurality of first bank match signals MATCH1_A and MATCH1_H. The second demultiplexer 467g transfers the second match signal MATCH2 in response to the bank address BANK_ADDR as one of a plurality of second bank match signals MATCH2_A and MATCH2_H. Accordingly, the first and second match signals MATCH1 and MATCH2 are applied to the bank corresponding to the bank address BANK_ADDR under the plurality of banks 365a and 465h. Fig. 25 shows the comparator unit 450g with a set of comparators 451g, 452g, and 453g, logic gates 461g, 462g, 463g, and 464g, and demultiplexers 466g and 467g for a single line address WEAK_ADDR of weak cells. However, the invention can also be implemented such that the comparator unit 450g has multiple sets of comparators, logic gates, and demultiplexers for multiple line addresses of weak cells. The refresh line address REF_ADDR from the refresh counter 430g is applied to the respective banks 365a and 365h via the line address multiplexers 340 of Fig. 4. Banks 365a and 365h receive the refresh line address REF_ADDR, the first bank match signals MATCH1_A and MATCH1_H, and the second match signals MATCH2_A and MATCH2_H, respectively. The address change unit 470g is located on banks 365a and 365h. For example, address change unit 470g includes first inverters 471g and 481g, first multiplexers 472g and 482g, second inverters 473g and 483g, and second multiplexers 474g and 484g in banks 365a and 365h, respectively. The first inverters, 471g and 481g, invert the first bit RA1 of the initial refresh line address REF_ADDR. The first multiplexers, 472g and 482g, output the first bit RA1 of the refresh line address REF_ADDR, or its inversion, in response to the first bank match signals MATCH1_A and MATCH2_H, respectively, as the first bits CRA1_A and CRA1_H of the respective final refresh line addresses CREF_ADDR. The second inverters 473g and 483g invert an Nth bit RAN of the initial refresh line address REF_ADDR. In response to the second bank match signals MATCH2_A and MATCH2_H, the second multiplexers 474g and 484g selectively output the Nth bit RAN and its inversion from the refresh line address REF_ADDR as the Nth bits CRAN_A and CRAN_H of the respective final refresh line addresses CREF_ADDR. Only one of the first bank match signals MATCH1_A and MATCH1_H, and only one of the second bank match signals MATCH2_A and MATCH2_H, indicated by the bank address BANK_ADDR, are activated. Accordingly, the address change unit 470g modifies the initial refresh line address REF_ADDR only for the bank indicated by the bank address BANK_ADDR. The respective final refresh line addresses CREF_ADDR from the address change unit 470g are applied to the bank line decoders 360a, 360b, 360c, and 360d shown in Fig. 4. In this way, the 400g refresh address generator allows a row with weak cells to be refreshed only in a selected memory bank corresponding to a bank address BANK_ADDR, instead of a first row with strong cells. Accordingly, refresh leveraging is performed on a bank-by-bank basis, and the refresh period for the row with weak cells is reduced without increasing the refresh current or power consumption. Fig. 26 shows a refresh address generator 400h for performing the refresh procedure of Fig. 24 with refresh leveraging on a bank basis using bank flags BANKA_FLAG and BANKH_FLAG according to a further exemplary embodiment of the invention. Furthermore, in Fig. 26, a first row address STR_ADDR_1 of strong cells is determined by inverting the MSB of a row address WEAK_ADDR of weak cells, and a second row address STR_ADDR_2 of strong cells is determined by inverting the LSB of the first row address STR_ADDR_1 of strong cells. Referring to Fig. 26, the refresh address generator 400h includes an address storage unit 410h, a refresh counter 430h, a comparison unit 450h, and an address change unit 470h. The refresh address generator 400h is essentially similar to the refresh address generator 400g of Fig. 25, except that the bank flags BANKA_FLAG and BANKH_FLAG are used. The address storage unit 410h includes a first memory area 411h for storing the first row address STR_ADDR_1 of strong cells and a second memory area 412h for storing the bank flags BANKA_FLAG and BANKH_FLAG. Each of the bank flags BANKA_FLAG and BANKH_FLAG can be a one-bit data value representing whether a refresh leveraging operation is to be performed in either bank 365a or 365h. Fig. 26 shows the address storage unit 410h, which stores a first row address STR_ADDR_1 of strong cells and bank flags BANKA_FLAG and BANKH_FLAG, which are associated with a row address WEAK_ADDR of weak cells. However, the invention can also be implemented such that the address storage unit 410h stores multiple first row addresses of strong cells and bank flags, which are associated with multiple row addresses of weak cells. The refresh counter 430h generates a refresh row address REF_ADDR and a flag STR_FLAG from strong cells by counting. The comparison unit 450h generates a first match signal MATCH1 by comparing the refresh row address REF_ADDR with the first row address STR_ADDR_1 of strong cells. The comparison unit 450h also generates a second match signal MATCH2 based on the flag STR_FLAG of strong cells and by comparing the refresh row address REF_ADDR with the second row address STR_ADDR_2 of strong cells. The comparator unit 450g selectively applies the first and second match signals MATCH1 and MATCH2 to a plurality of banks 365a and 365h according to the bank flags BANKA_FLAG and BANKH_FLAG. The comparator unit 450h includes a plurality of comparators 451h, 452h, and 453h, as well as a plurality of logic gates 461h, 462h, 463h, 464h, 465h, 466h, 467h, and 468h. Comparators 451h, 452h, and 453h, and a first AND gate 461h, are configured to generate the first match signal MATCH1 at a high logic level when the refresh line address REF_ADDR matches the first line address STR_ADDR_1 of strong cells. Comparators 451h, 452h, and 453h, an inverter 462h, a second AND gate 463h, and a third AND gate 464h are configured to generate the second match signal MATCH2 at a high logic level when the refresh line address REF_ADDR matches the line address STR_ADDR_2 of strong cells and the flag STR_FLAG of strong cells is at a high logic level. Fourth AND gates 465h and 467h are configured to generate multiple first bank match signals MATCH1_A and MATCH1_H by performing an AND operation on the first match signal MATCH1 and the bank flags BANKA_FLAG and BANKH_FLAG. Fifth AND gates 466h and 468h are configured to generate second bank match signals MATCH2_A and MATCH2_H by performing an AND operation on the second match signal MATCH2 and the bank flags BANKA_FLAG and BANKH_FLAG. Thus, the comparator 450h transfers the first and second match signals MATCH1 and MATCH2 to at least one bank with a corresponding bank flag set to a high logic level. Fig. 26 shows the comparator unit 450h with a set of comparators 451h, 452h and 453h and logic gates 461h, 462h, 463h, 464h, 465h, 466h, 467h and 468h for a single row address WEAK_ADDR of weak cells. However, the invention can also be implemented such that the comparator unit 450h has multiple sets of comparators and logic gates for multiple row addresses of weak cells. The initial refresh line address REF_ADDR, generated by the refresh counter 430h, is applied to the respective banks 365a and 365h via the line address multiplexers 340 shown in Fig. 4. Banks 365a and 365h receive the refresh line address REF_ADDR, the first bank match signals MATCH1_A and MATCH1_H respectively, and the second match signals MATCH2_A and MATCH2_H respectively. At least one of the first bank match signals MATCH1_A and MATCH1_H and at least one of the second bank match signals MATCH2_A and MATCH2_H are activated according to the bank flags BANKA_FLAG and BANKH_FLAG. Thus, the address change unit 470h only changes the initial refresh line address REF_ADDR in at least one selected memory bank where refresh leveraging is to be performed, as indicated by the bank flags BANKA_FLAG and BANKH_FLAG. The address change unit 470h is located at banks 365a and 365h. For example, address change unit 470h includes the respective first inverters 471h and 481h, first multiplexers 472h and 482h, second inverters 473h and 483h, and second multiplexers 474h and 484h in banks 365a and 365h. The respective final refresh line addresses CREF_ADDR from address change unit 470h are applied to the bank line decoders 360a, 360b, 360c, and 360d, respectively, shown in Fig. 4. In this way, the refresh address generator 400h allows a row with weak cells to be refreshed in at least one bank, instead of a row with strong cells, where refresh leveraging is to be performed, as indicated by the bank flags BANKA_FLAG and BANKH_FLAG. Thus, refresh leveraging is performed on a bank-by-bank basis, and the refresh period for the row with weak cells is reduced without increasing the refresh current or refresh power consumption. Fig. 27 illustrates steps for refreshing a volatile memory device using refresh leveraging with a plurality of rows of strong cells according to a further exemplary embodiment of the present invention. In Fig. 27, the minimum retention time of each row of weak cells is shorter than "refresh period (RP) / (L-1)" and longer than or equal to "refresh period (RP) / L", ​​where L is an integer greater than 1. Furthermore, L-1 first row addresses STR_ADDR_1s of strong cells and at least one second row address STR_ADDR_2 of strong cells are selected for each row address WEAK_ADDR of weak cells. In Fig. 27, when a refresh operation is initiated, a refresh counter is initialized, for example, to "0" (S1110), and a flag SGR_FLAG of strong cells is initialized to a low logic level. The initial refresh row address REF_ADDR is compared with the first L-1 row addresses STR_ADDR_1s of strong cells (S1120) and the at least one second row address STR_ADDR_2 of strong cells (S1125). In an exemplary embodiment of the invention, such comparisons (S1120 and S1125) are performed essentially simultaneously. If the initial refresh row address REF_ADDR does not match any of the first row addresses STR_ADDR_1s of strong cells (S1120: NO) or the second row addresses STR_ADDR_2 of strong cells (S1125: NO), a memory cell row corresponding to the initial refresh row address REF_ADDR is refreshed (S1140). If the refresh row address REF_ADDR matches any of the first row addresses STR_ADDR_1s (S1120: YES), a row of weak cells corresponding to the row address WEAK_ADDR of weak cells is refreshed (S1150). If the initial refresh row address REF_ADDR matches the second row address STR_ADDR_2 of strong cells (S1125: YES) and the strong cell flag STR_FLAG is at a low logic level (S1130: YES), a memory cell row corresponding to the initial refresh row address REF_ADDR is refreshed (S1140). If the initial refresh row address REF_ADDR matches the second row address STR_ADDR_2 of strong cells (S1125: YES) and the strong cell flag STR_FLAG is at a high logic level (S1130: NO), a first row of strong cells corresponding to one of the first row addresses STR_ADDR_1s of strong cells is refreshed (S1160). The refresh row address REF_ADDR is incremented by 1 each time a memory cell row is refreshed (S1170). If the refresh row address REF_ADDR exceeds the maximum row address MAX_ADDR (S1180: YES), the refresh row address REF_ADDR is initialized, and the strong cell flag STR_FLAG is inverted at each refresh period RP (S1185). In this way, a row with weak cells is refreshed instead of the majority of initial rows with strong cells. Accordingly, even if the minimum retention time of the row with weak cells is shorter than half the refresh period RP, the row with weak cells is refreshed repeatedly before the minimum retention time is reached, and the row with weak cells does not need to be replaced by a row of redundant cells. Furthermore, the refresh period of the row with weak cells is reduced without increasing the refresh current or refresh power consumption. Fig. 28 shows a time-based diagram of exemplary refreshes of a row with weak cells and of several first and second rows with strong cells, performed according to the refresh method of Fig. 27, in an exemplary embodiment of the invention. Fig. 28 represents an example of a row with weak cells being refreshed instead of three first rows with strong cells, wherein the three first rows with strong cells and three second rows with strong cells are refreshed alternately in each refresh period RP. Referring to Fig. 28, the row with weak cells is refreshed four times per refresh period. For example, in each refresh period RP, a refresh 1110 is performed for the row with weak cells when a row address is generated for the row with weak cells. Furthermore, refreshes 1111, 1112, and 1113 are performed for the row with weak cells instead of refreshes 1121, 1122, and 1123 for the first rows with strong cells when row addresses are generated for the first rows with strong cells. Each of the first rows of strong cells and the second row of strong cells is refreshed with a period 2RP, which is twice the refresh period RP. For example, in odd-numbered refresh periods, refreshes 1131, 1132, and 1133 are performed for the second rows of strong cells, and in even-numbered refresh periods, refreshes 1126, 1127, and 1128 are performed for the first rows of strong cells instead of refreshes 1136, 1137, and 1138 for the second row of strong cells. Fig. 29 shows a bank 600i of a memory element with one row of weak cells and several first and second rows of strong cells according to an exemplary embodiment of the invention. Fig. 29 shows an example in which a minimum retention time of a row 610i with weak cells is shorter than "refresh period (RP) / 3" and longer than or equal to "refresh period (RP) / 4". Fig. 29 also shows three first rows 621i, 622i and 623i with strong cells and three second rows 631i, 632i and 633i with strong cells, which are selected for the row 610i with weak cells. Referring to Fig. 29, a line address WEAK_ADDR of weak cells for line 610i containing weak cells is determined by examining the memory cell array. By inverting one N-1th bit of a line address WEAK_ADDR of weak cells for line 610i containing weak cells, a STR_ADDR_1_1 of three line addresses of strong cells for the first lines 621i, 622i, and 623i is determined. Another STR_ADDR_1_2 of the three line addresses of strong cells is determined by inverting one N-th bit (i.e., the MSB) of the line address WEAK_ADDR of weak cells. The other STR_ADDR_1_3 of the three line addresses of strong cells is determined by inverting the N-th bit and the N-1-th bit of the line address WEAK_ADDR of weak cells. Row 610i, containing weak cells, is refreshed instead of the first three rows 621i, 622i, and 623i, which contain strong cells corresponding to the first three row addresses STR_ADDR_1_1, STR_ADDR_1_2, and STR_ADDR_1_3. Thus, row 610i, containing weak cells, is refreshed with a period of one-quarter of the refresh period RP. Any three memory cell rows with minimum retention times longer than or equal to twice the refresh period RP can be selected as the three second rows 631i, 632i, and 633i with strong cells. For example, three second row addresses STR_ADDR_2_1, STR_ADDR_2_2, and STR_ADDR_2_3 of strong cells are designated for the three second rows 631i, 632i, and 633i by inverting the LSBs of the three first row addresses STR_ADDR_1_1, STR_ADDR_1_2, and STR_ADDR_1_3 of strong cells. The method for determining the first and second rows 621i, 622i, 623i, 631i, 632i, and 633i with strong cells of Fig. 29 can be applied to a case where the first and second rows 621i, 622i, 623i, 631i, 632i, and 633i with strong cells have minimum retention times that are longer than or equal to twice the refresh period RP. In an alternative embodiment of the invention, if rows with strong cells have minimum retention times that are longer than or equal to four times the refresh period RP, three first rows with strong cells and one second row with strong cells for each row with weak cells can be selected, as shown in Fig. 31. Fig. 30 shows a refresh address generator 400i for performing the refresh procedure of Fig. 27 according to a further exemplary embodiment of the invention. In Fig. 30, first and second line addresses STR_ADDR_1_1, STR_ADDR_1_2, STR_ADDR_1_3, STR_ADDR_2_1, STR_ADDR_2_2 and STR_ADDR_2_3 are set, as shown in Fig. 29. The refresh address generator 400i includes an address storage unit 410i, a refresh counter 430i, a comparison unit 450i, and an address change unit 470i. The address storage unit 410i includes a first memory area 411i for storing one of the first row addresses STR_ADDR_1_1, STR_ADDR_1_2, and STR_ADDR_1_3 of strong cells. Fig. 30 shows the address storage unit 410i, which stores a first row address STR_ADDR_1_1 of strong cells, which is related to a row address WEAK_ADDR of weak cells. However, the invention can also be implemented such that the address storage unit 410i stores several first row addresses of strong cells for several row addresses of weak cells. The refresh counter 430i generates a refresh row address REF_ADDR and a flag STR_FLAG from strong cells by counting. The comparator unit 450i generates initial match signals MATCH1_1, MATCH1_2, and MATCH1_3 by comparing the refresh row address REF_ADDR with the first row addresses STR_ADDR_1_1, STR_ADDR_1_2, and STR_ADDR_1_3, respectively, of strong cells. Furthermore, based on the flag STR_FLAG from strong cells and by comparing the refresh row address REF_ADDR with the second row addresses STR_ADDR_2_1, STR_ADDR_2_2, and STR_ADDR_2_3 of strong cells, the comparator unit 450i generates secondary match signals MATCH2_1, MATCH2_2, and MATCH2_3. The comparator unit 450i includes a plurality of comparators 451i, 452i, 453i and 454i as well as a plurality of logic gates 455i, 456i, 457i, 458i, 459i, 460i, 461i, 462i, 463i, 464i, 465i, 466i, 467i, 468i and 469i. The comparators 451i, 452i, 453i and 454i, first inverters 458i, 459i and 463i and first AND gates 455i, 460i and 464i are configured to activate one of the first matching signals MATCH_1, MATCH_2 and MATCH_3 when the refresh row address REF_ADDR matches one of the corresponding first row addresses STR_ADDR_1_1, STR_ADDR_1_2 and STR_ADDR_1_3 of strong cells. The comparators 451i, 452i, 453i and 454i, second inverters 456i, 461i and 465i, second AND gates 457i, 462i and 466i and third AND gates 467i, 468i and 469i are configured to activate one of the second matching signals MATCH2_1, MATCH2_2 and MATCH2_3 when the refresh line address REF_ADDR matches a corresponding second line address STR_ADDR_2_1, STR_ADDR_2_2 and STR_ADDR_2_3 of strong cells and the flag STR_FLAG of strong cells is at a high logic level. Fig. 30 shows the comparator unit 450i, which includes a set of comparators 451i, 452i, 453i and 454i and logic gates 455i, 456i, 457i, 458i, 459i, 460i, 461i, 462i, 463i, 464i, 465i, 466i, 467i, 468i and 469i for a single row address WEAK_ADDR of weak cells. However, the invention can also be implemented such that the comparator unit 450i has several corresponding sets of comparators and logic gates for multiple row addresses of weak cells. The address change unit 470i includes a plurality of OR gates 471i, 472i, and 473i, a plurality of inverters 481i, 483i, 485i, 487i, and 488i, and a plurality of multiplexers 482i, 484i, and 486i. These components of the address change unit 470i are configured to output the WEAK_ADDR row address of weak cells as a final refresh row address CREF_ADDR when any of the first match signals MATCH1_1, MATCH1_2, and MATCH1_3 are at a high logic level. The address change unit 470i outputs one of the first row addresses STR_ADDR_1_1, STR_ADDR_1_2 and STR_ADDR_1_3 of strong cells as the final refresh row address CREF_ADDR when a corresponding second match signal MATCH1_1, MATCH1_2 and MATCH1_3 is at a high logic level. In this way, the refresh address generator 400i outputs the row address WEAK_ADDR from weak cells when the refresh counter 430i generates one of the first row addresses STR_ADDR_1_1, STR_ADDR_1_2, and STR_ADDR_1_3 from strong cells. Accordingly, even if the minimum retention time of the weak cell row is shorter than half a refresh period RP, the weak cell row is refreshed repeatedly before the minimum retention time is reached, and the weak cell row does not need to be replaced by a row of redundant cells. Furthermore, the refresh period of the weak cell row is reduced without increasing the refresh current or refresh power consumption. Fig. 31 shows a time-based diagram of exemplary refreshes of a row with weak cells, several first rows with strong cells, and a second row with strong cells, performed according to the refresh method of Fig. 27, in an exemplary embodiment of the invention. In Fig. 31, a row with weak cells is refreshed instead of three first rows with strong cells, and the three first rows with strong cells and a second row with strong cells are refreshed alternately with a period approximately four times a refresh period RP. Referring to Fig. 31, a row with weak cells is refreshed four times per refresh period RP. For example, during each refresh period RP, a refresh 1110 is performed for the row with weak cells when a row address is generated for the row with weak cells, and further refreshes 1111, 1112, and 1113 for the row with weak cells are performed instead of refreshes 1121, 1122, and 1123 for the first rows with strong cells when row addresses are generated for the first rows with strong cells. Each of the first rows with strong cells and the second row with strong cells is refreshed with a period equal to four times the refresh period RP. For example, a refresh of 1131 is performed for the second row with strong cells in 4I+1 refresh periods, where I is an integer greater than or equal to 0. Also, in 4I+2 refresh periods, a refresh of 1126 is performed for one of the first rows with strong cells instead of a refresh of 1136 for the second row with strong cells. In 4I+3 refresh periods, a refresh of 1127 is performed for another of the first rows with strong cells instead of a refresh of 1137 for the second row with strong cells. In 4I+4 refresh periods, a refresh of 1128 is performed for the other of the first rows with strong cells instead of a refresh of 1138 for the second row with strong cells. In this example, an N+2-bit refresh counter can be used to refresh the first rows of strong cells and the second row of strong cells alternately at a period four times the refresh period. In this case, the upper two count bits generated by the N+2-bit counter are used as a 2-bit strong cell flag to select one of the first three rows of strong cells and the second row of strong cells. The first rows of strong cells and the second row of strong cells, refreshed as shown in Fig. 31, can have minimum retention times longer than or equal to four times the refresh period RP. Fig. 32 shows a timing diagram illustrating exemplary refreshes performed for each quarter of rows of a memory array in burst mode, according to an exemplary embodiment of the invention. For example, one quarter of memory cell rows of a memory cell array is refreshed sequentially. In this case, four refreshes are performed for a row with weak cells if the four quarters of the memory cell rows are refreshed each time. Accordingly, the row with weak cells itself is refreshed in a burst refresh mode with a period RP / 4, which is one quarter of the refresh period RP. Fig. 33 shows a refresh address generator 500 with multiple comparison units contained in the volatile memory element of Fig. 4 according to a further exemplary embodiment of the invention. The refresh address generator 500 includes a plurality of address storage units 510_1 and 501_M, a refresh counter 530, a plurality of comparison units 550_1 and 550_M, an OR operation unit 590, and an address change unit 570. The plurality of address storage units 510_1 and 510_M store a plurality of address information sets ADDR_INFO_1 and ADDR_INFO_M, respectively, for a plurality of rows containing weak cells. In an exemplary embodiment of the present invention, the address information sets ADDR_INFO_1 and ADDR_INFO_M each include at least one row address of weak cells and row addresses of strong cells that are related to the row address of weak cells. Alternatively, each of the address information sets ADDR_INFO_1 and ADDR_INFO_M includes the result of a predefined operation (e.g., an XOR operation) performed on the row address of weak cells and / or the row addresses of strong cells. In one embodiment of the invention, the plurality of address storage units 510_1 and 510_M are implemented with a single memory element. Alternatively, the plurality of address storage units 510_1 and 510_M are implemented with a plurality of memory elements. For example, each memory element can be an electrically programmable fuse memory, a laser-programmable fuse memory, an anti-fuse memory, a one-time programmable memory, a flash memory, or other types of non-volatile memory. The refresh counter 530 counts to generate an initial refresh row address REF_ADDR with N bits, where N is an integer greater than 1. The refresh counter 530 further generates a strong cell flag STR_FLAG to control refreshes of rows containing strong cells. In an exemplary embodiment of the invention, the refresh counter 530 is an N+M bit counter, where M is an integer greater than 0. The comparison units 550_1 and 550_M are coupled to the address storage units 510_1 and 510_M, respectively. These units compare the refresh line address REF_ADDR from the refresh counter 530 with the respective address information ADDR_INFO_1 and ADDR_INFO_M, which is read from the address storage units 510_1 and 510_M. Based on the STR_FLAG flag of strong cells, they generate corresponding match signals MATCH_1 and MATCH_M. The OR operation unit 590 then performs an OR operation on the MATCH_1 and MATCH_M signals to generate a match signal MATCH. The address change unit 570 can change the initial refresh row address REF_ADDR in response to the MATCH signal. For example, the address change unit 570 changes the initial refresh row address REF_ADDR to a row address for weak cells or a first row address for strong cells. In this way, the refresh address generator 500 stores the address information ADDR_INFO_1 and ADDR_INFOM_M for the majority of rows with weak cells, enabling the refreshing of rows with weak memory cells instead of rows with strong cells. Consequently, the refresh periods for rows with weak cells are reduced without increasing the refresh current or power consumption. Fig. 34 shows an exemplary refresh address generator 500a with several comparator units according to a further exemplary embodiment of the invention. In Fig. 34, first row addresses STR_ADDR_1 of strong cells are determined by inverting MSBs of row addresses of weak cells, and second row addresses of strong cells are determined by inverting LSBs of the first row addresses STR_ADDR_1 of strong cells. The refresh address generator 500a includes a plurality of address storage units 510_1a and 510_Ma, a refresh counter 530a, a plurality of comparison units 550_1a and 550_Ma, OR operation units 591a and 592a, and an address change unit 570a. The address storage units 510_1a and 510_Ma each include a memory area 511_1a for storing a respective first row address STR_ADDR_1 of strong cells, which is related to a respective row address of weak cells. In an alternative embodiment of the present invention, the address storage units 510_1a and 510_Ma store a plurality of second row addresses of strong cells or a plurality of row addresses of weak cells instead of the first row addresses STR_ADDR_1 of strong cells. The address storage units 510_1a and 510_Ma provide the first row addresses STR_ADDR_1 of strong cells to the comparison units 550_1a and 550_Ma, respectively. For example, a first address storage unit 510_1a provides the first to Nth bits SA11_1, SA12_1, and SA1N_1 of each of the first row addresses STR_ADDR_1 of strong cells to a first comparison unit 550_1a. Similarly, an M-th address storage unit 510_Ma provides the first to Nth bits SA11_M, SA12_M, and SA1N_M of each of the first row addresses STR_ADDR_1 of strong cells to an M-th comparison unit 550_Ma. The refresh counter 530a generates an initial refresh row address REF_ADDR and a strong cell flag STR_FLAG by counting. The refresh counter 530a is an N+1 bit counter, where the MSB of the count value is the strong cell flag STR_FLAG and the lower N bits of the count value are used as the initial refresh row address REF_ADDR. The comparison units 550_1a and 550_Ma generate a plurality of first match signals MATCH1_1 and MATCH1_M by comparing the initial refresh row address REF_ADDR with the respective first row addresses STR_ADDR_1 of strong cells. The comparison units 550_1a and 550_Ma also generate a plurality of second match signals MATCH2_1 and MATCH2_M based on the flag STR_FLAG of strong cells and by comparing the initial refresh row address REF_ADDR with the respective second row addresses of strong cells. Each comparison unit 550_1a or 550_Ma contains a respective plurality of comparators 551a, 552a, and 553a, as well as a respective plurality of logic gates 561a, 562a, 563a, and 564a. The OR operation units 591a and 592a are a first OR gate 591a and a second OR gate 592a. The first OR gate 591a generates a first match signal MATCH1 by performing a first OR operation on the plurality of first match signals MATCH1_1 and MATCH1_M. The second OR gate 592a generates a second match signal MATCH2 by performing a second OR operation on the plurality of second match signals MATCH2_1 and MATCH2_M. For example, if the refresh line address REF_ADDR matches one of the majority of first line addresses STR_ADDR_1 of strong cells, a corresponding majority of first match signals MATCH1_1 and MATCH1_M is at a high logic level, so the first OR gate 591a outputs the first match signal MATCH1 at a high logic level. If the refresh line address REF_ADDR matches one of the majority of second line addresses of strong cells and the flag STR_FLAG of strong cells is at a high logic level, a corresponding majority of second match signals MATCH2_1 and MATCH2_M is at a high logic level, so the second OR gate 592a outputs the second match signal MATCH2 at a high logic level. The address change unit 570a includes inverters 571a, 573a, 581a, 582a, 583a, and 584a, as well as multiplexers 572a and 574a. These components are configured to output a corresponding row address for weak cells by inverting the MSB of the refresh row address REF_ADDR in response to the first match signal MATC1. Alternatively, the address change unit 570a outputs a corresponding first row address for strong cells by inverting the LSB of the refresh row address REF_ADDR in response to the second match signal MATCH2. In this way, the refresh address generator 500a outputs a corresponding row address from weak cells when the refresh counter 530a generates one of the majority of first row addresses STR_ADDR_1 from strong cells. Furthermore, during each refresh period RP, the refresh address generator 500a alternately outputs one of the first row addresses from strong cells or one of the second row addresses from strong cells when the refresh counter 530a generates one of the second row addresses from strong cells. Accordingly, the refresh address generator 500a allows rows with weak cells to be refreshed instead of first rows with strong cells, thus reducing refresh periods for rows with weak cells without increasing the refresh current or refresh power consumption. Fig. 35 shows a refresh address generator 500b with several comparator units according to a further exemplary embodiment of the invention. In Fig. 35, first row addresses of strong cells are determined by inverting the respective MSB of the row addresses WEAK_ADDR of weak cells, and second row addresses of strong cells are determined by inverting the LSB of the first row addresses of strong cells. The refresh address generator 500b includes a plurality of address storage units 510_1b and 510_Mb, a refresh counter 530b, first and second inverters 581b and 582b, a plurality of comparison units 550_1b and 550_Mb, an address change unit 570b, and an OR operation unit with a first OR gate 591b, a second OR gate 592b, and an AND gate 593b. Each of the address storage units 510_1b and 510_MB includes a respective memory area 511_1a for storing a respective row address of weak cells. In an alternative embodiment of the invention, the address storage units 510_1b and 510_Mb store a plurality of first row addresses of strong cells or a plurality of second row addresses of strong cells instead of the plurality of row addresses WEAK_ADDR of weak cells. The address storage units 510_1b and 510_Mb assign the row addresses WEAK_ADDR of weak cells to the respective comparison units 550_1b and 550_Mb. The refresh counter 530b generates an initial refresh row address REF_ADDR and a flag STR_FLAG of strong cells by counting. The first inverter 581b inverts the first bit RA1 of the refresh row address REF_ADDR, and the second inverter 582b inverts the Nth bit RAN of the refresh row address REF_ADDR. The number or connections of inverters 581b and 582b can vary according to a method by which the first and second rows of strong cells are selected, and / or according to address information stored in the plurality of address memory units 510_1b and 510_Mb. For example, in a case where the plurality of first row addresses of strong cells are stored in address memory units 510_1b and 510_Mb, the refresh address generator might not include the second inverter 582b. The majority of comparator units 550_1b and 550_Mb receive a first bit, an inverted first bit, second to Nth bits, and an inverted Nth bit of the refresh line address REF_ADDR from the refresh counter 530b and the inverters 581b and 582b. The majority of comparator units 550_1b and 550_Mb also receive the line addresses WEAK_ADDR of weak cells from the address storage units 510_1b and 510_Mb, respectively. Each of the comparison units 550_1b and 550_Mb includes a first N-bit comparator 551b and a second N-bit comparator 552b. The first N-bit comparator 551b receives the first to N-1th bits and the inverted Nth bits of the refresh line address REF_ADDR at a first input terminal IN1. The first N-bit comparator 551b also receives the line address WEAK_ADDR of weak cells at a second input terminal IN2. The first N-bit comparator 551b produces a high-level output signal when the first to N-1 bits and the inverted N-th bit of the refresh line address REF_ADDR match the first to N bits of the line address WEAK_ADDR of weak cells. Thus, when the refresh line address REF_ADDR matches the first line address of strong cells, the first N-bit comparator 551b produces the high-level output signal. The second N-bit comparator 552b receives the inverted first bit, the second to N-1th bits, and the inverted Nth bit of the refresh row address REF_ADDR at a first input terminal IN1. The second N-bit comparator 552b also receives the row address WEAK_ADDR of weak cells at a second input terminal IN2. The second N-bit comparator 552b generates a high-level output signal when the inverted first bit, the second through N-1th bits, and the inverted Nth bit of the refresh row address REF_ADDR match the first through Nth bits of the row address WEAK_ADDR of weak cells. Thus, if the initial refresh row address REF_ADDR matches a second row address of strong cells, the second N-bit comparator 552b generates the high-level output signal. The first OR gate 591b generates a first match signal MATCH1 by performing an OR operation on the output signals of the first N-bit comparators 551b and the plurality of comparison units 550_1b and 550_Mb. The first OR gate 591b outputs the first match signal MATCH1 at a high logic level if the refresh row address REF_ADDR matches one of the plurality of first row addresses of strong cells. The second OR gate 592b performs an OR operation on the output signals of the second N-bit comparators 552b of the plurality of comparison units 550_1b and 550_Mb. The AND gate 593b performs an AND operation on an output signal of the second OR gate 592b and the STR_FLAG flag of strong cells. The second OR gate 592b and the AND gate 593b are configured to generate a second match signal MATCH2 at a high logic level when the refresh line address REF_ADDR matches one of the plurality of second line addresses of strong cells and when the STR_FLAG flag of strong cells is at a high logic level. The address change unit 570b can change the initial refresh row address REF_ADDR to a corresponding row address of weak cells in response to the first matching signal MATCH1. The address change unit 570b can also change the refresh row address REF_ADDR to a corresponding first row address of strong cells in response to the second matching signal MATCH2. In this way, the refresh address generator 500b allows rows with weak cells to be refreshed instead of the first rows with strong cells, thus reducing refresh periods for weak cell rows without increasing refresh current or power consumption. Fig. 36 shows a refresh address generator 500c with multiple comparator units according to a further exemplary embodiment of the invention. In Fig. 36, first row addresses of strong cells are determined by inverting the MSBs of the row addresses WEAK_ADDR of weak cells. Furthermore, the second row addresses of strong cells are determined by inverting the LSBs of the first row addresses of strong cells. The refresh address generator 500c includes a plurality of odd-numbered address storage units 510_O_1c and 510_O_Lc, a plurality of even-numbered address storage units 510_E_1c and 510_E_Kc, a refresh counter 530c, a first and second inverter 581c and 582c, and a plurality of odd-numbered comparison units 550_O_1c and 550_O_Lc. The refresh address generator 500c also includes a plurality of even-numbered comparison units 550_E_1c and 550_E_Kc, an OR operation unit with a first and second OR gate 591c and 592c, a plurality of logic gates 593c, 594c, 595c, 596c, 597c and 598c, and an address change unit 570c. In the refresh address generator 500c according to an exemplary embodiment of the invention, the address storage units 510_O_1c, 510_O_Lc, 510_E_1c and 510_E_Kc are divided into a plurality of groups. Furthermore, a row address to be stored in the address storage units 510_O_1c, 510_O_Lc, 510_E_1c and 510_E_Kc can be stored in an address storage unit that is contained in a corresponding group according to at least one bit of the row address. For example, M address memory units 510_O_1c, 510_O_Lc, 510_E_1c and 510_E_Kc are subdivided into a first group, which contains L odd-numbered address memory units 510_O_1c and 510_O_Lc, and a second group, which contains K even-numbered address memory units 510_E_1c and 510_E_Kc, where L is an integer greater than 0, K is an integer greater than 0 and M equals L+K. Upper N-1 bits of a WEAK_ADDR row address of weak cells where the LSB is "1" are stored in the odd-numbered address memory units 510_O_1c and 510_O_Lc. Upper N-1 bits of a WEAK_ADDR row address of weak cells where the LSB is "0" are stored in the even-numbered address memory units 510_E_1c and 510_E_Kc. In an exemplary embodiment of the invention, L and K have different values. Alternatively, L and K have the same value of M / 2. The refresh counter 530c generates an initial refresh row address REF_ADDR and a strong cell flag STR_FLAG by counting. The first inverter 581c inverts the first bit RA1 of the refresh row address REF_ADDR, and the second inverter 582c inverts the Nth bit RAN of the refresh row address REF_ADDR. The number or connections of inverters 581c and 582c can vary according to a method for selecting the first and second rows of strong cells and / or according to address information stored in the address memory units 510_O_1c, 510_O_Lc, 510_E_1c, and 510_E_Kc. The majority of comparison units 550_O_1c, 550_O_Lc, 550_E_1c, and 550_E_Kc are coupled to the majority of address storage units 510_O_1c, 510_O_Lc, 510_E_1c, and 510_E_Kc, respectively. Similar to the majority of address storage units 510_O_1c, 510_O_Lc, 550_E_1c, and 510_E_Kc, these majority of comparison units are subdivided into a majority of groups. For example, M comparison units 550_O_1c, 550_O_Lc, 550_E_1c and 550_E_Kc are divided into a first group, which includes L odd-numbered comparison units 550_O_1c and 550_O_Lc, and a second group, which includes K even-numbered comparison units 550_E_1c and 550_E_Kc. The odd-numbered comparison units 550_O_1c and 550_O_Lc receive the second to Nth bits and an inverted Nth bit of the refresh row address REF_ADDR from the refresh counter 530c. Additionally, the odd-numbered comparison units 550_O_1c and 550_O_Lc also receive upper N-1 bits of the row address WEAK_ADDR from weak cells from the odd-numbered memory units 510_O_1c and 510_O_Lc. The even-numbered comparison units 550_E_1c and 550_E_Kc receive the second to Nth bits and the inverted Nth bit of the refresh row address REF_ADDR from the refresh counter 530c. The even-numbered comparison units 550_E_1c and 550_E_Kc also receive upper N-1 bits of the row address WEAK_ADDR from weak cells from the even-numbered address storage units 510_E_1c and 510_E_Kc. Each odd-numbered comparator 550_O_1c and 550_O_Lc includes a first N-1-bit comparator 551c, and each even-numbered comparator 550_E_1c and 550_E_Kc includes a second N-1-bit comparator 552c. Each of the first N-1-bit comparator 551c and the second N-1-bit comparator 552c compares the upper N-1 bits of the refresh row address REF_ADDR, of which an Nth bit RAN (i.e., MSB) is inverted, with the upper N-1 bits of the row address WEAK_ADDR of weak cells. The first OR gate 591c performs an OR operation on the output signals of the odd-numbered comparison units 550_O_1c and 550_O_Lc. The second OR gate 592c performs an OR operation on the output signals of the even-numbered comparison units 550_E_1c and 550_E_Kc. Logic gates 593c, 594c, 595c, 596c, 597c, and 598c are configured to generate a first match signal MATCH1 and a second match signal MATCH2 based on the output signals of the first and second OR gates 591c and 592c, the first bit RA1 and its inversion from the refresh line address REF_ADDR, and the strong cell flag STR_FLAG. A first AND gate 593c performs an AND operation on the output signal of the first OR gate 591c and the first bit RA1 of the refresh line address REF_ADDR. The second AND gate 595c performs an AND operation on the output signal of the second OR gate 592c and the inverted first bit of the refresh line address REF_ADDR. If the upper N-1 bits of the refresh row address REF_ADDR, where the MSB is inverted, match the upper N-1 bits of the row address WEAK_ADDR of weak cells, and if the first bit RA1 (i.e., LSB) of the refresh row address REF_ADDR is '1', the first AND gate 593c produces a high logic level output signal. Since the row address WEAK_ADDR of weak cells, where the LSB is '1', is stored in the odd-numbered address memory units 510_O_1c and 510_O_Lc, the first AND gate 593c produces the high logic level output signal if only the MSB differs between the refresh row address REF_ADDR and the row address WEAK_ADDR of weak cells (i.e., if the initial refresh row address REF_ADDR matches a first row address of strong cells). If the upper N-1 bits of the refresh row address REF_ADDR, where the MSB is inverted, match the upper N-1 bits of the row address WEAK_ADDR of weak cells, and if the LSB of the refresh row address REF_ADDR is 0, the second AND gate 595c produces a high logic level output signal. Since the row address WEAK_ADDR of weak cells, where the LSB is 0, is stored in the even-numbered address memory units 510_E_1c and 510_E_Kc, the second AND gate 595c produces the high logic level output signal if only the MSB differs between the refresh row address REF_ADDR and the row address WEAK_ADDR of weak cells (i.e., if the refresh row address REF_ADDR matches a first row address of strong cells). A third AND gate 594c performs an AND operation on the output signal of the first OR gate 591c, the inverted first bit of the refresh row address, and the STR_FLAG flag of strong cells. A fourth AND gate 596c performs an AND operation on the output signal of the second OR gate 592c, the first bit RA1 of the refresh row address REF_ADDR, and the STR_FLAG flag of strong cells. If the upper N-1 bits of the refresh row address REF_ADDR, where the MSB is inverted, match the upper N-1 bits of the row address WEAK_ADDR of weak cells, and if the LSB of the refresh row address REF_ADDR is "0", and if the flag STR_FLAG of strong cells is at a high logic level, the third AND gate 594c produces a high logic level output signal. Since the row address WEAK_ADDR of weak cells, where the LSB is "1", is stored in the odd-numbered address memory units 510_O_1c and 510_O_Lc, the third AND gate 594c produces a high logic level output signal if the refresh row address REF_ADDR matches a second row address of strong cells, and if the flag STR_FLAG of strong cells is at a high logic level. If the upper N-1 bits of the refresh row address REF_ADDR, where the MSB is inverted, match the upper N-1 bits of the row address WEAK_ADDR of weak cells, the LSB of the refresh row address REF_ADDR is "1", and the flag STR_FLAG of strong cells is at a high logic level, the fourth AND gate 596c produces a high logic level output signal. Since the row address WEAK_ADDR of weak cells, where the LSB is "0", is stored in the even-numbered address memory units 510_E_1c and 510_E_Kc, the fourth AND gate 596c produces a high logic level output signal if the refresh row address REF_ADDR matches a second row address of strong cells and if the flag STR_FLAG of strong cells is at a high logic level. The third OR gate 597 generates the first match signal MATCH1 by performing an OR operation on the output signals of the first and third AND gates 593c and 594c. The third OR gate 597c generates the first match signal MATCH1 at a high logic level when the refresh row address matches one of a plurality of first row addresses of strong cells. The fourth OR gate 598c generates the second match signal MATCH2 by performing an OR operation on the output signals of the second and fourth AND gates 595c and 596c. The fourth OR gate 598c generates the second match signal MATCH2 with a high logic level if the refresh row address matches one of a plurality of second row addresses of strong cells and if the STR_FLAG flag of strong cells has a high logic level. The address change unit 570c can change the refresh row address REF_ADDR to a corresponding row address of weak cells in response to the first match signal MATCH1. The address change unit 570c can also change the refresh row address REF_ADDR to a corresponding first row address of strong cells in response to the second match signal MATCH2. In this way, the 500c refresh address generator allows rows with weak cells to be refreshed instead of the first rows with strong cells, thus reducing refresh periods for rows with weak cells without increasing refresh current or power consumption. Furthermore, since each comparator unit 550_O_1c, 550_O_Lc, 550_E_1c, and 550_E_Kc includes its own N-1-bit comparator, the 500c refresh address generator can be reduced in size and complexity. In Fig. 36, the address storage units and the comparison units are divided into odd and even groups according to the LSB of a row address of weak cells. However, the invention can also be implemented such that the address storage units and the comparison units are divided according to one or more arbitrary bits of a row address. For example, the address storage units and the comparison units can be divided into four groups according to the lower 2 bits of a row address of weak cells. In that case, upper N-2 bits of a row address (e.g., a row address of weak cells, a first row address of strong cells, or a second row address of strong cells) are stored in each address storage unit, and each comparison unit contains a respective N-2-bit comparator that compares the upper N-2 bits of a refresh row address with the upper N-2 bits of the row address stored in each address storage unit. Fig. 37 shows a refresh address generator 500d with several comparator units for several memory banks according to a further exemplary embodiment of the invention. The refresh address generator 500d includes A-th to H-th bank address storage units 510_A_1d, 510_A_Md, 510_H_1d and 510_H_Md, a refresh counter 530d, A-th to H-th comparator units 550_A_1d, 550_A_Md, 550_H_1d and 550_H_Md, an OR operation unit with OR gates and AND gates 591d, 592d, 593d, 594d, 595d and 596d, and an address change unit 570d. The address storage units 510_A_1d, 510_A_Md, 510_H_1d, and 510_H_Md are subdivided into multiple groups. A row address is stored in one of the address storage units 510_A_1d, 510_A_Md, 510_H_1d, and 510_H_Md that corresponds to a bank containing a corresponding row of weak cells. For example, the address storage units 510_A_1d, 510_A_Md, 510_H_1d, and 510_H_Md are subdivided according to A-th to H-th banks. In that case, a row address contained in bank A for a row of weak cells is stored in the A-th bank address storage units 510_A_1d and 510_A_Md. Similarly, a row address contained in bank H for a row with weak cells is stored in the H-th bank address storage units 510_H_1d and 510_H_Md. The refresh counter 530d generates an initial refresh row address REF_ADDR and a flag STR_FLAG of strong cells by counting. The refresh row address REF_ADDR is fed to the respective banks 365 via a row address multiplexer 340, similar to what is shown in Fig. 4. The comparison units 550_A_1d, 550_A_Md, 550_H_1d and 550_H_Md are divided into a plurality of groups, similar to the majority of address storage units 510_A_1d, 510_A_Md, 510_H_1d and 510_H_Md. For example, the comparison units 550_A_1d, 550_A_Md, 550_H_1d, and 550_H_Md are subdivided into A-th to H-th units corresponding to each memory bank. The A-th comparison units 550_A_1d and 550_A_Md compare the refresh line address REF_ADDR with line addresses received by the A-th bank address storage units 510_A_1d and 510_A_Md. The H-th comparison units 550_H_1d and 550_H_Md compare the refresh line address REF_ADDR with line addresses received by the H-th bank address storage units 510_H_1d and 510_H_Md. The OR operation unit includes a first, second, third, and fourth OR gate (591d, 592d, 594d, and 595d, respectively), as well as a first and second AND gate (593d and 596d, respectively). The first OR gate (591d) generates a first match signal, MATCH1_A, for Bank A. The second OR gate (592d) and the first AND gate (593d) generate a second match signal, MATCH2_A, for Bank A. Furthermore, the third OR gate (594d) generates a first match signal, MATCH1_H, for Bank H. The fourth OR gate (595d) and the second AND gate (596d) generate a second match signal, MATCH2_H, for Bank H. In an exemplary embodiment of the present invention, the address change unit 570d comprises components located at the respective banks 465. The address change unit 570d can change the initial refresh row address REF_ADDR in response to one of the first matching signals MATCH1_A and MATCH1_H for the respective banks 365 to a row address of weak cells as the final refresh row address in a corresponding bank. Furthermore, the address change unit 570d can change the refresh row address REF_ADDR in response to one of the second matching signals MATCH2_A and MATCH2_H for the respective banks 365 to a first row address of strong cells in a corresponding bank. For example, if the first match signal MATCH1_A for bank A is at a high logic level and other first match signals MATCH1_H are at a low logic level, the address change unit 570d generates the row address of weak cells as a final refresh row address CREF_ADDR_A in bank A, but generates the refresh row address REF_ADDR in the other banks, which is not changed as the final refresh row address. If the second match signal MATCH2_H for bank H is at a high logic level and other second match signals MATCH2_A are at a low logic level, the address change unit 570d generates the first row address of strong cells as the final refresh row address CREF_ADDR_H in bank H, but generates the refresh row address REF_ADDR in the other banks, which is not changed as the final refresh row address. In this way, the 500d refresh address generator allows rows with weak cells to be refreshed instead of the first rows with strong cells, thus reducing refresh periods for weak rows without increasing refresh current or power consumption. Furthermore, since the address storage units and comparison units are partitioned on a bank basis, refresh leveraging is performed in at least one selected bank, even if bank information is not stored in the address storage units. In Fig. 36, the address storage units and the comparison units are subdivided according to row addresses. In Fig. 37, the address storage units and the comparison units are subdivided according to banks. However, the invention can also be implemented such that the address storage units and the comparison units are subdivided according to both row addresses and banks. The foregoing exemplary embodiments of the invention were described for the use of rows with strong cells for refresh-leveraging a row with weak cells. However, the invention can also be implemented such that any unit of strong cells is used for refresh-leveraging any unit of a weak cell. For example, more generally, several strong cells can be used for refresh-leveraging a weak cell. Fig. 38 shows a memory module 1200 with a memory element featuring refresh leveraging, implemented according to exemplary embodiments of the invention. The memory module 1200 comprises a plurality of volatile memory elements 300. For example, the memory module 1200 is an unbuffered dual-in-line memory module (UDIMM), a registered dual-in-line memory module (RDIMM), a fully buffered dual-in-line memory module (FBDIMM), or a load-reduced dual-in-line memory module (LRDIMM). The memory module 1200 further includes a buffer 1210, which provides a command / address signal and data from a memory control unit via a plurality of transmission lines. In an exemplary embodiment, data transmission lines between the buffer 1200 and the volatile memory devices 300 are coupled in a point-to-point topology, and command / address transmission lines between the buffer 1200 and the volatile memory devices 300 are coupled in a multi-drop topology, a daisy-chain topology, a fly-by-daisy-chain topology, or the like. Since buffer 1200 buffers both the instruction / address signal and the data, the memory control unit acts as an interface to the memory module 1200 by driving only one load of buffer 1200. Accordingly, the memory module 1200 contains several volatile memory devices and / or several memory rows, and a memory system contains several memory modules. The volatile memory devices 300 perform refresh leveraging according to embodiments of the present invention, as described above. Thus, each of the volatile memory devices 300 refreshes at least one row of weak cells with a period that is shorter than a refresh period defined in the standard of the memory device, without increasing the refresh current and the refresh power consumption. Fig. 39 shows a mobile system 1400 with a refresh-leveraging memory element, implemented according to exemplary embodiments of the invention. The mobile system 1400 includes an application processor 1410, a connection unit 1420, a volatile memory element 1430, a non-volatile memory element 1440, a user interface 1450, and a power supply 1460. For example, the mobile system 1400 is a mobile phone, a smartphone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, or a navigation system. The 1410 application processor runs applications such as a web browser, a game application, or a video player. For example, the 1410 application processor may contain a single core or multiple cores, as in the case of a dual-core, quad-core, or hexa-core processor. The 1410 application processor may also include internal or external cache memory. The 1420 connection unit performs wired or wireless communication with an external component. For example, the 1420 connection unit performs Ethernet communication, near-field communication (NFC), radio-frequency identification (RFID) communication, mobile telecommunications, memory card communication, or communication via a universal serial bus (USB). For example, the 1420 connection unit includes a baseband chipset that supports communication protocols such as Global Mobile Communications (GSM), General Packet Radio Service (GPRS), Wideband Code Division Multiple Access (WCDMA), or High Speed ​​Downlink / Uplink Packet Access (HSxPA). The volatile memory device 1430 stores data that is processed by the application processor 1410 or functions as a working memory. For example, the volatile memory device 1430 is a random access dynamic memory, such as a DDR SDRAM, an LPDDR SDRAM, a GDDR SDRAM, or an RDRAM. Furthermore, the volatile memory device 1430 is a volatile memory device that performs a refresh operation with refresh leveraging according to the embodiments of the invention described above. Thus, the volatile memory device 1430 refreshes at least one row of weak cells with a period that is shorter than a refresh period defined in the standard of the memory device, without increasing the refresh current and refresh power consumption. The non-volatile memory element 1440 stores a boot image for starting the mobile system 1400. For example, the non-volatile memory element 1440 is an electrically erasable and programmable read-only memory (EEPROM), a flash memory, a phase-change random access memory (PRAM), a resistance random access memory (RRAM), a floating-gate nanomemory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), or a ferroelectric random access memory (FRAM). The user interface 1450 includes at least one input element, such as a keyboard or a touchscreen, and at least one output element, such as a speaker or a display device. The power supply 1460 provides power to the mobile system 1400. The mobile system 1400 may also include a camera image processor (CIS) and / or a storage element, such as a memory card, a solid-state drive (SSD), a hard disk drive (HDD), or a CD-ROM. The Mobile System 1400 and / or components of the Mobile System 1400 can be of any of the following types: Packaged-on-Package (PoP), Ball Grid Arrays (BGAs), Chip-Scale Packs (CSPs), Plastic-Leaded Chip Carriers (PLCCs), Plastic Dual-in-Line Packs (PDIPs), Die-in-Waffle Packs, Die-in-Wafer Forms, Chip-on-Board (COBs), Ceramic Dual-in-Line Packs (CERDIPs), Plastic Metric Quad Flat Packs (MQFPs), Thin Quad Flat Packs (TQFPs), Small-Outline ICs (SOICs), Shrink Small-Outline Packs (SSOPs), Thin Small-Outline Packages (TSOPs), System-in-Packs (SIPs), Multi-Chip Packs (MCPs), Wafer-Level Packs (WFPs), or Wafer-Level processed stackable packaging (WSP). Fig. 40 shows a computer system 1500 with a memory element featuring refresh leveraging, implemented according to exemplary embodiments of the invention. The computer system 1500 includes a processor 1510, an input / output hub (IOH) 1520, an input / output control hub (ICH) 1530, at least one memory module 1540, and a graphics card 1550. For example, the computer system 1500 is a personal computer (PC), a server computer, a workstation, a laptop computer, a mobile phone, a smartphone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a digital television, a set-top box, a music player, a portable game console, or a navigation system. The 1510 processor performs various computing functions, such as executing specific software to carry out specific calculations or tasks. For example, the 1510 processor is a microprocessor, a central processing unit (CPU), a digital signal processor, or the like, containing a single core or multiple cores, such as a dual-core, quad-core, or hexa-core processor. Figure 40 depicts the 1500 computer system, which includes a single 1510 processor; however, the 1500 computer system can also contain multiple processors. The 1510 processor can include internal or external cache memory. The processor 1510 includes a memory control unit 1511 for controlling operations of the memory module 1540. The memory control unit 1511, which is contained in the processor 1510, can be referred to as an integrated memory control unit (IMC). A memory interface between the memory control unit 1511 and the memory module 1540 can be implemented with a single channel, which includes a plurality of signal lines, or it can be implemented with multiple channels, each of which can be coupled to at least one memory module 1540. In some embodiments, the memory control unit 1511 can be located inside the input / output hub 1520, which can be referred to as a memory control hub (MCH). The 1540 memory module contains a plurality of volatile memory devices that store data provided by the 1511 memory control unit. The volatile memory devices perform an auto-refresh operation in response to a REF refresh instruction from the 1511 memory control unit and / or perform a self-refresh operation in response to a RSE self-refresh entry instruction from the 1511 memory control unit. During the auto-refresh operation or the self-refresh operation, the volatile memory devices perform refresh leveraging according to the embodiments of the present invention described above. This reduces the refresh period of at least one row with weak cells without increasing the refresh current or refresh power consumption. The 1520 input / output hub manages data transfer between the 1510 processor and components such as the 1550 graphics card. The 1520 input / output hub is connected to the 1510 processor via various interfaces. For example, the interface between the 1510 processor and the 1520 input / output hub can be a front-side bus (FSB), a system bus, HyperTransport, Lightning Data Transport (LDT), a QuickPath Intermediate Connection (QPI), or a Common System Interface (CSI). Figure 40 shows the Computer System 1500 with a single Input / Output Hub 1520; however, the Computer System 1500 can also include multiple Input / Output Hubs. The Input / Output Hub 1520 provides various interfaces to the components, such as an Accelerated Graphics Port (AGP) interface, a Peripheral Component Interface Express (PCIe) interface, or a Communications Streaming Architecture (CSA) interface. The 1550 graphics card is coupled to the 1520 input / output hub via AGP or PCIe to control a display device (not shown) to display an image. The 1550 graphics card includes an internal processor for processing image data and an internal memory component. For example, the 1520 input / output hub, located outside the 1550 graphics card, includes an internal graphics component along with, or instead of, the 1550 graphics card. The graphics component contained within the 1520 input / output hub can be referred to as integrated graphics. Furthermore, the 1520 input / output hub, which includes the internal memory control unit and the internal graphics component, can be referred to as a graphics and memory control hub (GMCH). The Input / Output Control Hub 1530 performs data buffering and interface allocation to efficiently operate various system interfaces. The Input / Output Control Hub 1530 is coupled to the Input / Output Hub 1520 via an internal bus, such as a Direct Media Interface (DMI), a hub interface, an Enterprise Southbridge Interface (ESI), or a PCIe interface. The Input / Output Control Hub 1530 provides an interface to peripheral components. For example, the Input / Output Control Hub 1530 offers a Universal Serial Bus (USB) port, a Serial Advanced Technology Attachment (SATA) port, a General Purpose Input / Output (GPIO) port, a Low Pin Count (LPC) bus, a Serial Peripheral Interface (SPI), a PCI interface, or a PCIe interface. The 1510 processor, the 1520 input / output hub, and the 1530 input / output control hub can be implemented as separate chipsets or separate integrated circuits. Alternatively, at least two of the 1510 processor, the 1520 input / output hub, and the 1530 input / output control hub can be implemented as a single chipset. Embodiments of the invention can be applied to any volatile memory device with a refresh operation and / or to a system with the volatile memory device.

Claims

A method for refreshing a memory element, comprising: - generating a refresh address with a refresh period, - performing each refresh at a weak cell with a first address when the refresh address is a second address, instead of a first strong cell with the second address, and - performing each refresh at a first strong cell or a second strong cell with a third address when the refresh address is the third address, - wherein address information is stored for only one of the first, second, and third addresses, and / or wherein the third address is selected from a pool of addresses with a range defined by at least two least significant bits of one of the first and second addresses. Method according to claim 1, wherein only one of the first, second and third addresses is stored and wherein the remaining two of the first, second and third addresses can be determined from a predetermined bit relationship. Method according to claim 1 or 2, wherein each of the first and second strong cells is not refreshed in every refresh period and wherein a further refresh is performed on the weak cell when the refresh address is the first address, so that the weak cell is refreshed several times during the refresh period. Method according to any one of claims 1 to 3, further comprising comparing the refresh address with the address information to determine if the refresh address is any of the second and third addresses. Method according to any one of claims 1 to 4, wherein the weak cell has a retention time that is shorter than the refresh period, and wherein the first and second strong cells each have a retention time that is longer than twice the refresh period. Method according to one of claims 1 to 5, wherein a respective refresh is performed on one of the first and second strong cells depending on a flag, if the refresh address is the third address. Method according to any one of claims 1 to 6, wherein the first and second addresses differ by inversion of a most significant bit and wherein the second and third addresses differ by inversion of a least significant bit. Method according to any one of claims 1 to 6, wherein the first and second addresses differ by inversion of a most significant bit and wherein the second and third addresses differ by inversion of a further bit that is not the most significant bit. Method according to any one of claims 1 to 6, wherein the third address is selected from a pool of addresses having a range defined by at least two least significant bits of one of the first and second addresses. A method according to any one of claims 1 to 9, wherein the first, second and third addresses are each a line address, and wherein the method further comprises: - performing a respective refresh on a weak line with the first address, if the refresh address is the second address, instead of a first strong line with the second address, and - performing a respective refresh on one of the first strong lines or a second strong line with the third address, if the refresh address is the third address. A method according to any one of claims 1 to 10, further comprising: - performing a respective refresh at a weak cell or the first strong cell depending on a flag, if the refresh address is the second address, and - performing a respective refresh at a weak cell or the second strong cell depending on the flag, if the refresh address is the third address. A method according to any one of claims 1 to 11, further comprising: - performing a refresh at the weak cell with the first address when the refresh address is the second address, instead of at the first strong cell in a selected memory bank, and - performing a refresh at a cell with the second address in a non-selected memory bank. The method of claim 12, further comprising: - performing a refresh on one of the first and second strong cells, if the refresh address is the third address in the selected memory bank, and - performing a refresh on a respective cell with the third address in the non-selected memory bank. Method according to any one of claims 1 to 13, further comprising performing a respective refresh at the weak cell when the refresh address is any one of several second addresses, instead of at respective cells of the second addresses. The method of claim 14, further comprising: - performing a refresh at one of the respective cells of the second addresses or of the respective cells of several third addresses, if the refresh address is any of the third addresses, or - performing a refresh at one of the respective cells of the second addresses or of the second strong cell, if the refresh address is the third address, or storing the second addresses for comparison with the refresh address, or - performing respective refreshes for a respective weak cell each time the refresh address is any of the respective several second addresses for each of the several memory banks. Refresh address generator comprising: - a counter (430) for generating an initial refresh address with a refresh period and - an address change unit (470) for generating a final refresh address, which is a first address of a weak cell, such that the weak cell is refreshed with a second address instead of a first strong cell if the initial refresh address is the second address, - wherein the address change unit generates the final refresh address as one of the second address and one of the third address of a second strong cell if the initial refresh address is the third address, and wherein one of the first and second strong cells is refreshed with the final refresh address, and - wherein a memory unit (410) for storing address information for only one of the first,the second and third addresses are provided and / or wherein the third address is selected from a pool of addresses with a range defined by at least two least significant bits of one of the first and second addresses. Refresh address generator according to claim 16, wherein the storage unit stores only one of the first, second and third addresses and wherein the remaining two of the first, second and third addresses can be determined from a predetermined bit relationship. Refresh address generator according to claim 16 or 17, wherein each of the first and second strong cells is not refreshed at every refresh period, and wherein the address change unit generates the final refresh address as the first address if the initial refresh address is the first address, so that the weak cell is refreshed several times during the refresh period. Refresh address generator according to one of claims 16 to 18, which further includes a comparison unit (450) for comparing the initial refresh address with the address information in order to determine if the initial refresh address is any of the second and third addresses. Refresh address generator according to one of claims 16 to 19, wherein the weak cell has a retention time that is shorter than the refresh period, and wherein the first and second strong cells each have a retention time that is longer than twice the refresh period. Refresh address generator according to one of claims 16 to 20, wherein the address change unit generates the final refresh address as one of the second and third addresses depending on a flag when the initial refresh address is the third address. Refresh address generator according to one of claims 16 to 21, wherein the first and second addresses differ by inversion of a most significant bit and wherein the second and third addresses differ by inversion of a least significant bit. Refresh address generator according to one of claims 16 to 21, wherein the first and second addresses differ by inversion of a most significant bit and wherein the second and third addresses differ by inversion of a further bit that is not the most significant bit. Refresh address generator according to one of claims 16 to 21, wherein the third address is selected from a pool of addresses with a range defined by at least two least significant bits of one of the first and second addresses. Refresh address generator according to one of claims 16 to 24, wherein the first, second and third addresses are each a row address, and wherein a refresh is performed on a weak row with the first address instead of on a first strong row with the second address when the initial refresh address is the second address, and wherein a refresh is performed on one of the first strong rows or a second strong row with the third address when the initial refresh address is the third address. Refresh address generator according to one of claims 16 to 25, wherein the address change unit generates the initial refresh address as one of the first and second addresses depending on a flag when the initial refresh address is the second address, and wherein the address change unit generates the final refresh address as one of the first and third addresses depending on the flag when the refresh address is the third address. Refresh address generator according to one of claims 16 to 26, wherein the storage unit stores bank address information such that a respective refresh is performed at the weak cell, if the initial refresh address is the second address, instead of at the first strong cell in a selected memory bank, as indicated by the bank address, and wherein a respective refresh is performed at a respective cell with the second address in a non-selected memory bank. Refresh address generator according to claim 27, wherein a respective refresh is performed on one of the first and second strong cells if the initial refresh address is the third address in the selected memory bank, and wherein a respective refresh is performed on a respective cell with the third address in the non-selected memory bank. Refresh address generator according to any one of claims 16 to 28, wherein the address change unit generates the final refresh address as the first address each time the initial refresh address is any one of several second addresses. Refresh address generator according to claim 29, wherein the address change unit generates the final refresh address as one of the second addresses and several third addresses if the initial refresh address is any of the third addresses, or generates the final refresh address as one of the second and third addresses if the initial refresh address is the third address. Refresh address generator according to claim 29 or 30, wherein the storage unit stores the second addresses for comparison with the initial refresh address. Refresh address generator according to one of claims 29 to 31, wherein respective refreshes for a respective weak cell are performed each time the initial refresh address is any of the respective multiple second addresses, for each of the multiple memory banks. Memory element comprising: - a cell array (380a to 380d) and - a refresh address generator (440) according to one of claims 16 to 32 for refreshing the cell array.

Images