Compute-task-state encapsulation

Abstract

A method for encapsulating and scheduling computational tasks, the method comprising: Allocating memory to store a task metadata structure; Storing initialization parameters in the task metadata structure that configure a streaming multiprocessor to execute a compute task; Storing scheduling parameters in the task metadata structure that control the scheduling of the computing task; Storing execution parameters in the task metadata structure that control execution of the computing task by the streaming multiprocessor; and Scheduling the compute task based on the scheduling parameters in the task metadata structure for execution of the compute task by the streaming multiprocessor based on the execution parameters in the task metadata structure.

Description

BACKGROUND OF THE INVENTIONField of the invention

[0001] The present invention relates generally to the execution of compute tasks and, more particularly, to the encapsulation of compute task state. Description of the technology in question

[0002] Conventional execution of computational tasks in multiprocessor systems receives processing tasks from a stream of instructions that encode state information for configuring the multiple processors to interleave data to be processed. The data is processed in the order in which the data appears in the stream. If processing of data later in the stream does not depend on the completion of processing of data earlier in the stream, the data can be processed out of order compared to the order in which the data appears in the stream. One advantage is that non-dependent processing tasks can be executed concurrently if suitable processing resources are available for multiple processing tasks. From the paper Kato et al., TimeGraph: GPU scheduling for real-time multi-tasking environments, USENIX ATC, 2011, is a method for the time-controlled allocation of GPU resources in multi-tasking systems using scheduling policies.

[0003] What is needed in the art, accordingly, is a system and method for encapsulating compute task state to enable out-or-order scheduling and execution of compute tasks. SUMMARY OF THE INVENTION

[0004] A system and method for encapsulating task state enables out-of-order or in-order scheduling and execution of the tasks. The scheduling circuitry organizes the tasks into groups based on priority levels. The tasks can then be selected for execution using different scheduling schemes. Each group is maintained as a linked list of pointers to tasks, encoded as task metadata (TMD) stored in memory. TMD encapsulates the state and parameters needed to initialize and execute a task.

[0005] Various embodiments of a method of the invention for encapsulating computing tasks include allocating memory to store a task metadata structure. The method also includes storing initialization parameters in the task metadata structure that configure a streaming multiprocessor to execute a computing task, storing scheduling parameters in the task metadata structure that control scheduling of the computing task, storing execution parameters in the task metadata structure that control execution of the computing task by the streaming multiprocessor, and executing the computing task.

[0006] Various embodiments of the invention include a system for encapsulating computing tasks, comprising a memory configured to store a task metadata structure corresponding to the computing tasks, and a multi-threaded processor. The multi-threaded processor is configured to allocate a portion of the memory to store the task metadata structure, store initialization parameters in the task metadata structure that configure the streaming multiprocessor to execute a computing task, store scheduling parameters in the task metadata structure that control the scheduling of the computing task, and store execution parameters in the task metadata structure that control the execution of the computing task by the multi-threaded processor. The multi-threaded processor is also configured to execute the computing task.

[0007] Encapsulating compute tasks in TMDs allows for scheduling the compute tasks for out-of-order execution. Additionally, the compute tasks can be executed concurrently, and parameters controlling the execution of the compute tasks can be encoded in the TMD. Initialization and execution scheduling parameters are used to configure streaming multiprocessor and memory resources for executing each TMD. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] So that the above-cited features of the present invention may be understood in detail, a particular description of the invention, briefly summarized above, may be taken by reference to embodiments, some of which are illustrated in the accompanying drawings. It is to be noted, however, that the accompanying drawings illustrate only typical embodiments of this invention and are therefore not to be construed as limiting its scope, for the invention may admit to other equally effective embodiments. Fig. 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the present invention; Fig. 2 is a block diagram of a parallel processing subsystem for the computer system of the Fig. 1, according to an embodiment of the present invention; Fig. 3 is a block diagram of the task / work unit of the Fig. 2, according to an embodiment of the invention; Fig. Figure 4A is another block diagram of the task / work unit of the Fig. 3, according to an embodiment of the invention; Fig. Figure 4B illustrates a flowchart of a method for loading an entry into the task metadata (TMD) cache of the Fig. 4A, according to an embodiment of the invention; Fig. Figure 5A is a conceptual diagram of the contents of a TMD of Fig. 3 and Fig. 4A, according to an embodiment of the invention; Fig. Figure 5B illustrates pointers to queue entries of Fig. 5A, according to an embodiment of the invention; Fig. Figure 6 illustrates a method for encapsulating compute task state in a lattice TMD of Fig. 3, Fig. 4A and Fig. 5, according to an embodiment of the invention; and Fig. Figure 7 illustrates a method for encapsulating compute task state in a queue TMD of Fig. 3, Fig. 4A and Fig. 5, according to an embodiment of the invention. DETAILED DESCRIPTION

[0009] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described to avoid obscuring the present invention. System overview

[0010] Fig. 1 is a block diagram illustrating a computer system 100 configured to implement one or more aspects of the present invention. Computer system 100 includes a central processing unit (CPU) 102 and system memory 104 communicating via an interconnection path, which may include a memory bridge 105. Memory bridge 105, which may be, for example, a northbridge chip, is connected to an I / O (input / output) bridge 107 via a bus or other communication path 106 (e.g., HyperTransport link). I / O bridge 107, which may be, for example, a southbridge chip, receives user input from one or more user input devices 108 (e.g., keyboard, mouse) and forwards the input to CPU 102 via path 106 and memory bridge 105. A parallel processing subsystem 112 is connected to the memory bridge 105 via a bus or other communication path 113 (e.g.a PCI Express Accelerated Graphics Port, or HyperTransport link); in one embodiment, the parallel processing subsystem 112 is a graphics subsystem that provides pixels to a display device 110 (e.g., a conventional CRT or LCD-based monitor). A system board 114 is also connected to the I / O bridge 107. A switch 116 provides connections between the I / O bridge 107 and other components, such as a network adapter 118 and various add-in cards 120 and 121. Other components (not explicitly shown), including USB or other port connections, CD drives, DVD drives, movie capture devices, and the like, may also be connected to the I / O bridge 107. Communication paths connecting the various components in . Fig. 1 interconnect may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect), PCI-Express, AGP (Accelerated Graphics Port), HyperTransport, or any bus or point-to-point communication protocol(s), and connections between different devices may use different protocols, as is known in the art.

[0011] In one embodiment, parallel processing subsystem 112 incorporates circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). In another embodiment, parallel processing subsystem 112 includes circuitry optimized for general-purpose processing while maintaining the underlying computer architecture described in greater detail herein. In yet another embodiment, parallel processing subsystem 102 may be integrated with one or more other system elements, such as memory bridge 105, CPU 102, and I / O bridge 107, to form a system-on-chip (SoC).

[0012] It will be appreciated that the system shown herein is illustrative and that variations and modifications are possible. The interconnect topology, including the number and arrangement of bridges, the number of CPUs 102, and the number of parallel processing subsystems 112, may be modified as desired. For example, in some embodiments, system memory 104 is directly coupled to CPU 102 rather than through a bridge, and other devices communicate with system memory 104 via memory bridge 105 and CPU 102. In other alternative topologies, parallel processing subsystem 112 is connected to I / O bridge 107 or directly to CPU 102 rather than to memory bridge 105. In still other embodiments, I / O bridge 107 and memory bridge 105 may be integrated into a single chip. Large embodiments may include two or more CPUs 102 and two or more parallel processing subsystems 112.The specific components shown herein are optional; for example, any number of add-on cards or peripheral devices could be supported. In some embodiments, switch 116 is eliminated, and network adapter 116 and add-on cards 120, 121 connect directly to I / O bridge 107.

[0013] Fig. Figure 2 illustrates a parallel processing subsystem 112 according to an embodiment of the present invention. As shown, the parallel processing subsystem 112 includes one or more parallel processing units (PPUs) 202, each of which is coupled to a local parallel processing (PP) memory 204. In general, a parallel processing subsystem includes a number U of PPUs, where U ≥ 1 (herein, multiple instances of similar objects are denoted by reference numbers identifying the object, and numbers in parentheses identify the instance, if needed). PPUs 202 and parallel processing memory 204 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or memory devices, or in any other technically feasible manner.

[0014] With reference again to Fig. 1, in some embodiments, some or all of the PPUs 202 in the parallel processing subsystem 112 are graphics processors with render pipelines that may be configured to perform various tasks including generating pixel data from graphics data supplied by the CPU 102 and / or system memory 104 via memory bridge 105 and communication path 113, interacting with local parallel processing memory 204 (which may be used as graphics memory, including, for example, a conventional frame buffer) to store and update pixel data, delivering pixel data to the display device 110, and the like. In some embodiments, the parallel processing subsystem 112 may include one or more PPUs 202 that operate as graphics processors and one or more other PPUs 202 that may be used for general-purpose computations.The PPUs may be identical or different, and each PPU may have its own dedicated parallel processing memory device(s) or may not have dedicated parallel processing memory device(s). One or more PPUs 202 may output data to the display device 110, or each PPU 202 may output data to one or more display devices 110.

[0015] In operation, CPU 102 is the master processor of computer system 100, which controls and coordinates operations of other system components. In particular, CPU 102 issues instructions that control the operation of PPUs 202. In some embodiments, CPU 102 writes a stream of instructions for each PPU 202 to a data structure (not explicitly described in either Fig. 1 more Fig. 2), which may be located in system memory 104, parallel processing memory 204, or any other memory location accessible to both CPU 102 and PPU 202. A pointer to each data structure is written to a push buffer to initiate processing of the stream of instructions in the data structure. PPU 202 reads instruction streams from one or more push buffers and then executes instructions asynchronously relative to the operation of CPU 102. Execution priorities may be specified for each push buffer to control scheduling of the various push buffers.

[0016] With reference now back to Fig. 2, each PPU 202 includes an I / O (input / output) unit 205 that communicates with the rest of computer system 100 via communication path 113, which connects to memory bridge 105 (or, in another embodiment, directly to CPU 102). The connection of PPU 202 to the rest of computer system 100 can also be varied. In some embodiments, parallel processing subsystem 112 is implemented as an add-on card that can be inserted into an expansion slot of computer system 100. In other embodiments, a PPU 202 can be integrated on a single chip with a bus bridge, such as memory bridge 105 or I / O bridge 107. In still other embodiments, some or all elements of PPU 202 can be integrated on a single chip with CPU 102.

[0017] In one embodiment, communication path 113 is a PCI Express link in which dedicated lanes are allocated to each PPU 202, as is known in the art. Other communication paths may also be used. An I / O unit 205 generates packets (or other signals) for transmission on communication path 113 and also receives any incoming packets (or other signals) from communication path 113, directing the incoming packets to the appropriate components of PPU 202. For example, commands relating to processing tasks may be directed to a host interface 206, while commands relating to memory operations (e.g., reading from or writing to parallel processing memory 204) may be directed to a memory crossbar unit 202.Host interface 206 reads each push buffer and outputs the work specified by the push buffer to a frontend 212.

[0018] Each PPU 202 advantageously implements a highly parallel processing architecture. As shown in detail, PPU 202(0) includes a processing cluster array 230 comprising a number C of general purpose processing clusters (GPCs) 208, where C ≥ 1. Each GPC 208 is capable of executing a large number (e.g., hundreds or thousands) of threads concurrently, where each thread is an instance of a program. In different applications, different GPCs 208 may be allocated to process different types of programs or to perform different types of computations. The allocation of GPCs 208 may vary depending on the workload encountered for each type of program or computation.

[0019] GPCs 208 receive processing tasks to be executed from a work distribution unit within a task / work unit 207. The work distribution unit receives pointers to computational processing tasks (task pointers), which are encoded as task metadata (TMD) and stored in memory. The task pointers to TMDs are included in the instruction stream, which is stored in a shift buffer and received from the host interface 206 via the front-end unit 212. Processing tasks, which may be encoded as TMDs, include indices of data to be processed, as well as status or state parameters and commands that define how the data is to be processed (e.g., which program is to be executed).The task / work unit 207 receives tasks from the frontend 212 and ensures that the GPCs 208 are configured in a valid state before initiating the processing specified by each of the TMDs. A priority may be specified for each TMD, which is used to schedule the execution of the processing tasks.

[0020] Memory interface 214 includes a number D of partition units 215, each directly coupled to a portion of parallel processing memory 204, where D ≥ 1. As shown, the number of partition units 215 is generally equal to the number of DRAM 220. In other embodiments, the number of partition units 215 need not be equal to the number of memory devices. Those skilled in the art will appreciate that DRAM 220 may be replaced by any other suitable memory devices and may be of a generally conventional design. A detailed description is therefore omitted. Render targets, such as frame buffers or texture maps, may be stored via DRAMs 220, allowing partition units 215 to write portions of each render target in parallel to effectively utilize the available bandwidth of parallel processing memory 204.

[0021] Any one of the GPCs 208 can process data to be written to any one of the DRAMs 220 within the parallel processing memory 204. Crossbar unit 210 is configured to route the output of each GPC 208 to the input of any partition unit 215 or to any GPC 208 for further processing. GPCs 208 communicate with the memory interface 214 through the crossbar 210 to write to or read from various external storage devices. In one embodiment, the crossbar unit 210 has a connection to memory interface 214 to communicate with I / O unit 205, as well as a connection to local parallel processing memory 204, thereby enabling the processing cores within the various GPCs 208 to communicate with system memory 104 or other memory that is not local to the PPU 202. In the Fig. In the embodiment shown in Figure 2, the crossbar unit 210 is directly connected to the I / O unit 205. The crossbar unit 210 can use virtual channels to separate traffic flows between the GPCs 208 and the partition units 215.

[0022] In turn, GPCs 208 may be programmed to perform processing tasks relating to a wide variety of applications, including, but not limited to, linear or non-linear data transformations, filtering of video and / or audio data, modeling operations (e.g., applying the laws of physics to determine position, velocity, and other attributes of objects), image rendering operations (e.g., tessellation shading, vertex shading, geometry shading, and / or pixel shading programs), etc.PPUs 202 may transfer data from system memory 104 and / or local parallel processing memory 204 to internal (on-chip) memory, process the data, and write result data back to system memory 104 and / or local parallel processing memory 204, where such data may be accessed by other system components, including CPU 102 or another parallel processing subsystem 112.

[0023] A PPU 202 may be provided with any amount of local parallel processing memory 204, including no local memory, and may use local memory and system memory in any combination. For example, a PPU 202 may be a graphics processor in a unified memory architecture (UMA) embodiment. In such embodiments, little or no dedicated graphics (parallel processing) memory would be provided, and PPU 202 would exclusively or almost exclusively use system memory. In UMA embodiments, a PPU 202 may be integrated into a bridge chip or processor chip, or provided as a discrete chip with a high-speed link (e.g., PCI Express) connecting the PPU 202 to system memory via a bridge chip or other communication means.

[0024] As noted above, any number of PPUs 202 may be included in a parallel processing subsystem 112. For example, multiple PPUs 202 may be provided on a single add-on card, or multiple add-on cards may be connected to the communication path 113, or one or more of the PPUs 202 may be integrated into a bridge chip. PPUs 202 in a multi-PPU system may be identical or different from one another. For example, different PPUs 202 could have different numbers of processing cores, different amounts or sizes of local parallel processing memory, etc. Where multiple PPUs 202 are present, these PPUs may be operated in parallel to process data at a higher throughput than is possible with a single PPU 202.Systems incorporating one or more PPUs 202 may be implemented in a variety of configurations and form factors, including desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, embedded systems, and the like. Multiple concurrent task scheduling

[0025] Multiple processing tasks can be executed concurrently on the GPCs 204, and a processing task can spawn one or more child processing tasks during execution. The task / work unit 207 receives the tasks and dynamically schedules the processing tasks and child processing tasks for execution via the GPCs 208.

[0026] Fig. 3 is a block diagram of the task / work unit 207 of the Fig. 2, according to one embodiment of the present invention. The task / work unit 207 includes a task management unit 300 and the work distribution unit 340. The task management unit 300 organizes tasks to be scheduled based on execution priority levels. For each priority level, the task management unit 300 stores a list of task pointers to the TMDs 322 corresponding to the tasks in the scheduler table 321, which list can be implemented with a linked list. The TMDs 322 can be stored in the PP memory 204 or system memory 104.The rate at which the task management unit 300 accepts tasks and stores the tasks in the scheduler table 321 is decoupled from the rate at which the task management unit 300 schedules tasks for execution, allowing the task management unit 300 to schedule tasks based on priority information or using other techniques.

[0027] The work distribution unit 340 includes a task table 345 with slots, each of which may be occupied by the TMD 322 for a task being executed. The task management unit 300 may schedule tasks for execution if there is a free slot in the task table 345. If there is no free slot, a higher-priority task that does not occupy a slot may displace or evict a lower-priority task that does occupy a slot. When a task is displaced or evicted, the task is stopped, and if the task's execution is incomplete, the task is added to a linked list in the scheduler table 321. When a child processing task is created, the child task is added to the linked list in the scheduler table 321. A child task may be created by means of a TMD 322 executing in the processing cluster array 230.A task is removed from a subject when the task is evicted.

[0028] Those in the technical field will understand that the architecture used in Fig. 1, Fig. 2 and Fig. 3 in no way limits the scope of the present invention and that the techniques taught herein may be implemented on any suitably configured processing unit, including, without limitation, one or more CPUs, one or more multi-core CPUs, one or more PPUs 202, one or more GPCs 208, one or more graphics or special-purpose processing units, or the like, without departing from the scope of the present invention. Task planning and management

[0029] The task management unit 300 manages compute tasks to be scheduled as an array of TMD groups stored in the scheduler table 321. A TMD group is a set of compute tasks with the same scheduling priority. The number of TMD groups or priority levels can be one or more. Within each TMD group, the compute tasks at the respective priority level are stored in a list, which can be implemented with a linked list, and a linked list is assumed below. Each TMD in a linked list stores a pointer to the next TMD in the corresponding linked list. A head pointer and a tail pointer for the linked list are stored for each TMD. A TMD group that has no tasks has a head pointer equal to the tail pointer, and an empty bit is set to true.

[0030] When computing tasks are received from the host interface, the task management unit 300 inserts the computing tasks into a TMD group. Specifically, a task pointer to the TMD corresponding to the computing task is added to the tail of the linked list for that group, unless a special TMD bit is set, which causes the task to be added to the head of the linked list. Although all tasks within a TMD group have the same scheduling priority level, the head of the TMD group linked list is the first computing task selected by the task management unit 300 and scheduled for execution. Thus, the computing task at the head of the linked list has a relatively higher priority compared to other computing tasks at the same priority level.Similarly, each subsequent compute task in the linked list at the same priority level has a lower priority relative to preceding compute tasks in the linked list. Therefore, task management unit 300 is able to schedule the compute tasks within a TMD group in entry order relative to each other (assuming none are specifically marked to be added to the head of the TMD group). Because the TMD group is specified as part of the TMD structure, the TMD group of a compute task cannot be changed while the compute task is executing. Compute tasks can also be received from processing cluster array 230.

[0031] Collecting compute tasks into groups based on priority levels prior to scheduling the compute tasks allows for decoupling the rate at which compute tasks are received by task management unit 300 from the rate at which compute tasks are issued to work distribution unit 340 for execution. Task management unit 300 is generally capable of receiving compute tasks from one or more shift buffers issued by host interface 206 at a higher rate than the compute tasks can be issued for execution by work distribution unit 340. The input to the various shift buffers are independent streams, typically generated by the same application program to have multiple sets of dependent tasks, but in some embodiments, multiple application programs may write to the shift buffers.The task management unit 300 may be configured to buffer the computing tasks in the scheduling table 321 and later select one or more computing tasks from the scheduling table 321 for output to the work distribution unit 340. By selecting the computing tasks after they are buffered, the task management unit can make the selection based on more information compared to selecting a computing task as computing tasks are received. For example, the task management unit 300 may buffer multiple low-priority tasks that are received before a high-priority task. Buffering allows the task management unit 300 to select the high-priority task for output before the low-priority tasks.

[0032] The task management unit 300 can perform a selection to schedule the computing tasks using several different techniques: round-robin, priority, or partitioned priority scheduling. For each of the different scheduling techniques, when a computing task is selected to be scheduled, the selected computing task is removed from the group in which the selected computing task is stored. Regardless of the scheduling technique, the task management unit 300 is able to quickly select a computing task by selecting the first entry in the linked list of the appropriate group. The task management unit 300 can easily organize and, if necessary, reorder computing tasks by simply changing the order of the task pointers in the linked lists of the TMD groups.Therefore, the computational tasks may be scheduled and / or executed in an order that is different from the order in which the task pointers are received from the host interface 206 by the task management unit 300.

[0033] The simplest scheduling scheme for task management unit 300 is to schedule the computing task at the head of each group (if a computing task exists in the group) and rotate it through the groups in a circular distribution order. Another scheduling technique is priority scheduling, which selects the computing tasks in strict priority order. Task management unit 300 selects a computing task from the highest-priority group that has at least one computing task, starting at the head of the group.

[0034] Fig. Figure 4A is another block diagram of the task / work unit 207 of the Fig. 3, according to one embodiment of the invention. The task / work unit 207 includes a task management unit 400 and a work distribution unit 440, which perform similar functions to the task management unit 300 and the work distribution unit 340. The task management unit 400 includes a scheduler table 421 and a TMD cache 405. The TMD cache 405 stores one or more TMDs 322. The work distribution unit 440 includes a task table 445.

[0035] Each TMD 322 can be a large structure, e.g., 256 bytes or more, which is typically stored in PP memory 204. Due to the large size, accessing the TMDs 322 is expensive in terms of bandwidth. Therefore, TMD cache 405 only stores the (relatively small) portion of the TMD 322 required by the task management unit 600 for scheduling. The remainder of the TMD 322 can be fetched from PP memory 204 when the task is scheduled, e.g., transferred to the work distribution unit 640.

[0036] The TMDs 322 are written under software control, and when a task completes execution, the TMD associated with the completed task can be recycled to store information for another task. Because a TMD 322 can be stored in the TMD cache 405, the entries storing information for the completed task should be deleted or flushed from the TMD cache 405. The flush operation is complicated because writing the information for the new task is decoupled from writing back information stored in the TMD cache 205 to the TMD 322 resulting from the flush. Specifically, the information for the new task is written to the TMD 322, and then the TMD 322 is output to the frontend 212 as part of a shift buffer.Thus, the software does not receive acknowledgment that the cache has been flushed, so a write to the TMD 322 may be delayed. Because the cache writeback may overwrite information stored in the TMD 322 for the new task, a "hardware-only" portion of each TMD 322 is set aside for access only by the task management unit 300 or 400. The remainder of the TMD 322 can be accessed by software and the task management unit 300 or 400. The portion of the TMD 322 that is accessible by software is typically filled by software to initiate a task. The TMD 322 is then accessed by the task management unit 600 and other processing units in the GPC 208 during task scheduling and execution.When information for a new task is written to a TMD 322, the instruction that launches or launches the TMD 322 may specify whether bits are to be copied into the hardware-only portion of the TMD 322 the first time the TMD 322 is loaded into the TMD cache 405. This ensures that the TMD 322 will correctly store only information for the new task, since any information for the completed task would have been stored only in the hardware-only portion of the TMD 322.

[0037] Fig. Figure 4B illustrates a flowchart for a method for loading an entry into the TMD cache 405 according to an embodiment of the invention. Although the method steps are described in connection with the systems of Fig. 1, Fig. 2, Fig. 3 and Fig. 4A, those skilled in the art will understand that any system configured to perform the method steps, in any order, is within the scope of the inventions.

[0038] At step 402, an entry in the TMD cache 405 is identified to be loaded with information stored in a TMD 322. The entry may be identified in response to a cache miss. At step 412, the task management unit 600 stores the TMD information in the cache entry. At step 420, the task management unit 400 determines whether the instruction launching or launching the TMD 322 specifies that bits be copied into the hardware-only portion of the TMD 322, and if so, then at step 450, filling the entry in the TMD cache 405 is done. Otherwise, at step 425, the task management unit 400 copies the bits from the part of the TMD 322 that is not the hardware-only part to the part of the entry that stores the hardware-only part of the TMD 322.Copying the bits from the part of the TMD 322 that is not hardware-only to the part of the entry that stores the hardware-only part of the TMD 322 overwrites data stored for the executed arithmetic task with data for the new arithmetic task. Compute-task-state encapsulation

[0039] Fig. 5A is a conceptual diagram of the contents of a TMD 322 stored in PP memory 204, according to one embodiment of the invention. The TMD 322 is configured to store initialization parameters 505, scheduling parameters 510, execution parameters 515, CTA state 520, a hardware-only field 422, and a queue 525. The hardware-only field 522 stores the hardware-only portion of the TMD 322, which includes one or more hardware-only parameters. A state, or status, common to all TMDs 322 is not included in each TMD 322. Because a TMD 322 is a data structure stored in PP memory 204, a computing program executing on CPU 102 or PPU 112 can create a TMD 322 structure in memory and then submit the TMD 322 for execution by sending a task pointer to the TMD 322 to the task / work unit 207.

[0040] The initialization parameters 505 are used to configure the GPCs 208 when the TMD 322 is introduced or launched and may include the startup program address and the size of the queue 525. Note that the queue 525 may be stored separately from the TMD 322 in memory, in which case the TMD 322 includes a pointer to the queue 525 (queue pointer) instead of the actual queue 525.

[0041] Initialization parameters 405 may also include bits to indicate whether various caches, such as a texture header cache, a texture sampler cache, a texture data cache, a data cache, a constant cache, and the like, are invalidated when TMD 322 is launched. A bit indicating whether texture samplers are linked 1:1 with texture heads may also be included in initialization parameters 505. Initialization parameters 505 may also include dimensions of a CTA in threads, a TMD version number, an instruction set version number, dimensions of a grid in CTA width, height, and depth, memory bank mapping parameters, depth of a call stack as seen by an application program, and a call-return stack size for the TMD.The initialization parameters 505 may include a size of a constant buffer, an address of the constant buffer, a bit indicating that a constant buffer bind is valid, and a bit indicating that the data from the constant buffer is invalidated in the cache before the TMD is initiated, and may be stored in the initialization parameters 505.

[0042] Finally, the initialization parameters 505 may include several parameters related to the amount of memory available to each thread of a CTA. When a TMD 322 requiring multiple CTAs, each requiring a large amount of shared memory, is ready to be scheduled for execution, the task / work unit 207 may limit (i.e., throttle) the number of CTAs executing concurrently so that the CTAs do not attempt to consume more memory than is available for access via the TMD 322. Examples of parameters related to the amount of memory available to each thread of a CTA include a size of one or more local memory regions, a number of registers, an amount of memory that can be allocated directly via the TMD 322 through an L1 cache, an amount of shared memory for a single CTA, and a number of barrier operations for each CTA.

[0043] Scheduling parameters 510 control how task / work unit 207 schedules TMD 322 for execution. Scheduling parameters 510 may include a bit indicating whether TMD 322 is a queue TMD or a grid TMD. If TMD 322 is a grid TMD, then the queue feature of TMD 322, which allows additional data to be queued after TMD 322 is triggered, is unused, and execution of TMD 322 results in a fixed number of CTAs being triggered and executed to process the fixed amount of data stored in queue 525. The number of CTAs is specified as the product of the grid width, height, and depth. Queue 525 is replaced by a queue pointer to the data processed by the CTAs executing the program specified by TMD 322.

[0044] If the TMD 322 is a queue TMD, then the queue feature of the TMD 322 is used, meaning that the data in the queue 525 is stored as queue entries. Queue entries are input data for CTAs of the TMD 322. The queue entries may also represent child tasks created by another TMD 322 during execution of a thread, thereby providing nested parallelism. Typically, execution of the thread, or of a CTA encompassing the thread, is suspended until the execution of the child task is completed. The queue 525 may be implemented as a circular queue so that the total amount of data is not limited to the size of the queue 525. As previously described, the queue 525 may be stored separately from the TMD 322, and the TMD 322 may store a queue pointer to the queue 525.Advantageously, queue entries for the child task can be written to the queue 525 while the TMD 322 representing the child task is executing.

[0045] A variable number of CTAs are executed for a queue TMD, where the number of CTAs depends on the number of entries written to the queue 525 of the TMD queue. The scheduling parameters 510 for a queue TMD also include the number of entries (N) of queue 525 that are processed by each CTA. When N entries are added to the queue 525, a CTA for the TMD 322 is triggered. The task / work unit 207 may construct a directed graph of processes, where each process is a TMD 322 with a queue. The number of CTAs to be executed for each TMD 322 may be determined based on the value of N for each TMD 322 and based on the number of entries written to the queue 525.

[0046] The scheduling parameters 510 of a queue TMD may also include a coalesce waiting time parameter, which sets the amount of time to wait before executing a CTA with fewer than N queue entries. The coalesce waiting time parameter is required when the queue is almost empty but there is an insufficient number of queue entries, which can occur when the total number of queue entries over the course of an execution is not evenly divisible by N. The coalesce waiting time parameter is also necessary in the case of producer-consumer queues to avoid deadlock. In the case of a CTA executing with fewer than N entries, the number of queue entries is passed as a parameter to the TMD program so that the number of entries can be taken into account during execution.

[0047] Alternative embodiments have different structures for a lattice TMD and a queue TMD, or implement only either lattice TMDs or queue TMDs. The scheduling parameters 510 of the TMD 322 may include a bit indicating whether scheduling the dependent TMD also results in TMD fields being copied to the hardware-only field 522. The scheduling parameters 510 may also include the TMD group ID, a bit indicating where the TMD 322 is added to a linked list (head or tail), and a pointer to the next TMD 322 in the TMD group. The scheduling parameters 510 may also include masks that enable / disable specific streaming multiprocessors within the GPCs 208.

[0048] A TMD 322 may include a task pointer to a dependent TMD, which is automatically triggered when the TMD 322 completes. Semaphores may be executed via the TMDs 322 to ensure that dependencies between the various TMDs 322 and the CPU 102 are met. For example, the execution of a first TMD 322 may depend on the completion of a second TMD, so that the second TMD generates a semaphore release and executes the first TMD after the corresponding semaphore acquisition is successful. In some embodiments, the semaphore acquisition is performed in the host interface 206 or in the frontend 212.The execution parameters 515 for a TMD 322 can store a plurality of semaphore enable details, including the type of memory barrier, the address of the semaphore data structure in memory, the size of the semaphore data structure, the payload and enable, and the type and format of a reduce operation. The semaphore data structure can be stored in the execution parameters 515 or can be stored external to the TMD 322.

[0049] The execution parameters 515 may also include the starting address of the program to be executed for the TMD 322, the type of memory barrier operation to be performed when the execution of the TMD 322 is completed, a serial execution flag indicating whether only a single CTA is executed at a time (serially) for the TMD 322, and a throttle enable flag controlling whether or not the task / work unit 207 should limit the number of CTAs that run simultaneously based on the memory limits specified for the TMD 322.

[0050] The execution parameters 515 also store various flags that control behavior of arithmetic operations performed by the processing task being executed for the TMD 322, e.g., not-a-number (NaN) handling, floating-point number-to-integer conversion, and rounding modes of various instructions.

[0051] The CTA state 520 for the TMD 322 may include an ID of a reference counter used by the TMD 322, an enable to increment the reference counter, and a separate enable to decrement the reference counter. When a process is bypassed or preempted, processing of the TMD 322 may be stopped at an instruction boundary or a CTA boundary, and the identification of the CTA at which processing will resume is stored in the CTA state 520. The status information required to continue execution of the TMD 322 after preempting may be stored in the CTA state 520 or in a separate area in PP memory or in system memory 104.

[0052] The CTA state 520 also stores data pointers to entries of the queue 525 and counter overflow flags, which indicate when each data pointer increments past the end of the queue 525 and needs to wrap back to the start of the queue 525. Hardware-only versions of the one or more data pointers and the scheduling flag may be stored in the hardware-only field 522.

[0053] Fig. 5B illustrates data pointers to queue 525 entries of Fig. 5A, according to one embodiment of the invention. Writing data for a processing task encoded in queue 525 is decoupled from the allocation of entries in queue 525. First, a process reserves or allocates a number of entries in queue 525, and later, the process stores the data to be processed using the CTAs in the entries. An outer set pointer 545 points to the next available entry in queue 525 to be allocated, and an inner set pointer 540 points to the oldest entry in queue 525 that has been allocated and not yet written. The entries are not necessarily written in the order in which the entries are allocated, so there may be entries between inner set pointer 540 and outer set pointer 545 that have been written.

[0054] An outer get pointer 530 points to the oldest entry of queue 525, which stores data that has been assigned to a CTA for processing, i.e., a CTA that will process the data that has been triggered, but the CTA has not yet read the data. An inner get pointer 535 points to the most recent entry of queue 525 that has been assigned to a CTA for processing. Data that has been written to queue 525 but has not yet been assigned to a CTA for processing is stored in the entries between the inner get pointer 535 and the inner set pointer 545. Data that has been assigned to a CTA for processing and has not been read is stored between the outer get pointer 530 and the inner get pointer 535.

[0055] Fig. Figure 6 illustrates a method for encapsulating computational task state in a TMD 322 of Fig. 3, Fig. 4A and Fig. 5A for a lattice TMD, according to an embodiment of the invention. Although the method steps in connection with the systems of Fig. 1, Fig. 2, Fig. 3 and Fig. 4A, those skilled in the art will understand that any system configured to perform the method steps, in any order, is within the scope of the inventions.

[0056] At step 605, a TMD 322 is allocated, i.e., memory in which the TMD 322 data is to be stored is allocated. At step 610, the initialization parameters 505 are stored in the TMD 322. At step 615, the scheduling parameters 510 are stored in the TMD 322. At step 620, the execution parameters 515 are stored in the TMD 322. At step 630, if the TMD 322 is not waiting for an event to occur (e.g., a semaphore release) before execution can proceed, the task / work unit 207 proceeds directly to step 635 and schedules the TMD 322. Otherwise, if at step 630 the TMD 322 is waiting for an event to occur, then at step 632 the TMD 322 determines whether a signal is received indicating that the execution of the TMD 322 may continue or continue. If the event occurs, the method proceeds to step 635.

[0057] At step 635, the task / work unit 207 schedules the TMD 322 and the GPCs 208, and memory available for use by the TMD 322 is configured based on the initialization parameter 505. The TMD 322 is scheduled by the task / work unit 207 based on the scheduling parameters 510. At step 640, one or more CTAs are launched to execute the TMD 322 on the GPCs 208. During execution of the CTAs, processing tasks are performed based on the execution parameters 515. At step 655, when the one or more CTAs complete executions and exit, the TMD 322 is deallocated.

[0058] Fig. Figure 7 illustrates a method for encapsulating a computational task state in a TMD 322 of Fig. 3, Fig. 4A and Fig. 5A for a queue TMD according to an embodiment of the invention. Although the method steps in connection with the system of Fig. 1, Fig. 2, Fig. 3 and Fig. 4A, those skilled in the art will understand that any system configured to perform the method steps in any order is within the scope of the inventions.

[0059] At step 705, a TMD 322 is allocated, i.e., memory in which the TMD 322 data is to be stored is allocated. At step 710, the initialization parameters 505 are stored in the TMD 322. At step 715, the scheduling parameters 510 are stored in the TMD 322. At step 720, the execution parameters 515 are stored in the TMD 322. Entries may be written to the queue 525 after the TMD 322 is allocated, and additional entries may be written to the queue 525 when CTAs for the TMD 322 are executed. If the queue 525 is a circular queue, entries read by a CTA may be overwritten with additional queue entries by another TMD 322 or by the CPU 102 via the frontend 212. Writing to queue 525 is decoupled from reading to queue 525 using the CTAs and can occur simultaneously with reading.

[0060] At step 730, the task / work unit 207 determines whether enough entries have been written to queue 525 to trigger a CTA, and if not, the task / work unit 207 waits for more entries to be written to queue 525. If enough entries have been written to queue, then at step 730, the task / work unit 207 schedules the TMD 322 at step 735. The task / work unit 207 configures GPCs 208 and memory available for use by the TMD 322 based on the initialization parameters 505. The TMD 322 is scheduled by the task / work unit 207 based on the scheduling parameters 510.

[0061] At step 740, based on the number of entries written to queue 525, one or more CTAs are triggered to execute the TMD 322 on the GPCs 208. At step 742, the triggered CTAs each read a number of entries (N) written to queue 525 such that the total number of entries read equals N * number of triggered CTAs. During the execution of the CTAs, the processing tasks are performed based on the execution parameters 515, and each CTA processes data written to N entries of queue 525. At step 745, the task / work unit 207 determines whether enough entries have been written to queue 525 to trigger a CTA, and if not, the task / work unit 207 proceeds to step 750. Otherwise, the task / work unit 207 returns directly to step 740 to initiate one or more CTAs.Therefore, when CTAs for a TMD write entries to queue 525, additional CTAs can be triggered without scheduling TMD 322 again, because TMD 322 is currently scheduled.

[0062] If, at step 750, the task / work unit 207 determines that no more entries are being written to the queue 525 and no more entries can be written to the queue 525, the TMD 322 is deallocated at step 755. If there are more entries in the queue 525 that are being written or more entries that can be written to the queue 525, then the task / work unit 207 returns to step 730.

[0063] The encapsulation mechanism of encoding computational processing tasks in TMDs 322 allows each TMD 322 to store initialization, scheduling, and execution parameters specific to that particular TMD 322. The initialization and execution scheduling parameters are used to configure streaming multiprocessors and memory resources for executing the TMD 322. The scheduling parameters are used to control the scheduling of the TMDs 322 for execution, including out-of-order execution.

[0064] An embodiment of the invention may be implemented as a program product for use with a computer system. The program or programs of the program product define functions of the embodiments (including the methods described herein) and may be embodied on a variety of computer-readable storage media. Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media, e.g., read-only memory devices within a computer (such as CD-ROM disks readable by a CD-ROM drive, flash memory, ROM chips, or any other type of solid-state non-volatile semiconductor memory) on which information is permanently stored; and (ii) writable storage media (e.g.,Floppy disks within a floppy disk drive or a hard disk drive, or any other type of solid-state semiconductor random access memory (SSM) on which alterable information is stored.

[0065] The invention has been described above with reference to specific embodiments. However, those skilled in the art will understand that various modifications and changes may be made therein without departing from the broader spirit and scope as set forth in the appended claims. The foregoing description and drawings are accordingly to be regarded in an illustrative rather than a restrictive sense.

Claims

[1] A method for encapsulating and scheduling computational tasks, the method comprising: Allocating memory to store a task metadata structure; Storing initialization parameters in the task metadata structure that configure a streaming multiprocessor to execute a compute task; Storing scheduling parameters in the task metadata structure that control the scheduling of the computing task; Storing execution parameters in the task metadata structure that control execution of the computing task by the streaming multiprocessor; and Scheduling the compute task based on the scheduling parameters in the task metadata structure for execution of the compute task by the streaming multiprocessor based on the execution parameters in the task metadata structure. [2] The method of claim 1, further comprising storing a pointer to a queue in the task metadata structure, the queue storing data for the compute task. [3] The method of claim 2, further comprising storing status information in the task metadata structure, which includes an outer set pointer indicating a next entry in the queue available for allocation to store data for the compute task. [4] The method of claim 2, further comprising storing status information in the task metadata structure, which includes an inner set pointer indicating an oldest entry of the queue that is not empty and that has been allocated to store data for the compute task. [5] The method of claim 2, wherein the queue is circular, and wherein the task metadata structure stores an overflow flag for at least one of the data pointers. [6] The method of claim 1, further comprising receiving task pointers including a task pointer to the task metadata structure and additional task pointers to additional task metadata structures associated with additional compute tasks, wherein the compute task and the additional compute tasks are executed in an order different from the order in which the task pointers are received. [7] The method of claim 1, further comprising: Determining that the task metadata structure waits for an event to occur before resuming execution of the compute task; and Wait to receive a scheduling signal before scheduling the computation task for execution. [8] The method of claim 1, further comprising storing a task pointer to a next task metadata structure in a linked list comprising the task metadata structure and the next task metadata structure. [9] The method of claim 1, wherein the task metadata structure stores a group identifier, the task metadata structure being organized in a linked list with other task metadata structures storing the same group identifier. [10] A system for encapsulating and scheduling computing tasks, the system comprising: a memory configured to store task metadata corresponding to the computing tasks; and a streaming multiprocessor configured to: allocate a portion of memory to store the task metadata in a task metadata structure; Store initialization parameters in the task metadata structure that configure the streaming multiprocessor to execute a compute task; to store scheduling parameters in the task metadata structure that control the scheduling of the computing task; Store execution parameters in the task metadata structure that control execution of the compute task by the streaming multiprocessor; and schedule the compute task based on the scheduling parameters in the task metadata structure for executing the compute task based on the execution parameters in the task metadata structure.

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