Superjunction semiconductor device with one cell region and one border region

Abstract

Superjunction semiconductor device comprising: at least one doped zone (110) in a cell region (210), a drift layer (120) formed in the cell region (210) and in a border region (290) surrounding the cell region (210) and having first parts (121) of the first conductivity type and second parts (122) of a second conductivity type opposite to the first conductivity type, wherein the first parts (121) in the cell region (210) are arranged in a current path of a forward or through current to / from the at least one doped zone (110), and wherein at least a part of the first and second parts (121, 122) in the border region (290) and / or at least a part of the second parts (122) in the cell region (210) contains auxiliary foreign materials (400) to locally reduce an avalanche rate.

Description

BACKGROUNDIn semiconductor devices having a superjunction structure, a drift layer typically includes n-doped pillars forming a current path and p-doped pillars provided to obtain a high reverse breakdown voltage between a drain electrode and a source electrode of the semiconductor device. A high impurity concentration in the n-columns results in a low on-resistance. When a reverse voltage is applied, depletion regions extend between the n-type pillars and the p-type pillars in a lateral direction, so that a high reverse breakdown voltage can be achieved even at high impurity concentrations in the n-type pillars. It is desirable to improve the reliability of superjunction semiconductor devices in the reverse direction.The document DE 10 2006 047 489 A1 describes a semiconductor component with charge compensation regions in an active cell region and in an edge region. The compensation regions in the edge region have a finer pattern than in the active cell region, thereby moving the location of avalanche breakdown into the active cell region. In a direction parallel to a transition between cell region and edge region, p-doped compensation regions are formed at a greater distance than in a direction transverse to the transition between cell region and edge region. The publication DE 10 2006 004 627 B3 describes a further power semiconductor component having a charge compensation structure. Diffusion-inhibiting regions are formed in the n-type drift zone sections. To form p-doped charge compensation zones, acceptors are implanted through openings in an implantation mask and subsequently diffused substantially vertically. The diffusion-inhibiting regions reduce the lateral out-diffusion of the acceptors into the current path formed from the n-conducting drift zone sections. In the publication DE 10 2006 004 405 A1, structures made of a highly dielectric material essentially form the compensation zones of a charge compensation structure. Polarization charges in the high dielectric material compensate for the dopant charge in the n-doped drift zone portions. The dielectric constant of the dielectric materials is greater than 50. The highly dielectric material may directly adjoin the respective adjacent n-doped drift zone section or may be separated from the adjacent n-doped drift zone section by a p-doped region.SUMMARYIt is therefore an object of the present invention to provide a superjunction semiconductor device and a method for manufacturing the same, each satisfying the above requirements.To achieve this object, the invention provides a superjunction semiconductor device having the features of claim 1, a superjunction semiconductor device having the features of claim 10, and a method having the features of claim 21.Advantageous refinements of the invention are specified in the dependent claims.According to an embodiment, a superjunction semiconductor device includes at least one doped region in a cell region. A drift layer is formed in the cell region and in an edge region surrounding the cell region. The drift layer includes first portions of a first conductivity type and second portions of a second conductivity type opposite to the first conductivity type. First parts in the cell region are arranged in a current path of an on-state or forward current from / to the at least one doped zone. At least a part of the first and second parts other than the first parts in the cell region contains auxiliary impurities or an auxiliary structure capable of locally reducing an avalanche rate.According to another embodiment, a method of manufacturing a superjunction semiconductor device includes forming a drift layer in both regions of a cell region and an edge region surrounding the cell region. The drift layer includes first portions of a first conductivity type and second portions of a second conductivity type opposite to the first conductivity type. At least one doped zone is formed over the drift layer in the cell region, wherein the first parts in the cell region are arranged in a current path of a forward or forward current from / to the at least one doped zone. At least a part of the first and second parts other than the first parts in the cell region is provided with auxiliary impurities or an auxiliary structure operable to locally reduce an avalanche rate.Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and viewing the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of the disclosure of the invention. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the invention and intended advantages will be immediately appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale with respect to each other. Like reference numerals indicate corresponding similar parts. FIG. 1A is a schematic cross-sectional view of a portion of a semiconductor body of a superjunction semiconductor device in a plane parallel to a surface according to an embodiment related to a drift layer having stripe-shaped p-doped parts including auxiliary impurities in a cell region and an edge region. FIG. 1B is a schematic cross-sectional view of the superjunction semiconductor device of FIG. 1A along a line B-B. FIG. 2A is a schematic cross-sectional view of a portion of a semiconductor body of a superjunction semiconductor device in a plane parallel to a surface according to an embodiment relating to stripe-shaped p-doped parts in the drift layer and auxiliary impurities provided in an edge region of the semiconductor body. FIG. 2B is a schematic cross-sectional view of the superjunction semiconductor device of FIG. 2A along a line B-B. FIG. 3A is a schematic cross-sectional view of a portion of a semiconductor body of a superjunction semiconductor device in a plane parallel to a surface according to an embodiment related to a drift layer having stripe-shaped p-doped parts including an auxiliary structure. FIG. 3B is a schematic cross-sectional view of the superjunction semiconductor device of FIG. 3A along a line B-B. FIG. 4A is a schematic cross-sectional view of a portion of a semiconductor body of a superjunction semiconductor device in a plane parallel to a surface according to an embodiment providing a drift layer with stripe-shaped p-doped parts including a multi-layer auxiliary structure. FIG. 4B is a schematic cross-sectional view of the superjunction semiconductor device of FIG. 4A along a line B-B. FIG. 5A is a schematic cross-sectional view through a drift layer of a superjunction semiconductor device according to an embodiment providing stripe-shaped first and second portions extending from a cell region into first edge regions and parallel to the cell region into second edge regions. FIG. 5B is a schematic cross-sectional view through a drift layer according to a further embodiment providing stripe-shaped first and second portions extending from the cell region into first edge regions and parallel to the cell region into second edge regions. FIG. 5C is a schematic cross-sectional view through a drift layer of a superjunction semiconductor device according to an embodiment providing parallel first and second portions in a cell region and frame-like first and second portions in an edge region. FIG. 6A is a schematic sectional illustration through a drift layer of a superjunction semiconductor device parallel to a surface according to an embodiment with first parts of the drift layer formed by out-diffusion of trench sidewalls. FIG. 6B is a schematic cross-sectional view of the superjunction semiconductor device of FIG. 6A along a line B-B. FIG. 7A is a schematic cross-sectional view through a drift layer of a superjunction semiconductor device according to an embodiment related to p-doped pillars embedded in an n-type lattice. FIG. 7B is a schematic cross-sectional view of the superjunction semiconductor of FIG. 7A along a line B-B. FIG. 8 is a simplified cross-sectional view of a superjunction semiconductor device according to an embodiment related to a superjunction diode. FIG. 9 is a simplified flow diagram of a method of manufacturing a superjunction semiconductor device.DETAILED DESCRIPTIONIn the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. For example, features illustrated or described for one embodiment may be used in or in conjunction with other embodiments to arrive at yet another embodiment. It is intended that the present invention also encompasses such modifications and variations. The examples are described by means of a specific language, which should not be understood as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements are provided with the same reference numerals throughout the several drawings unless otherwise stated.The terms "have," "contain," "include," "comprise," and similar terms are open ended terms, and the terms indicate the presence of the stated elements or features, but do not exclude additional elements or features. The indefinite and distinct articles are intended to include both plural and singular, unless the context clearly indicates otherwise.The figures represent relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n -" means a doping concentration lower than the doping concentration of an "n" doping region, while an "n +" doping region has a higher doping concentration than an "n" doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions may have the same or different absolute doping concentrations.The term "electrically connected" describes a low-ohmic connection between the electrically connected elements, for example a direct contact between the relevant elements or a connection via a metal and / or a highly doped semiconductor. The term "electrically coupled" includes that one or more intermediate element(s) may(s) be provided between the electrically coupled elements, for example elements that are controllable to temporarily provide a low impedance connection and, at another time, a non-low impedance connection.FIGS. 1A and 1B show a superjunction semiconductor device 500, wherein FIG. 1A is a sectional view in a plane parallel to a first surface 101 of a semiconductor body 100 as indicated by a line A-A in FIG. 1B, and FIG. 1B is a sectional view perpendicular to the sectional plane of FIG. 1A along a line B-B in FIG. 1A.A semiconductor body 100 comprises a single-crystalline semiconductor material, for example silicon Si, silicon carbide SiC, germanium Ge, a silicon germanium SiGe or gallium arsenide GaAs. The semiconductor body 100 has a first surface 101 and a second surface 102 parallel to the first surface 101. A distance between the first surface 101 and the second surface 102 is in the range of several tens of micrometers or more, and is closely related to the reverse breakdown voltage, which is the minimum applied voltage that causes the semiconductor device 500 to break down.The semiconductor body 100 may have a rectangular shape having an edge length in the range of a few millimeters. The semiconductor body 100 comprises a doped layer 130 of a first conductivity type. A net doping concentration in the doped layer 130 is comparatively high and may be at least 10 17 cm -3 for example. The doped layer 130 may extend along a complete cross-sectional plane of the semiconductor body 100 parallel to the second surface 102. According to an embodiment, the doped layer 130 directly adjoins the second surface 102. According to other embodiments, a further layer may be provided between the doped layer 130 and the second surface 102. For example, another doped layer of a second conductivity type opposite to the first conductivity type may be provided between the doped layer 130 and the second surface 102. The doped layer 130 forms a contact layer to an electrode and may be doped by implantation from the second surface 102.A drift layer 100 is formed between the first surface 102 and the doped layer 130. For example, the doped layer 130 may be a base substrate for epitaxial growth of the drift layer 120. The drift layer 120 comprises first parts 121 of the first conductivity type and second parts 122 of the second conductivity type. The second portions 122 may be formed in direct contact with the doped layer 130. According to other embodiments, the second portions 122 are formed offset from the doped layer 130 such that the drift layer 120 includes an adjacent portion 123 of the first conductivity type extending between the first and second portions 121, 122 on the one hand and the doped layer 130 on the other hand. The drift layer 120 may directly adjoin the doped layer 130. According to other embodiments, a further layer of the first conductivity type may be provided between the drift layer 120 and the doped layer 130.The semiconductor body 100 comprises a cell region 210 and an edge region 290 surrounding the cell region 210, wherein the edge region 290 extends along the edge of the semiconductor body 100. Through those first portions 121 located in the cell region 210, in the on state of the semiconductor device 500, a forward current flows through the drift layer 120 to the doped layer 130. On the other hand, first portions 121 located in the edge region 290 do not contribute significantly or at all to the forward current.At least one structure or component that allows forward or forward current to flow into the first portions 121 of the cell region 210, for example a gate electrode, a source zone, a source contact, a base zone or a gate contact, is not provided in the edge region 290, without connection or for other reasons inoperative.The semiconductor body 100 further comprises at least one doped zone 110 formed in the cell region 210. According to an embodiment, a plurality of doped zones 110 of the first conductivity type is provided, wherein each of the doped zones 110 directly adjoins a base zone 115 of the second conductivity type and each base zone 115 directly adjoins at least a part of the first and one of the second parts 121, 122 in the cell region 210 to form a superjunction IGFET (insulated gate field effect transistor) or a superjunction IGBT (insulated gate bipolar transistor) device. According to another embodiment, the at least one doped zone 110 is of the second conductivity and directly adjoins the first and second portions 121, 122 in the cell region 210 to form a superjunction diode. In the edge region 290, the doped zones 110 are inoperative, without connection to an electrode, or for other reasons.The gate electrode structures 315 may be provided to control a charge carrier distribution in the base zone 115 in a channel region between the doped zones 110 and the first portions 121 of the drift layer 120 along a gate dielectric 316. The gate dielectric 316 is arranged between the gate electrode structures 315 and the base zones 115. A first electrode 310 may be electrically coupled to the base zones 115 and the doped zones 110. A dielectric layer 330 between the first electrode 310 and the semiconductor body 100 electrically isolates the first portions 121 from the first electrode 310. In the illustrated embodiment, the gate electrode structures 315 may be disposed over the first surface 101. According to other embodiments related to IGFETs and IGBTs, the gate electrode structures may be formed in trenches etched into the drift layer 120 from the first surface 102.The first electrode 310 electrically contacts the doped regions 110 and the base regions 115 through openings in the dielectric layer 330. According to an embodiment, the first electrode 310 does not contact the second portions 122 in the edge region 290. According to other embodiments, the first electrode 310 may contact a part or a plurality of parts of the first parts 122 in the edge region 290 via further openings in the dielectric layer 330.A second electrode 320 may directly adjoin the doped layer 130. According to embodiments related to IGBTs, a further doped layer of the second conductivity type may be formed between the doped layer 130 and the second electrode 320. According to the illustrated embodiment, the first conductivity type is the n-type, the second conductivity type is the p-type, the first electrode 310 is a source electrode, the doped regions are source regions, and the second electrode 320 is a drain electrode. According to other embodiments, the first conductivity type is the p-type.At least a part of the first and second parts 121, 122 other than the first parts 121 in the cell region 210 includes an auxiliary structure, contains auxiliary impurities, or includes an auxiliary structure, and contains auxiliary impurities. Auxiliary structures and auxiliary contaminants are substantially absent or missing from the cell region.According to an embodiment related to the auxiliary contaminants, the auxiliary contaminants locally reduce a mean free path length of the charge carriers, which is the mean distance a charge carrier travels between successive collisions. With a reduced mean free path length, the charge carriers can absorb less energy between collisions such that a higher electric field strength is required to generate electron-hole pairs and to trigger avalanche breakdown.According to another embodiment related to auxiliary contaminants, the auxiliary contaminants are operable to locally reduce an electric field strength. Locally reducing the electric field strength and / or the mean free path length of the charge carriers reduces the avalanche rate in selected regions such that the reverse breakdown voltage can be locally increased. According to embodiments related to an auxiliary structure, the auxiliary structure is operable to locally reduce an electric field strength.FIGS. 1A and 1B relate to an embodiment in which the second parts 122 of the cell region 210 and the edge region 290 both contain auxiliary contaminants 400. The first portions 121 in the cell region 210 do not contain or contain auxiliary impurities at a concentration that is significantly lower than outside the first portions 121 in the cell region 210, for example at a concentration that is lower than 10% of that in the other portions. The auxiliary contaminants 400 at least reduce the charge carrier mobility. As a result, the mean free path length for charge carriers is reduced and a reverse breakdown voltage may be locally increased without increasing the on-state resistance defined by the first portions 212 in the cell region 210.Typically, in superjunction semiconductor devices, the maximum electric field strength is near the center of the first and second parts 121, 122. Depending on the manufacturing process, the maximum electric field strength may occur in the middle of the second parts 122. By reducing the mean free path length of the charge carriers at least in the central parts of the second parts 122, a critical electric field strength at which a local avalanche breakdown occurs in the second parts 122 may be increased such that the reverse breakdown voltage of the semiconductor device 500 is defined only by the minimum reverse breakdown voltage of the first parts 121.According to an embodiment, the auxiliary contaminants 400 are predominantly provided in and near a central portion of the second portions 122. According to other embodiments, the auxiliary contaminants 400 are distributed over approximately the entire volume of the second portions 122. According to an embodiment providing an epitaxial process for forming the drift layer 120 in an iterative process, wherein each iteration step provides growth of an underlayer and implanting donors and / or acceptors into the grown underlayer to form the first and second portions 121, 122, the auxiliary impurities 400 may be implanted in at least one of the iteration steps, in some of the iteration steps, or in each of the iteration steps. The auxiliary impurity implantations may be different in implantation energy, and more than one auxiliary impurity implantation may be performed at different implantation energies in at least one of the iteration steps.The auxiliary impurities 400 may be atoms of elements capable of enhancing scattering of carriers in the drift layer 120. According to an embodiment, the auxiliary impurities 400 are atoms that increase scattering of charge carriers by perturbation of a crystal potential due to substituting atoms of the semiconductor material of the drift layer 120 in the crystal lattice, thereby causing alloy scattering. For example, the drift layer 120 is provided of silicon, and the auxiliary impurity atoms are germanium or Ge or carbon or C atoms, respectively, which replace some of the silicon atoms in the silicon crystal lattice of the drift layer 120.According to other embodiments, the auxiliary impurity atoms are dopants of the first conductivity type. For example, when the conductivity type of the second portions 122 is the p-type, the impurity atoms are of the n-type, for example, phosphorus atoms or arsenic atoms. Counter-doping may also reduce minority carrier lifetime by increasing the recombination rate. The avalanche rate is reduced. Counter-doping by auxiliary impurities 400 acting as donors or acceptors may be compensated by increasing the concentration of the dopants of the other conductivity type to maintain a predetermined net dopant concentration for achieving the desired compensation effect between the first and the second parts 121, 122. For example, an auxiliary implant includes molecules containing the same number of donor and acceptor atoms or ions.A concentration of the auxiliary impurities 400 is at least in the range of that of the dopants. The auxiliary impurity concentration may be higher than that of the dopant concentration, for example by a factor of 10. For example, the second portions 122 may have a net dopant concentration of about 10 15 cm -3 to 10 16 cm -3 and an auxiliary impurity concentration, e.g., an absolute n-type dopant concentration of 10 17 cm -3.While the embodiment illustrated in FIGS. 1A and 1B provides the auxiliary contaminants 400 in the second portions 122 of the cell region 210 and the edge region 290, other embodiments may provide the auxiliary contaminants 400 only in second portions 122 located near an edge of the cell region 210 and in the edge region 290, or only in all or some of the second portions 122 present in the edge region 290.Given a similar construction and arrangement of the first and second parts 121, 122 in the cell region 210 and the edge region 290, the electric field strength is higher near the edge region 290 than in the cell region 210 because in the edge region 290 and near the edge region 290 equipotential lines are bent from a horizontal direction parallel to the first and second surfaces 101, 102 in a direction perpendicular to the first and second surfaces 101, 102 so as to locally increase the electric field strength. In the corners of a rectangular semiconductor body 100, the bending is further increased. Therefore, providing impurities in the second parts 122 in the edge region 290 or in the edge region 290 and a portion of the cell region 210 adjacent to the edge region 290 contributes to the reliability of the semiconductor device 500 to a higher extent than providing auxiliary impurities in the second parts 122 of a central portion of the cell region 210.The embodiment illustrated in FIGS. 2A and 2B refers to a region having auxiliary impurities 410 in the edge region 290, the region including the auxiliary impurities 410 overlapping with both first and second parts 121, 122 in the edge region 290. The auxiliary contaminants 410 reduce the mean free path length in both first and second parts 121, 122 of the edge region 210. The reduction of the mean free path length in both parts 121, 122 locally increases the critical electric field strength in the entire edge region 290 and contributes to an increased reliability of the semiconductor device 500.According to the illustrated embodiment, the first electrode 310 contacts the second portions 122 in the edge region 290. According to other embodiments, the second portions 122 and the first portions 121 may be floating in the edge region 290. Since no gate electrodes and / or doped zones 110 are provided in the edge region 290, the first portions 121 in the edge regions 290 do not significantly contribute to forward current. Thus, the reduction of the mean free path length in the first portions 121 in the edge region 290 does not increase the on-resistance of the semiconductor device 500.The exemplary embodiment shown in FIGS. 3A and 3B differs from the exemplary embodiment of FIGS. 2A and 2B in that an auxiliary structure 420 is provided instead of auxiliary impurities. The auxiliary structure 420 may be provided in a central portion of one or each of the second portions 122, as illustrated. According to other embodiments, the auxiliary structure 420 may also be provided in a central part of the first parts 121 in the edge region 290 or in the central regions of the first parts 121 located in the edge region 290 and in further parts 121 located in the cell region 210 in a region close to the edge region 290. The auxiliary structure 420 may be provided of oxides, for example oxides containing a positive charge. According to one embodiment, a silicon oxide with cesium Cs forms the charged oxide. According to another embodiment, the auxiliary structure 420 is provided of a dielectric material having a dielectric constant equal to or close to that of the semiconductor material of the drift layer 120. For example, the material of the drift layer 120 is silicon, and the dielectric material is aluminum oxide Al 2 O 3.According to the embodiment shown in FIGS. 4A and 4B, the dielectric structure 420 comprises at least two sub-layers of different materials, wherein an average dielectric constant deviates from that of the semiconductor material of the drift layer 120 by not more than 20%. For example, one of the first sub-layers 421, 422 may be a silicon oxide, and the other sub-layer 422, 421 may be an aluminum nitride AlN or a hafnium oxide HfO 2. According to another embodiment, one of the sub-layers 421, 422 is made of zirconium oxide ZrO 2 and the other sub-layer 422, 421 is made of titanium oxide TiO 2.FIGS. 5A and 5B show, for example, designs or layouts for the first and second parts 121, 122, for which auxiliary contaminants and / or auxiliary structures can be provided, as described above.FIG. 5A shows a regular arrangement of first and second parts 121, 122, wherein the first and second parts 121, 122 are strip-shaped and arranged in alternating order and parallel to one of the edges of a semiconductor body 100 of a superjunction semiconductor device 500. A subset of the first and second portions 121, 122 extends from the cell region 210 into first edge regions 291 that are extended along two opposite edges of the semiconductor body 100. At least one second part 122 is formed completely in one of the two second edge regions 292 between the cell region 210 and further edges of the semiconductor body 100. The cell region 210 differs from the edge regions 291, 292 in that in the cell region 210 all components and structures which cause a forward or forward current through the first parts 121 are fully functional, whereas in the edge regions 291, 292 at least one of these components or structures is missing, not connected or not functional. While the first portions 121 in the cell region 210 contribute forward current, the first portions located in the edge regions 291, 292 do not.The embodiment illustrated in FIG. 5B differs from the embodiment of FIG. 5A in further edge regions 291, 292 and in that at least two complete second parts 122 are formed in each of the second edge regions 292.FIG. 5C relates to an embodiment in which first and second portions 121, 122 are formed in the cell region 210. In the edge region 290, frame-like first and second parts 121 b, 122 bsurround the cell region 210 in alternating order. The first and second frame-like parts 121 b, 122 bmay be adjacent as illustrated, or may be discontinuously formed. For example, the second frame-like parts 122 bmay include four separate portions that are not connected at the corners or near the corners of the frame.FIGS. 6A and 6B relate to an embodiment that provides the first and second parts 121, 122 by out-diffusion of sidewalls of trenches etched into an intrinsic or homogeneously doped layer. The trenches may be strip-shaped grooves or trenches. According to the illustrated exemplary embodiment, the trenches are approximately square. According to other embodiments, the trenches have a hexagonal or round cross-sectional shape.A semiconductor body 100 has a first surface 101 and a second surface 102 parallel to the first surface 101. At least one doped region 110 is formed directly adjacent to the first surface 101. Further, a doped layer 130 that is of a first conductivity type is formed in the semiconductor body 100. According to embodiments related to superjunction diodes and superjunction IGFETs, the doped layer 130 directly adjoins the second surface 102. According to other embodiments, e.g. embodiments related to IGBTs, at least one further layer of a second conductivity type opposite to the first conductivity type may be arranged between the doped layer 130 and the second surface 102. The at least one doped region 110 may be a single doped region of the second conductivity type formed in the cell region 210, for example, when the semiconductor device is a superjunction diode. According to embodiments related to IGFETs and IGBTs, a plurality of doped zones of the first conductivity type is provided in the cell region 210 of the semiconductor body 100, wherein each doped zone 110 is formed as a well in a base zone 115 of the second conductivity type.In the cell region 210 and in an edge region 290 extending along an edge of the semiconductor body 100 and surrounding the cell region 210, a drift layer 120 is arranged between the at least one doped zone 110 and the doped layer 130. The drift layer 120 comprises first parts 121 of the first conductivity type and second parts 122 of the second conductivity type. The drift layer 120 further comprises dielectric structures 340 resulting from filling the trenches etched for sidewall implantation. The first parts 121 surround the dielectric structures 340, which form a rectangular hollow cylinder of uniform thickness. The second parts 122 form a grid embedding the cylindrical first parts 121.Gate electrode structures 315 may be provided in the cell region 210 to control a minority charge carrier distribution in a portion of the base zones 115 between the doped zones 110 and the first portions 121. A first electrode 310 may be electrically connected to the doped regions 110 and the base region 115. Each base zone 115 may be a portion of or directly adjoin the second parts 122. A dielectric layer 330 may separate the first electrode 310 from the first parts 121. The first electrode 310 may or may not be electrically connected to the second parts 122 in the edge region 290.A forward current flows through the first portions 121 in the cell region 210. At least a portion of the first and second portions 121, 122 other than the first portions 121 in the cell region 210 comprises an auxiliary structure or includes auxiliary contaminants 410 that locally reduce the mean free path length or dielectric field strength at least in a central portion of the respective first and second portions 121, 122.For example, at least in the second parts 122 in the edge region 290, auxiliary impurities 410 are implanted which reduce the mean free path length of the charge carriers in the second parts 122 in the edge region 290, for example auxiliary impurity atoms which replace atoms of the semiconductor material in the monocrystalline lattice or auxiliary impurity atoms which are effective as donors or acceptors. According to an embodiment, the second parts 122 include first auxiliary impurities of the first conductivity type and second auxiliary impurities of the second conductivity type that compensate for the first auxiliary impurities of the first conductivity type. Since the mean free path length is reduced in portions of the drift layer 120 where the electric field strength is increased due to edge effects, the blocking voltage capability of the edge region 290 is locally increased and operable up to that in the cell region 210 without increasing the on-resistance. According to another embodiment, at least central portions of the second portions 122 comprise an auxiliary structure or are counter doped to locally reduce the electric field strength.The embodiment of FIGS. 7A and 7B relates to pillar-like second parts 122 embedded in a grid formed by the first parts 121. The cross section of the second portion 122 may be round, elliptical, square, rectangular, or polygonal.FIG. 8 shows a superjunction diode 501. A semiconductor body 100 comprises a doped zone 110 and a doped layer 130. The doped layer 130 may be an n-type. The doped region 110 may be of the p-type. The doped zone 110 directly adjoins a first surface 101 of the semiconductor body 100. The doped layer 130 directly adjoins a second surface 102 of the semiconductor body 100, which is parallel to the first surface 101. An anode electrode 301 is in direct electrical contact with the doped region 110. A cathode electrode 302 is in direct electrical contact with the doped layer 130. Between the doped zone 110 and the doped layer 130, a drift layer 120 is formed in a cell region 210 and in an edge region 290 surrounding the cell region 210. The drift layer 120 includes first n-type portions 121 and second p-type portions 122.When the superjunction diode 501 is forward biased, a forward current flows through the first parts 121 in the cell region 210. At least a portion of the first and second portions 121, 122 other than the first portions 121 in the cell region 210 includes auxiliary contaminants 400 and / or an auxiliary structure where the mean free path length is reduced compared to areas outside the auxiliary structure and without auxiliary contaminants 400. According to an embodiment, at least a portion of the second portions 122 in the edge region 290, for example the second portions 122 closest to an edge of the semiconductor body 100, includes the auxiliary contaminants 400 or comprises the auxiliary structures. According to other embodiments, each of the second parts 122 in the edge region 290 is provided with an auxiliary structure and / or contains auxiliary contaminants 400. According to another embodiment, at least some of the second portions 122 in the cell region 210, or all of these may include or contain auxiliary contaminants. According to further embodiments, one, some or all of the first parts 121 in the edge region 290 may comprise an auxiliary structure or may contain auxiliary contaminants 400. The auxiliary contaminants 400 may be provided in a sub-region of the edge region 290 close to the edge of the semiconductor body 100 or in the entire edge region 290.The auxiliary contaminants 400 reduce the mean free path length of the charge carriers in the regions of the drift layer 120 in which the electric field strength has a maximum. The charge carriers absorb less energy and thus a critical electric field strength at which electrode-hole pairs are generated and avalanche breakdown is triggered is increased. The auxiliary impurities 400 increase the voltage blocking capability in the edge region 290 of the superjunction diode 501 and may at least approximate the voltage blocking capability in the edge region 290 to that in the cell region 290.FIG. 9 relates to a method of manufacturing a superjunction semiconductor device. A doped layer of a first conductivity type is formed (902). A drift layer is formed on the doped layer, wherein the drift layer comprises a cell region and an edge region surrounding the cell region, and wherein first portions of the first conductivity type and second portions of a second conductivity type opposite to the first conductivity type are formed in the cell and edge regions (904). Above the drift layer, at least one doped region is formed in the cell region, wherein a forward current flows between the at least one doped region and the doped layer through the first portions in the cell region (906). At least a portion of the first and second portions other than the first portions in the cell region is provided with an auxiliary structure or with auxiliary impurities, which reduces the avalanche rate (908).According to an embodiment, the drift layer is formed by epitaxial growth. For example, the drift layer may be formed by a growth step. Thereafter, trenches may be etched into the epitaxial layer being grown, and the first and second portions may be formed by out-diffusion of sidewall implants and / or further epitaxial growth in the etched trenches.According to another embodiment, the drift layer is formed by repeating a process sequence again, which comprises epitaxial growth of an underlayer and at least one implantation. For example, the grown underlayer may be of the first conductivity type, and the grown underlayer may be counter doped in regions allocated to the second portions by using an implantation mask that shields regions reserved for the first portions. According to another embodiment, an intrinsic underlayer is grown, the first portions are formed by an implantation using a first implantation mask shielding at least the second portions, and the second portions are formed by an implantation using a second implantation mask shielding at least the first portions.According to an embodiment, at least one of the repeated sequences comprises providing auxiliary impurities in selected regions provided for the auxiliary impurities. According to an embodiment, the implantation process may comprise a masked auxiliary implantation using an implantation mask that shields the cell region or a central portion of the cell region and does not shield the edge region.The auxiliary contaminants may be implanted at different depths using different implantation energies. A net dopant concentration may vary from sublayer to sublayer, and for each sublayer, the net dopant concentration may be a function of a distance to the cell region.According to a further embodiment, the grown underlayer is doped by a first mask implant using a first implantation mask that shields regions allocated to the second parts in the cell region and by a second mask implant using a second implantation mask that shields regions allocated to the first parts in the cell region. The one of the first and second mask implants with the lower implantation dose uses a mask that does not shield the edge region, and the one of the first and second mask implants with the higher implantation dose uses a mask with further openings in the edge region than in the cell region. The same net dopant concentration as with two usually patterned implants, but at a higher absolute dopant concentration, can be achieved, resulting in increased scattering and a lower avalanche rate.Although specific embodiments are illustrated and described herein, it will be understood by those skilled in the art that a variety of other and / or equivalent implementations may be utilized for the specific embodiments shown and described without departing from the scope of the present invention. For example, embodiments related to IGFETs and IGBTs may include gate electrode structures formed in trenches etched into the drift layer from the first surface. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein.

Claims

A superjunction semiconductor device comprising: at least one doped region (110) in a cell region (210); a drift layer (120) formed in the cell region (210) and in an edge region (290) surrounding the cell region (210) and having first parts (121) of the first conductivity type and second parts (122) of a second conductivity type opposite to the first conductivity type, wherein the first parts (121) in the cell region (210) are arranged in a current path of a forward or forward current from / to the at least one doped region (110), and wherein at least a part of the first and second parts (121, 122) in the edge region (290) and / or at least a part of the second parts (122) in the cell region (210) includes auxiliary impurities (400), to locally reduce an avalanche rate.The superjunction semiconductor device according to claim 1, wherein the auxiliary impurities (400) are effective to locally reduce a mean free path length of the carriers.The superjunction semiconductor device according to claim 1 or 2, wherein the auxiliary impurities (400) are effective to locally reduce an electric field strength.The superjunction semiconductor device according to any one of claims 1 to 3, wherein the auxiliary impurities (400) are effective to increase scattering of carriers in the drift layer (120).The superjunction semiconductor device according to any one of claims 1 to 4, wherein the auxiliary impurities (400) replace atoms of a semiconductor material forming the drift layer (120) in a crystal lattice of the semiconductor material and are capable of scattering carriers by the perturbation of a crystal potential of the crystal lattice.The superjunction semiconductor device according to any one of claims 1 to 5, wherein the auxiliary impurities (400) act as donors or acceptors and at least partially compensate for doping of the second portions (122) with second conductivity type impurities.The superjunction semiconductor device according to any one of claims 1 to 6, wherein the auxiliary impurities (400) function as donors and acceptors and compensate each other.The superjunction semiconductor device according to any one of claims 1 to 7, wherein at least one of the first parts (121) in the peripheral region (290) includes the auxiliary impurities (400).The superjunction semiconductor device according to any one of claims 1 to 8, wherein all the first and second parts (121, 122) in the peripheral region (290) include the auxiliary impurities (400).A superjunction semiconductor device comprising: at least one doped region (110) in a cell region (210); a drift layer (120) formed in the cell region (210) and in an edge region (290) surrounding the cell region (210) and comprising first portions (121) of the first conductivity type and second portions (122) of a second conductivity type opposite to the first conductivity type, wherein the first portions (121) in the cell region (210) are arranged in a current path of a forward or forward current from / to the at least one doped region (110), and wherein at least one part of the first and second portions (121, 122) in the edge region (290) and / or at least one part of the second portions (122) in the cell region (210) comprises an auxiliary structure (420), In order to locally reduce an avalanche rate and wherein the auxiliary structure (420) has an average dielectric constant which deviates from that of a semiconductor material of the drift layer (120) by not more than 20%.The superjunction semiconductor device according to claim 10, wherein the auxiliary structure (420) is operative to locally reduce an electric field strength.The superjunction semiconductor device according to any one of claims 10 or 11, wherein the auxiliary structure (420) is formed of a charged dielectric material.Superjunction semiconductor device according to any one of claims 10 to 12, wherein the auxiliary structure (420) comprises at least two sub-layers (421, 422) of different materials.The superjunction semiconductor device according to any one of claims 10 to 13, wherein the auxiliary structure (420) is disposed in a central part of one of the second parts (122).The superjunction semiconductor device according to any one of claims 1 to 14, wherein at least one of the second parts (122) in the peripheral region (290) includes the auxiliary impurities (400) or has the auxiliary structure (420).The superjunction semiconductor device according to any one of claims 1 to 15, wherein all the second parts (122) in the cell and edge regions (210, 290) include the auxiliary impurities (400) or have the auxiliary structures (420).The superjunction semiconductor device according to any one of claims 1 to 16, wherein the first and second parts (121, 122) are strip-shaped and arranged in alternating order along a direction perpendicular to the flow direction of the forward current.The superjunction semiconductor device according to any one of claims 1 to 17, wherein the auxiliary impurities (400) and the auxiliary structure (420) are absent in the first parts (121) in the cell region (210), or wherein the first parts (121) in the cell region (210) contain the auxiliary impurities (400) at a concentration lower than 10% of that in the other parts.A superjunction diode with the superjunction semiconductor device according to any one of claims 1 to 18, wherein the at least one doped region (110) is of the second conductivity type and directly adjoins the first and second parts (121, 122) in the cell region (210).An insulated gate superjunction field effect transistor comprising the superjunction semiconductor device according to any one of claims 1 to 18, wherein each of the doped regions (110) is of the first conductivity type and directly adjoins a base region (115) of the second conductivity type, each base region (115) directly adjoining at least a part of the first and a part of the second parts (121, 122).A method of manufacturing a superjunction semiconductor device, comprising: forming a drift layer (120) having, in a cell region (210) and in an edge region (290) surrounding the cell region (210), first portions (121) of the first conductivity type and second portions (122) of a second conductivity type opposite to the first conductivity type; forming at least one doped region (110) over the drift layer (120) in the cell region (210), wherein the first portions (121) in the cell region (210) are arranged in a current path of a forward current from / to the at least one doped region (110); and providing auxiliary impurities (400) in at least one portion of the first and second portions (121, 121, 121, 122) in the edge region (290) and / or at least in a part of the second parts (122) in the cell region (210) in order to locally reduce an avalanche rate.The method of claim 21, wherein the drift layer (120) is formed by repeating a process sequence of growing a sublayer by epitaxy and implanting dopants into the sublayer.The method of claim 22, wherein at least one of the repeated process sequences comprises providing auxiliary contaminants (400) through an auxiliary implantation process.The method of claim 23, wherein the auxiliary implantation process comprises a masked implantation by means of an implantation mask that shields the cell region (210) and does not shield at least a portion of the edge region (290).The method of claim 23, wherein the grown underlayer is intrinsic, portions of the first parts (121) are implanted using a first implantation mask shielding the second parts (122), and portions of the second parts (122) are implanted using a second implantation mask shielding the first parts (121).The method of claim 25, wherein the one of the first and second masked implants having the lower implantation dose uses a mask that does not shield the edge region (290), and wherein the one of the first and second masked implants having the higher implantation dose uses a mask having additional openings in the edge region (290) than in the cell region (210).

Images