High-performance single-chip semiconductor package and methods for its manufacture and semiconductor assembly including this

Abstract

Semiconductor package, comprehensive: a single semiconductor chip, comprising: a semiconductor body with opposing first and second faces; a first electrode on the first surface; and a second electrode on the second surface, wherein the individual semiconductor chip has a defined thickness, measured between the first and second surfaces; and an electrically and thermally conductive base attached to the second electrode on the second surface of the individual semiconductor chip, wherein the base has a first side attached to the second electrode on the second surface of the individual semiconductor chip and has five additional sides that are not covered by the individual semiconductor chip, each side of the base not attached to the individual semiconductor chip being covered by a solderable protective layer.

Description

[0001] The present application relates to semiconductor packages and in particular single-chip semiconductor packages.

[0002] High-power components, such as IGBTs (Insulated Gate Bipolar Transistors), power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), power diodes, etc., are typically assembled by sawing (singling) individual chips from a wafer and assembling the individual chips into packages. Electrical connections to each encapsulated chip are made by wire bonding, metal tapes, metal clips, etc. For many power components with a vertical current path between electrodes on opposite sides of the chip, it is advantageous to fabricate them as thin as possible to reduce the one-state resistance (Rdson) of the component. However, conventional high-power semiconductor packages are not designed for very thin chips, for example, chips < 50 µm (micrometers) thick.Chips less than 50 µm (micrometers) thick are highly prone to cracking during sawing (sing) and chip assembly processes due to the forces involved. Therefore, conventional semiconductor chips typically have a vertical current path much thicker than 50 µm (micrometers). Chips of this thickness have a higher Rdson and inefficient heat transfer due to the limitations imposed by the thick semiconductors. Furthermore, most conventional packages offer only one-sided or two-sided cooling, which reduces continuous heat dissipation for high-performance devices.

[0003] The publication DE 10 2009 044 641 A1 relates to a device with a semiconductor chip and metal foils and a method for manufacturing them.

[0004] According to one aspect, a semiconductor package comprises: a single semiconductor chip, comprising: a semiconductor body with opposing first and second faces; a first electrode on the first face; and a second electrode on the second face, wherein the single semiconductor chip has a defined thickness, measured between the first and second faces; and an electrically and thermally conductive base attached to the second electrode on the second face of the single semiconductor chip, wherein the base has a first side attached to the second electrode on the second face of the single semiconductor chip and five additional sides that are not covered by the single semiconductor chip, each side of the base not attached to the single semiconductor chip being covered by a solderable protective layer.

[0005] According to another aspect, a method for fabricating semiconductor packages comprises: thinning a semiconductor wafer on a second side of the wafer opposite a first side of the wafer, wherein the wafer has several semiconductor chips spaced apart from one another on the first side; applying an electrically and thermally conductive base substrate to the thinned wafer on the second side; separating the semiconductor chips from one another into singular semiconductor chips after applying the base substrate to the second side of the thinned wafer; and separating the base substrate along lines aligned with gaps between adjacent of the singular semiconductor chips to form individual semiconductor packages, each semiconductor package containing one of the singular semiconductor chips and a singular section of the base substrate applied to that chip.

[0006] According to another aspect, a semiconductor assembly comprises: a substrate with multiple conductive regions on a mounting surface of the substrate; and a semiconductor package on the mounting surface of the substrate, wherein the semiconductor package comprises: a single semiconductor chip, comprising: a semiconductor body with opposing first and second faces; a first electrode on the first face that is electrically connected to a conductive region of the substrate; and a second electrode on the second face, wherein the single semiconductor chip has a defined thickness, measured between the first and second faces;and an electrically and thermally conductive base attached to the second electrode on the second face of the single semiconductor chip, wherein the base is electrically connected to a different conductive region of the substrate than the first electrode, wherein the base is connected to a conductive region of the substrate that is not covered by the single semiconductor chip by a metal connector extending from the conductive region along a side of the base facing away from the substrate.

[0007] According to another aspect, a semiconductor package comprises: a single semiconductor chip, comprising: a semiconductor body with opposing first and second faces; a first electrode on the first face; and a second electrode on the second face, wherein the single semiconductor chip has a defined thickness, measured between the first and second faces;and an electrically and thermally conductive base attached to the second electrode on the second face of the individual semiconductor chip, the base having a first side attached to the second electrode on the second face of the individual semiconductor chip and five additional sides not covered by the individual semiconductor chip, each side of the base not attached to the individual semiconductor chip being covered by a protective layer, the base comprising copper and the protective layer being plated onto each side of the base not attached to the individual semiconductor chip.

[0008] The expert will recognize further features and advantages when reading the following detailed description and looking at the accompanying drawings.

[0009] The components in the figures are not necessarily to scale; rather, emphasis has been placed on a clear illustration of the principles of the invention. Furthermore, identical reference numerals in the figures denote corresponding parts. The drawings depict the following: Fig. Figures 1A to 1C illustrate different views of a single-chip semiconductor package according to one embodiment; Fig. Figures 2A to 2L illustrate cross-sectional views of a semiconductor wafer during various stages of a process for manufacturing single-chip semiconductor packages from the semiconductor wafer; Fig. 3A and Fig. Figure 3B illustrates different perspective views of a semiconductor assembly with a single-chip semiconductor package according to one embodiment; Fig. 4A and Fig. Figure 4B illustrates different perspective views of a semiconductor assembly with a single-chip semiconductor package according to another embodiment; and Fig. Figure 5 illustrates a sectional view of a semiconductor assembly with a single-chip semiconductor package according to a further embodiment.

[0010] The embodiments described in this text provide a single-chip semiconductor package that can support ultra-thin semiconductor chips, thereby reducing the one-state resistance for devices with a vertical current path and increasing the package's thermal transfer capability. Furthermore, the single-chip semiconductor package allows for up to six-sided cooling of the device, thus increasing continuous heat dissipation.

[0011] Fig. Figure 1A illustrates a perspective view of an embodiment of a single-chip semiconductor package 100, Fig. Figure 1B illustrates a top-down plan view of the single-chip semiconductor package 100, and Fig. Figure 1C illustrates a sectional view of Package 100 along line AA' in Fig. 1B. The semiconductor package 100 contains a single semiconductor chip 102 and an electrically and thermally conductive base 104. The single semiconductor chip 102 contains a semiconductor body 106 with opposing first (e.g., upper) and second (e.g., lower) surfaces 107, 109 and insulated sides 108 between the first and second surfaces 107, 109. The chip 102 also contains a first electrode 110 on the first surface 107 and a second electrode 112 on the second surface 109. An additional electrode 111 may be arranged on the first surface 107 of the chip 102, depending on the type of component (e.g., in the case of a transistor).

[0012] The individual semiconductor chip 102 has a defined thickness (Tdie), measured between the first and second surfaces 107, 109, a defined width (Wdie), measured along one of the insulated sides 108, and a defined length (Ldie), measured along another of the insulated sides 108, where Ldie ≥ Wdie. The base 104 consists of an electrically and thermally conductive material, such as copper, copper alloy (e.g., Cu-Fe, Cu-Sn, Cu-Zr, Cu-Ni-Si, Cu-Cr-Sn-Zn, etc.), aluminum, aluminum alloy (e.g., Al-Ag, Al-Au, Al-Co, Al-Fe, etc.), copper-plated aluminum, etc.

[0013] Generally, the base 104 is attached to the second electrode 112 on the second surface 109 of the individual semiconductor chip 102. In one embodiment, the base 104 has a first side 114 that is bonded or sintered to the second electrode 112 of the chip 102 by a bonding layer 116, so that the base 104 has five additional sides that are not covered by the chip 102. Up to six sides of the package 100 can be cooled according to this embodiment, i.e., along the five uncovered sides of the base 104 and along the first surface 107 of the individual semiconductor chip 102. Each side of the base 104 that is not attached to the individual semiconductor chip 102 can be covered by a protective layer 118. In the case of a copper-containing base 104, the protective layer 118 can be plated onto each uncovered side of the base 104.The protective layer 118 prevents the copper-containing base 104 from oxidizing and provides a solderable material for the base 104.

[0014] The base 104 has the same length (Lbase) and width (Wbase) as the individual semiconductor chip 102. The thickness (Tbase) of the base 104 is greater than the thickness (Tdie) of the chip 102. For example, Tbase can be in the micrometer range, such as 300 µm (micrometers), 400 µm (micrometers), or even thicker. In one embodiment, the semiconductor body 106 of the chip 102 comprises silicon, and Tdie ≤ 50 µm (micrometers). Other chip and base thicknesses can be implemented, depending on the type of chip 102 and the application for which the chip 102 is intended. For example, in the case of a power transistor (for example, an IGBT or a power MOSFET) formed in the semiconductor body 106, Tdie ≤ 20 µm (micrometers). In the case of a power diode formed in the semiconductor body 106, Tdie can be ≤ 10 µm (micrometers).In any case, the one-state resistance (Rdson) of the chip 102 is reduced by means of an ultra-thin semiconductor body 106, for example ≤ 50 µm (micrometers).

[0015] Such a thin semiconductor body can be realized in a semiconductor package without damaging the chip by attaching a base substrate to the wafer from which the chips are manufactured. The base substrate is split as part of the separation process, creating a stable support structure in the form of separate, electrically and thermally conductive bases. These are attached to each ultra-thin chip before interconnects, such as bond wires, tapes, clips, etc., are connected to the electrodes of the respective chips. This type of semiconductor package allows for reduced Rdson and increased heat transfer capability, while simultaneously reducing or eliminating the likelihood of the ultra-thin chips cracking during or after separation from the common wafer.

[0016] Next, a method for manufacturing the single-chip semiconductor package 100, which is used in the Fig. 1A to 1C illustrates this, with reference to the Fig. 2A to 2L described. The Fig. 2A to 2L illustrate sectional views during different stages of the manufacturing process.

[0017] Fig. Figure 2A shows a semiconductor wafer 200 with opposing first and second faces 201, 203. Any suitable semiconductor wafer 200 can be used, such as single-element semiconductors (e.g., Si, Ge, etc.), silicon-on-insulator semiconductors, binary semiconductors (e.g., SiC, GaN, GaAs, etc.), ternary semiconductors, etc., with or without epitaxial layers. Several semiconductor chips 202 are spaced apart on the first face 201 of the wafer 200, for example, by an insulating region 204, which can be an insulating material, such as SiO2, an implanted region of the wafer 200, etc. Any desired types of components can be formed in the semiconductor body 206 of the chips 202, such as transistors, diodes, etc. One region of the wafer 200 forms the semiconductor body 206 of each chip 202.The Wafer 200 has a defined pre-thinning thickness (Twafer1), including any epitaxial layers and face-side metallizations that may be present. The pre-thinning thickness Twafer1 of the Wafer 200 is in the micrometer range, for example, 500 µm (micrometers) or greater.

[0018] Fig. Figure 2B shows the semiconductor wafer 200 after a support substrate 208 has been attached to the wafer 200 on the first side 201, before the wafer 200 is thinned. The support substrate 208 supports the wafer 200 during the subsequent thinning process on the second side 203 of the wafer 200. In one embodiment, the support substrate 208 comprises a glass material that is bonded to the first side 201 of the wafer 200. However, other types of support substrates 208 can also be used.

[0019] Fig. Figure 2C shows the structure after the semiconductor wafer 200 has been thinned on the second side 203 of the wafer 200. Any standard semiconductor wafer thinning process can be used to thin the wafer 200, such as mechanical grinding, chemical-mechanical polishing (CMP), wet etching and atmospheric downstream plasma (ADP), chemical dry etching (DCE), etc. In one embodiment, the wafer 200 has a thickness after thinning (Twafer2) of 50 µm (micrometers) or less. In the case of transistors fabricated in the semiconductor body 206 of the chips 202, Twafer2 can be 20 µm (micrometers) or less. In the case of diodes fabricated in the semiconductor body 206 of the chips 200, Twafer2 can be 10 µm (micrometers) or less. In any case, the thickness (Twafer2) of the thinned wafer 200 corresponds to the final thickness (Tdie) of the individual chips 202 after separation into individual packages, as for example in Fig. 1C shown. The support substrate 208 sufficiently supports the wafer 200 during the thinning process to obtain ultra-thin chips 202 with minimal damage.

[0020] Fig. Figure 2D shows the structure after an electrically conductive layer 210 has been formed on the second side 203 of the thinned wafer 200. In one embodiment, the electrically conductive layer 210 is a eutectic bonding layer, such as Si / Ti / NiV / Cu / Sn or Al / Ti / NiV / AuSn. In another embodiment, the electrically conductive layer 210 is a sintering paste, such as a silver paste. In a further embodiment, the electrically conductive layer 210 is a conductive adhesive film, such as a silver-filled chip mounting film.

[0021] Fig. Figure 2E shows the structure during the attachment of an electrically and thermally conductive base substrate 212 to the thinned wafer 200 on the second side 203 of the wafer 200, as indicated by the upward-pointing arrows in Fig. 2E indicated. The base substrate 212 can consist of any suitable electrically and thermally conductive material, such as copper, copper alloy (e.g., Cu-Fe, Cu-Sn, Cu-Zr, Cu-Ni-Si, Cu-Cr-Sn-Zn, etc.), aluminum, aluminum alloy (e.g., Al-Ag, Al-Au, Al-Co, Al-Fe, etc.), copper-plated aluminum, etc. The thickness (Tbase_sub) of the base substrate 212 is significantly greater than the thickness (Twafer2) of the thinned wafer 200. For example, Tbase_sub can be 300 µm (micrometers), 400 µm (micrometers), or even greater. In any case, according to the Fig. In the illustrated embodiment shown in Figure 2E, the electrically conductive layer 210 is arranged between the base substrate 212 and the second side 203 of the thinned wafer 200, and the base substrate 212 is attached to the thinned wafer 200.

[0022] In the case of a non-paste-like sintering material as the electrically conductive layer 210, a sintered bond between the base substrate 212 and the thinned wafer 200 can be formed in a single sintering process or in two sintering processes. For example, if the support substrate 208 comprises a glass material with a relatively low melting point, for example, about 200°C, a partially sintered bond between the base substrate 212 and the thinned wafer 200 can be formed under pressure and at a first temperature below the melting point of the glass material. The partially sintered bond is strong enough to press the base substrate 212 at least temporarily against the thinned wafer 200 while the support substrate 208 is removed from the thinned wafer 200.The sintered bond between the base substrate 212 and the thinned wafer 200 is strengthened under pressure and at a second temperature higher than the melting temperature of the glass material after the support substrate 208 has been removed from the thinned wafer 200 (for example, approximately 250°C to 350°C in the case of a CuSn sintered material). Alternatively, the base substrate 212 is eutectically bonded to the thinned wafer 200 on the second side 203 of the wafer 200 if a eutectic bonding material is used as the electrically conductive layer 210. In the case of a conductive adhesive film, the base substrate 212 is bonded to the thinned wafer 200 on the second side 203 of the wafer 200 at approximately 150°C to 250°C with or without pressure.

[0023] Fig. Figure 2F shows the structure after the base substrate 212 has been attached to the thinned wafer 200 on the second side 203 of the wafer 200 and the support substrate 208 has been removed. In some embodiments, the side 213 of the base substrate 212 facing away from the thinned wafer can be roughened so that this side 213 of the base 212 has a larger surface area than other sides of the base 212. For example, a region with microstructures can be formed on this side 213 of the base substrate 212.

[0024] Fig. Figure 2G shows the structure after the semiconductor chips 202 have been separated from each other into singular semiconductor chips 202'. The base substrate 212 provides sufficient support during the separation process and subsequent processing, minimizing tearing of the resulting ultra-thin chips 202'. Any suitable singulation (sawing) technique can be used to separate the chips 202, such as chemical etching, mechanical sawing (singulation), laser cutting, etc. The singulation (sawing) process can be stopped at the electrically conductive layer 210, which attaches the base substrate 212 to the second side 203 of the thinned wafer 200, so that the base substrate 212 remains completely intact after separation. Gaps 214 exist between adjacent separated chips 202'.

[0025] Fig. Figure 2H shows the structure after the gaps 214 between adjacent singular semiconductor chips 202' have been filled with an insulating material 216. The insulating material 216 can be a laminate, potting compound, passivation material, or other suitable material for protecting the exposed sidewalls of the separated chips 202'. For example, organosilicate glass (SiCOH) or silicon nitride can be used. For certain types of edge-sensitive semiconductor chips, the insulating material 216 can be selected to protect the edge. In general, the insulating material 216 insulates the sidewalls of the separated chips 202'. The insulating material 216 can also be selected to provide passivation and / or corrosion protection.

[0026] Fig. Figure 2I shows the structure after a first support layer 218, such as a carrier or tape, has been attached to the back of the structure, i.e., the side of the structure with the base substrate 212. The first support layer 218 holds the separated chips 202' in place during the separation of the base substrate 212.

[0027] Fig. Figure 2J shows the structure after the base substrate 212 has been separated along lines aligned with the columns 214 between the separated chips 202' to form individual semiconductor packages 220, which are held together by the first support layer 218. Each semiconductor package 220 contains one of the separated semiconductor chips 202' and a singular section 212' of the base substrate 212 attached to that separated chip 202'. The sidewalls of each separated chip 202' remain covered by the insulating material 216 in the individual semiconductor packages 220, as also shown in the Fig. 1A to 1C is shown.

[0028] According to the in Fig. In the embodiment shown in Figure 2J, the separation of the base substrate 212 can begin at the front face of the structure, where the separated chips 202' are located. The gaps 214 between the separated chips 202' are clearly visible in this case. Alternatively, the separation of the base substrate 212 can begin on side 213 of the base substrate 212, facing away from the separated chips 202'. The separation of the base substrate 212 can begin on this side 213, for example, by sawing or structuring along the structure, if the gaps 214 between the separated chips 202' are known or visible. In one embodiment, infrared light can be used to detect the structure of the separated chips 202' if the thinned wafer 200 has a thickness of less than 50 µm (micrometers).In another embodiment, cameras facing the chip side and the base substrate side of the structure can be used in coordination to detect the structure of the separated chips 202'. In general, any suitable technique, such as mechanical sawing, chemical etching (with photolithography), EDM (electro discharge machining), etc., can be used to separate the base substrate 212 to form the individual semiconductor packages 220.

[0029] Fig. Figure 2K shows the structure after the first support layer 218 has been removed from the back of the structure and a second support layer 222, such as a carrier or strip, has been applied to the front of the structure, i.e., the side of the structure with the separate chips 202'. The second support layer 222 holds the individual packages 220 in place, while a protective layer 224 is applied to the exposed sides of the singular base sections 212'. In the case of copper-containing base sections 212', the protective layer 224 can be plated onto each exposed side of the base sections 212'. For example, tinning, gold plating, or silver plating can be used. Such plating protects the copper from oxidation and provides a solderable material for the base sections 212'.The reverse side 213 of the singular base sections 212' can be marked after plating using any suitable marking technique, such as laser marking or bar coding.

[0030] Fig. Figure 2L shows the structure after the second support layer 218 has been removed from the front of the structure and a third support layer 226, such as a carrier or tape, has been attached to the back of the structure. Reattaching a support layer 226 to the back of the structure allows for a final package test. The third support layer 226 can be an electrically conductive material to ensure good electrical contact with the back electrode of the individual packages 220, which is formed by the respective singular base sections 212'. The third support layer 226 can be removed after testing, yielding the individual semiconductor packages 220, for example, of the type shown in the Fig. 1A to 1C are shown. The individual semiconductor packages 220 are ready for use on the next assembly level.

[0031] The Fig. 3A and Fig. Figure 3B shows an embodiment of a semiconductor assembly containing a semiconductor package 300 of the type previously described in this text. Fig. Figure 3A shows the semiconductor package 300 during the assembly process, indicated by the curved arrow in Fig. 3A is indicated, and Fig. Figure 3B shows the assembly after package assembly.

[0032] The semiconductor assembly comprises a substrate 302 with several conductive regions 304, 306, 308, such as bonding islands, on a mounting surface 303 of the substrate 302. The substrate 302 can contain an insulating material, such as ceramic, with a top and / or bottom metallization structured to form the conductive regions 304, 306, 308. In other embodiments, the substrate 302 is a leadframe, and the conductive regions 304, 306, 308 are part of the leadframe, for example, so-called die pads or terminal leads. Other types of substrates can also be used, as is known to those skilled in the art in semiconductor encapsulation.

[0033] The semiconductor package 300 contains a single semiconductor chip comprising a semiconductor body 310 with opposing first and second faces and insulated sides between the first and second faces. The chip 310 also has a first electrode 312 on the first face, which is electrically connected to a conductive region 306 of the substrate 302, and a second electrode (not shown) on the second face. The chip 310 has a defined thickness (Tdie), measured between the first and second faces, a defined width (Wdie), measured along one of the insulated sides, and a defined length (Ldie), measured along another of the insulated sides. An electrically and thermally conductive base 314 is attached to the second electrode on the second face of the single semiconductor chip 310. The base 314 has the same length (Lbase) and width (Wbase) as the single semiconductor chip 310 and is thicker (Tbase) than the chip 310.The base 314 is electrically connected to another conductive region 304, 308 of the substrate 302 as the first electrode 312.

[0034] According to the Fig. 3A and Fig. In the semiconductor assembly embodiment shown in Figure 3B, the semiconductor chip 310 is a diode chip and therefore has one electrode 312 on the first face of the chip 310 and one electrode (not shown) on the second face of the chip 310. For example, the emitter electrode 312 of the diode can be located on the first face of the chip 310, facing away from the assembly substrate 302, and the base / collector electrode (not shown) of the diode can be located on the second face of the chip 310, facing away from the substrate 302. The emitter electrode 312 can be bonded or sintered to the conductive region 306 of the substrate beneath the emitter electrode 312 by a bonding layer 316 between the conductive region 306 and the emitter electrode 312.The base 314 is connected to a conductive region 304, 308 of the substrate 302 that is not covered by the single semiconductor chip 310, in order to form an electrical connection to the base / collector electrode of the diode. In one embodiment, the base 314 is connected to conductive regions 304, 308 adjacent to opposite sides of the chip 310 by a respective solder joint 318, 320, which extends from each of these conductive regions 304, 308 along the corresponding side of the base 314 that does not face the substrate 302, i.e., the lateral sides of the base 314. The conductive regions 304, 308 of the substrate 302 that are connected to the base 314 have the same potential. The insulated sides of chip 310 electrically isolate the semiconductor body and the emitter electrode 312 of chip 310 from the solder joints 318, 320.

[0035] The Fig. 4A and Fig. Figure 4B shows a further embodiment of a semiconductor assembly containing a semiconductor package 400 of the type previously described in this text. Fig. Figure 4A shows the semiconductor package 400 during the assembly process, indicated by the curved arrow in Fig. 4A is indicated, and Fig. Figure 4B shows the assembly after package assembly.

[0036] The semiconductor assembly in the Fig. 4A and Fig. 4B is similar to the one used in the Fig. 3A and Fig. As shown in Figure 3B, the single semiconductor chip 402 contained in package 400 is a transistor chip instead of a diode chip. For example, chip 402 can be an IGBT, MOSFET, or JFET chip. Transistors have three terminals. To make the electrical connections to the respective terminals, two electrodes 404, 406 are formed on the first face (top) of chip 402, and one electrode (not shown) is provided on the second face (bottom) of chip 402. For example, the source / emitter and gate / base electrodes 404, 406 of the transistor can be located on the first face of chip 402, which faces the assembly substrate 408, and the drain / collector electrode of the transistor can be located on the second face of chip 402, which faces away from the substrate 408.

[0037] The gate / base electrode 406 of the chip 402 can be bonded or sintered to a first conductive region 410 of the substrate 408 beneath the gate / base electrode 406 by a first interconnection layer 412 between the first conductive region 410 and the gate / base electrode 406. The source / emitter electrode 404 of the chip 402 can be bonded or sintered to a second (different) conductive region 414 of the substrate 408 beneath the source / emitter electrode 404 by a second (different) interconnection layer 416 between the second conductive region 414 and the source / emitter electrode 404. The base 418 of the semiconductor package 400 is connected to a conductive region 420, 422 of the substrate 408 that is not covered by the individual semiconductor chip 402 to form an electrical connection to the drain / collector electrode of the transistor.In one embodiment, the base 418 is connected to conductive regions 420, 422 adjacent to opposite sides of the chip 402 by a respective solder joint 424, 426, which extends from each of these conductive regions 420, 422 along the corresponding lateral side of the base 418. The conductive regions 420, 422 of the substrate 408 that are connected to the base 418 have the same potential. The insulated sides of the chip 402 electrically isolate the semiconductor body and the source / emitter and gate / base electrodes 404, 406 of the chip 402 from the solder joints 424, 426.

[0038] Fig.Figure 5 shows a sectional view of another embodiment of a semiconductor assembly containing a semiconductor package 500 of the type previously described in this text. According to this embodiment, the semiconductor chip 502 is a transistor chip with two electrodes 504, 506 formed on a first surface (bottom) of the chip 502, which faces a substrate 508, for example, of the type previously described in this text, and an electrode 510 formed on the second surface (top) of the chip 502, which faces away from the substrate 508. For example, the source / emitter and gate / base electrodes 504, 506 of the transistor can be arranged on the first surface of the chip 502, which faces the substrate 508, and the drain / collector electrode 510 of the transistor can be arranged on the second surface of the chip 502, which faces away from the substrate 508.

[0039] The gate / base electrode 506 of the chip 502 can be bonded or sintered to a first conductive region 512 of the substrate 508 beneath the gate / base electrode 506 by a first interconnect layer between the first conductive region 512 and the gate / base electrode 506. The source / emitter electrode 504 of the chip 502 can be bonded or sintered to a second (different) conductive region 514 of the substrate 508 beneath the source / emitter electrode 504 by a second (different) interconnect layer between the second conductive region 514 and the source / emitter electrode 504. The base 516 of the package 500 is connected to a conductive region 518 of the substrate 508, which is not covered by the individual semiconductor chip 502, by a metal connector 520, such as a clip, a tape or bond wires, extending from the conductive region 518 along the side of the base 516 facing away from the substrate 508.The metal connector 520 can be a single continuous structure (for example, a clip) that connects conductive regions 518 on opposite sides of the chip 502 to the side of the base 516 facing away from the substrate 508. In either case, the conductive regions 518 of the substrate 508 connected to the base 516 have the same potential. An epoxy resin 522 can be used to attach the metal connector 520 to the top of the base 516, i.e., the side of the base 516 facing away from the substrate 508. In any case, the insulated sides of the chip 502 electrically isolate the semiconductor body and the source / emitter and gate / base electrodes 504, 506 of the chip 502 from the metal connector 520. In further embodiments, the base 516 can face the substrate 508 instead of the chip 502.According to this embodiment, the base 516 is connected to a conductive region of the substrate 508 below the base 516, and the electrodes 504, 506 on the other side of the semiconductor package 500 are connected to other conductive regions of the substrate 508 by solder joints or metal connectors, as previously described in this text.

[0040] In general, the single semiconductor package containing an ultra-thin single chip, as described herein, can be included as a component or chip within any conventional semiconductor package. The single semiconductor package can be bonded or mounted in standard packages using common chip bonding, wire bonding, and clipping technologies, just like any conventional power chip. Some purely illustrative examples of standard packages in which the single semiconductor package described herein can be used are TO2XX, SON, TDSON8, TSDSON8, WISON8, etc. The single semiconductor package described herein can be used as a standalone chip or with other chips in the same package, for example, in a chip-by-chip, chip-on-chip, chip-by-chip-by-chip, or chip-by-chip-on-chip configuration, etc. Examples

[0041] The following section explains semiconductor packages, methods for manufacturing semiconductor packages, and semiconductor assemblies using examples.

[0042] Example 1 is a semiconductor package comprising: a single semiconductor chip, comprising: a semiconductor body with opposing first and second faces, and insulated sides between the first and second faces; a first electrode on the first face; and a second electrode on the second face, wherein the single semiconductor chip has a defined thickness, measured between the first and second faces, a defined width, measured along one of the insulated sides, and a defined length, measured along another of the insulated sides; and an electrically and thermally conductive base attached to the second electrode on the second face of the single semiconductor chip, wherein the base has the same length and width as the single semiconductor chip.

[0043] Example 2 is a semiconductor package according to Example 1, where the defined thickness of the individual semiconductor chip is 50 micrometers or less.

[0044] Example 3 is a semiconductor package according to Example 2, wherein a transistor is formed in the semiconductor body, wherein the individual semiconductor chip further comprises a third electrode on the first surface of the semiconductor body, and the defined thickness of the individual semiconductor chip is 20 micrometers or less.

[0045] Example 4 is a semiconductor package according to Example 2, wherein a diode is formed in the semiconductor body and the defined thickness of the individual semiconductor chip is 10 micrometers or less.

[0046] Example 5 is a semiconductor package according to one of the preceding examples, wherein the base has a first side which is bonded or sintered to the second electrode on the second face of the individual semiconductor chip by a bonding layer, and has five additional sides which are not covered by the individual semiconductor chip.

[0047] Example 6 is a semiconductor package according to one of the preceding examples, wherein each side of the base that is not attached to the individual semiconductor chip is covered by a protective layer.

[0048] Example 7 is a semiconductor package according to Example 6, wherein the base comprises copper and the protective layer is plated onto each side of the base that is not attached to the individual semiconductor chip.

[0049] Example 8 is a semiconductor package according to one of the preceding examples, wherein one side of the base facing away from the single semiconductor chip has a roughened surface with microstructures, such that this side of the base has a larger surface area than other sides of the base.

[0050] Example 9 is a method for fabricating semiconductor packages, comprising: thinning a semiconductor wafer on a second side of the wafer opposite a first side of the wafer, wherein the wafer has several semiconductor chips spaced apart from one another on the first side; depositing an electrically and thermally conductive base substrate onto the thinned wafer on the second side; separating the semiconductor chips from one another into singular semiconductor chips after depositing the base substrate on the second side of the thinned wafer; filling gaps between adjacent singular semiconductor chips with an insulating material;and separating the base substrate along lines aligned with the columns to form individual semiconductor packages, each semiconductor package containing one of the singular semiconductor chips and a singular section of the base substrate attached to that chip, the sidewalls of each chip remaining covered by the insulating material in the individual semiconductor packages.

[0051] Example 10 is a method according to Example 9, wherein the individual semiconductor chips each contain a transistor and the wafer is thinned on the second side to a thickness of 50 micrometers or less.

[0052] Example 11 is a method according to Example 9 or 10, wherein the individual semiconductor chips each contain a diode and the wafer is thinned on the second side to a thickness of 50 micrometers or less.

[0053] Example 12 is a method according to any of Examples 9 to 11, further comprising forming an electrically conductive layer on the second side of the thinned wafer before the base substrate is applied to the thinned wafer, such that the electrically conductive layer is arranged between the base substrate and the second side of the thinned wafer.

[0054] Example 13 is a method according to any of Examples 9 to 12, further comprising the application of a support substrate to the wafer on the first side before the wafer is thinned, wherein the support substrate supports the wafer during thinning on the second side.

[0055] Example 14 is a method according to Example 13, wherein the support substrate comprises a glass material, and wherein the application of the base substrate to the thinned wafer on the second side comprises: forming a partially sintered bond between the base substrate and the thinned wafer under pressure and at a first temperature below the melting temperature of the glass material; removing the support substrate from the thinned wafer after the partially sintered bond between the base substrate and the thinned wafer has been formed; and strengthening the sintered bond between the base substrate and the thinned wafer under pressure and at a second temperature higher than the melting temperature of the glass material after the support substrate has been removed from the thinned wafer.

[0056] Example 15 is a method according to any of Examples 9 to 14, wherein the separation of the base substrate along lines aligned with the columns begins on a side of the base substrate pointing away from the singular semiconductor chips.

[0057] Example 16 is a method according to any of Examples 9 to 15, which further comprises roughening a side of the base substrate facing away from the thinned wafer, so that this side of the base has a larger surface area than other sides of the base.

[0058] Example 17 is a method according to any of Examples 9 to 16, which further comprises: mounting the individual semiconductor packages onto a support layer on one side of the singular semiconductor chips facing away from the singular sections of the base substrate; and covering each free side of the singular sections of the base substrate with a protective layer when the individual semiconductor packages are mounted onto the support layer.

[0059] Example 18 is a method according to Example 17, wherein the singular sections of the base substrate comprise copper and the protective layer is plated onto each free side of the singular sections of the base substrate.

[0060] Example 19 is a semiconductor assembly comprising: a substrate with multiple conductive regions on a mounting surface of the substrate; and a semiconductor package on the mounting surface of the substrate, wherein the semiconductor package comprises: a single semiconductor chip comprising: a semiconductor body with opposing first and second faces, and insulated sides between the first and second faces; a first electrode on the first face electrically connected to a conductive region of the substrate; and a second electrode on the second face, wherein the single semiconductor chip has a defined thickness, measured between the first and second faces, a defined width, measured along one of the insulated sides, and a defined length, measured along another of the insulated sides;and an electrically and thermally conductive base attached to the second electrode on the second face of the single semiconductor chip, the base having the same length and width as the single semiconductor chip and being electrically connected to a different conductive region of the substrate than the first electrode.

[0061] Example 20 is a semiconductor assembly according to Example 19, wherein a transistor is formed in the semiconductor body, wherein the individual semiconductor chip further comprises a third electrode on the first surface of the semiconductor body which is electrically connected to a different conductive region of the substrate than the first electrode and the base, and the defined thickness of the individual semiconductor chip is 20 micrometers or less.

[0062] Example 21 is a semiconductor assembly according to Example 19, wherein a diode is formed in the semiconductor body and the defined thickness of the individual semiconductor chip is 10 micrometers or less.

[0063] Example 22 is a semiconductor assembly according to any of Examples 19 to 21, wherein the first face of the semiconductor body faces the substrate, the first electrode is bonded or sintered to a conductive region of the substrate below the first electrode by a bonding layer between the conductive region and the first electrode, and the base is connected to a conductive region of the substrate that is not covered by the individual semiconductor chip.

[0064] Example 23 is a semiconductor assembly according to Example 22, wherein the base is connected to a conductive region of the substrate not covered by the individual semiconductor chip by a solder joint extending from the conductive region along a side of the base not facing the substrate, and wherein the insulated sides of the semiconductor body electrically isolate the semiconductor body and the first electrode from the solder joint.

[0065] Example 24 is a semiconductor assembly according to Example 22, wherein the base is connected to a conductive region of the substrate not covered by the individual semiconductor chip by a metal connector extending from the conductive region along the side of the base facing away from the substrate, and wherein the insulated sides of the semiconductor body electrically insulate the semiconductor body and the first electrode from the metal connector.

[0066] Spatially relative terms, such as "under," "below," "lower," "above," "above," and the like, are used to simplify the description and explain the positioning of one element relative to another. These terms should be understood as encompassing orientations of the structural element other than those shown in the figures. Furthermore, terms such as "first," "second," and the like are also used to describe different elements, regions, sections, etc., and should likewise not be understood in a restrictive sense. The same terms always refer to the same elements in the description.

[0067] For the purposes of this text, the terms "with," "exhibit," "contain," "comprise," and the like are open-ended terms that indicate the presence of the mentioned elements or characteristics but do not exclude the presence of further elements or characteristics. The articles "a / an / an" or "the / a / an" are to be understood as including both the plural and singular meanings, unless the context clearly suggests otherwise.

Claims

[1] Semiconductor package, comprising: a single semiconductor chip, comprising: a semiconductor body with opposing first and second faces; a first electrode on the first surface; and a second electrode on the second surface, wherein the individual semiconductor chip has a defined thickness, measured between the first and second surfaces; and an electrically and thermally conductive base attached to the second electrode on the second surface of the single semiconductor chip, wherein the base has a first side attached to the second electrode on the second surface of the single semiconductor chip and has five additional sides that are not covered by the single semiconductor chip, each side of the base not attached to the single semiconductor chip being covered by a solderable protective layer. [2] Semiconductor package according to claim 1, wherein the base has a larger area than the semiconductor body. [3] Semiconductor package according to claim 1 or 2, wherein the individual semiconductor chip further comprises insulated sides between the first and second faces of the semiconductor body, wherein the insulated sides surround the semiconductor body. [4] Semiconductor package according to any of the preceding claims, wherein the base has the same length and width as the individual semiconductor chip. [5] Semiconductor package according to any of the preceding claims, wherein the first side of the base is attached to the second electrode by bonding or sintering through a compound layer. [6] Semiconductor package according to any of the preceding claims, wherein the defined thickness of the individual semiconductor chip is 50 micrometers or less. [7] Semiconductor package according to claim 6, wherein a transistor is formed in the semiconductor body, wherein the individual semiconductor chip further comprises a third electrode on the first surface of the semiconductor body, and the defined thickness of the individual semiconductor chip is 20 micrometers or less. [8] Semiconductor package according to claim 6, wherein a diode is formed in the semiconductor body and the defined thickness of the individual semiconductor chip is 10 micrometers or less. [9] Semiconductor package according to any of the preceding claims, wherein the base comprises copper and the protective layer is plated onto each side of the base that is not attached to the individual semiconductor chip. [10] Method for manufacturing semiconductor packages, the method comprising: Thinning of a semiconductor wafer on a second side of the wafer opposite a first side of the wafer, wherein the wafer has multiple semiconductor chips spaced apart from each other on the first side; Applying an electrically and thermally conductive base substrate to the thinned wafer on the second side; Separating the semiconductor chips from each other into singular semiconductor chips after applying the base substrate to the second side of the thinned wafer; and Separating the base substrate along lines aligned with gaps between adjacent singular semiconductor chips to form individual semiconductor packages, each semiconductor package containing one of the singular semiconductor chips and a singular section of the base substrate attached to that chip. [11] The method of claim 10, further comprising: Filling the gaps between adjacent singular semiconductor chips with an insulating material. [12] Method according to claim 10 or 11, further comprising: Applying a support substrate to the wafer on the first side before the wafer is thinned, with the support substrate supporting the wafer during thinning on the second side. [13] Method according to claim 12, wherein the support substrate comprises a glass material, and wherein the application of the base substrate to the thinned wafer on the second side comprises: Forming a partially sintered bond between the base substrate and the thinned wafer under pressure and at a first temperature below the melting temperature of the glass material; Removal of the support substrate from the thinned wafer after the partially sintered bond between the base substrate and the thinned wafer has formed; and Strengthening the sintered bond between the base substrate and the thinned wafer under pressure and at a second temperature higher than the melting temperature of the glass material, after the support substrate has been removed from the thinned wafer. [14] Method according to any one of claims 10 to 13, further comprising: Mounting the individual semiconductor packages onto a support layer on one side of the singular semiconductor chips, pointing away from the singular sections of the base substrate; and Covering each free side of the singular sections of the base substrate with a protective layer when the individual semiconductor packages are mounted on the support layer. [15] Method according to claim 14, wherein the singular sections of the base substrate comprise copper and the protective layer is plated onto each free side of the singular sections of the base substrate. [16] Semiconductor assembly comprising: a substrate with multiple conductive regions on a mounting surface of the substrate; and a semiconductor package on the mounting surface of the substrate, wherein the semiconductor package comprises: a single semiconductor chip, comprising: a semiconductor body with opposing first and second faces; a first electrode on the first surface, which is electrically connected to a conductive region of the substrate; and a second electrode on the second surface, wherein the individual semiconductor chip has a defined thickness, measured between the first and second surfaces; and an electrically and thermally conductive base which is attached to the second electrode is attached to the second surface of the single semiconductor chip, with the base being electrically connected to a different conductive region of the substrate than the first electrode is connected wherein the base is connected to a conductive region of the substrate, which is not covered by the single semiconductor chip, by a metal connector extending from the conductive region along a side of the base facing away from the substrate. [17] Semiconductor assembly according to claim 16, wherein the individual semiconductor chip further comprises insulated sides between the first and second surfaces, and wherein the base has the same length and width as the individual semiconductor chip, and wherein the insulated sides of the semiconductor body electrically insulate the semiconductor body and the first electrode from the metal connector. [18] Semiconductor assembly according to claim 16 or 17, wherein a transistor is formed in the semiconductor body, wherein the individual semiconductor chip further comprises a third electrode on the first surface of the semiconductor body which is electrically connected to a different conductive region of the substrate than the first electrode and the base, and the defined thickness of the individual semiconductor chip is 20 micrometers or less. [19] Semiconductor assembly according to claim 16 or 17, wherein a diode is formed in the semiconductor body and the defined thickness of the individual semiconductor chip is 10 micrometers or less. [20] Semiconductor package, comprising: a single semiconductor chip, comprising: a semiconductor body with opposing first and second faces; a first electrode on the first surface; and a second electrode on the second surface, wherein the individual semiconductor chip has a defined thickness, measured between the first and second surfaces; and An electrically and thermally conductive base attached to the second electrode on the second face of the individual semiconductor chip, wherein the base has a first side attached to the second electrode on the second face of the individual semiconductor chip and has five additional sides that are not covered by the individual semiconductor chip, wherein each side of the base not attached to the individual semiconductor chip is covered by a protective layer, wherein the base comprises copper and the protective layer is plated onto each side of the base that is not attached to the individual semiconductor chip.

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