Semiconductor devices with gate structures and methods for manufacturing them

Abstract

Semiconductor device with: an active layer (110) with germanium on a substrate (100), wherein the active layer (110) contains: a first area (112) with a first germanium concentration; and a second region (114) on both sides of the first region (112), wherein the second region (114) has a top surface that is higher than a top surface of the first region (112), wherein the second region (114) has a first section adjacent to the first region (112) and a second section higher than the top surface of the first region (112), and the second region (114) has a second germanium concentration lower than the first germanium concentration; a gate structure (272; 274; 276) on the first area (112) of the active layer (110); a spacer (192; 194; 196) that overlaps the second region (114) of the active layer (110) at least partially in a vertical direction that is substantially perpendicular to an upper surface of the substrate (100), the spacer (192; 194; 196) being in contact with a side wall of the gate structure (272; 274; 276); and a source / drain layer (210) adjacent to the second area (114) of the active layer (110).

Description

AREA

[0001] The inventive concept relates generally to semiconductor devices and in particular to transistors with a silicon-germanium channel and to methods for manufacturing them. BACKGROUND

[0002] A finite field-effect transistor (FinFET) can be used to reduce short-channel effects. Silicon-germanium channel regions have been used to increase charge carrier mobility. However, a silicon-germanium channel has a band gap that is smaller than that of a silicon channel, and thus a leakage current in the off-state can increase due to band-to-band tunneling (BTBT). Improved methods to reduce leakage current in the off-state while maintaining high charge carrier mobility are desirable.

[0003] US 2005 / 0133834A1 discloses a semiconductor device and a method for its fabrication. A semiconductor device comprises: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a pair of source and drain electrodes, each formed in regions of the semiconductor substrate located on opposite sides of the gate electrode in a top view; and a germanium-containing channel layer located beneath the gate electrode to enclose a gate insulator between it and the pair of source and drain electrodes, wherein a silicide layer forming at least a portion of the source and drain electrodes has a lower germanium concentration than the channel layer.

[0004] US 2005 / 0250301A1 discloses a self-aligning metal for producing contacts to Ge-containing substrates and a structure formed thereby. A method for forming germano-silicide contacts on a Ge-containing layer, which is more resistant to etching than conventional silicide contacts formed from a pure metal, is provided. The method of the present invention first comprises providing a structure comprising a plurality of gate regions located on a Ge-containing substrate with source / drain regions therein. Following this step of the present invention, a Si-containing metal layer is formed on the Ge-containing substrate. In the exposed regions, the Ge-containing substrate is in contact with the Si-containing metal layer.Subsequently, an annealing process is carried out to form a germano-silicide compound in the areas where the silicon-containing metal layer and the germanium-containing substrate are in contact; thereafter, any unreacted silicon-containing metal layer is removed from the structure by a selective etching process. In some embodiments, the removal step may be followed by an additional annealing step. The method of the present invention provides a structure with a germano-silicide contact layer on a germanium-containing substrate, wherein the germano-silicide contact layer contains more silicon than the underlying germanium-containing substrate.

[0005] US 2008 / 0157119A1 discloses a stacked SiGe for improving short channels. A semiconductor structure includes a first compound layer comprising an element and a first impurity with a first impurity concentration; and a second compound layer comprising the element and a second impurity of the same conductivity type as the first impurity, the second impurity having a second impurity concentration, and the second compound layer being located on top of the first compound layer.The semiconductor structure further comprises a third compound layer, which includes the element and a third impurity of the same conductivity type as the first impurity, wherein the third impurity has a third impurity concentration, and wherein the third compound layer is located on top of the second compound layer, and wherein the second impurity concentration is significantly lower than the first and third impurity concentrations.

[0006] US 2012 / 0181625 A1 discloses a method for fabricating strained source / drain structures. An integrated circuit device and a method for fabricating the integrated circuit device are disclosed. The disclosed method provides a processing step for forming enhanced source / drain features in the semiconductor device. Semiconductor devices with the enhanced source / drain features can prevent or reduce defects and achieve a high strain effect resulting from epi-layers. The source / drain features comprise a second section surrounding a first section and a third section between the second section and the semiconductor substrate, the second section having a different composition than the first and third sections. SUMMARY

[0007] The invention is defined by the features of the attached claims.

[0008] Some embodiments of the present inventive concept provide a semiconductor device with an active layer, a gate structure, a spacer, and a source / drain layer. The active layer is formed on a substrate and contains germanium. The active layer comprises a first region with a first germanium concentration and a second region on both sides of the first region. The second region has a top surface area that increases from a first section of the second region adjacent to the first region to a second section of the second region furthest from the first region, and has a second germanium concentration that is lower than the first germanium concentration. The gate structure is formed on the first region of the active layer.The spacer overlaps the second region of the active layer at least partially in the vertical direction, which is essentially perpendicular to an upper surface of the substrate, and touches a side wall of the gate structure. The source / drain layer is adjacent to the second region of the active layer.

[0009] In further embodiments, the first germanium concentration can be essentially constant in the first region, and the second germanium concentration can decrease from the first section to the second section of the second region.

[0010] In further embodiments, the source / drain layer can have a third germanium concentration, and the maximum value of the third germanium concentration can be greater than that of the first germanium concentration.

[0011] In some embodiments, the base surface of the spacer can increase in height from a first section of the spacer adjacent to the first area to a second section of the spacer located away from the first area.

[0012] In further embodiments, the spacer can have a recess on an inner side wall thereof in a horizontal direction, which touches the side wall of the gate structure.

[0013] In further embodiments, the spacer can have a vertical inner side wall which touches the side wall of the gate structure.

[0014] In some embodiments, the gate structure may have a gate electrode with a metal as well as a high-k dielectric layer pattern surrounding a bottom and a side wall of the gate electrode.

[0015] In further embodiments, the gate structure can further comprise a silicon oxide layer pattern between the active layer and the high-k dielectric layer pattern.

[0016] In further embodiments, the silicon oxide layer pattern can be formed only on the first area of ​​the active layer.

[0017] In some embodiments, the silicon oxide layer pattern can be formed not only on the first area of ​​the active layer, but also on at least one section of the second area of ​​the active layer.

[0018] In other embodiments, the side wall of the gate structure can have a projection in a horizontal direction.

[0019] In further embodiments, the side wall of the gate structure can have a vertical side wall.

[0020] In some embodiments, the active layer and the source / drain layer may contain silicon germanium.

[0021] In further embodiments, the source / drain layer can be heavily doped with p-foreign atoms, and the second region of the active layer can be lightly doped with p-foreign atoms.

[0022] In further embodiments, the upper surface of the first region of the active layer can be flat in one direction and may not be higher than the second region of the active layer.

[0023] In some embodiments, the semiconductor device includes an insulating layer pattern on the substrate, which may surround a side wall of the active layer.

[0024] In other embodiments, the upper surface of the insulating layer can be lower than that of the active layer.

[0025] Further embodiments of the present inventive concept provide a semiconductor device with an active layer, a gate structure, a spacer, and a source / drain layer. The active layer is formed on a substrate and contains germanium. The active layer comprises a first region with a first germanium concentration and a second region on both sides of the first region. The second region has a second germanium concentration that decreases from the first germanium concentration at a first section of the second region adjacent to the first region to a second section of the second region located away from the first region. The gate structure is formed on the first region of the active layer.The spacer overlaps the second region of the active layer at least partially in the vertical direction, perpendicular to an upper surface of the substrate, and contacts a side wall of the gate structure. The source / drain layer is adjacent to the second region of the active layer.

[0026] In some embodiments, the upper surface of the second area of ​​the active layer can increase in height from the first section towards the second section.

[0027] In further embodiments, the base surface of the spacer can increase in height from a first section of the spacer adjacent to the first area to a second section of the spacer away from the first area.

[0028] In further embodiments, the gate structure can include a silicon oxide layer pattern on the active layer, a high-k dielectric layer pattern on the silicon oxide layer pattern and an inner sidewall of the spacer, as well as a metal gate electrode. The base and sidewall of the gate electrode can be surrounded by the high-k dielectric layer pattern.

[0029] In some embodiments, the source / drain layer can be heavily doped with p-foreign atoms, and the second region of the active layer can be lightly doped with p-foreign atoms.

[0030] Further embodiments of the present inventive concept provide methods for fabricating semiconductor devices by forming a silicon-germanium active layer on a substrate. The active layer is partially oxidized to form a silicon oxide layer on the active layer, such that a first region of the active layer beneath the silicon oxide layer has a first germanium concentration, and a second region of the active layer adjacent to the first region beneath the silicon oxide layer has a second germanium concentration lower than the first germanium concentration. The silicon oxide layer is removed to expose the first and second regions of the active layer. A source / drain layer is formed on the active layer adjacent to the second region of the active layer. A gate structure is formed on the exposed first region of the active layer.

[0031] In further embodiments, a mask can be formed during partial oxidation to create the silicon oxide layer on the active layer, partially covering the active layer, and the active layer can be oxidized.

[0032] In some embodiments, a section of the active layer not covered by the mask and a section of the active layer covered by the active layer can be oxidized by oxidizing the active layer.

[0033] In further embodiments, the second area of ​​the active layer can be vertically overlapped by the mask, and the first area of ​​the active layer cannot be vertically overlapped by the mask.

[0034] In further embodiments, after the silicon oxide layer has been removed to expose the first and second regions of the active layer, a dummy gate insulating layer can be formed on the exposed first and second regions of the active layer and the mask. A dummy gate electrode layer can be formed on the dummy gate insulating layer to adequately cover the mask. The dummy gate electrode layer and the dummy gate insulating layer can be planarized until a top surface of the mask is exposed to form a dummy gate electrode or a dummy gate insulating layer pattern. The mask can then be removed to expose the active layer.

[0035] In some embodiments, when the mask is removed to expose the active layer, a section of the dummy gate insulating layer pattern on a side wall of the dummy gate electrode may be at least partially removed, and a remaining section of the dummy gate insulating layer pattern on the active layer and the dummy gate electrode may form a dummy gate structure.

[0036] In further embodiments, a spacer covering one side wall of the dummy gate structure can be formed.

[0037] In further embodiments, when the mask is removed to expose the active layer, the second area of ​​the active layer can be exposed and the second area of ​​the exposed layer can be doped with foreign atoms before the spacer, which covers the side wall of the dummy gate structure, is formed.

[0038] In some embodiments, the dummy gate structure can be formed on the first region of the active layer, and the spacer can be formed, wherein the spacer overlaps the second region of the active layer at least partially in the vertical direction, which is substantially perpendicular to an upper surface of the substrate, and is formed on a side wall of the gate structure.

[0039] In further embodiments, during the formation of the gate structure on the first region of the exposed active layer, an insulating intermediate layer can be formed on the substrate to cover the dummy gate structure and the spacer. The insulating intermediate layer can be planarized until a top surface of the dummy gate structure is exposed to form an insulating intermediate layer pattern. The exposed dummy gate structure can be removed to form an opening that exposes the first region of the active layer. The gate structure can then be formed to fill the opening.

[0040] In further embodiments, a high-k dielectric layer can be formed on the base and sidewall of the opening and the insulating interlayer pattern during gate structure formation. A gate electrode layer can be formed on the high-k dielectric layer to adequately fill the opening. The gate electrode layer and the high-k dielectric layer can be planarized until a top surface of the insulating interlayer pattern is exposed to form the gate structure with a gate electrode and a high-k dielectric layer pattern surrounding the base and sidewall of the gate electrode.

[0041] In some embodiments, a silicon oxide layer pattern can be formed on the exposed first region of the active layer before the high-k dielectric layer is formed on the bottom and side wall of the aperture and the insulating interlayer pattern. The high-k dielectric layer can be formed on a top surface of the silicon oxide layer pattern, a side wall of the aperture, and the insulating interlayer pattern.

[0042] In further embodiments, when forming the source / drain layer on the active layer adjacent to the second region of the active layer, an upper section of the active layer that is not covered by the dummy gate structure and the spacer can be removed to form a depression. An epitaxial layer growth process can be carried out to form a silicon-germanium layer that fills the depression.

[0043] In further embodiments, a silicon-germanium layer doped with p-foreign atoms can be formed during the formation of the silicon-germanium layer.

[0044] In some embodiments, an insulating layer pattern, which at least partially covers a side wall of the active layer, can be formed after the active layer has been formed with silicon germanium on the substrate.

[0045] In further embodiments of the present inventive concept, a semiconductor device with the active layer can possess high charge carrier mobility because the active layer is formed such that it contains silicon germanium. In particular, a first region of the active layer, which serves as a channel, can have a high germanium concentration, and thus the charge carrier mobility can be increased. A second region of the active layer, serving as an LDD region, can have a lower germanium concentration than the first germanium concentration, and thus a leakage current in a switched-off state can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Exemplary embodiments are more clearly understood with reference to the following detailed description in conjunction with the accompanying drawings. Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30, Fig. 31, Fig. 32, Fig. 33, Fig. 34, Fig. 35, Fig. 36, Fig. 37, Fig. 38, Fig. 39, Fig. 40, Fig. 41, Fig. 42, Fig. 43, Fig. 44, Fig. 45, Fig. 46, Fig. 47, Fig. 48 to Fig. 49 provide non-limiting exemplary embodiments as described herein. Fig. 1 and Fig. Figure 2 shows cross-sectional views of a semiconductor device according to some embodiments of the present inventive concept. Fig. 3 is a top view showing the semiconductor device. Fig. 1 represents. Fig. Figure 4 is a cross-section representing a semiconductor device according to some embodiments of the present inventive concept. Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30, Fig. 31 to Fig. Figure 32 are top views and cross-sections which represent process steps in the manufacture of semiconductor devices according to some embodiments of the present inventive concept. Fig. 33 to Fig. Figure 34 are top views illustrating process steps in the manufacture of semiconductor devices according to some embodiments of the inventive concept. Fig. Figure 35 is a cross-section representing a semiconductor device according to some embodiments of the present inventive concept. Fig. 36, Fig. 37 to Fig. Figure 38 are cross-sections which represent process steps in the manufacture of semiconductor devices according to some embodiments of the present inventive concept. Fig. Figure 39 is a cross-section representing a semiconductor device according to some embodiments of the present inventive concept. Fig. 40, Fig. 41 to Fig. Figure 42 are cross-sections which represent process steps in the manufacture of semiconductor devices according to some embodiments of the present inventive concept. Fig. Figure 43 is a cross-section representing a semiconductor device according to some embodiments of the present inventive concept. Fig. 44, Fig. 45, Fig. 46, Fig. 47, Fig. 48 to Fig. Figure 49 are cross-sections which represent process steps in the manufacture of a semiconductor device according to some embodiments of the present inventive concept. DESCRIPTION OF EXECUTION FORMS

[0047] Several exemplary embodiments will be described in more detail below with reference to the accompanying drawings, which show some of these exemplary embodiments. However, the present inventive concept can be implemented in various forms and should not be interpreted as being limited to the exemplary embodiments presented below. Rather, these exemplary embodiments are provided so that this description will be comprehensive and complete, fully conveying the scope of the present inventive concept to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions have been exaggerated for clarity.

[0048] It will be understood that when an element or layer is described as "on," "connected to," or "coupled to" another element or layer, it may be directly on, connected to, or coupled to that other element or layer, or there may be intervening elements or layers. In contrast, when an element is described as "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. The same reference signs consistently refer to the same elements. As used here, the term "and / or" includes any and all combinations of one or more of the linked items listed.

[0049] It will be understood that, although the terms first, second, third, fourth, and the like may be used here to describe different elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections are not to be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another. Thus, a first element, component, region, layer, or section discussed below could be called a second element, component, region, layer, or section without departing from the teachings of the present inventive concept.

[0050] Spatially relative terms, such as "below," "under," "lower," "above," "above," and the like, may be used here for the sake of simplicity in describing an element or a feature's relationship to another element (or other elements) or feature (or features), as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. For example, if the device in the figures is inverted, elements described as "below" or "under" other elements or features would then be oriented "above" those other elements or features. Thus, the exemplary term "under" can encompass both an orientation above and below.The device may be oriented differently (rotated 90° or in other orientations) and the spatially relative descriptors used here may be interpreted accordingly.

[0051] The terminology used herein is provided solely for the purpose of describing certain exemplary embodiments and is not intended to limit the present inventive concept. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms "comprises" and / or "comprehensive," when used in these documents, will be understood to indicate the presence of the specified features, integers, steps, process steps, elements, and / or components, but will not exclude the presence or addition of one or more other features, integers, steps, process steps, elements, components, and / or groups thereof.

[0052] Exemplary embodiments are described here with reference to cross-sectional views, which are schematic representations of idealized exemplary embodiments (and intermediate structures). As such, deviations from the shapes of the representations are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be interpreted as limiting the specific shapes of the areas described herein, but rather as encompassing deviations in shape that result, for example, from the manufacturing process. For instance, an implanted area represented as a rectangle will typically exhibit rounded or rounded features and / or gradients of implantation concentration at its corners, rather than a binary change from the implanted to the non-implanted area.Similarly, a buried area formed by implantation can lead to some implantation in the area between the buried area and the surface through which the implantation takes place. Thus, the areas depicted in the figures are schematic by nature, and their shapes are not intended to represent the actual shape of any area or device, nor are they intended to limit the scope of the present inventive concept.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as they are normally understood by a person skilled in the art in the field of technology to which the inventive concept belongs. It is further understood that terms such as those defined in commonly used dictionaries are to be interpreted in a manner consistent with their meaning in the context of the relevant field of technology and will not be interpreted in an idealized or overly formal manner unless expressly defined herein.

[0054] Fig. 1, Fig. 2 to Fig. Figure 3 shows cross-sections and a top view illustrating a semiconductor device according to some embodiments of the inventive concept. In particular, Fig. 1 and Fig. 2 cross-sections and is Fig. 3 A top view showing the semiconductor device. Fig. 1 is a cross-sectional view along a line II' from Fig. 3 and Fig. 2 is a cross-sectional view along a line II-II' from Fig. 3.

[0055] Referring to Fig. 1, Fig. 2 to Fig. 3. The semiconductor device can have an active layer 110 on a substrate 100, a first gate structure 272 on the active layer 110, a first spacer 192 on a side wall of the first gate structure 272, and a source / drain layer 210 on a section of the active layer 110 adjacent to the first spacer 192. Furthermore, the semiconductor device can include a first insulating layer pattern 130, covering a side wall of the active layer 110, on the substrate 100, and an insulating interlayer pattern 220, covering the source / drain layer 210 and surrounding the first gate structure 272 and the first spacer 192, on the first insulating layer pattern 130.

[0056] The substrate 100 can contain a semiconductor material, e.g., silicon, germanium, and the like, or III-V compound semiconductor materials. In some embodiments, the substrate 100 can be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0057] The active layer 110 can contain germanium (Ge). In some embodiments, the active layer 110 can be an epitaxial layer with silicon-germanium.

[0058] The active layer 110 can contain a first region 112 with a first germanium concentration and a second region 114 with a second germanium concentration. The second region 114 can be formed on both sides of the first region 112 in a direction substantially parallel to a top surface of substrate 100 and can touch both sides of the first region 112. The first and second regions 112 and 114 can be formed on upper sections of the active layer 110, and other regions of the active layer 110 can have a germanium concentration lower than those of the first and second regions 112 and 114.

[0059] In some embodiments, the first germanium concentration in the first region 112 can be essentially constant, and the second germanium concentration can decrease from a section of the second region 114 adjacent to the first region 112 to a section of the second region 114 located away from the first region 112. In other words, the second germanium concentration can have a maximum value at a first section of the second region 114 touching the first region 112 and a minimum value at a second section of the second region 114 touching the source / drain layer 210. The second germanium concentration can decrease slowly from the first section to the second section of the second region 114. Thus, the second germanium concentration can generally be lower than the first germanium concentration.

[0060] In some embodiments, the first region 112 of the active layer 110 can have a top surface with a substantially constant height in the first direction, and the second region 114 of the active layer 110 can have a top surface that increases successively in height from the first section of it, which contacts the first region 112, to the second section of it, which contacts the source / drain layer 210. Thus, the top surface of the second region 114 can have a minimum height that is substantially equal to that of the top surface of the first region 112 at the first section of it, which contacts the first region 112, and a maximum height at the second section of it, which contacts the source / drain layer 210. The top surface of the second region 114 can increase successively in height from the first section to the second section of the second region 114.

[0061] The first and second regions 112 and 114 may protrude from other regions of the active layer 110 and a width of each of the first and second regions 112 and 114 in a second direction substantially parallel to the top surface of the substrate 100 and substantially perpendicular to the first direction may decrease from a bottom section to a top section thereof.

[0062] The active layer 110 can be partially doped with foreign atoms. In some embodiments, the second region 114 of the active layer 110 can be lightly doped with p-type foreign atoms, e.g., boron, aluminum, and the like, and the first region 112 of the active layer 110 can be lightly doped with n-type foreign atoms, e.g., phosphorus, arsenic, and the like.

[0063] The first gate structure 272 can contain a first silicon oxide layer pattern 242, a first high-k dielectric layer pattern 252 and a first gate electrode 262, which are stacked sequentially on the active layer 110.

[0064] In some embodiments, the first silicon oxide layer pattern 242 can be formed on the first region 112 of the active layer 110, and thus the first gate structure 272, which contains the first silicon oxide layer pattern 242, can be formed on the first region 112 of the active layer 110. The first high-k dielectric layer pattern 252 can be formed on the first silicon oxide layer pattern 242 and an inner side wall of the first spacer 192. The first gate electrode 262 can fill an interior formed by the first high-k dielectric layer pattern 252, and thus a bottom and a side wall of the first gate electrode 262 can be covered by the first high-k dielectric layer pattern 252.

[0065] In some embodiments, the first gate structure 272 may have a projection extending in the first direction from one of its side walls. In other words, both the first high-k dielectric layer pattern 252 and the first gate electrode 262 may have an outwardly projecting projection in the first direction on a section of one of its side walls at a height approximately equal to the maximum height of the upper surface of the second region 114 of the active layer 110.

[0066] The first high-k dielectric layer pattern 252 can contain a metal oxide with a high dielectric constant, e.g. hafnium oxide, tantalum oxide, zirconium oxide and the like, and the first gate electrode 262 can contain a metal, e.g. aluminium, copper, tantalum and the like, and / or a metal nitride.

[0067] In some embodiments, the first spacer 192 can be formed on the second area 114 of the active layer 110 and can thus be formed on both sides of the first gate structure 272 in the first direction and can touch both sides of the first gate structure 272.

[0068] The base surface of the first spacer 192 can gradually increase in height from a section of the first spacer 192 adjacent to the first region 112 to a section of the first spacer 192 away from the first region 112, corresponding to the upper surface of the second region 114 of the active layer 110. However, the first spacer 192 can also be partially formed on a section of the first region 112 adjacent to the second region 114, and thus a base surface of the section of the first spacer 192 on the section of the first region 112 adjacent to the second region 114 can have a substantially constant height, corresponding to the upper surface of the first region 112 of the active layer 110.

[0069] In some embodiments, the first spacer 192 may have a recess in the first direction on an inner side wall that contacts the side wall of the first gate structure 272. In other words, the first spacer 192 may have a recess in the first direction on a section of its inner side wall at a height around the maximum height of the upper surface of the second region 114 of the active layer 110, which may correspond to the projection of the side wall of the first gate structure 272.

[0070] The first spacer 192 can contain a nitride, e.g. silicon nitride.

[0071] The source / drain layer 210 can be formed on the active layer 110 and touch the second region 114 as well as the first spacer 192. Thus, the source / drain layer 210 can be formed on both sides of the first gate structure 272 and can touch the second region 214 and the first spacer 192.

[0072] The source / drain layer 210 can be a silicon-germanium epitaxy layer. The source / drain layer 210 can have a third germanium concentration.

[0073] In some embodiments, the third germanium concentration can increase from a section of the source / drain layer 210 adjacent to the second region 114 towards a section of the source / drain layer 210 located away from the second region 114. In other words, the third germanium concentration can have a minimum value that is essentially equal to that of the second germanium concentration at a third section of the layer that touches the second region 114 and can gradually increase from that third section towards an outer sidewall of the source / drain layer 210 in the first direction. A maximum value of the third germanium concentration can be higher than that of the first germanium concentration.

[0074] In some embodiments, the source / drain layer 210 can be highly doped with p-foreign atoms, e.g. boron, aluminum and the like.

[0075] In some embodiments, the upper surface of the first insulating layer pattern 130 can be deeper than that of the active layer 110. In other words, the upper surface of the first insulating layer pattern 130 can be deeper than that of the first and second regions 112 and 114 of the active layer 110. Thus, the active layer 110 can have a fin-like shape projecting from the upper surface of the first insulating layer pattern 130, which can be referred to as an active fin. The first insulating layer pattern 130 can contain an oxide, e.g., silicon oxide.

[0076] The insulating layer intermediate pattern 220 can contain an oxide, e.g. silicon oxide.

[0077] The semiconductor device can be a transistor with the first gate structure 272 on the active layer 110 and with the source / drain layer 210. The first region 112 of the active layer 110 under the first gate structure 272 can serve as a channel, and the second region 114 of the active layer 110 can be formed between the channel and the source / drain layer 210 to serve as a lightly doped drain (LDD) region.

[0078] Since the active layer 110 is a silicon-germanium layer, the channel can have a higher charge carrier mobility than a silicon channel and, in particular, the channel can have a higher germanium concentration, so that the charge carrier mobility can be increased.

[0079] Germanium has a band gap that is smaller than that of silicon, and therefore a leakage current in a switched-off state can be higher due to the band-to-band tunnel (BTBT). However, according to some embodiments, the second region 114 of the active layer 110, which serves as the LDD region, can have a germanium concentration that is lower than that of the first region 112 of the active layer 110, which serves as the channel, and thus the BTBT can be reduced, and the leakage current in a switched-off state can be reduced.

[0080] Accordingly, the transistor can possess both high charge carrier mobility and low leakage current in a switched-off state.

[0081] Although Fig. 1, Fig. 2 to Fig. Figure 3 shows that the transistor has a single active layer 110 on the substrate 100 and a single first gate structure 272 on the active layer 110. It should be understood that embodiments of the present inventive concept are not limited to this. For example, a plurality of active layers can be formed on the substrate 100 in the second direction, and a plurality of first gate structures 272 can be formed on each active layer 110 in the first direction, without departing from the scope of the present inventive concept.

[0082] Referring to Fig. 4. Each of the plurality of first gate structures 272 can extend in the second direction. Thus, each first gate structure 272 can cover the plurality of active layers 110 that are arranged in the second direction.

[0083] It will be understood that although a positive-channel metal-oxide-semiconductor (PMOS) transistor with the source / drain layer 210 doped with p-type foreign atoms has been discussed here, embodiments of the present inventive concept are not limited to this configuration. For example, a negative-channel metal-oxide-semiconductor (NMOS) transistor may also fall within the scope of the present inventive concept. In other words, even if the source / drain layer 210 is doped with n-type foreign atoms, the silicon germanium channel may have a germanium concentration higher than that of the LDD region, thus enabling high charge carrier mobility and low leakage current.

[0084] Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30, Fig. 31 to Fig. Figure 32 are top views and cross-sections illustrating process steps in the manufacture of semiconductor devices according to some embodiments of the present inventive concept. In particular, they are Fig. 5-6, 8-12, 14, 16-18, 20-21, 23, 25, 27, 29 and 31 cross-sections and are Fig. 7, Fig. 13, Fig. 15, Fig. 19, Fig. 22, Fig. 24, Fig. 26, Fig. 28, Fig. 30 and Fig. 32 top views. The cross-sections are taken along a first direction of the corresponding top views.

[0085] Referring first to Fig. 5. An active layer 110 and a first mask 120 can be formed successively on a substrate 100, and the active layer 110 can be etched using the first mask 120 as an etching mask to partially expose a top surface of the substrate 100.

[0086] The substrate 100 can contain a semiconductor material, e.g., silicon, germanium, and the like, or III-V compound semiconductor materials. In some embodiments, the substrate 100 can be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0087] The active layer 110 can contain germanium (Ge). In some embodiments, the active layer 110 can be a silicon-germanium-containing epitaxial layer.

[0088] The active layer 110 can be configured to contain germanium (Ge). In some embodiments, the active layer 110 can be formed by an epitaxial growth process using a top surface of the substrate 100 with silicon as a seed. In some embodiments, the epitaxial growth process can be carried out using a silicon source gas, e.g., dichlorosilane (SiH₂Cl₂) gas, and a germanium source gas, e.g., monogerman (GeH₄) gas, thus forming a single-crystal silicon-germanium epitaxial layer.

[0089] In some embodiments, the active layer 110 can be formed such that it extends in the first direction essentially parallel to the upper surface of the substrate 100, and a plurality of active layers 100 can be formed in a second direction essentially parallel to the upper surface of the substrate 100 and essentially perpendicular to the first direction. For the sake of simplicity, the following is shown: Fig. 5 only one active layer 110.

[0090] Before the formation of the first mask 120, foreign atoms can be implanted into the active layer 110 to form a well region. In some embodiments, the well region can be formed during the formation of a PMOS transistor by implanting n-type foreign atoms, e.g., phosphorus, arsenic, and the like. When an NMOS transistor is formed, the well region can be formed by implanting p-type foreign atoms, e.g., boron, aluminum, and the like.

[0091] Referring to Fig. 6 and Fig. 7. An insulating layer can be formed on the substrate 100 to cover the active layer 110 and the first mask 120, and the insulating layer can be planarized until an upper surface of the first mask 120 is exposed. In some embodiments, the planarization process can be carried out by a chemical-mechanical polishing (CMP) process and / or a back-etching process. After removal of the first mask 120, the insulating layer can be etched until an upper sidewall of the active layer 110 is exposed to form a first insulating layer pattern 130. The insulating layer pattern can be formed such that it contains an oxide, e.g., silicon oxide.

[0092] Since the first insulating layer pattern 130 can expose the upper side wall of the active layer 110, the active layer 110 can have a fin-like shape that protrudes from an upper surface of the first insulating layer pattern 130 and can be referred to as an active fin.

[0093] An active layer containing germanium can also be formed by the following, with reference to Fig. 8, Fig. 9, Fig. 10 to Fig. 11 procedures presented. Referring first to Fig. 8. A second mask 510 can be formed on a substrate 500, and an upper section of the substrate 500 can be etched using the second mask 510 as an etching mask to form a first trench 520. The substrate 500 can contain a semiconductor material, e.g., silicon, germanium, and the like.

[0094] Referring to Fig. 9. An epitaxial growth process can be carried out using a section of the substrate 500 exposed by the first trench 520 to form an active layer 530 that fills the first trench 520. The active layer 530 can be a silicon-germanium epitaxial layer.

[0095] Referring to Fig. 10. A third mask 510 can be formed on the active layer 530 after the removal of the second mask 510 to expose a top surface of the substrate 500, and the exposed section of the substrate 500 can be etched using the third mask 540 as an etching mask until a side wall of the active layer 530 can be exposed. Thus, the active layer 530 and the third mask 540 can be formed sequentially on the substrate 500.

[0096] Referring to Fig. 11. A procedure that is substantially the same or similar to that which was used with reference to Fig. The process shown in Figure 6 is carried out to form a first insulating layer pattern 550, which surrounds a lower side wall of the active layer 530 on the substrate 500.

[0097] Referring to Fig. 12 and Fig. 13. A fourth mask 140 can be formed to partially cover the active layer 110. In some embodiments, the fourth mask 140 can have a first opening 145 which exposes a central upper surface of the active layer 110 and can cover the upper surfaces and sidewalls located at the edges in the first direction of the active layer 110. In other words, two fourth masks 140 can be formed, one at each edge of the active layer 110 in the first direction. The fourth mask 140 can be formed such that it contains a nitride, e.g., silicon nitride.

[0098] Referring to Fig. 14 and Fig. 15. An oxidation process can be carried out on the active layer 110 with the fourth mask 140 on it to form a silicon oxide layer 150.

[0099] Thus, a section of the active layer 110 not covered by the fourth mask 140, e.g., an upper section of the active layer 110 exposed through the first opening 145, can be oxidized. Through the oxidation process, silicon of the active layer 110, including silicon-germanium, can be bonded with oxygen to form the silicon oxide layer 150, and the germanium concentration of the remaining active layer 110 can be increased. A section of the active layer 110 adjacent to the first opening, which cannot be directly exposed through the first opening 145, can also be oxidized.

[0100] Since the silicon oxide layer 150 can be formed by the oxidation process, a first region 112 with a first germanium concentration and a second region 114 with a second germanium concentration, which is lower than the first germanium concentration, can be formed on a section of the active layer 110 beneath the silicon oxide layer 150. In some embodiments, the first region 112 can be a section of the active layer 110 that vertically overlaps the first opening 145, and the second region 114 can be a section of the active layer 110 on both sides of the first region 112 in the first direction, touching both sides of the first region 112.

[0101] In some embodiments, the first germanium concentration can be essentially constant in the first region, and the second germanium concentration can have a maximum value at a first section of the second region 114, which touches the first region 112, and can gradually decrease from the first section to a second section of the second region 114 furthest from the first region 112 in the first direction. Thus, the second germanium concentration can generally be lower than the first germanium concentration.

[0102] In some embodiments, the first region 112 of the active layer 110 can have a top surface with a substantially constant height in the first direction, and the second region 114 of the active layer 110 can have a top surface that gradually increases in height from the first section towards the second section. Thus, a bottom section of the fourth mask 140 adjacent to the first opening 145 does not touch the second region 114 of the active layer 110, but instead touches the silicon oxide layer 150.

[0103] The upper surface of the second area 114 of the active layer 110 can be found in Fig. 14 shown form and can also possess the form shown in the Fig. 16 and Fig. 17 forms shown. This means that the height of the upper surface of the second region 114 of the active layer 110 is linear (see Fig. 16) or non-linear (see Fig. 14 and Fig. 17) can increase in the first direction.

[0104] Referring to Fig. 18 and Fig. 19 The silicon oxide layer 150 can be removed to form a second opening 155, which exposes the upper surfaces of the first and second regions 112 and 114 of the active layer 110.

[0105] A section of the second opening 155, where the upper surface of the second area 114 of the active layer 110 and the fourth mask 140 touch each other, has a width in the first direction that is greater than that of other sections of the second opening 155.

[0106] The first and second areas 112 and 114, which are defined by the reference to Fig. 14, Fig. 15, Fig. 16 to Fig. The oxidation processes described in Figure 17 can protrude upwards compared to other areas of the active layer 110, and both the first and second areas 112 and 114 can have a width in the second direction that gradually increases from a bottom section to an upper section thereof (see Figure 112). Fig. 2) Thus, a section of the active layer 110, which actually acts as a channel, can have a width in the second direction that is smaller than a lower section of the active layer 110, which is in Fig. 19 may be indicated by a dashed line.

[0107] Referring to Fig. 20 a first dummy gate insulating layer 160 can be formed on the first and second areas 112 and 114 of the active layer 110, the fourth mask 140 and the first insulating layer pattern 130 and a dummy gate electrode layer 170 can be formed on the first dummy gate insulating layer 160 to adequately fill the second opening 155.

[0108] In some embodiments, the first dummy gate insulating layer 160 can be formed with correct angles and can thus have a curved section in the first direction at a position where the upper surface of the second region 114 of the active layer 110 and the fourth mask 140 touch each other, and the dummy gate electrode layer 170 can have a projection in the first direction at a position adjacent to the curved section of the first dummy gate insulating layer 160.

[0109] The first dummy gate insulating layer 160 can be formed such that it has an oxide, e.g. silicon oxide, and the dummy gate electrode layer 170 can be formed such that it contains, e.g., polysilicon.

[0110] Referring to the Fig. 21 and Fig. 22 The dummy gate electrode layer 170 and the first dummy gate insulating layer 160 can be planarized until an upper surface of the fourth mask 140 is exposed to form a dummy gate electrode 175 or a preliminary dummy gate insulating layer pattern 162. In some embodiments, the planarization process can be carried out by a CMP process and / or a back-etching process.

[0111] The dummy gate electrode 175 can have a projection in the first direction at a position where the upper surface of the second area 114 and the fourth mask 140 touch each other.

[0112] Referring to the Fig. 23 and Fig. 24 A fifth mask 180 can be formed, which covers the fourth masks 140, a section of the dummy gate electrode 175 between the fourth masks 140, and a section of the preliminary dummy gate insulating layer pattern 162 on side walls of the fourth masks 140, and the dummy gate electrode 175 can be etched using the fifth mask 180 as an etching mask.

[0113] Thus, all sections of the dummy gate electrode 175, with the exception of the section of the dummy gate electrode 175 between the fourth masks 140, can be removed, and a section of the preliminary dummy gate insulating layer pattern 162 below the exposed section of the dummy gate electrode 175 can be exposed.

[0114] Referring to the Fig. 25 and Fig. 26 can be removed after removing the fifth mask 180 to expose the fourth masks 140, the section of the dummy gate electrode 175 between the fourth masks 140 and the section of the preliminary dummy gate insulating layer pattern 162 on the side walls of the fourth masks 140, the exposed fourth masks 140 and the section of the preliminary dummy gate insulating layer pattern 162 on the side walls of the fourth masks 140.

[0115] Thus, the preliminary dummy gate insulating layer pattern 162 can be converted into a first dummy gate insulating layer pattern 164 under the dummy gate electrode 175. In some embodiments, the portion of the preliminary dummy gate insulating layer pattern 162 on the side walls of the fourth masks can be removed by a wet etching process.

[0116] The first dummy gate insulating layer pattern 164 can be formed on the first area 112 of the active layer 110 and the first dummy gate insulating layer pattern 164 and the dummy gate electrode 175, which are stacked sequentially, can form a first dummy gate structure.

[0117] Foreign atoms can be weakly implanted into an upper portion of the active layer 110 that is not covered by the first dummy-gate structure to form an LDD region. In some embodiments, after forming a sixth mask (not shown) covering the first dummy-gate structure, an ion implantation procedure can be performed on the active layer 110, with the sixth mask acting as an ion implantation mask to form the LDD region on the upper portion of the active layer 110 that is not covered by the sixth mask. Alternatively, an ion implantation procedure can be performed without using an ion implantation mask, and in these embodiments, foreign atoms can be implanted not only into the active layer 110 but also into the dummy-gate electrode 175.

[0118] The LDD area can be formed not in the first area 112 of the active layer 110 and can be formed in the second area 114 of the active layer 110 as well as a section of the active layer 110 adjacent to the second area 114 in the first direction.

[0119] When a PMOS transistor is formed, the LDD region can be formed by implanting p-type foreign atoms, and when an NMOS transistor is formed, the LDD region can be formed by implanting n-type foreign atoms. In some embodiments, the LDD region may not be formed.

[0120] Referring to the Fig. 27 and Fig. 28 A first spacer 192 can be formed on a side wall of the first dummy gate structure. In some embodiments, the first spacer 192 can be formed by forming a spacer layer on the first dummy gate structure, the active layer 110, and the first insulating layer pattern 130, and by anisotropic etching of the spacer layer. Thus, the first spacer layer 192 can be formed on both sides of the first dummy gate structure, such that it contacts both sides of the first dummy gate structure. The spacer layer can be formed such that it contains a nitride, e.g., silicon nitride.

[0121] In some embodiments, the first spacer 192 can be formed on the second region 114 of the active layer 110 and a first section of the first region 112 of the active layer 110. Since the dummy gate electrode 175 has the projection, the first spacer 192 can have a depression in the first direction on an inner side wall. Since the upper surface of the second region of the active layer 110 becomes higher in the first direction from the first section to a second section, a bottom surface of the first spacer 192 can become higher in the first direction from a section adjacent to the first region 112 of the active layer 110 to a section away from the first region 112 of the active layer 110.

[0122] Referring to the Fig. 29 and Fig. 30 Sections of the active layer 110 adjacent to the first spacers 192 on both sides of the first dummy gate structure can be partially etched in the first direction to form a second trench 200 and a selective epitaxial growth (SEG) process can be carried out using the active layer 110 exposed by the second trench 200 to form a source / drain layer 210 to fill the second trench 200.

[0123] In some embodiments, the second trench 200 can be formed by creating a seventh mask covering the first dummy gate structure and etching the active layer 110 using the seventh mask and the first spacer 192 as an etching mask. Alternatively, the sixth mask used in creating the LDD region can remain in place, and the active layer 110 can be etched using the sixth mask and the first spacer 192 as an etching mask to create the second trench 200.

[0124] Since the second trench 200 is formed on the active layer 110, the LDD area can only remain in the second area 114 of the active layer 110.

[0125] In some embodiments, the SEG process can be used to form a PMOS transistor, employing a silicon source gas, e.g., dichlorosilane (SiH₂Cl₂) gas, and a germanium source gas, e.g., monogerman (GeH₄) gas, thus forming a single-crystal silicon-germanium epitaxy layer. In these embodiments, a p-type foreign atom gas, e.g., diborane (B₂H₆) gas, can also be used to form a single-crystal silicon-germanium layer that is highly doped with p-type foreign atoms. The single-crystal silicon-germanium layer can possess a third germanium concentration, and in some embodiments, the maximum value of the third germanium concentration can be higher than that of the first germanium concentration of the first region 112 of the active layer 110.

[0126] In some embodiments, a SEG process can be used to form an NMOS transistor using a silicon source gas, e.g., disilane (Si₂H₆) gas, to form a single-crystal silicon layer. In these embodiments, an n-foreign atom source gas, e.g., phosphine (PH₃) gas, can also be used to form a single-crystal silicon layer that is highly doped with n foreign atoms. Alternatively, the SEG process can be carried out using a silicon source gas, e.g., disilane (Si₂H₆) gas, together with a carbon source gas, e.g., monomethylsilane (SiH₃CH₃) gas, to form a single-crystal silicon carbide layer. In these embodiments, an n-foreign atom source gas, e.g. phosphine (PH3) gas, can also be used to form a single-crystal silicon carbide layer that is highly doped with n foreign atoms.

[0127] The source / drain layer 210 formed by the SEG process can grow in both a vertical and a horizontal direction, and an upper section of the source / drain layer 210 can have a cross-section along the second direction with a pentagonal or hexagonal shape.

[0128] In some embodiments, the source / drain layer 210 can fill the second trench 200 and cover a lower side wall of the first spacer 192.

[0129] Referring to the Fig. 31 and Fig. 32 An insulating intermediate layer with a top surface area higher than that of the first dummy gate structure can be formed on the first dummy gate structure, the first spacer 192, the source / drain layer 210, and the first insulating layer pattern 130, and can be planarized until the top surface of the first dummy gate structure is exposed to form an insulating intermediate layer pattern 200. For example, the insulating intermediate layer can be formed such that it contains an oxide, e.g., silicon oxide.

[0130] The exposed dummy gate electrode structure can be removed to form a third opening 230, which exposes the upper surface of the first region 112 of the active layer 110. Thus, the inner side wall of the first spacer 192, which contacts the first dummy gate structure, can be exposed.

[0131] Referring again to the Fig. 1, Fig. 2 to Fig. 3 A first gate structure 272, which fills the third opening 230, can be formed.

[0132] In particular, after performing a thermal oxidation process on the upper surface of the first region 112 of the active layer 110, which is exposed through the third opening 230, to form a first silicon oxide layer pattern 242, a high-k dielectric layer can be formed on an upper surface of the first silicon oxide layer pattern 242, the inner side wall of the first spacer 192 and an upper surface of the insulating interlayer pattern 220, and a gate electrode layer can be formed on the high-k dielectric layer to adequately fill the third opening 230.

[0133] The high-k dielectric layer can be formed by depositing a metal oxide with a high dielectric constant, such as hafnium oxide, tantalum oxide, zirconium oxide, and the like, using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or the like. The gate electrode layer can be formed by an ALD process, a physical vapor deposition (PVD) process, or the like, containing a low-resistance metal and / or a metal nitride, such as aluminum, copper, tantalum, and the like. In some embodiments, a further heat treatment process, such as rapid thermal annealing (RTA), spike rapid thermal annealing (Spike-RTA), flash rapid thermal annealing (Flash-RTA), or laser annealing, can be performed. Alternatively, the first gate electrode layer can be formed in such a way that it contains doped polysilicon.

[0134] The gate electrode layer and the high-k dielectric layer can be planarized until an upper surface of the insulating interlayer pattern 220 can be exposed to form a first high-k dielectric layer pattern 252 on the upper surface of the silicon oxide layer pattern 242 and the inner side wall of the first spacer 192, wherein a first gate electrode 262 fills the remaining portion of the third opening 230 on the first high-k dielectric layer pattern 252. In some embodiments, the planarization process can be carried out by a CMP process and / or a back-etching process.

[0135] The first silicon oxide layer pattern 242, the first high-k dielectric layer pattern and the first gate electrode 262, stacked sequentially, can form a first gate structure 272 and the first gate structure 272 and the source / drain layer 210 can form a PMOS transistor or an NMOS transistor.

[0136] The first silicon oxide layer pattern 242 can be formed only on the first region 112 of the active layer 110. The first silicon oxide layer pattern 242 can increase the adhesive force between the active layer 110 and the first high-k dielectric layer pattern 252, and in some embodiments the first silicon oxide layer pattern 242 cannot be formed.

[0137] The semiconductor device can be formed by the methods described above. During the fabrication of the semiconductor device, an oxidation process can be carried out on the active layer 110 between the fourth masks 140 to form the first region 112 with a relatively high germanium concentration and the second region 114 with a relatively low germanium concentration in the upper sections of the active layer 110. This increases the charge carrier mobility of the first region 112 of the active layer 110, which acts as a channel, and reduces the charge carrier mobility (BTBT) through the second region 114 of the active layer 110, which acts as an LDD region. Thus, the semiconductor device can exhibit high operating speed and low leakage current.

[0138] As with reference to Fig. As shown in section 4, the semiconductor device with a first gate structure extending in the second direction can be fabricated as follows. First, methods that are essentially the same or similar to those described with reference to the Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21 to Fig. 22 were discussed, will be carried out. Referring now to Fig. 33 an eighth mask 185 can be formed, which covers a first section of the first dummy gate electrode 175 between the fourth masks 140, a second section of the dummy gate electrode 175 adjacent to the first section therein in the second direction, and a section of the preliminary dummy gate insulating layer pattern 162 on side walls of the fourth masks 140, and the dummy gate electrode 175 can be etched using the eighth mask 185 as an etching mask.

[0139] Thus, all sections of the dummy gate electrode 175, except for the first and second sections thereof, can be removed, and a section of the preliminary dummy gate insulating layer pattern 162 beneath the removed sections of the dummy gate electrode 175 can be exposed.

[0140] Referring to Fig. 34 can be removed after removing the eighth mask 185 to expose the fourth masks 140, the first and second sections of the dummy gate electrode 175 and the section of the preliminary dummy gate insulating layer pattern 162 on the side walls of the fourth masks 140, the fourth masks 140 and the section of the preliminary dummy gate insulating layer pattern 162 on the side walls of the fourth masks 140.

[0141] Thus, the preliminary dummy gate insulating layer pattern 162 can be transformed into a first dummy gate insulating layer pattern 164 beneath the dummy gate electrode 175. The first dummy gate insulating layer pattern 164 can be formed on the first region 112 of the active layer 110 and the first insulating layer pattern 130, and the dummy gate electrode 175 can extend in the second direction onto the first dummy gate insulating layer pattern 164. Therefore, the first dummy gate insulating layer pattern 164 and the dummy gate electrode 175, stacked sequentially, can form a first dummy gate structure.

[0142] Then procedural steps that are essentially the same or similar to those described above with reference to the Fig. 27, Fig. 28, Fig. 29, Fig. 30, Fig. 31 to Fig. 32 were discussed, to be carried out to manufacture the semiconductor device.

[0143] Fig. Figure 35 is a cross-sectional view showing a semiconductor device according to some embodiments of the inventive concept. The semiconductor device may be substantially the same or similar to that described with reference to the Fig. 1, Fig. 2 to Fig. The diagram is shown in section 3, with the exception of the gate structure and the spacer. Therefore, identical reference symbols refer to the same elements, and detailed descriptions of these are omitted for the sake of brevity.

[0144] Referring to Fig. 35 The semiconductor device can include an active layer 110 on a substrate 100, a second gate structure 274 on the active layer 110, a second spacer 194 on a side wall of the second gate structure 274, and a source / drain layer 210 on a section of the active layer 110 adjacent to the second spacer 194. Furthermore, the semiconductor device can include a first insulating layer pattern 130 on the substrate 100, which covers a side wall of the active layer 110, and an insulating interlayer pattern 220 on the first insulating layer pattern 130, which covers the source / drain layer 210 and surrounds the second gate structure 274 and the second spacer 194.

[0145] The second gate structure 274 can contain a second silicon oxide layer pattern 244, a second high-k dielectric layer pattern 254 and a second gate electrode 264, which are sequentially stacked on the active layer 110.

[0146] In some embodiments, the second silicon oxide layer pattern 244 can be formed not only on the first region 112 of the active layer 110, but also on a section of the second region 114 of the active layer 110. The second high-k dielectric layer pattern 254 can be formed on the second silicon oxide layer pattern 244 and an inner side wall of the second spacer 194. The second gate electrode 264 can fill an interior space formed by the second high-k dielectric layer pattern 254, and thus a base and a side wall of the second gate electrode 264 can be covered by the second high-k dielectric layer pattern 254.

[0147] In some embodiments, a lower section of the second gate structure 274 can have a width in the first direction that is greater than that of an upper section of the second gate structure 274. In other words, the lower section of the second gate structure 274 can protrude from the upper section in the first direction.

[0148] In some embodiments, the second spacer 194 can be formed on the second area 114 of the active layer 110 and the lower section of the second gate structure 274, and thus does not contact an entire side wall of the second gate structure 274. A bottom surface of the second spacer 194 can be higher than that of the second gate structure 274.

[0149] A bottom surface of a section of the second spacer 194 on the lower section of the second gate structure 274 can be flat, and a bottom surface of a section of the second spacer 194 on the second area 114 of the active layer 110 can gradually rise in the first direction from a section of the second spacer 194 adjacent to the first area 112 towards a section of the second spacer 194 away from the first area 112.

[0150] Fig. 36, Fig. 37 to Fig. Figure 38 are cross-sections representing process steps in the manufacture of semiconductor devices according to some embodiments of the present inventive concept. These process steps are identical or similar to those described above with reference to the Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30, Fig. 31 to Fig. The 32 steps discussed can be carried out. Therefore, identical reference symbols refer to identical elements, and detailed descriptions of these are omitted for the sake of brevity.

[0151] First, procedures can be carried out that are essentially the same or similar to those used with regard to the Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23 to Fig. 24 were shown. Referring now to Fig. 36. Procedures may be carried out which are substantially the same or similar to those which are carried out with regard to the Fig. 25 and Fig. 26 were shown. However, if the fourth masks 140 and a section of the preliminary dummy gate insulating layer pattern 162 on side walls of the fourth masks 140 are removed, the section of the preliminary dummy gate insulating layer pattern 162 on the side walls of the fourth masks 114 cannot be completely removed.

[0152] In other words, most of a section of the preliminary dummy-gate insulating layer pattern 162 on the second region 114 of the active layer 110 cannot be removed, but remains to form a second dummy-gate insulating layer pattern 166, which can be formed not only on the first region 112 of the active layer 110, but also on a section of the second region 114 of the active layer 110. In some embodiments, the removal can be carried out by a wet etching process. In the wet etching process, the preliminary dummy-gate insulating layer pattern 162 can have a projection on the second region 114 of the active layer 110, and thus an etching solution cannot easily penetrate under the projection, allowing the second dummy-gate insulating layer pattern 166 to be formed.

[0153] Accordingly, a second dummy gate structure with the second dummy gate insulating layer pattern 166 and the dummy gate electrode 175 can have a projection on a lower section thereof, and thus the lower section of the second dummy gate structure can have a width in the first direction that is greater than that of an upper section thereof.

[0154] Referring to Fig. 37. Procedures may be carried out which are substantially the same or similar to those described above with reference to the Fig. 27 and Fig. 28 were discussed. Thus, a second spacer 194 can be formed on a side wall and a lower section of the second dummy gate structure, as well as on the second area 114 of the active layer 110. The second spacer 194 does not have to cover an entire side wall of the second dummy gate structure, and a bottom surface of the second spacer 194 can be higher than that of the second dummy gate structure.

[0155] Referring to Fig. 38. Procedures may be carried out which are substantially the same or similar to those described above with reference to the Fig. 29, Fig. 30, Fig. 31 to Fig. 32 were discussed. Thus, a third opening 230 can be formed, which exposes an upper surface of the first region 112 of the active layer 110 as well as a section of the upper surface of the second region 114 of the active layer 110.

[0156] Referring again to Fig. 35. Procedures may be carried out which are substantially the same or similar to those described above with reference to the Fig. 1, Fig. 2 to Fig. 3 were discussed in order to complete the semiconductor device.

[0157] Referring now to Fig. 39 A cross-sectional view, which represents a semiconductor device according to some embodiments of the present inventive concept, will be discussed. The semiconductor device may be substantially the same or similar to that described with reference to the Fig. 1, Fig. 2 to Fig. Figure 3 shows the elements, with the exception of the gate structure and the spacer. Therefore, identical reference symbols refer to identical elements, and detailed descriptions of these elements can be omitted for the sake of brevity.

[0158] As in Fig. As shown in Figure 39, the semiconductor device can include an active layer 110 on a substrate 100, a third gate structure 276 on the active layer 110, a third spacer 196 on a side wall of the third gate structure 296, and a source / drain layer 210 on a section of the active layer 110 adjacent to the third spacer 196. Furthermore, the semiconductor device can include a first insulating layer pattern 130 on the substrate 100, which covers a side wall of the active layer 110, and an insulating interlayer pattern 220 on the first insulating layer pattern 130, which covers the source / drain layer 210 and surrounds the third gate structure 276 and the third spacer 196.

[0159] The third gate structure 276 can contain a third silicon oxide layer pattern 246, a third high-k dielectric layer pattern 256 and a third gate electrode 266, which are stacked sequentially on the active layer 110.

[0160] In some embodiments, the third silicon oxide layer pattern 246 can be formed on the first region 112 of the active layer 110. The third high-k dielectric layer pattern 256 can be formed on the third silicon oxide layer pattern 246 and an inner side wall of the third spacer 196. The third gate electrode 266 can fill an interior formed by the third high-k dielectric layer pattern 256, and thus a base and a side wall of the third gate electrode 266 can be covered by the third high-k dielectric layer pattern 256.

[0161] In some embodiments, the third gate structure 276 may have a vertical side wall. In other words, the third gate structure 276 may not have a projection or recess on one of its side walls.

[0162] In some embodiments, the third spacer 196 can be formed on the second area 114 of the active layer 110 and a section of the first area 112 of the active layer 110 and can touch an entire side wall of the third gate structure 276.

[0163] A floor surface of a section of the third spacer 196 on the first area 112 of the active layer 110 can be flat, and a floor surface of a section of the third spacer 196 on the second area 114 of the active layer 110 can gradually rise in the first direction from a section of the third spacer 196 adjacent to the first area 112 to a section of the third spacer 196 away from the first area 112.

[0164] Fig. 40, Fig. 41 to Fig. Figure 42 are cross-sections representing process steps in the manufacture of semiconductor devices according to some embodiments of the inventive concept. Process steps can be carried out that are essentially the same or similar to those described above with reference to the Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30, Fig. 31 to Fig. 32 were discussed. Thus, identical reference symbols refer to identical elements, and detailed descriptions of them can be omitted for the sake of brevity.

[0165] First, procedures can be carried out that are essentially the same or similar to those described above with reference to the Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18 to Fig. 19 were discussed.

[0166] Referring to Fig. 40. A procedure may be carried out which is substantially the same or similar to the one described above with reference to Fig. 20 was discussed. However, a second dummy-gate insulating layer 161 can be formed on the first and second regions 112 and 114 of the active layer 110, the fourth masks 140, and the first insulating layer pattern 130 such that it has sufficient thickness so that the second dummy-gate insulating layer 161 cannot have a depression, even with a projection that extends outwards in the first direction at a point where the upper surface of the second region 114 of the active layer 110 and the fourth mask 140 touch each other. Thus, a dummy-gate electrode layer 170, which fills a second opening 155 on the second dummy-gate insulating layer 161, can be formed such that it has a vertical sidewall in the second opening 155.

[0167] Referring to Fig. 41. Procedures may be carried out which are substantially the same or similar to those described above with reference to the Fig. 21 and Fig. 26 were discussed. Thus, a third dummy gate structure with a third dummy gate insulating layer pattern 163 and a dummy gate electrode 175, which are sequentially stacked, can be formed on the first region 112 of the active layer 110. The third dummy gate structure can have a vertical side wall.

[0168] Referring to Fig. 42. Procedures may be carried out which are substantially the same or similar to those described above with reference to the Fig. 27, Fig. 28, Fig. 29, Fig. 30, Fig. 31 to Fig. 32 were discussed. Thus, a third spacer 196 can be formed on the second region 114 of the active layer 110 and a section of the first region 112 of the active layer 110 such that it has a vertical inner side wall, and a third opening 230 can be formed to expose an upper surface of the first region 112 of the active layer 110. A bottom surface of the third spacer 196 on the first region 112 of the active layer 110 can be flat, and a bottom surface of the third spacer 196 on the second region 114 of the active layer 110 can be raised from a section of the third spacer 196 adjacent to the first region 112 to a section of the third spacer 196 away from the first region 112 in the first direction.

[0169] Referring again to Fig. 39. Methods may be carried out to complete the semiconductor device which are substantially the same or similar to those described above with reference to the Fig. 1, Fig. 2 to Fig. 3 were discussed.

[0170] Referring now to Fig. 43 A cross-sectional view will be discussed, which represents a semiconductor device according to some embodiments of the present inventive concept. The semiconductor device may be substantially the same or similar to that which is described with reference to the Fig. 1, Fig. 2 to Fig. Figure 3 was shown, with the exception of the height of the insulating layer pattern. Therefore, identical reference symbols refer to identical elements, and detailed descriptions of these can be omitted for the sake of brevity.

[0171] As in Fig. As shown in Figure 43, the semiconductor device can include an active layer 110 on a substrate 100, a first gate structure 272 on the active layer 110, a first spacer 192 on a side wall of the first gate structure 272, and a source / drain layer 210 on a section of the active layer 110 adjacent to the first spacer 192. Furthermore, the semiconductor device can include a second insulating layer pattern 135 on the substrate 100, which covers a side wall of the active layer 110, and an insulating interlayer pattern 220 on the second insulating layer pattern 135, which covers the source / drain layer 210 and surrounds the first gate structure 272 and the first spacer 192.

[0172] In some embodiments, an upper surface of the second insulating layer pattern 135 can be substantially coplanar with a highest section of the upper surface of the second region 114 of the active layer 110. Thus, the semiconductor device can consist of the Fig. 1, Fig. 2 to Fig. 3. A FinFET on an active fin, while the semiconductor device consists of Fig. 43 is a planar transistor.

[0173] Referring now to the Fig. 44, Fig. 45, Fig. 46, Fig. 47, Fig. 48 to Fig. Section 49 discusses cross-sections that represent process steps in the manufacture of semiconductor devices according to some embodiments of the present inventive concept. Process steps can be carried out that are essentially the same or similar to those described above with reference to the Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30, Fig. 31 to Fig. 32 were discussed. Thus, identical reference symbols refer to identical elements, and detailed descriptions of them can be omitted for the sake of brevity.

[0174] First, a procedure can be carried out that is essentially the same or similar to the one described above with reference to Fig. 5 was discussed. Referring to Fig. 44. Procedures may be carried out which are substantially the same or similar to those described above with reference to the Fig. 6 and Fig. 7 were discussed. However, the insulating layer can be etched until a top surface of the active layer 110 can be exposed, so that a second insulating layer pattern 135 can be formed with a top surface that is essentially coplanar with a top surface of the active layer 110.

[0175] Referring to Fig. 45. Procedures may be carried out which are substantially the same or similar to those described above with reference to the Fig. 12 and Fig. 13 were discussed. However, the fourth mask 140 can be formed in such a way that it does not cover a side wall of the active layer 100, but partially covers the upper surface of the active layer 110.

[0176] Referring to Fig. 46. ​​Procedures may be carried out which are substantially the same or similar to those described above with reference to the Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18 to Fig. 19 were discussed. Thus, a second opening 155 can be formed, which exposes the first and second areas 112 and 114 of the active layer 110.

[0177] Referring to Fig. 47. A procedure may be carried out which is substantially the same or similar to the one described above with reference to Fig. 20 was discussed. However, the second insulating layer pattern 135 may have a high top surface area, and thus there may be no height difference between upper sections of the active layer 110 and the second insulating layer pattern 135.

[0178] Referring to Fig. 48. Procedures may be carried out which are substantially the same or similar to those described above with reference to the Fig. 21 and Fig. 22 were discussed. Thus, a dummy gate electrode 175 and a preliminary dummy gate insulating layer pattern 162 can be formed.

[0179] Referring to Fig. 49. Procedures may be carried out which are substantially the same or similar to those described above with reference to the Fig. 23 and Fig. 26 were discussed. Thus, a first dummy gate structure can be formed with a first dummy gate insulating layer pattern 164 and a dummy gate electrode 175, which are sequentially stacked on the first region 112 of the active layer 110.

[0180] Referring again to Fig. 43. Methods may be carried out for completing the semiconductor device which are substantially the same or similar to those described above with reference to the Fig. 27 to 32 and 1 to 3 were discussed.

[0181] As briefly discussed above, some embodiments of the present inventive concept provide for an active fin region adjacent to the channel region, which may have a low germanium concentration, while the channel region may have a high germanium concentration. Thus, the leakage current can be reduced and the charge carrier mobility increased, according to some embodiments discussed here. Furthermore, the channel region can be oxidized to form a silicon oxide layer after forming a mask that exposes the channel region at the active silicon-germanium fin, in order to realize different germanium concentrations in the channel region and the region of the adjacent active fin. Thus, the channel region can have a relatively high germanium concentration, and the region adjacent to the channel region can have a relatively low germanium concentration, according to embodiments discussed here.

[0182] The semiconductor device described above can be applied to various memory devices with transistors featuring a silicon-germanium channel. For example, the semiconductor device can be applied to logic devices such as central processing units (CPUs), main processing units (MPUs), or application processors (APs), and the like. Furthermore, the semiconductor device can be applied to volatile memory devices such as DRAM or RAM devices, or to non-volatile memory devices such as flash memory devices, PRAM, MRAM, RRAM, and the like.

Claims

[1] Semiconductor device with: an active layer (110) with germanium on a substrate (100), wherein the active layer (110) contains: a first area (112) with a first germanium concentration; and a second region (114) on both sides of the first region (112), wherein the second region (114) has a top surface that is higher than a top surface of the first region (112), wherein the second region (114) has a first section adjacent to the first region (112) and a second section higher than the top surface of the first region (112), and the second region (114) has a second germanium concentration lower than the first germanium concentration; a gate structure (272; 274; 276) on the first area (112) of the active layer (110); a spacer (192; 194; 196) that overlaps the second region (114) of the active layer (110) at least partially in a vertical direction that is substantially perpendicular to an upper surface of the substrate (100), the spacer (192; 194; 196) being in contact with a side wall of the gate structure (272; 274; 276); and a source / drain layer (210) adjacent to the second area (114) of the active layer (110). [2] Semiconductor device according to claim 1, wherein the first germanium concentration is substantially constant in the first region (112) and the second germanium concentration decreases from the first section to the second section of the second region (114). [3] Semiconductor device according to claim 1, wherein the source / drain layer (210) has a third germanium concentration, and a maximum value of the third germanium concentration is greater than that of the first germanium concentration. [4] Semiconductor device according to claim 1, wherein a bottom surface of the spacer (192; 194; 196) becomes higher from a first section of the spacer (192; 194; 196) adjacent to the first region (112) towards a second section of the spacer (192; 194; 196) away from the first region (112). [5] Semiconductor device according to claim 4, wherein the spacer (192; 194) has a recess in a horizontal direction on an inner side wall thereof, which contacts the side wall of the gate structure (272; 274). [6] Semiconductor device according to claim 4, wherein the spacer (196) has a vertical inner side wall which contacts the side wall of the gate structure (276). [7] Semiconductor device according to claim 1, wherein the gate structure (272; 274; 276) has a gate electrode (262; 264; 266) comprising a metal and a high-k dielectric layer pattern (252; 254; 256) which surrounds a bottom and a side wall of the gate electrode (262; 264; 266). [8] Semiconductor device according to claim 7, wherein the gate structure (272; 274; 276) further comprises a silicon oxide layer pattern (242; 244; 246) between the active layer (110) and the high-k dielectric layer pattern (252; 254; 256). [9] Semiconductor device according to claim 8, wherein the silicon oxide layer pattern (242; 246) is formed only on the first region (112) of the active layer (110). [10] Semiconductor device according to claim 8, wherein the silicon oxide layer pattern (244) is formed not only on the first area (112) of the active layer (110) but also on at least one section of the second area (114) of the active layer (110). [11] Semiconductor device according to claim 7, wherein the side wall of the gate structure (272; 274) has a projection in a horizontal direction. [12] Semiconductor device according to claim 7, wherein the side wall of the gate structure (276) has a vertical side wall. [13] Semiconductor device according to claim 1, wherein both the active layer (110) and the source / drain layer (210) contain silicon germanium. [14] Semiconductor device according to claim 1, wherein the source / drain layer (210) is highly doped with p-foreign atoms and the second region (114) of the active layer (110) is lightly doped with p-foreign atoms. [15] Semiconductor device according to claim 1, wherein an upper surface of the first region (112) of the active layer (110) is flat and is not higher than an upper surface of the second region (114) of the active layer (110). [16] Semiconductor device according to claim 1, further comprising an insulating layer pattern (130; 135) on the substrate (100), wherein the insulating layer pattern (130; 135) surrounds a side wall of the active layer (110). [17] Semiconductor device according to claim 16, wherein an upper surface of the insulating layer pattern (130) is lower than that of the active layer (110). [18] Semiconductor device with: an active layer (110) containing germanium on a substrate, wherein the active layer (110) contains: a first area (112) with a first germanium concentration; and a second region (114) on both sides of the first region (112), wherein the second region (114) has a second germanium concentration which decreases from the first germanium concentration from a first section of the second region (114) adjacent to the first region (112) to a second section of the second region (114) away from the first region (112); a gate structure (272; 274; 276) on the first area (112) of the active layer (110); a spacer (192; 194; 196) that overlaps the second region (114) of the active layer (110) at least partially in a vertical direction that is substantially perpendicular to an upper surface of the substrate (100), the spacer being in contact with a side wall of the gate structure (272; 274; 276); and a source / drain layer (210) adjacent to the second area (114) of the active layer (110). [19] Semiconductor device according to claim 18, wherein an upper surface of the second region (114) of the active layer (110) is higher than an upper surface of the first region (112). [20] Semiconductor device according to claim 19, wherein a bottom surface of the spacer (192; 194; 196) becomes higher from a first section of the spacer (192; 194; 196) adjacent to the first region (112) towards a second section of the spacer (192; 194; 196) away from the first region (112). [21] Semiconductor device according to claim 18, wherein the gate structure comprises (272; 274; 276): a silicon oxide layer pattern (242; 244; 246) on the active layer (110); a high-k dielectric layer pattern (252; 254; 256) on the silicon oxide layer pattern (242; 244; 246) and an inner side wall of the spacer (192; 194; 196); and a gate electrode (262; 264; 266) with a metal, wherein a bottom and a side wall of the gate electrode (262; 264; 266) is surrounded by the high-k dielectric layer pattern (252; 254; 256). [22] Semiconductor device according to claim 21, wherein: the source / drain layer (210) is highly doped with p-type foreign atoms; and wherein the second region (114) of the active layer (110) is slightly doped with p-foreign atoms. [23] Method for manufacturing a semiconductor device with: a formation of an active layer (110) with silicon germanium on a substrate (100); a partial oxidation of the active layer (110) to form a silicon oxide layer (150) on the active layer (110), such that a first region (112) of the active layer (110) under the silicon oxide layer (150) has a first germanium concentration, and a second region (114) of the active layer (110) adjacent to the first region (112) under the silicon oxide layer (150) has a second germanium concentration which is lower than the first germanium concentration; a removal of the silicon oxide layer (150) to expose the first and second regions (112, 114) of the active layer (110); a source / drain layer (210) on the active layer (110) adjacent to the second region (114) of the active layer (110); and a gate structure (272; 274; 276) forming on the exposed first region (112) of the active layer (110); and forming a spacer (192; 194; 196) on a side wall of the gate structure (272; 274; 276), wherein the spacer (192; 194; 196) overlaps the second region (114) of the active layer (110) at least partially in a vertical direction that is essentially perpendicular to an upper surface of the substrate (100). [24] Method according to claim 23, wherein the partial oxidation of the active layer (110) to form the silicon oxide layer (150) on the active layer (110) comprises the following: a mask formation (140) to partially cover the active layer (110); and an oxidation of the active layer (110) according to the mask (140). [25] Method according to claim 24, wherein a section of the active layer (110) not covered by the mask (140) is oxidized by oxidizing the active layer (110).

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