Pauseable bisynchronous FIFO

Abstract

A process that exhibits: Writing data synchronously with a first clock signal of a first clock domain into an entry of a dual-port memory array; Generating an increment signal in the first clock domain; Determine that the increment signal changes near an edge of a second clock signal, where the second clock signal is a pausable clock signal; Delaying the next edge of the second clock signal of the second clock domain, wherein the next edge of the second clock signal is delayed until the metastability of the increment signal is resolved; and Transferring the increment signal to the second clock domain.

Description

Field of invention

[0001] The present invention relates to synchronization and, in particular, to synchronization using a pauseable clock.

[0002] Modern system-on-a-chip (SOC) designs built in deeply scaled process nodes present extraordinary design challenges. Slow lines and process, voltage, and temperature (PVT) fluctuations make synchronous abstraction across large chip areas, which requires immense effort to achieve timing completion, unsustainable. The globally asynchronous, locally synchronous (GALS) design method is a means of mitigating the global timing completion problem. GALS design flows delimit "synchronous islands" of logic that operate based on local clocks and communicate asynchronously with each other.

[0003] Individual clock domains in large commercial designs span many square millimeters, and GALS systems exhibit many of the design challenges posed by a fully synchronous design. The sweeping benefits of GALS design can only be realized when large SoCs are divided into a myriad of small synchronous blocks, rather than a handful of large domains—an approach known as fine-grained GALS. The industry has been hesitant to adopt the fine-grained GALS approach for three main reasons: the difficulty of generating many local clocks, the latency introduced by asynchronous boundary crossings, and the challenge of integrating the GALS methodology into the design tool flows of standard application-specific integrated circuits (ASICs).There is therefore a need to address these and / or other aspects related to the state of the art.

[0004] US Patent 8,428,207 B1 describes a method for determining a time for reliably sampling a signal in a clock domain. A FIFO synchronizer is implemented using two even / odd (I / O) synchronizers. The FIFO memory uses a dual-port memory that is written synchronously and read asynchronously. The FIFO memory is written to, and an end pointer is incremented on a rising edge of the input clock if the input is valid and the FIFO memory is not full. The start pointer selects the value at the beginning of the FIFO to be displayed at the memory's output port. The start pointer is incremented on the rising edge of the output clock if the FIFO memory is not empty. The end pointer and the fill logic reside in the input clock domain, while the start pointer and the empty logic reside in the output clock domain. A pair of E / O synchronizers shifts the start and end pointers between the two clock domains.One synchronizer transfers the end pointer from the input clock domain to the output clock domain, and a second synchronizer transfers the start pointer from the output clock domain to the input clock domain.

[0005] US Patent 2011 / 0204932A1 concerns an asynchronous scheme for transitioning between clock domains, for example, between a first clock domain and a second clock domain, driven by pausable clocks and controlled by handshakes. A device includes a first control logic element for processing a handshake signal and generating a first arbiter signal. Simultaneously, a second control logic element processes a second handshake signal and generates a second arbiter signal. For example, an arbitrator receives the first and second arbitrator signals and outputs a first clock signal to a first sequential element and a second clock signal to a second sequential element.To control metastability by controlling the timing of the clock inputs of the sequential devices, the device comprises a first controllable latching delay element selected to satisfy the setup constraint of the second sequential element, and a second controllable latching delay element selected to satisfy the hold constraint of the second sequential element.

[0006] The task is therefore to improve the transmission of a signal, especially an increment signal, between two clock domains of a dual-port memory array, and in particular to reliably avoid metastability without additional synchronization stages or increased latency. Summary

[0007] This problem is solved by a method according to claim 1 and a system according to claim 18. The dependent claims define embodiments.

[0008] A system and method for a pausable bisynchronous first-in, first-out (FIFO) buffer are provided. In this method, data is written synchronously with a clock signal from a first clock domain to an entry in a dual-port memory array, and an increment signal is generated in the first clock domain. It is determined that the increment signal transitions near the edge of a second clock signal. The second clock signal is a pausable clock signal. The next edge of the second clock signal of the second clock domain is delayed until the metastability of the increment signal is resolved, and the increment signal is then passed to the second clock domain. If the increment signal does not transition near the edge of the second clock signal, the increment signal is passed to the second clock domain without delaying the next edge of the second clock signal. Brief description of the drawings Fig. Figure 1 illustrates a method for updating a read pointer of a pausable bisynchronous FIFO according to one embodiment. Fig. Figure 2A illustrates an adaptive clock generator according to one embodiment. Fig. Figure 2B illustrates a pausable clock synchronizer according to one embodiment. Fig. Figure 2C illustrates a timing diagram according to one embodiment, showing the transmission of a signal between two clock domains. Fig. Figure 2D illustrates a timing diagram according to one embodiment, showing a delayed transmission of a signal between two clock domains. Fig. Figure 2E illustrates a timing diagram according to one embodiment, showing a transmission of a signal between two clock domains when a clock signal is paused. Fig.Figure 3A illustrates a pausable bisynchronous FIFO according to one embodiment. Fig. Figure 3B illustrates another pausable bisynchronous FIFO according to one embodiment. Fig. Figure 3C illustrates a method for updating the read pointer and the write pointer of the pausable bisynchronous FIFO according to one embodiment. Fig. 3D illustrates another pausable clock synchronizer according to a different embodiment. Fig. 4A illustrates timing paths of the in Fig. 2B shown a pausable clock synchronizer according to one embodiment. Fig. Figure 4B illustrates a clock-period-timing constraint of the in Fig. 2B shown a pausable clock synchronizer according to one embodiment. Fig. 4C illustrates another clock-period-timing constraint of the one in Fig.2B shown a pausable clock synchronizer according to one embodiment. Fig. 4D illustrates a setup timing limitation of the in Fig. 2B shown a pausable clock synchronizer according to an embodiment. Fig. Figure 5 illustrates the effect of an insertion delay on the in Fig. 2B shown a pausable clock synchronizer according to one embodiment. Fig. Figure 6A illustrates a block diagram according to an embodiment showing a physical placement of a pausable clocking system. Fig. Figure 6B shows another block diagram according to an embodiment, which shows a physical placement of a pausable clocking system. Fig. Figure 7 illustrates an exemplary system in which the different architectures and / or functionalities of the various previous embodiments can be implemented. Detailed description

[0009] Many of the challenges of a modern system-on-a-chip (SoC) can be mitigated or eliminated using globally asynchronous, locally synchronous (GALS) design techniques. Dividing a design into many synchronous islands introduces a myriad of asynchronous boundary crossings, which typically result in high latency. A pausable bisynchronous first-in, first-out (FIFO) buffer can achieve low interface latency when a pausable clocking scheme is used. While traditional synchronizers have a non-zero probability of metastability and failure, a pausable clock enables error-free operation by allowing sporadic slowdowns in the clock rate.

[0010] Low-latency asynchronous boundary crossings can be achieved using pausable clocks. In one embodiment, an interface uses a dual-port memory array to store data and synchronizes read and write pointers using two phase signals, allowing the data written to and read from the dual-port memory array to traverse the interface with very low latency.

[0011] The dual-port memory array is configured as a bisynchronous two-port FIFO, a circuit element that integrates well into standard computer-aided design (CAD) tool flows. In one embodiment, the pausable bisynchronous FIFO can achieve an average latency of 1.34 cycles through an asynchronous interface, while consuming less power and area than traditional synchronizers. In other embodiments, the pausable bisynchronous FIFO achieves various average latencies when traversing the asynchronous interface. Generally, the average latency can vary depending on the process technology, clock rates, circuit topologies, and similar factors.

[0012] Fig.Figure 1 illustrates a method 100 for updating a read pointer of a pausable bisynchronous FIFO according to one embodiment. In step 110, data is written synchronously with a first clock signal of a first clock domain to an entry of a dual-port memory. In the context of this description, a dual-port memory array comprises a write port and a read port, which can be accessed simultaneously. A write pointer indicates the next entry to be written to, and a read pointer indicates the next entry to be read. If the dual-port memory array is configured as a first-in, first-out buffer, the write pointer indicates the next entry into which the data is pushed, and the read pointer indicates the next entry from which the data is retrieved. The data is read synchronously from the dual-port memory with a second clock signal of a second clock domain.In one embodiment, both the first and second clock signals are pausable. In another embodiment, either the first clock signal or the second clock signal is pausable, and the other clock signal is not. The first and second clock signals can operate at the same frequency or at different frequencies. Unlike a clock signal with a fixed frequency (and a fixed period), a pausable clock signal does not have a fixed frequency, since one or more edges of the pausable clock signal can be delayed.

[0013] In step 120, an increment signal is generated in the first clock domain. This increment signal is generated in response to a write of data to the entry. In one embodiment, the increment signal is configured to increment the read pointer located in the second clock domain. In the context of the following description, the increment signal is a pulse that is asserted until an acknowledgment is received that the increment signal has been received in the second clock domain.

[0014] In step 130, if the increment signal changes near an edge of the second clock signal, the second clock signal is paused in step 140 to delay the next edge of the second clock signal. Otherwise, the increment signal is transferred from the first clock domain to the second clock domain in step 150. In one embodiment, the increment signal is designed to change near the edge of the second clock signal if the increment signal changes while the second clock signal is in a low phase (e.g., the second clock signal is FALSE). In another embodiment, the increment signal is designed to change near the edge of the second clock signal if the increment signal changes while the second clock signal is in a high phase (e.g., the second clock signal is TRUE).In step 160, a read pointer of the dual-port memory array is incremented in response to receiving the increment signal. In one embodiment, an acknowledgment signal is transmitted from the second clock domain to the first clock domain to confirm that the increment signal has been received.

[0015] More illustrative information will now be presented regarding various optional architectures and features that may or may not be used to implement the preceding framework, depending on the user's requirements. It should be emphasized that the following information is provided for illustrative purposes and should not be interpreted as restrictive in any way. Each of the following features can be included optionally, with or without excluding the other described features.

[0016] Historically, on-chip clock signals were generated by phase-locked loop (PLL) circuits. While PLLs can reliably generate a fixed target frequency, they are large, power-hungry, and difficult to design, making them poor candidates for inclusion in any synchronous island of a GALS system. In contrast, an adaptive clock scheme does not operate at a specific frequency and instead uses replica-critical path circuits to continuously adjust the generated clock signal. The clock period of an adaptive clock signal can vary temporarily, and adaptive clock generators do not introduce the complexity of clock schemes implemented using PLLs.

[0017] Fig.Figure 2A illustrates an adaptive clock generator 200 according to one embodiment. A simple adaptive clock circuit, such as the adaptive clock generator 200, comprises one or more inverting delay lines introduced into the input of a Müller C element 205. The delay lines replicate the various critical paths found on the synchronous logic island; the Müller C element 205 ensures that the next clock edge will not be generated until the slowest replicated critical path has cleared. Adaptive clock circuits may already be present in many GALS implementations, and a pausable clock circuit can be combined with the adaptive clock generator 200 to reduce synchronization latency.

[0018] Signals that cross the boundaries between fully asynchronous clock domains, such as signals traveling between synchronous islands in a GALS design, must be synchronized to minimize the risk of metastability and operational disturbances. This synchronization is typically achieved by sending such signals through several cascaded flip-flops in the receiver's clock domain. The flip-flops delay the signal for one or more cycles, providing additional time to eliminate any metastability. While these brute-force (BF) synchronizers do not eliminate the possibility of metastability, they can reduce the probability to negligible levels. Brute-force synchronizers can be used with a FIFO memory to construct a bisynchronous brute-force FIFO.A bisynchronous brute-force FIFO reliably transfers data between two clock domains, synchronizing the read and write pointers with the BF synchronizers. The read and write pointers must be gray-coded so that any synchronization error does not disturb the pointer position by more than one increment; the logic for encoding and decoding the read and write pointers represents circuit overhead in a bisynchronous brute-force FIFO implementation.

[0019] Brute-force synchronizers deliberately add latency to the domain crossing path to allow for any metastability state time to be cleared. However, the added latency slows down communication between clock domains, creating a significant barrier to adapting a chip with many different clock domains. Additionally, it is impossible to completely eliminate the potential for a metastable state to propagate, giving these circuits an "average time to failure" that must be carefully considered.

[0020] Conventional approaches reduce clock domain crossing latency by making assumptions about the relative frequency or phase of the two clocks. However, these conventional approaches are unreliable because the assumptions are not valid for a fully asynchronous interface. Other approaches use fully asynchronous logic that is independent of clocks. However, asynchronous logic often consumes more power than its synchronous equivalent, and it can be difficult to integrate it into standard CAD flows for synthesis and verification.

[0021] In one embodiment, a synchronizing FIFO utilizes the advantage of an asynchronous technique based on pausable clocks. This technique delays data signals arriving within an uncertain window in order to receive the clock signal, thus preventing data signals from being sampled at a problematic time. Fig.Figure 2B illustrates a pausable clock synchronizer 210 according to one embodiment. A mutual exclusion element (mutex) 215 is a circuit that assigns priority to either an incoming (non-synchronized) request signal (input R1) or the approaching clock edge (input R2). The mutex 215 ensures that the asynchronous request signal received at input R1 cannot switch simultaneously with the rising clock edge. In particular, the mutex 215 ensures that the g1 output does not switch while the R2 input is in high phase, which in turn ensures that the g1 output does not switch simultaneously with the rising clock edge.In another embodiment, the mutex circuit is configured to ensure that the g1 output does not switch while the R2 input is in a low phase, which in turn ensures that the g1 output does not switch simultaneously with the falling clock edge.

[0022] The Mutex 215 is added to a ring oscillator clock circuit, which can be implemented as an adaptive clock generator. The clock input to the Mutex should have priority for the next clock edge to be output, and this priority is enforced by the Mutex 215. A Müller C-element 205 ensures that the next clock edge waits until the clock input to the Mutex 215 (e.g., R2) receives priority. The clock input is the receiving clock with which the request signal will be synchronized. If a request signal (e.g., a rising edge of a pulse) arrives during a low phase of the clock (before a change in the request signal could trigger metastability), the request signal cannot be given priority and is delayed by one clock cycle. The delayed request signal is output by the Mutex 215 as a synchronized request to a receiving block. The one at the R2 input to the Mutex 215 (e.g.The signal received (with an inverted clock) is output as g2.

[0023] Fig. Figure 2C illustrates a timing diagram 220 according to one embodiment, showing the transmission of a signal between two clock domains. The clock waveform is a receiving clock, and the pausable clock synchronizer 210 synchronizes the request signal with the receiving clock to generate the synchronized request signal. When the R2 input is low, the mutex 215 is transparent, and the request signal at R1 is passed through to generate the synchronized request signal.

[0024] If a request signal arrives during a high phase of the clock, the request signal is safe from metastability and is immediately output by the pausable clock synchronizer 210 as the synchronized request to the receiving block. Fig.Figure 2D illustrates a timing diagram 220 according to an embodiment, showing a delayed transmission of the request signal between two clock domains. When the R2 input of the mutex 215 is high, the mutex 215 is opaque, and the request signal at the R1 input is delayed until the clock edge has passed. The signal received at the R2 input to the mutex 215 (e.g., an inverted clock) is output as g2. In the event that the mutex 215 becomes metastable, the next clock edge is simply delayed, thus making the pausable clock synchronizer 210 immune to disturbances associated with metastability.

[0025] Fig.Figure 2E illustrates a timing diagram 230 according to one embodiment, showing the transmission of a signal between two clock domains when a clock signal is paused. Since the mutex 215 can become metastable if the R1 and R2 inputs switch simultaneously, the clock can pause for an arbitrarily long duration (with a vanishingly small probability) if R1 and R2 switch to high at the same time. However, there is no risk of metastability at the asynchronous input, and typical circuit operation synchronizes the input signals with approximately one latency cycle. As shown in Fig. As shown in 2E, the signal received at the R2 input to the Mutex 215 (e.g., inverted clock) is delayed and output as g2.

[0026] As previously explained, a pausable clock allows for low-latency synchronization of signals with any relative phase and, as such, represents an attractive option for pushing the boundaries in GALS design. In one embodiment, a pausable clock is used to perform flow control of a synchronous two-port memory array to implement a bisynchronous FIFO. A "synchronous" FIFO / memory is one in which read and write operations are clocked by the same clock. A "bisynchronous" FIFO / memory is one in which read operations are synchronous with one clock, and write operations are synchronous with a second clock. An "asynchronous" FIFO is not clocked but is read and written according to arbitrarily clocked signals (such as request and acknowledge signals).A simple "asynchronous" FIFO functions like a shift register, in which written data moves forward toward the end of the FIFO whenever the register preceding the written data is empty, without needing to wait for the next clock cycle. Asynchronous FIFOs are usually energy-intensive because the data moves through each entry in the FIFO rather than remaining in one place (i.e., the entry that was written) and the read / write pointers move.

[0027] Conventional asynchronous FIFOs have several disadvantages compared to synchronous FIFOs. Instead of keeping the data stored in an entry in one place and updating read and write pointers as data is read and written, conventional asynchronous FIFOs spread the data through different entries from back to front of a queue. Moving the data through the various entries incurs a penalty in both energy and latency, a penalty that increases with the depth of the queue. Furthermore, many conventional asynchronous FIFOs require careful delay balancing to meet two-way timing constraints. Conventional asynchronous FIFOs inevitably require careful asynchronous circuit design, and verification of asynchronous FIFOs is inadequately supported by standard Very Large Scale Integration (VLSI) tool flows.

[0028] A pausable clocking technique can be used with a synchronous two-port memory array to implement a pausable FIFO that can be written to synchronously in one clock domain and read synchronously in another. The data is stored in the synchronous two-port memory array, while the read and write pointers are synchronized between the clock domains. Unlike a conventional bisynchronous FIFO, the synchronization of the read and write pointers is completed using a pausable clock network within the pausable bisynchronous FIFO, rather than slow (i.e., high-latency) brute-force synchronizers. The pausable bisynchronous FIFO design benefits from the low-latency synchronization inherent in pausable clocking while retaining the favorable characteristics of a standard two-port FIFO.

[0029] Fig.Figure 3A illustrates a pausable bisynchronous FIFO 300 according to one embodiment. For clarity, only one increment-acknowledgment path is shown; in the complete system, each increment and acknowledgment line can be implemented using a dedicated mutex 215 and a synchronization circuit. The identifying letters (e.g., A, B, C, D, E, F, and G) indicate the sequence necessary to synchronize the data through the pausable bisynchronous FIFO 300 and are described below. Pausable clock synchronizers 305 and 310 provide synchronization in both the transmit (TX) and receive (RX) clock domains. The circuits used to implement the 305 and 310 pausable clock synchronizers are similar to those of the 210 pausable clock synchronizers, including a feedback latch and an exclusive OR (XOR) gate.A latch is used instead of a flip-flop to reduce overhead. The XOR gate terminates a request pulse after synchronizing a request with the receive clock. As in... Fig. As shown in Figure 3A, the request (e.g., a pointer increment signal or pointer acknowledgment signal) to the second clock domain is transmitted via the feedback latch, which is coupled to a flip-flop. The feedback latch can be directly coupled to the flip-flop or indirectly coupled to it via one or more buffers or other circuitry.

[0030] It should be noted that in one embodiment, each of the pausable clock synchronizers 305 and 310 relies on an input pointer increment or an acknowledgment signal to implement a two-phase request-acknowledgment protocol. The two-phase request-acknowledgment protocol ensures that the unsynchronized request signal is asserted only once, and an acknowledgment should be received before the request signal is asserted again. The two-phase request-acknowledgment protocol prevents additional switching of the request signal during an unsafe clock phase.The design of the two-phase request-acknowledgment protocol prevents multiple assertions within a single clock period; however, limiting the frequency of requests is problematic for synchronizing pointer updates, as it implies that each pointer can only be updated once per cycle, thus limiting throughput to the slower of the two clock periods.

[0031] Accordingly, the pausable bisynchronous FIFO 300 does not directly synchronize the multi-bit pointers. Instead, various single-bit, two-phase pointer increment lines signal an update to the read or write pointers, and corresponding pointer acknowledgment signals are returned once the relevant increments have been synchronized. Multiple pointer increments can occur sequentially within a single clock period, and full throughput is permitted even with mismatched clock periods. In one embodiment, three increment acknowledgment pairs are implemented in each direction. Additional increment and acknowledgment lines can be added to ensure full throughput in the event of extreme mismatches between TX and RX clock periods.

[0032] Each increment and acknowledgment signal is synchronized by a dedicated Mutex 215 in a corresponding pausable clock synchronizer (e.g., a TX pausable synchronizer 305 and an RX pausable synchronizer 310), which has a corresponding pausable clock network. The g2 outputs of all Mutex 215s within each pausable clock synchronizer 305 and 310 are ANDed together, and the result is used as the synchronizing input to the Müller C-element 205, ensuring that the clock edge is not generated until each Mutex 215 guarantees a safe phase. Additional interfaces (e.g., to multiple different synchronous islands) can also be included in the same way: the g2 outputs of each interface can be ANDed together to ensure that all interfaces synchronize correctly.Synchronizing multiple interfaces does not have the side effect that a clock pause from any interface will delay the entire synchronous domain.

[0033] In the TX domain, the write pointer logic 315 stores the value of the write pointer, as well as the value of an approximate read pointer (possibly delayed from the actual read pointer position, as updates are synchronized from the RX domain). The write pointer logic 315 uses the values ​​of the write pointer and the approximate read pointer to calculate whether the dual-port FIFO 325 is full and to signal a backpressure accordingly. The write pointer logic 315 also transmits write pointer increment signals to the receive clock domain (RX clock) by switching one of the two-phase write pointer increment lines when writing to an entry of the dual-port FIFO 325. A state machine within the write pointer logic 315 tracks which write pointer increment signals are inflight and which write pointer increment signals have been acknowledged and can be reused.

[0034] In the RX domain, the read pointer logic 320 stores the value of the read pointer, as well as the value of an approximate write pointer (possibly delayed from the actual write pointer position because updates are synchronized from the TX domain). If multiple write pointer increment signals are received in the same clock cycle, the read pointer logic 320 combines the individual write pointer increment signals so that the value of the approximate write pointer is incremented by one, two, three, or more in a single clock cycle. The read pointer logic 320 uses the values ​​of the read pointer and the approximate write pointer to calculate whether the dual-port FIFO 325 is empty. The read pointer logic 320 also transmits read pointer increment signals to the transmit clock domain (TX clock) by switching one of the two-phase read pointer increment lines in the event of a read operation from an entry of the dual-port FIFO 325.In one embodiment, when multiple read pointer increment signals are received by the write pointer logic 315 in the same clock cycle, the write pointer logic 315 combines the individual write pointer increment signals such that the value of the approaching read pointer is increased by one, two, three or more in a single clock cycle.

[0035] A state machine within the read-pointer logic 320 tracks which read-pointer increment signals are inflight and which have been acknowledged and are available for reuse. In one embodiment, when multiple acknowledgment signals are received in the same clock cycle, the read-pointer logic 320 combines the individual acknowledgment signals so that the number of inflight read-pointer increment signals can be updated by one, two, three, or more in a single clock cycle. By combining the write-pointer logic 315, the read-pointer logic 320, and the pausable clock synchronizers 305 and 310, the pausable bisynchronous FIFO 300 can synchronize new input data on average in approximately one cycle.

[0036] The Dual-Port FIFO 325 is clocked by the TX clock and includes a memory array that can be implemented as flip-flops, a latch array, or static random access memory (SRAM). Such FIFOs are standard circuit elements in modern designs, and the numerous area and power optimizations developed for FIFOs can be effectively utilized without additional design effort. In one embodiment, no special design is required to implement the Dual-Port FIFO 325, and standard sampling and test structures can be easily implemented.

[0037] Fig.Figure 3A illustrates another pausable bisynchronous FIFO 301 according to one embodiment. In this embodiment, the pausable bisynchronous FIFO 301 is modified to couple between a clock domain with a pausable clock and a clock domain with a traditionally fixed reference, such as a PLL. By replacing the pausable synchronizer on the fixed-reference side with brute-force synchronizing flip-flops to synchronize the increment and acknowledge pointers, low latency in one direction can be maintained. Consequently, a system can be partially converted to a GALS design while retaining the legacy logic with the traditional clock where appropriate. These advantages make the pausable bisynchronous FIFO 300 and 301 a good candidate for overcoming the hurdles to widespread GALS adoption.

[0038] The marked sequence in Fig. Figure 3A shows the sequence of steps involved in writing a data word to the pausable bisynchronous FIFO 300. In an example, the pausable bisynchronous FIFO 300 is initially empty, and all two-phase increment and acknowledgment lines are available for use. On a rising edge of the TX clock, data is written to the entry specified by the write address (i.e., corresponding to the write pointer), and the valid input signal is asserted (label A). Once the data has been written to the entry, the data is available to read from the pausable bisynchronous FIFO 300. The write pointer logic 315 increments the write pointers for the TX domain and toggles one of the two-phase write pointer increment lines (label B).

[0039] The write pointer increment line is switched to the TX domain. Therefore, the write pointer increment line is asynchronous to the RX domain and should be synchronized by the RX pauseable synchronizer 310. Depending on the phase at which the write pointer increment switch arrives in the RX domain, the write pointer increment may pass through the mutex 214 immediately, be delayed until the next RX clock edge, or (in rare cases) cause metastability in the mutex 215 and be delayed for a longer period. However, the write pointer increment may be synchronized to the RX domain (label C), after which the read pointer logic 320 can increase the approach of the internal write pointer and establish a valid signal at the output of the pauseable bisynchronous FIFO 300 (label D).

[0040] Once the valid signal is established, data can be read synchronously from the dual-port FIFO 325 in the RX domain. As soon as a read operation occurs, the RX pointer logic 320 toggles one of the read pointer increment signals to inform the TX domain that a read operation has occurred and that the read pointer has been updated (these series of toggles are described in Fig.3A not marked). From the perspective of the TX domain, however, once the valid signal has been asserted by the read pointer logic 320, the write pointer increment is still in flight, as a corresponding acknowledgment signal has not yet been received from the RX domain by the write pointer logic 315. Accordingly, after the write pointer update has been synchronized, the RX clock edge switches the corresponding acknowledgment line (marked E). Since the switching of the corresponding acknowledgment line occurs in the RX clock domain, the pointer acknowledgment signal must be synchronized by the TX-pauseable synchronizer 305 (marked F). The synchronized pointer acknowledgment signal then updates the TX logic state machine in the write pointer logic 315, which releases the write pointer increment line for future use (label G).

[0041] As previously explained, the pausable bisynchronous FIFO 300 is modified in one embodiment to couple between a clock domain with a pausable clock and a clock domain with a traditional fixed reference, such as a PLL. Specifically, in one embodiment, the pointer increment signals generated by the read pointer logic 320 can be brute-force synchronized using multiple flip-flops clocked using the first clock signal, instead of synchronizing the (read) pointer increment signals using a second RX pausable synchronizer 310 (not shown).Similarly, the corresponding (read) pointer acknowledgment signal can be brute-force synchronized using multiple flip-flops clocked using the second clock signal, instead of synchronizing the (read) pointer acknowledgment signal using a second TX pausable synchronizer 305 (not shown). In another embodiment, the pointer increment signals generated by the write pointer logic 325 can be brute-force synchronized using multiple flip-flops clocked using the second clock signal, instead of synchronizing the (write) pointer increment signals using the RX pausable synchronizer 310, as shown in Figure 1. Fig.3A shows how to synchronize the corresponding (write) pointer acknowledgment signal. Similarly, the corresponding (write) pointer acknowledgment signal can be brute-force synchronized using multiple flip-flops clocked using the first clock signal, instead of using the TX pausable synchronizer 305, as shown in Fig. 3A shown, to synchronize.

[0042] Fig.Figure 3C illustrates a method 350 for updating the read pointer and the write pointer of the pausable bisynchronous FIFO according to one embodiment. Although the method 350 is described in the context of the pausable bisynchronous FIFO 300, the method 350 can also be performed by a custom-designed circuit or by a combination of one or more custom-designed circuits, a software driver, and / or a program. Furthermore, those skilled in the art will recognize that any system performing the method 350 falls within the scope and spirit of the embodiments of the present invention.

[0043] In step 302, the data is written synchronously with a first clock signal from a first clock domain to an entry in a dual-port memory. In one embodiment, the first clock domain is a TX clock domain. The data is read from the dual-port memory synchronously with a second clock signal from a second clock domain. In one embodiment, both the first and second clock signals are pauseable. In another embodiment, either the first clock signal or the second clock signal is pauseable, and the other clock signal is not. The first and second clock signals can operate at the same frequency or at different frequencies.

[0044] In step 312, an increment signal is generated in the first clock domain. In step 330, the pausable clock synchronizer 210 determines whether the increment signal transitions near an edge of a second clock signal, and if so, the pausable clock synchronizer 210 determines in step 335 whether the increment signal synchronized with respect to the second clock domain is metastable. In one embodiment, the second clock domain is an RX clock domain. If the increment signal synchronized with respect to the second clock domain is not metastable, the increment signal is passed to the second clock domain as the synchronized increment signal in step 345. Otherwise, if the increment signal synchronized with respect to the second clock domain is metastable, the next edge of the second clock signal is delayed in step 360 before returning to step 335.

[0045] If the pausable clock synchronizer 210 determines in step 330 that the increment signal does not change near the edge of a second clock signal, the increment signal is transferred from the first clock domain to the second clock domain as the synchronized increment signal in step 355. In step 365, a read pointer of the dual-port memory array is incremented in response to receiving the increment signal. In one embodiment, an acknowledgment signal is transferred from the second clock domain to the first clock domain to confirm that the increment signal has been received. In another embodiment, a second increment signal is generated in the second clock domain when the data is read synchronously with the second clock signal of the second clock domain. An acknowledgment signal can be transferred from the first clock domain to the second clock domain to confirm that the second increment signal has been received.

[0046] In real systems, the clock distribution network within the synchronous island will have some insertion delay t. ins The insertion delay occurs between the generation of the clock edges and their propagation through the clock network to the register endpoints. This insertion delay alters the transparent phase of the mutex, which can lead to circuit disturbances, as seen in conjunction with... Fig. As described in section 5, handling large insertion delays is a fundamental challenge for pausable clock schemes. One well-known technique for allowing larger insertion delays places all flip-flops adjacent to the interface on a separate clock with a much smaller clock tree. However, this approach can pose challenges for standard ASIC design tool flows.

[0047] Fig.Figure 3D illustrates another pausable clock synchronizer 370 according to a different embodiment. The pausable clock synchronizer 370 includes an added blocking latch 375 between a latch 325 and a flip-flop 380 to protect against runs caused by long insertion delays. The blocking latch 375 protects the clocked flip-flop 280 until the clock can propagate from the root through the clock tree.

[0048] A high latch (375) is a transparent high latch activated by the R2 input. Thus, the high latch is only transparent if the mutex 215 is not transparent. The high latch allows requests to propagate through the transparent mutex 215 before the clock signal arrives at the leaf node. It then delays the request at the transparent mutex 215 until the clock edge has reliably arrived at the flip-flop clock input. The high latch does not increase the interface latency because signals that would not be transmitted at the current clock would still have to wait for the next clock edge to be synchronized. Adding the locking latch 375 does not significantly increase the area and energy of the circuit, but it additionally allows T / 2 of the insertion delay, where T is the nominal clock period of the synchronous logic in a clock domain.

[0049] The pausable clock integrates the logic for asynchronous boundary crossings into the clock generation mechanism for the entire synchronous island. This integration imposes constraints on the operating conditions of each of these systems. Previous work on pausable clocks has not fully addressed these constraints. As described below, an in-depth account of the capabilities and limitations of pausable clock timing is presented, which is crucial for designing a realistic system. Expressions for the average latency of the pausable interface are derived, as well as the constraints imposed by the synchronous island on the clock period, insertion delay, and wire delay.In one embodiment, the effects of variation are neglected and circuit delays are treated as fixed values ​​when deriving the timing constraints. Stochastic or worst-case corner analysis can be used to ensure the robustness of the timing, and post-silicon tuning could mitigate the effects of process variation in one embodiment.

[0050] Fig. 4A illustrates timing paths of the in Fig. Figure 2B shows a pausable clock synchronizer 210 according to one embodiment. The significant delays caused by the pausable clock network are described in Figure 2B. Fig. Figure 4A is shown. Table I describes each of the timing variables used in the following analysis. TABLE I. TIMING VARIABLES variable Description T The nominal clock period of the synchronous block T L The average latency of a data word through the interface t ins The insertion delay of the clock signal for the synchronous block t r2 The delay from the output of the C element to the Mutex-r2 input t fb The delay from the Mutex-r2 input through the Mutex and around the feedback path to the Mutex-r1 input t g2 The delay from the mutex-r1 input through the mutex output of the C element t CL The minimum time available to perform a combinational operation on the synchronized request signal before the next clock edge. t m The time allocated to resolve the mutex metastability, which is used to reduce the frequency of clock pauses. t w The wire delay from the border of the synchronous island also includes a local clock generator.

[0051] t r2 is the delay from the output of the C element to the R2 input of the Mutex 215. t fbThe delay from the r2 input through the mutex 215 and the feedback loop to the R1 input is t. g2 The delay from the Mutex 215 R1 input to the output of the Müller C element 205 includes a delay through the AND tree if multiple Mutexes 215 contribute to the timing information. The sum of the three delays cannot exceed the delay of the clock generator, or the clock will frequently pause, increasing the clock period T over the target for the synchronous island, as shown in Fig. 4B shown.

[0052] Fig. Figure 4B illustrates a clock-period-timing constraint of the in Fig.Figure 2B shows a pausable clock synchronizer 210 according to one embodiment. In the worst case, a request arrives shortly before R2 goes high. If the sum of the delays by the pausable circuit is longer than half the clock period T, the next clock edge is delayed, as shown in Figure 2B. Fig. 4B shown.

[0053] Fig. 4C illustrates another clock-period-timing constraint of the one in Fig. Figure 2B shows a pausable clock synchronizer 210 according to one embodiment. If the sum of the delays due to the pausable circuit is shorter than half the clock period T, the clock edge occurs on time.

[0054] Since the clock generator delay is set to T / 2 for a desired clock period T, three delays together enforce a minimum clock period for the synchronous block: T / 2≥tr2+tfb+tg2

[0055] If this clock-period limit is exceeded, the timing dip in the system transforms into a limit t. m , which protects against the effect of pauses in the beat: tm=T / 2−(tr2+tfb+tg2)

[0056] The metastability of Mutex 215 can be described as a temporary increase in t fb This can be seen as being triggered by simultaneously switching inputs R1 and R2. If equation (1) is satisfied (i.e., if T / 2 = t r2 + t fb + t g2 ), then t m = 0, and any mutex metastability that delays the output g2 of the mutex 215 will cause the clock to pause. If t m If the metastability is greater than 0, some metastability can be tolerated before the occurrence of a clock pause. In practice, mutex metastability in one embodiment is a sporadic event, and long clock pauses are rare. Therefore, a carefully considered increase in t can be used. mThis represents a good strategy in favor of other, more critical timing parameters.

[0057] In one embodiment, the low latency of the pausable bisynchronous FIFO 300 depends on the ability of the RX pointer logic to respond immediately to a write pointer update by asserting valid data before the next RX clock edge arrives. Fig. 4D illustrates a setup timing limitation of the in Fig. Figure 2B shows a pausable clock synchronizer 210 according to one embodiment. In one embodiment, the setup timing limit is the worst-case setup time.

[0058] The time available to complete the combinatorial work within the same cycle as a received request is t CLIn the worst-case scenario for the timing path, metastability in the mutex 215 causes a clock pause before the metastability resolves in favor of R1. When g1 switches, a clock edge will be generated as soon as this signal propagates around the feedback loop to the clock generator. Thus, the time t CL , which is available to the logic before this clock edge, only tCL=tfb+tg2

[0059] The parameter t CL is limited by the complexity of the pointer logic; if a sufficiently long time for t CL If the value is not allocated, an additional register should be inserted before the logic to handle communication via pipelines, which increases the interface latency by one cycle. m > 0, increasing t fb by adding the delay to the feedback path the excess t mto increase the time available for the combinatorial work of the same cycle.

[0060] To derive the average latency of the interface, the phase in which the request signal arrives must be considered. If a request signal (e.g., R2) arrives while the mutex 215 is transparent, the request can be served within the same cycle. Assuming that the fully asynchronous request signal arrives with equal probability in each phase, the average latency of such requests is 0.75T - t r2 If the request arrives while the Mutex 215 is opaque, the request cannot be served until the next cycle. The average latency of such requests is 1.25T - t r2 If the working phase of the clock cycle is 50%, taking the average of these two expressions yields the average latency f. L the interface as a whole: tL=T−tr2

[0061] A rising t r2 This reduces the average latency of the interface because it shifts the transparent phase of the Mutex 215 closer to the next clock edge. If t m > 0, increasing t r2 by adding a delay to the R2 input of the Mutex 215, the excess t m to reduce the average latency across the interface. Since t m also for an additional t CL This means that a trade-off can be negotiated between reducing latency and increasing the time available for combinatorial work in the read-pointer logic.

[0062] In real systems, the clock distribution network within the synchronous island will have some insertion delay t. insbetween the generation of the clock edges and their propagation through the clock network to the register endpoints. The insertion delay distorts the transparent phase of the Mutex 215, which can lead to circuit disturbances, as shown in Fig. 5 shown. Fig. Figure 5 illustrates the effect of an insertion delay on the in Fig. Figure 2B shows a pausable clock synchronizer according to one embodiment. Small insertion delays can be avoided by intentionally increasing t. r2 , in order to ins to comply, can be compensated by readjusting the phases and by protecting against metastability. However, the clock-period constraint from (1) limits the increase of t r2 Setting t r2 = t ins provides the restriction regarding the insertion delay that is allowed for a given clock period: tins≤T / 2−tfb−tg2

[0063] As explained previously, a locking latch can be added to the pausable synchronizer circuit shown, as in Fig. Figure 4B shows how to protect against runs caused by large insertion delays. Adding latches marginally increases the area and energy of the circuit, but allows for an additional T / 2 of insertion delay. tins≤T−tfb−tg2

[0064] However, t CL The delay is reduced by the transparent latch, since the asynchronous request must be propagated through the synchronous island, with the local clock generator, as in Fig. 6A is centrally located. This adds a wire delay. w to t r2 and t g2 in addition, which increases the minimum achievable cycle time (from (1)) and decreases the maximum permissible insertion delay (from (5)).

[0065] Fig.Figure 6A illustrates a chip layout 600 according to an embodiment, showing the physical placement of a pausable clock system. The physical location of the logic within the pausable clock synchronizer 210 and / or 370, corresponding to each synchronous island, determines the wire delays in the pausable clock system caused by the wire delay required to traverse each synchronous island. In the chip layout 600, the synchronizer circuitry (i.e., mutex 215, XOR gate, latch(s), and flip-flop) is placed near the boundary of the synchronous island, and the portion of the clock generator (i.e., the Müller C element 205 and the critical path delay line) of the pausable clock synchronizer 210 and / or 370 is placed near the center of the chip.

[0066] Fig.Figure 6B illustrates another chip plan 620 according to an embodiment, showing a physical placement of a pausable clocking system. In the chip plan 620, the synchronizer circuit (i.e., mutex 215, XOR gate, latch(s), and flip-flop) is placed near the center of the chip, and the portion of the clock generator (i.e., the Müller C element 205 and the critical path delay line) of the pausable clock synchronizers 210 and / or 370 is also placed near the center of the chip. Placing the synchronizer circuit near the portion of the clock generator adds w This adds to the system latency, but does not affect the cycle time or insertion delay constraints. w This can be reduced for the 600 and / or 620 chip footprints by using higher metal layers and dedicated routing channels to transmit these critical signals. Even with these considerations, tw For most systems, this will likely be a significant fraction of the clock period and will therefore have a noticeable impact on system performance.

[0067] The Pausable Bisynchronous FIFO 300 provides a low-latency asynchronous interface that integrates well with standard design tools. It combines pausable clocking techniques with standard synchronous two-port FIFOs, easily incorporating them into standard tool flows. In one embodiment, the Pausable Bisynchronous FIFO 300 achieves an average latency of 1.34 cycles while incurring minimal power and area overhead over a synchronous interface. The flow control scheme of the Pausable Bisynchronous FIFO 300 for the read and write pointers uses two-phase increment and acknowledge signals to transfer data through the asynchronous interface.

[0068] The timing constraints imposed by pausable clocking systems include considering the delay required for signals to traverse the distance between the interface and the clock generator circuit. A careful analysis of these system-imposed timing constraints allows for full integration with standard ASIC design tool flows. Therefore, the pausable bisynchronous FIFO 300 is a key foundational technology for fine-grained GALS systems, mitigating many of the challenges of modern SoC design.

[0069] Fig.Figure 7 illustrates an exemplary System 700 in which the various architectures and / or functionalities of the different preceding embodiments can be implemented. As shown, a System 700 is provided that includes at least one central processor 701 connected to a communication bus 702. The communication bus 702 can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol (protocols). The System 700 also includes a main memory 704. The control logic (software) and data are stored in the main memory 704, which can be in the form of random access memory (RAM).

[0070] The system 700 also includes input devices 712, a graphics processor 706, and a display 708, i.e., a conventional CRT (cathode ray tube), an LCD (liquid crystal display), an LED (light-emitting diode), a plasma display, or the like. In one embodiment, a distortion function is defined for the display 708. User input can be received by the input devices 712, e.g., from a keyboard, mouse, touchpad, microphone, or the like. In one embodiment, the graphics processor 706 can comprise a plurality of shader modules, a raster module, etc. Each of the aforementioned modules can even be housed on a single semiconductor platform to form a graphics processing unit (GPU).

[0071] In this description, a single semiconductor platform can refer to a single, unified semiconductor-based integrated circuit or a single, unified semiconductor-based integrated chip. It should be noted that the term "single semiconductor platform" can also refer to multi-chip modules with enhanced connectivity that simulate on-chip operation and offer significant improvements over using a conventional central processing unit (CPU) and a conventional bus implementation. Naturally, the various modules can be placed separately or in various combinations of semiconductor platforms, depending on the user's requirements.

[0072] The System 700 can also include a secondary storage device 710. The secondary storage device 710 includes, for example, a hard disk drive and / or a removable storage device, such as a floppy disk drive, a magnetic tape drive, a CD drive, a DVD drive, a recording device, or Universal Serial Bus (USB) flash memory. The removable storage device reads from and writes to removable storage in a well-known manner. Computer programs or computer control logic algorithms can be stored in the main memory 704 and / or the secondary storage device 710. Such computer programs, when executed, enable the System 700 to perform various functions. The main memory 704, the secondary storage device 710, and / or any other storage device are possible examples of a computer-readable medium.

[0073] In one embodiment, the architecture and / or functionality of the various preceding figures can be implemented in the context of the central processor 701, the graphics processor 706, an integrated circuit (not shown) which has at least some of the capabilities of the central processor 701 and the graphics processor 706, a chipset (i.e., a group of integrated circuits designed to operate and function as a unit for performing appropriate functions, etc.), and / or an integrated circuit designed for this purpose.

[0074] The architecture and / or functionality of the various preceding figures can also be implemented in the context of a general-purpose computer system, a printed circuit board system, a game console system set up for entertainment purposes, an application-specific system, and / or any other desired system. System 700 can be in the form of, for example, a desktop computer, a laptop, a server, a workstation, game consoles, an embedded system, and / or another type of logic. System 700 can also be in the form of various other devices, including, but not limited to, a personal digital assistant (PDA) device, a mobile phone, a television, etc.

[0075] Furthermore, although not shown, the System 700 can be coupled to a network for communication purposes (e.g., a telecommunications network, a local area network (LAN), a wireless network, a wide area network (WAN) such as the Internet, a peer-to-peer network, a cable network, or similar).

[0076] While various embodiments have been described above, it should be understood that these are presented merely as examples and not as limiting. Therefore, the scope and extent of a preferred embodiment should not be limited by any of the exemplary embodiments described above, but should only be defined according to the following claims and their equivalents.

Claims

[1] Method which features: Writing data synchronously with a first clock signal of a first clock domain into an entry of a dual-port memory array; Generating an increment signal in the first clock domain; Determine that the increment signal changes near an edge of a second clock signal, where the second clock signal is a pausable clock signal; Delaying the next edge of the second clock signal of the second clock domain, wherein the next edge of the second clock signal is delayed until the metastability of the increment signal is resolved; and Transferring the increment signal to the second clock domain. [2] The method of claim 1, further comprising: Receiving the increment signal in the second clock domain; and Increasing the value of an approximate writing pointer. [3] The method of claim 2, further comprising: Determining whether the dual-port memory array is full by comparing the value of the approximate write pointer with a value of a read pointer. [4] The method of claim 2, further comprising in response to receiving the increment signal in the second domain: Generating an acknowledgment signal in the second clock domain; and Transmission of the acknowledgment signal to the first clock domain. [5] The method of claim 4, further comprising, before the acknowledgment signal is received in the first clock domain: Writing second data synchronously with the first clock signal of the first clock domain into a second entry of the dual-port memory array; Generating a second increment signal in the first clock domain; and Transferring the second increment signal to the second clock domain. [6] The method of claim 1, further comprising in response to the reception of the increment signal in the second domain: Generating an acknowledgment signal in the second clock domain; Determine that the acknowledgment signal changes near an edge of the first clock signal; Delaying the next edge of the first clock signal of the first clock domain; and Transmission of the acknowledgment signal to the first clock domain. [7] The method of claim 1, further comprising in response to receiving the increment signal in the second domain: Generating an acknowledgment signal in the second clock domain; Determine that the acknowledgment signal changes while the first clock signal is high; and Transmission of the acknowledgment signal to the first clock domain. [8] The method of claim 1, further comprising in response to receiving the increment signal in the second domain: Generating an acknowledgment signal in the second clock domain; Determine that the acknowledgment signal changes while the first clock signal is low; and Transmission of the acknowledgment signal to the first clock domain after the next edge of the first clock signal. [9] The method of claim 1, further comprising: Writing second data synchronously with the first clock signal of the first clock domain to a second entry of the dual-port memory array; Generating a second increment signal in the first clock domain; Determine that the second increment signal changes while the second clock signal is high; and Transferring the second increment signal to the second clock domain. [10] The method of claim 1, further comprising: Writing second data synchronously with the first clock signal of the first clock domain into a second entry of the dual-port memory array; Generating a second increment signal in the first clock domain; Determine that the second increment signal changes while the second clock signal is low; and Transferring the second increment signal to the second clock domain after the next edge of the second clock signal. [11] The method of claim 1, further comprising: Reading the data synchronously with the second clock signal of the second clock domain from the entry of the dual-port memory array; Generating a second increment signal in the second clock domain; and Transferring the second increment signal to the first clock domain. [12] Method according to claim 1, further comprising raising a write pointer in the first clock domain. [13] Method according to claim 1, wherein the first increment signal is connected to the second clock domain by means of a latch coupled to a flip-flop. [14] Method according to claim 13, wherein a second latch is coupled between the latch and the flip-flop. [15] Method according to claim 1, wherein a circuit of the mutual exclusion elements is configured to determine whether the increment signal changes near an edge of the second clock signal. [16] Method according to claim 1, wherein the first clock signal is a pauseable clock signal. [17] Method according to claim 1, wherein the first clock signal is not a pauseable clock signal. [18] System which features: a pauseable bisynchronous First-In First-Out (FIFO) buffer that features: a dual-port FIFO that features a dual-port memory array; A disk-pointer logic coupled to the dual port, configured to: Writing data synchronously with a first clock signal of a first clock domain to an entry of a dual-port memory array; and Generating an increment signal in the first clock domain; a pausable clock synchronizer circuit coupled to the write pointer logic and configured to: Delaying the next edge of a second clock signal of a second clock domain when the increment signal changes near an edge of the second pausable clock signal of the second clock domain, where the second clock signal is a pausable clock signal; and Transferring the increment signal to the second clock domain. [19] System according to claim 18, wherein the pausable clock synchronizer circuit is further configured to delay the next edge of the second clock signal until a metastability of the increment signal is resolved.

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