Semiconductor element and method for manufacturing this

Abstract

Procedure (100; 300), comprising: Providing (110) a machined substrate arrangement (10; 70) comprising a machined semiconductor substrate (12) and a metallization layer structure (14) on a major surface (16) of the machined semiconductor substrate (12), and Release etching (120) from an area of ​​the metallization layer structure (14) towards the processed semiconductor substrate (12) to create a cut (22) in the metallization layer structure (14) at a separation region (25) in the processed semiconductor substrate (12), wherein the separation region (25) defines a boundary between a die region (27; 34a-b) of the processed substrate arrangement (10; 70) and at least a second region of the processed substrate arrangement (10; 70); where the release etching (120) further includes: Exposure of a MEMS functional element (18) arranged on the machined semiconductor substrate (12), wherein the MEMS functional element is a MEMS sensor and / or comprises a silicon material.

Description

Technical field

[0001] The invention relates to semiconductor elements and methods for manufacturing them. The invention further relates to the dual use of a MEMS release etch and a passivation process. Technical background

[0002] The term microelectromechanical system (MEMS) is often used to refer to small integrated devices or systems that combine electrical and mechanical components.

[0003] Microelectromechanical systems (MEMS) can be used, for example, as actuators, transducers, or sensors, such as pressure sensors, loudspeakers, or microphones. Pressure sensors are now mass-produced in automotive and consumer electronics. In many of these application systems, the sensor is integrated into an application-specific integrated circuit (ASIC). MEMS, in particular, are manufactured in high volumes simultaneously on a single wafer. The processing involves separating the microelectromechanical systems from one another.

[0004] DE 10 2007 030 284 A1 relates to the encapsulation of electronic components in wafer composites and describes a method for packaging semiconductor components in which a first wafer is connected to at least one further wafer with a first side

[0005] DE 199 62 431 A1 relates to a method for manufacturing a semiconductor arrangement, wherein in particular a wafer is manufactured with a plurality of chip-forming semiconductor arrangements and the wafer is then cut and the semiconductor arrangements are thereby separated.

[0006] US 2012 / 0241914 A1 describes a method for reducing fluorine contamination of contact surfaces in a metallization system of a semiconductor device.

[0007] US 2014 / 0054730 A1 describes a system and a method for manufacturing a sensor element with a buried first electrode, which includes providing a first silicon area with an electrode layer and a second silicon area with a component layer.

[0008] DE 10 2015 208 689 A1 describes a semiconductor device manufacturing process in which a first trench and a second trench in a semi-finished semiconductor device are etched simultaneously.

[0009] US 2012 / 0175778 A1 describes a manufacturing process for a wafer structure comprising the provision of a substrate with a plurality of chip areas and a perimeter area surrounding the chip areas defined thereon. Brief description

[0010] Exemplary embodiments of the present invention are defined in the independent patent claims.

[0011] Embodiments provide a method in which a machined substrate assembly, comprising a machined semiconductor substrate and a metallization layer structure on a major surface of the machined semiconductor substrate, is provided. A release etch is performed from a surface of the metallization layer structure toward the machined semiconductor substrate to create an incision in the metallization layer structure at a separation region in the machined semiconductor substrate, wherein the separation region defines a boundary between a die region (chip region) of the machined substrate assembly and at least one other region of the machined substrate assembly. The release etch can be used to expose a functional element located on the machined semiconductor substrate.

[0012] Further embodiments provide a method in which a machined substrate arrangement is provided. The machined substrate arrangement comprises a machined semiconductor substrate and a metallization layer structure on a major surface of the machined semiconductor substrate structure, wherein the metallization layer structure includes a cut, the cut in the metallization layer structure being located at a separation region in the machined semiconductor substrate, the separation region defining a boundary between a die region of the machined substrate arrangement and at least a second region of the machined substrate arrangement.The method comprises depositing a passivation layer on a cut surface of the cut, wherein the metallization layer structure further comprises a recess, the recess exposing a MEMS functional element arranged on the machined semiconductor substrate, wherein the MEMS functional element is a MEMS sensor and / or comprises a silicon material.

[0013] The process further includes the deposition of a passivation layer (insulation layer) on a first surface (recess surface) of the recess and a second surface (cut surface) of the cut, such that the passivation layer covers the MEMS functional element, the recess surface and a side wall structure of the recess.

[0014] Further embodiments provide a semiconductor element comprising a machined substrate assembly, which in turn includes a machined semiconductor substrate and a metallization layer assembly. The semiconductor element further comprises a passivation layer arranged at an outer boundary of the machined substrate assembly and a recess (24) in the metallization layer structure (14). The semiconductor element further comprises a functional element arranged in the recess on the machined semiconductor substrate. The MEMS functional element and the sidewall structures of the recess in the metallization layer structure are covered by the passivation layer.The metallization layer structure comprises a cut, wherein the cut in the metallization layer structure is arranged at a separation region in the processed semiconductor substrate, the separation region defining a boundary between a die region of the processed substrate arrangement and at least a second region of the processed substrate arrangement.

[0015] The inventors found that by using two etching or passivation steps, the efficiency of the separation could be increased, so that a wafer yield (i.e., MEMS per wafer) could be high, and so that mechanical defects of the MEMS that occur as a result of the separation could be low. Brief description of the drawings

[0016] Embodiments of the present invention are described here with reference to the accompanying drawings. Fig. Figure 1 shows a schematic flowchart of a process that can be used to manufacture or produce a semiconductor element according to one embodiment; Fig. Figure 2 shows a schematic flowchart of another method, which can be used, for example, to manufacture or produce a semiconductor element, according to one embodiment; Fig. Figure 3 shows a schematic flowchart of a process for manufacturing a semiconductor element, which includes steps of the process described in Fig. 1 and / or Fig. The method described in section 2 comprises, according to one embodiment; Fig. Figure 4a shows a schematic cross-sectional view of a machined substrate arrangement according to one embodiment; Fig. Figure 4b shows a schematic cross-sectional view of the processed substrate arrangement of Fig. 4a, comprising a cut and a recess formed in the processed substrate arrangement, according to one embodiment; Fig. Figure 4c shows a schematic cross-sectional view of the machined substrate arrangement after a passivation layer has been applied to the recess and the incision, according to one embodiment; Fig. 5 shows a schematic top view of the machined substrate arrangement, which is a wafer, according to one embodiment; Fig. Figure 6 shows a schematic cross-sectional view of the machined substrate arrangement after a step has been performed which includes separating the die area from a second area of ​​the machined substrate arrangement, according to one embodiment; Fig. Figure 7 shows a schematic cross-sectional view of a machined substrate arrangement comprising the metallization layer structure, which includes a plurality of layers, according to one embodiment, and Fig. Figure 8 shows a schematic cross-sectional view of the processed substrate arrangement of Fig. 7, after an insulating layer has been arranged on surfaces of the metallization layer structure, according to one embodiment. Detailed description of the embodiments

[0017] Before embodiments of the present invention are described in detail with reference to the accompanying figures, it should be noted that the same or functionally equivalent elements have been provided with the same reference numerals in the figures, and that repeated descriptions of elements with the same or similar reference numerals are generally omitted. Therefore, descriptions provided for elements with the same reference numerals are mutually interchangeable and applicable.

[0018] MEMS can be manufactured using silicon technology. MEMS can be designed to operate as sensors, actuators, and / or transducers and may optionally include at least one functional element, such as a diaphragm, a temperature element, or other components that are connected to a physical, chemical, and / or electrical medium. For example, a pressure sensor may include a diaphragm connected to a medium in which the pressure is to be measured. Microphones or loudspeakers may include a diaphragm to detect or excite sound waves. Alternatively or additionally, a temperature probe may be exposed and connected to a medium in which the temperature is to be measured.

[0019] Some MEMS that include such a functional element can be arranged or attached to a semiconductor substrate. For example, the semiconductor substrate can be a locally doped or undoped silicon substrate, but it can also include other materials, such as gallium arsenide (GaAs). To operate the MEMS, and therefore the functional element, a metallization layer structure can be arranged on the processed semiconductor substrate to receive, process, and / or transmit electrical signals to or from the functional element—that is, to operate the functional element.

[0020] For example, the optional functional element can be placed or created on the semiconductor substrate during machining. Other electrical and / or mechanical components can be machined in or on the semiconductor substrate to create a machined semiconductor substrate. The machined semiconductor substrate can be covered with a variety of layers, including semiconductor materials, insulating materials, and / or metallic materials.

[0021] The processing of the semiconductor substrate and / or the arrangement of the metallization layer structure can be referred to as a back-end-of-line (BEOL) process. The BEOL process can be performed, for example, after a front-end-of-line (FEOL) process, during which the semiconductor substrate can be structured to create devices or elements such as transistors, capacitors, resistors, or the like within the semiconductor substrate.

[0022] Typically, a large number of semiconductor devices are simultaneously manufactured or produced on a wafer. After the production or manufacturing of these numerous semiconductor devices (chips), they are separated from one another, a process also known as die forming (dicing). Dicing can be performed, for example, by etching, cutting, and / or fracturing (cracking) the wafer into pieces to separate (individualize) the individual components.

[0023] Wafer breakage can lead to cracks in BEOL layers, which can result in rejects during manufacturing, a shortened product lifespan, or operational drift because media can impair the facultative functional element through the cracks.

[0024] Fig. Figure 1 shows a schematic flowchart of a process 100 that can be used to manufacture or produce a semiconductor element.

[0025] Method 100 comprises providing a machined substrate array in step 110 of Method 100. The machined semiconductor substrate comprises a machined semiconductor substrate and a metallization layer structure on a major surface of the machined semiconductor substrate. The metallization layer structure can comprise multiple layers, one or more of which may be a metallic material, such as gold, platinum, copper, silver, tungsten, aluminum, other materials, and / or a combination thereof. The metallization layer structure can be placed on the major surface of the machined semiconductor substrate, for example, during a BEOL process.

[0026] Method 100 further comprises a step 120, which includes a release etch. The release etch can be performed from an area of ​​the metallization layer structure towards the processed semiconductor substrate, creating a cut in the metallization layer structure at a separation region in the processed semiconductor substrate. The separation region can define a boundary between a die region of the processed substrate array and at least one other region (e.g., other chip regions or the like) of the processed substrate array.

[0027] Furthermore, release etching can also be carried out from the surface of the metallization layer structure towards the processed semiconductor substrate in such a way that an optional functional element located on the processed semiconductor substrate is exposed.

[0028] Release etching can be performed, for example, using a dry or wet etching process designed to selectively remove the metallization layer structure at an area of ​​an optional recess (trench) etched towards the optional functional element and at a cut area. The cut area can be positioned to partially or substantially overlap the separation area. The separation area can be, for example, a predefined fracture line, a predefined saw line, or a predefined etch line from which the die area can be separated in subsequent steps. The cut area can therefore be referred to as a dicing street, which refers to a linear structure (cut) in the metallization layer structure. In simpler terms, by forming the cut area, the metallization layer structure is at least partially removed at the separation area.In summary, release etching can be a BEOL etching step to expose the dicing areas of the wafer, thus facilitating the implementation of the subsequent dicing step.

[0029] The optional recess and the incision can be formed by a trenching process, such as a dry etching process, a wet etching process, or a physical or chemical etching process. Therefore, both the incision and the optional recess can be described as a trench, but for clarity, they are referred to as incision and recess.

[0030] Method 100 further comprises an optional step 130. Step 130 involves depositing a passivation layer on a first surface (recess surface) of the optional recess (which exposes the optional functional element) in the metallization layer structure and on a second surface (cut surface) of the cut. The first surface can be achieved, at least partially, during the release etching to expose the functional element, i.e., during the formation of the recess. The second surface can, for example, be achieved, at least partially, by creating the cut.The requirement that the first and second surfaces should be at least partially achieved can be understood to mean that there may be additional steps between step 120 and step 130, for example, to extend (enlarge) the recess and the incision, so that the position and / or size of the surfaces in the metallization layer structure and / or the processed semiconductor substrate can be modified by this additional step. The passivation layer can be deposited on the first and second surfaces achieved after step 120 or after the additional steps. The first surface can comprise one or more sidewall structures of the recess in the metallization layer structure and / or a surface of the functional element defined by the recess.The second surface can comprise one or more sidewall structures of the incision in the metallization layer structure and / or a (lower) surface thereof or of the processed semiconductor substrate. Release etching can be used to create the incision.

[0031] Optionally, the recess and the cutout can be etched simultaneously during the 120 release etch. In simpler terms, the release etch, which can be used to expose the functional element, can be used twice to create the cutout. This dual use of the release etch allows for high process efficiency with little or no additional time or cost.

[0032] The incision allows for increased efficiency during the separation of the die, as the metallization layer structure (arrangement) at the separation area is removed, thus preventing the metallization layer structure from suffering damage (e.g., cracking) during sawing or breaking of the processed semiconductor substrate.

[0033] Fig. Figure 2 shows a schematic flowchart of a process 200, which can be used, for example, to fabricate or manufacture a semiconductor device. The process 200 includes an optional step 210. Step 210 involves etching from an area of ​​the metallization layer structure towards the processed semiconductor substrate to create a cut in the metallization layer structure at a separation region. Step 210 may also include etching from an area of ​​the metallization layer structure towards the processed semiconductor substrate to expose the optional functional element by creating the recess in the metallization layer structure. Step 210 may be identical or substantially the same as step 120.

[0034] Method 220 comprises a step 220, which includes the provision of a machined substrate assembly. The machined substrate assembly comprises a machined semiconductor substrate and a metallization layer structure on a major surface of the machined semiconductor substrate. The metallization layer structure may include an optional recess and a notch, wherein the optional recess exposes an optional functional feature located on the machined semiconductor substrate. The notch is located in the metallization layer structure at a discontinuity region in the machined semiconductor substrate. The recess and / or the notch may be achieved, for example, by step 210 or other processes. The discontinuity region may define a boundary between a die region of the machined substrate assembly and at least one other region of the machined substrate assembly.For example, step 220 may involve providing an etched and machined semiconductor substrate obtained by performing step 120 or step 210.

[0035] The process 200 comprises a step 230 in which a passivation layer is deposited on a first surface (recess surface) of the recess and a second surface (cut surface) of the cut. Step 230 may be the same as or substantially the same as step 130.

[0036] The passivation layer can comprise a passivation or sealing ring material, such as silicon oxide, silicon nitride, or other materials. Passivating the surfaces of the recess and the cut achieves passivation of the metallization layer structure and, in particular, protects its layers. Furthermore, it can prevent short circuits or similar issues between layers of the metallization layer structure. Alternatively or additionally, the passivation layer applied to the surface of the cut provides a high level of protection for the device during the separation of the die from other areas of the wafer (the processed substrate array). The cut can at least partially define a separation path (fracture line) of the metallization layer structure when the processed semiconductor substrate is separated, e.g., sawn or broken.

[0037] The cut and the notch can be the cut and the notch achieved during the execution of process 100. Therefore, the cut can facilitate simplified separation of the die and can alternatively or additionally enable a reduced and / or controlled distribution or propagation of cracks resulting from the separation. In particular, the cut can hinder crack propagation when the processed semiconductor substrate is fractured, cut, or divided. By providing the cut in the metallization layer structure that is aligned with a separation area (dicing path) of the processed semiconductor substrate, cracks propagating through the material (BEOL material) due to the separation (e.g., dicing) can, in simplified terms, be avoided or at least reduced.Furthermore, the protection of the metallization layer structure achieved by the passivation layer can include, but is not limited to, high resistance to aggressive chemical media. Aggressive or corrosive media can include, for example, acids or bases and / or methane-based materials, e.g., diiodomethane.

[0038] For example, the robustness of silicon nitride used as a passivation layer material can be increased compared to an array of sealing rings around the die if the semiconductor device is designed for contact with diiodomethane. Diiodomethane can attack metal-based sealing rings, while silicon nitride is affected to a lesser degree or not at all by such a medium. Thus, the robustness, and therefore the lifetime and precision, of the semiconductor device can be high. Passivation of the recess surfaces can be performed sequentially or simultaneously, i.e., during the passivation step. Such dual use of the passivation step can enable high robustness with little or no additional time or cost.

[0039] Steps of processes 100 and 200 can be combined and / or mutually substituted for one another. In particular, process 100 can include a step in which the passivation layer is applied and / or process 200 can include a step in which the incision is created.

[0040] Fig. Figure 3 shows a schematic flowchart of a process 300 for fabricating a semiconductor device. The process 300 includes an optional step 340 in which a predefined fracture line is defined in the separation region. For example, a machined or an unmachined wafer can be provided. Between regions of the wafer where functionality of the semiconductor device will be implemented (machined) at least partially during later steps, the separation region can be implemented by defining boundaries between different die areas. This can, for example, involve an etching process to remove material from the wafer in the separation region to achieve a predefined fracture line in the separation region. A predefined fracture line can enable precise breaking (separation) of the subsequent dies.

[0041] Alternatively, a so-called stealth dicing process can be used to implement the predefined fracture line in the separation region. During a stealth dicing process, a laser can be used to cut a semiconductor material, for example, the wafer, into pieces (die regions) through internal treatment. The stealth dicing process can involve using a laser beam with a wavelength that is transparent to the semiconductor material. The laser beam can be focused by an objective lens onto a point within the semiconductor layer. The laser beam can be guided in such a way that it is rasterized along a dicing line (a predefined fracture line) and / or along the separation region.An optical system can provide high focusing power, capable of collecting light up to the diffraction limit, allowing the short-pulsed laser beam to be focused temporally and spatially at a high repetition rate onto a highly localized area near the focal point to deliver a high peak power density. The laser beam, which is transparent to the semiconductor substrate, can begin to exhibit high absorption at a localized point when the peak power density exceeds a certain threshold in the light-collecting process. The characteristics of the optical system and the laser can control this threshold so that it is only exceeded near the focal point within the semiconductor wafer. The laser beam can selectively process only specific localized points without damaging the surface and back surfaces of the semiconductor substrate.In simpler terms, a buried (hidden, stealthy) predetermined fracture line can be created in the semiconductor substrate. This predetermined fracture line can be achieved by applying a laser beam from a first principal surface (e.g., a front surface) and / or from a second principal surface (e.g., a back surface) of the semiconductor substrate.

[0042] Pre-treating the specified fracture line, e.g. by performing step 340, can enable a reduced damage and / or crack extent compared to a separation process in which the dies are separated by breaking and in which the breaking is carried out at the cut without such pre-treatment.

[0043] The process 300 includes a step 310 during which a front-end-of-line process is carried out to process a major area of ​​a semiconductor substrate in order to obtain the processed semiconductor substrate.

[0044] In step 320 of process 300, a back-end-of-line process is performed to create the metallization layer structure on the main surface of the processed semiconductor substrate.

[0045] Procedure 100 or procedure 200 are carried out at step 330 of procedure 300.

[0046] In step 350 of process 300, the die region is separated from the second region (e.g., another die) of the processed substrate array by breaking the processed substrate array at the separation region. The efficiency of step 350 can be high if step 340 is performed before step 350, for example, after step 330. Step 340 can also be performed before step 310 or 320, for example, if a region of the processed semiconductor substrate can be processed (e.g., if the region is exposed). For example, the laser beam can be guided through the incision after the incision has been prepared or etched.

[0047] Fig. Figure 4a shows a schematic cross-sectional view of a machined substrate assembly 10, comprising a machined semiconductor substrate 12 and a metallization layer structure 14 arranged on a major surface 16 of the machined semiconductor substrate 12. The major surface can, for example, be a side of the wafer that covers a large or even the largest area. For example, but without limitation, this can be a front or a back face of a wafer having a cylindrical shape, with a side face located between the two major surfaces (i.e., the front and back faces). The major surface 16 can be the surface that includes structures incorporated into the machined semiconductor substrate 12, such as transistors, resistors, and / or capacitors.

[0048] A functional element 18 is optionally arranged on the processed semiconductor substrate 12. The processed substrate arrangement 10 can, for example, be provided in step 110. The processed semiconductor substrate 12 can encompass the predefined fracture line 32, for example, in a separation region 25, and can be obtained during step 340.

[0049] Fig. Figure 4b shows a schematic cross-sectional view of the machined substrate arrangement 10, compared to the one in Fig. In the processed substrate arrangement 10 shown in Figure 4a, a cut 22 and an optional recess 24 were formed in the processed substrate arrangement 10 and at the separation region 25, for example by carrying out step 120 or 210. The separation region 25 can surround a die region 27 and form a boundary between the die region 27 and other sections or regions 29 of the processed substrate arrangement 10.

[0050] The optional functional element 18 is exposed at least on one side (e.g., the upper side) of the metallization layer structure 14 and in relation to a surrounding medium of the processed substrate arrangement 10. That is, the optional functional element 18 can be in contact with the medium. Alternatively, the recess can leave the functional element at least partially covered.

[0051] Although the incision 22 is depicted as etching through the entire metallization layer structure 14 (i.e., extending down to the processed semiconductor substrate 12), the incision 22 can be designed such that one or more of the metallization layer structure 14 remain attached to or within the incision 22. Alternatively, the incision 22 can be designed such that it extends into the semiconductor substrate 12.

[0052] Fig. Figure 4c shows a schematic cross-sectional view of the machined substrate arrangement 10 after a passivation layer 26 has been applied to the optional recess 24 and the incision 22. The passivation layer 26 can cover (or be applied to) an area of ​​the metallization layer structure 14 defined (opened) by the incision 22 and / or the optional recess 24. The passivation layer 26 can also cover the bottom of the incision 22 and / or the optional recess 24. The bottom (where "bottom" is understood simply as one end of the incision in the machined semiconductor substrate) of the incision 22 can be the machined semiconductor substrate 12 or a layer of the metallization layer structure 14.If, for example, the depth of the incision 22 is less than the thickness of the metallization layer structure 14 along a thickness direction 28, one or more layers of the metallization layer structure may remain in the separation area. The thickness direction 28 may be parallel to a surface normal of the machined semiconductor substrate 12. The passivation layer 26 may be arranged on almost all or all of the surfaces of the machined substrate assembly 10, such that the passivation layer is located at the incision 22, at the recess 24, and at least partially on other surfaces of the machined substrate assembly. Alternatively, the passivation layer 26 may optionally be located, for example, on sidewall structures of the incision 22 and / or the recess 24, whereby sections of the remaining surface(s) of the machined substrate assembly may remain uncovered by the passivation layer 26.

[0053] The thickness of the processed substrate array can be, for example, at least 5 µm and at most 1000 µm, at least 10 µm and at most 400 µm, or at least 20 µm and at most 300 µm. The thickness of the processed semiconductor substrate can be, for example, at least 2 µm and at most 1000 µm, at least 5 µm and at most 800 µm, or at least 100 µm and at most 500 µm, for example, between 200 µm and 300 µm. The thickness of the metallization layer structure (BEOL) can be, for example, at least 100 nm and at most 100 µm, at least 1 µm and at most 10 µm, or at least 4 µm and at most 6 µm, such as 5 µm. The fracture line can have a lateral extent of, for example, at least 1 µm and at most 200 µm, at least 5 µm and at most 100 µm, or at least 10 µm and at most 60 µm.Therefore, the fracture line 32 can encompass a greater lateral extent along a direction perpendicular to the thickness direction 28 when compared with a lateral extent of the cut 22 along the same direction.

[0054] Although the passivation layer 26 is shown to be arranged on or at the optional functional element 18, the functional element 18 can remain uncovered by the passivation layer 26. Alternatively, the passivation layer can be removed, for example, in a subsequent processing step.

[0055] Although the passivation layer 26 is depicted as covering the processed semiconductor substrate 12 in the incision 22, the processed semiconductor substrate 12 in the incision 22 can remain uncovered by the passivation layer 26. Alternatively, the passivation layer can be removed, for example, in a subsequent processing step. In simplified terms, at least the sidewalls (sidewall structure) of the incision 22 and the optional recess 24 are covered by the passivation layer 26.

[0056] The machined semiconductor substrate 12 includes, for example, the predefined fracture line 32, which can be achieved by performing step 340. Although the machined semiconductor substrate 12 is described as including the fracture line 32 before the formation of the incision 22 and the recess 24, the fracture line 32 can also be achieved during a process performed before separating the region 27 from other regions 29. For example, the incision 22 can be formed first, and then step 340 can be performed, e.g., using stealth dicing. The predefined fracture line 32 can be placed in the separation region 25 and in the machined semiconductor substrate 12 before the passivation layer 26 is applied, for example, after etching the incision 22 and / or before arranging or providing the machined substrate assembly 10. In simplified terms, the fracture line 32 can be applied to the surface of the substrate 12 before the incision 22 is formed. Fig. 4a or Fig. The modified substrate arrangement 10 shown in 4b can be implemented without encompassing the specified fracture line 32.

[0057] The incision 22 can have a width of at most 100 µm, 50 µm, or 30 µm along a lateral direction perpendicular to the thickness direction 28. For example, the incision can have a width of 16 µm (e.g., between 10 and 20 µm). The passivation layer 26 is then applied, and the passivation layer 26 can have a thickness between 10 and 200 nm, between 20 and 100 nm, or between 40 and 60 nm, and can have a thickness of approximately 50 nm. The passivation layer 26 can have other extensions along the thickness direction 28, for example, at least 1 nm, at least 1 µm, or at least 50 µm. The recess 24 can have a width along the direction perpendicular to the thickness direction 28, which depends on the extent of the functional element 18 along that direction and can be, for example, between 10 µm and 2000 µm, between 20 µm and 1000 µm or between 30 µm and 800 µm.When viewed from a direction perpendicular to the side view (e.g. in a top or bottom view), the recess can, for example, have an extent of 30 x 500 µm. 2 The stress decoupling trenches can be arranged adjacent to the recess 28, for example between the recess 28 and the cut 22. The stress decoupling trenches can have a width along the lateral direction perpendicular to the thickness direction 28, which can be, for example, at least 1 µm and at most 100 µm, at least 3 µm and at most 50 µm, or at least 5 µm and at most 10 µm, such as 8 µm.

[0058] Fig. Figure 5 shows a schematic top view of the processed substrate assembly 10, where the processed substrate assembly 10 is, for example, a wafer. The predefined fracture line 32 is located on the wafer and can define a plurality of die regions 34ab, which are separated by discontinuities encompassing the predefined fracture line 32. The discontinuities surround the die regions 34a-b and form a boundary between them.

[0059] Fig. Figure 6 shows a schematic cross-sectional view of the processed substrate assembly 10 after step 350 has been performed. The passivation layer 26 is arranged on a surface of the metallization layer structure 14, which is defined (opened) by the incisions 22a and 22b and the recess 24. The protective layer 26 arranged on the metallization layer structure 14 provides protection and / or insulation for the metallization layer structure 14.

[0060] As in Fig. As shown in Figure 6 as an example, the passivation layer 26 can optionally be arranged, for example, on side wall structures of the incision 22 and / or the optional recess 24, whereby sections of the remaining area(s) of the processed substrate arrangement may remain uncovered by the passivation layer 26.

[0061] Alternatively, the passivation layer 26 can be arranged on additional surfaces, e.g. on the functional element 18, or on almost all or all of the surfaces of the processed substrate arrangement 10, so that the passivation layer is arranged at the incision 22, at the optional recess 24 and at least partially on other surfaces of the processed substrate arrangement (see, for example, Fig. 4c).

[0062] The processed semiconductor substrate 12 can include one or more fracture edges 33a-b in the separation region and in a region where the cut was located. The fracture edges 33a-b can extend to the passivation layer 26, for example, if the passivation layer 26 is located at the bottom of the cut, as described above. The passivation layer 26 enables a low or at least a controlled propagation of cracks that may occur when the processed semiconductor substrate 12 is fractured. This can help overcome cracking problems when stealth dicing processes designed to prepare for fracture separation are used.

[0063] In other words, the discontinuity zone can surround the corresponding die area 34a-b. In the absence of the predefined fault line 32, the discontinuity zone continues to surround die areas 34a-b and form a boundary around them.

[0064] Fig. Figure 7 shows a schematic cross-sectional view of a machined substrate arrangement 70, comprising the machined semiconductor substrate 12 and the metallization layer structure 14. The incision 22 is arranged such that it completely separates the metallization layer structure at the separation region 25. The predetermined fracture line 32 is located at the total separation region 25, but it can alternatively extend beyond the separation region 25 or be located only partially within the separation region 25.

[0065] The incision 22 and the recess 24 are etched such that they form a conical shape, i.e., an extension along a lateral direction 34 perpendicular to the thickness direction 28 can vary along the thickness direction 28. This can also be described as the incision 22 having a taper (an angle). The taper can have an angle of at least 30°, at least 60°, or at least 80°, such as 84°. For example, the metallization layer structure 14 can have a thickness of 5 µm. On the processed semiconductor substrate 12, the incision 22 can have a width (e.g. 16 µm) that is reduced by approximately 500 nm per edge (for example, and without restriction: left and right e.g. to 15 µm) compared with a width of the incision 22 on a surface of the metallization layer structure 14 that is facing away from the processed semiconductor substrate 12.The extent along the lateral direction 34 can decrease towards the processed semiconductor substrate 12, but it can also increase or remain constant. Assuming an example taper of 84° and a BEOL height of approximately 5 µm, the lower dimension of the incision 22 is therefore approximately 500 nm / edge smaller than the upper dimension. Assuming an incision 22 with an upper width of 16 µm, the incision thus has a lower dimension of approximately 15 µm.

[0066] The processed substrate arrangement 70 can be achieved, for example, by performing one of steps 120, 210 or 220.

[0067] The incision 22 can be achieved by release etching, whereby the incision can define a so-called stealth dicing path, whereby the release etching can stop, for example, on a last FEOL module, i.e., an FEOL layer adjacent to the processed substrate layer 12.

[0068] The recess 24 can be etched simultaneously with the incision 22, whereby the etching process can be stopped on the functional element 18, for example a MEMS sensor.

[0069] The processed substrate arrangement 70 includes a sealing ring 36, which comprises, for example, a metallic material such as copper, extending through one, several, or even all of the layers of the metallization layer structure 14. The sealing ring 36 is designed to protect the metallization layer structure 14, which is located between the sealing ring 36 and the recess 24, but it can be affected, for example, by moisture or an aggressive environment upon contact. Contact can occur, for example, through cracks resulting from separation by breaking.

[0070] Without passivation at the cut, the sealing ring 36 can corrode because moisture, especially in pre-molded packages, penetrates the oxide layers and reaches the metal. Besides this obvious reliability issue, corrosion can also cause stress and lead to sensor drift. This can be prevented by the passivation described above, which uses, for example, silicon nitride (SiN), a proven moisture barrier. In simplified terms, MEMS release etching is applied to both the MEMS area and the dicing area. MEMS passivation is applied to the entire wafer, making it effective on both the MEMS device and the sidewall of the BEOL (the metallization layer structure) at the chip edge.This can be achieved without additional manufacturing costs, without changing the integration plan of the resulting semiconductor element, and without reducing the chip area. It enables improved crack propagation, especially when using stealth dicing, while reducing the dicing path dimension (division path dimension). Furthermore, it improves the robustness of the BEOL to media because the BEOL sidewall is protected by the passivation nitride. Reduced moisture drift can also be achieved.

[0071] The metallization layer structure 14 can be covered with a resistive layer 38, which comprises, for example, a polymer material or any other suitable material. The metallization layer structure 14 can comprise a plurality of insulating layers 42a-h, separated from one another by a plurality of layers 44a-i. The recess 24 partially exposes the functional element 18. The insulating layers 42a-h can, for example, comprise a silicon oxide material. The layers 44a-i can, for example, comprise a silicon nitride material. The functional element 18 can, for example, comprise a silicon material. The layer structure can comprise fewer or more layers. The insulating layers can have a thickness (extent along the thickness direction) of, for example, at least 1 nm and at most 2000 nm, at least 5 nm and at most 1500 nm, or at least 10 nm and at most 1000 nm.

[0072] The metallization layer structure further includes an optional sealing ring 36, which may comprise a metal material. The sealing ring may surround a region of the functional element 18. Although the sealing ring 36 is shown to be arranged with respect to only some of the layers of the metallization layer structure, it may also be arranged with respect to other or even all of the layers. The sealing ring may have a thickness between 5 and 20 µm or between 7 and 11 µm and may comprise a thickness of approximately 9 µm.

[0073] In Fig. Figure 7 shows a marking indicating the different materials used as examples for the various structures and elements of the processed substrate arrangement 70. The marking is merely an example; other materials with comparable functionality can be used alternatively.

[0074] Fig. Figure 8 shows a schematic cross-sectional view of the machined substrate assembly 70 after the insulating layer 26 has been applied to surfaces of the metallization layer structure 14, defined by the notch 22 and the recess 24, and to the functional element 18. This allows for improved crack propagation when the machined semiconductor substrate 12 is fractured at the discontinuity area 24, and provides a protected die edge defined by the notch 22. The passivation layer 26 further protects the metallization layer 14 at the recess 25 (its sidewall) and the functional element 18. Fracture of the machined substrate assembly at the notch 22 can result in a structure as described above. Fig. 6 enable.

[0075] The passivation layer 26 can be applied (produced) simultaneously at the incision 22 and the recess 24. This allows for reduced time and / or costs; for example, the additional effort compared to applying the insulation layer 26 at the recess 24 can be zero or almost zero if the passivation layer 26 is deposited simultaneously at the incision 22.

[0076] In other words, an integrated pressure sensor can be fabricated using stealth dicing as a separation technique and a thin terminal SiN passivation layer in the sensor area. Stealth dicing (SD) can be a preferred separation process because it requires only a narrow incision and can therefore save wafer area. Furthermore, it prevents the use of separation fluid or small particles that could contaminate the sensor membrane. The embodiments described above overcome uncontrolled breakage in BEOL layers, which can be a major risk for many technologies because it is critical for the FEOL and BEOL stacks within the incision.

[0077] Films, such as HDP oxides (HDP = high-density plasma) with high layer strain, which are incorporated into sensor processes, can actually increase SD-induced delamination, leading to a severe yield loss. This severe yield loss can be reduced or even eliminated by implementing the embodiments described above. Furthermore, these embodiments enable greater robustness of sensors that can be installed in pressure sensing applications in harsh environments. In harsh environments, ordinary pads and metal O-rings on chip edges can provide inadequate protection, whereas the passivation layer protection described above makes such applications possible.

[0078] In the embodiments described above, a dual use of processes for etching (etching the cut and the notch) and passivation (of the edges of the cut and the notch) has been described. MEMS release etching can be used to at least partially or even completely remove the BEOL insulating dielectric layer stack (ILD stack; ILD = insulating dielectric layer) in the chip parting area (dicing section, parting zone), and can therefore guide the crack line (or saw line in conventional sawing) more precisely and thus prevent uncontrolled cracking. Dicing can be effective for separating only the substrate (processed semiconductor substrate), regardless of the method used.

[0079] Therefore, the dimensions of the dicing section can be reduced, which directly impacts the yield (chips per wafer).

[0080] Furthermore, the thin MEMS passivation layer deposited after MEMS release etching does not affect chip separation, but can itself seal the outer BEOL stack and therefore improve the media robustness of the etched die. This can be essential for pressure sensing applications in harsh environments, especially when robustness against diiodomethane is required and a conventional (copper) sealing ring might not provide sufficient protection for the chip.

[0081] Uncontrolled cracking during stealth dicing can be overcome using the embodiments described above. These embodiments employ MEMS release etching to remove the ILD in the SD area, thereby improving SD yield. Additionally, a thin MEMS passivation can be used to seal the edge, preventing moisture absorption and metal corrosion of the protective ring. Therefore, the embodiments described above can be considered a combination of MEMS release etching and MEMS passivation for application in a MEMS area and a dicing section (chip edge) for improved chip separation yield, MEMS quality, and chip edge sealing. This can also be viewed as a dual application of MEMS release etching and passivation.

[0082] Although some aspects have been described in relation to a device, it is evident that these aspects also represent a description of the corresponding process, where a block or device corresponds to a process step or a feature of a process step. Likewise, aspects described in relation to a process step also represent a description of a corresponding block, element, or feature of a corresponding device.

[0083] The embodiments described above are merely an illustration of the principles of the present invention. It is understood that modifications and variations of the arrangements and details described herein will be obvious to a person skilled in the art. Therefore, it is intended that any limitation is defined solely by the scope of the preceding claims and not by the specific details presented here as a description and explanation of the embodiments.

Claims

[1] Procedure (100; 300), comprising: Providing (110) a machined substrate arrangement (10; 70) comprising a machined semiconductor substrate (12) and a metallization layer structure (14) on a major surface (16) of the machined semiconductor substrate (12), and Release etching (120) from an area of ​​the metallization layer structure (14) towards the processed semiconductor substrate (12) to create a cut (22) in the metallization layer structure (14) at a separation region (25) in the processed semiconductor substrate (12), wherein the separation region (25) defines a boundary between a die region (27; 34a-b) of the processed substrate arrangement (10; 70) and at least a second region of the processed substrate arrangement (10; 70); where the release etching (120) further includes: Exposure of a MEMS functional element (18) arranged on the machined semiconductor substrate (12), wherein the MEMS functional element is a MEMS sensor and / or comprises a silicon material. [2] Method according to claim 1, wherein the metallization layer structure (14) comprises a plurality of layers, wherein at least one of the plurality of layers comprises a metal material, wherein the release etching is carried out such that the cut (22) separates the metal material at the separation area (25). [3] Method according to claim 1 or 2, wherein during a time interval of the release etching, the exposure of the MEMS functional element (18) and the etching of the cut (22) are carried out simultaneously. [4] Method according to any one of claims 1 to 3, wherein the separation region (25) surrounds the die region (27, 34a-b) and forms the boundary around the die region (27, 34a-b). [5] Method according to any one of claims 1 to 4, further comprising: Deposition (130) of a passivation layer (26) at a recess surface of a recess (24) in the metallization layer structure (14) and at a cut surface of the cut (22), wherein the recess surface is obtained at least partially during the release etching (120) to expose the MEMS functional element (18) and the cut surface is obtained at least partially by generating the cut (22). [6] Method according to claim 5, wherein the deposition (130) of the passivation layer (26) comprises the deposition of an insulating material comprising a silicon nitride material. [7] Method according to claim 5 or 6, wherein the passivation layer (26) is deposited such that the MEMS functional element (18) and side wall structures of the recess (24) in the metallization layer structure (14) are covered by the passivation layer (26), wherein the recess (24) is obtained by exposing the MEMS functional element (18). [8] Method according to one of claims 5 to 7, wherein during a time interval of deposition (130) the passivation layer (26) is deposited simultaneously at the incision (22) and at the recess (24). [9] Method according to any one of claims 1 to 8, wherein providing (110) the processed substrate arrangement (10; 70) comprises: Performing (310) a front-end-of-line process to process a major area region of a semiconductor substrate to obtain the processed semiconductor substrate (12), and Performing (320) a back-end-of-line process to generate the metallization layer structure (14) on the main surface (16) of the processed semiconductor substrate (12). [10] Method according to claim 9, further comprising defining (340) a predetermined fracture line (32) in the separation area (25). [11] Method according to claim 10, wherein the predetermined fracture line (32) is defined by a stealth dicing process. [12] Method according to any one of claims 1 to 11, further comprising: Separating (350) the die area (27; 34a-b) from the second area (29) of the processed substrate arrangement (10; 70) by breaking the processed substrate arrangement (10; 70) at the separation area (25). [13] Procedure (200; 300), comprising: Providing (220) a machined substrate arrangement (10; 70) comprising a machined semiconductor substrate (12) and a metallization layer structure (14) on a major surface (16) of the machined semiconductor substrate (12), wherein the metallization layer structure (14) comprises a cut (22), the cut (22) in the metallization layer structure (14) being arranged at a separation region (25) in the machined semiconductor substrate (12), the separation region (25) defining a boundary between a die region (27; 34a-b) of the machined substrate arrangement (10; 70) and at least a second region (29) of the machined substrate arrangement (10; 70), and Deposition (230) of a passivation layer (26) on a cut surface of the cut (22); wherein the metallization layer structure (14) further comprises a recess (24) wherein the recess (24) exposes a MEMS functional element (18) arranged on the machined semiconductor substrate (12), wherein the MEMS functional element is a MEMS sensor and / or comprises a silicon material, wherein the method further comprises: Deposition (230) of a passivation layer (26) on a recess surface of the recess (24); so that the passivation layer covers the MEMS functional element (18), the recess area and a side wall structure of the recess. [14] Method according to claim 13, wherein during a time interval of deposition (230) the passivation layer (26) is deposited simultaneously at the incision (22) and at the recess (24). [15] Method according to claim 13 or 14, wherein providing the processed substrate arrangement (10; 70) comprises: Release etching (210) from an area of ​​the metallization layer structure (14) to the processed semiconductor substrate (12) to expose the MEMS functional element (18) by creating the recess (24) and to create the cut (22) in the metallization layer structure (14) at the separation area (25). [16] Method according to claim 15, wherein during a time interval of the release etching (210) the MEMS functional element (18) is exposed and the cut (22) is etched simultaneously. [17] Method according to any one of claims 13 to 16, wherein the deposition (230) of the passivation layer (26) comprises the deposition of an insulating material comprising a silicon nitride material. [18] Method according to any one of claims 13 to 17, wherein the passivation layer (26) is deposited such that the MEMS functional element (18) and the side wall structures of the recess (24) in the metallization layer structure (14) are covered by the passivation layer (26). [19] Method according to any one of claims 13 to 18, wherein providing (220) the processed semiconductor substrate (12) comprises: Performing (310) a front-end-of-line process to process an area of ​​a main surface (16) of a semiconductor substrate to obtain the processed semiconductor substrate (12), and Performing (320) a back-end-of-line process to generate the metallization layer structure (14) on the main surface (16) of the processed semiconductor substrate (12). [20] Method according to claim 19, further comprising defining (340) a predetermined fracture line (32) in the separation area (25). [21] Method according to claim 20, wherein the predetermined fracture line (32) is defined by a stealth dicing process. [22] Method according to any one of claims 13 to 21, further comprising: Separation of the die area (27; 34a-b) from the second area (29) of the processed substrate arrangement (10; 70) by breaking the processed substrate arrangement (10; 70) at the separation area (25). [23] Procedure (200; 300), comprising: Providing (220) a machined substrate arrangement (10; 70) comprising a machined semiconductor substrate (12) and a metallization layer structure (14) on a major surface (16) of the machined semiconductor substrate (12), wherein the metallization layer structure (14) comprises a cut (22), the cut (22) in the metallization layer structure (14) being arranged at a separation region (25) in the machined semiconductor substrate (12), the separation region (25) defining a boundary between a die region (27; 34a-b) of the machined substrate arrangement (10; 70) and at least a second region (29) of the machined substrate arrangement (10; 70), and the provision of the processed substrate arrangement (10; 70) includes: Release etching (210) from an area of ​​the metallization layer structure (14) to the processed semiconductor substrate (12) to expose a MEMS functional element (18) by creating a recess (24) and to create the cut (22) in the metallization layer structure (14) at the separation area (25); and Deposition (230) of a passivation layer (26) on a recess surface of the recess (24). [24] Semiconductor element, comprising: a machined substrate arrangement (10; 70) comprising a machined semiconductor substrate (12) and a metallization layer structure (14) on a main face of the machined semiconductor substrate (12); a passivation layer (26) arranged at an outer boundary of the processed substrate arrangement (10; 70); and a recess (24) in the metallization layer structure (14); a MEMS functional element (18) arranged on the machined semiconductor substrate (12) in the recess (24), wherein the MEMS functional element is a MEMS sensor and / or comprises a silicon material wherein the MEMS functional element and sidewall structures of the recess (24) in the metallization layer structure (14) are covered by the passivation layer, and wherein the metallization layer structure (14) comprises a cut (22), wherein the cut (22) in the metallization layer structure (14) is arranged at a separation region (25) in the processed semiconductor substrate (12), wherein the separation region (25) defines a boundary between a die region (27; 34a-b) of the processed substrate arrangement (10; 70) and at least a second region (29) of the processed substrate arrangement (10; 70). [25] Semiconductor element according to claim 24, wherein the MEMS functional element (18) is a MEMS sensor, a MEMS actuator or a MEMS transducer. [26] Semiconductor element according to claim 24 or 25, wherein the MEMS functional element (18) is exposed from the metallization layer structure (14) through the recess (24) in the metallization layer structure (14), and wherein the passivation layer (26) is arranged at the outer boundary of the processed substrate arrangement (10; 70) and at the side wall structure of the recess (24). [27] Semiconductor element according to one of claims 24 to 26, wherein the passivation layer (26) comprises an insulating material comprising a silicon nitride material. [28] Semiconductor element according to one of claims 24 to 27, wherein the machined substrate arrangement (10; 70) comprises a fracture edge at the outer boundary.

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