Method for producing semiconductor structures comprising transistor channels with different voltage states

Abstract

A method for producing a semiconductor structure (130) comprising: Providing a multilayer substrate (140) comprising: a base substrate (102), a buried oxide layer (104) over a surface of the base substrate (102), and a strained semiconductor layer (106) over the buried oxide layer (104) on a side thereof opposite the base substrate (102), the strained semiconductor layer (106) comprising crystalline semiconductor material; Implanting ions into a second region of the strained semiconductor layer (106B) without implanting ions into a first region of the strained semiconductor layer (106A) and converting a portion of the crystalline semiconductor material in the second region of the strained semiconductor layer (106B) into amorphous material, such that the second region of the strained semiconductor layer (106B) has an amorphous region and an underlying crystalline region; Recrystallization of the amorphous region; Diffusing elements from a portion of the second region of the strained semiconductor layer (106B) into another portion of the strained semiconductor layer (106) such that a concentration of the diffused elements is enriched in the other portion of the second region of the strained semiconductor layer (106B) and the strain state of the second region of the strained semiconductor layer (106B) is changed such that the second region of the strained semiconductor layer is in a strain state that is different from the strain state of the first region of the strained semiconductor layer (106A); and forming a first plurality of transistor channel structures, each comprising a portion of the first region of the semiconductor layer, and a second plurality of transistor channel structures, each comprising a portion of the second region of the semiconductor layer (106B).

Description

Field of TechnologyEmbodiments of the present disclosure relate to methods that can be used to produce n-type metal oxide semiconductors (NMOS) field effect transistors and p-type metal oxide semiconductors (PMOS) field effect transistors of different voltage states in a common layer on a semiconductor substrate, and to semiconductor structures and assemblies manufactured using these methods.Prior ArtSemiconductor devices, such as microprocessors and memory devices, utilize solid state transistors as the basic, primary operative structure of their integrated circuits. One type of transistor commonly used in semiconductor structures and elements is the field effect transistor (FET), which typically includes a source contact, a drain contact, and one or more gate contacts. A semiconducting channel region extends between the source contact and the drain contact. One or more pn junctions are defined between the source contact and the gate contact. The gate contact is located adjacent to at least a portion of the channel region, and the conductivity of the channel region is changed by an electric field present. Thus, an electric field is provided between the channel region in the channel region by applying a voltage to the gate contact. Thus, for example, an electric current may flow through the transistor from the source contact to the drain contact through the channel region when a voltage is applied to the gate contact, but may not flow through the transistor from the source contact to the drain contact when no voltage is applied to the gate contact.US 2012 / 0 068 267 A1 relates to semiconductor structures and methods for production. US 2014 / 0 008 729 A1 relates to semiconductors.Recently, field effect transistors (FETs) have been developed that utilize discrete, elongated channel structures referred to as "fins" (fins). Such a transistor is often referred to in the art as a finFET. Many different configurations of finFETs have been proposed in the prior art.The elongated channel structures of the fins of a finFET include a semiconductor material that is either n-doped or p-doped. It has also been shown that the conductivity of an n-type semiconductor material can be improved when the n-type semiconductor material is in the tensile state, and the conductivity of a p-type semiconductor material can be improved when the p-type semiconductor material is in the compressive state.Brief SummaryThis summary is provided to introduce a selection of concepts in a simplified form. These concepts are described in more detail in the detailed description of exemplary embodiments of the following disclosure. This summary is not intended to identify key or key features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.In some aspects, the present disclosure includes a method of manufacturing a semiconductor structure. A multilayer substrate is provided that includes a base substrate, a buried oxide layer over a surface of the base substrate, and a strained semiconductor layer over the buried oxide layer on a side thereof opposite the base substrate. The strained semiconductor layer contains crystalline semiconductor material. The method further includes implanting ions into a second region of the strained semiconductor layer without implanting ions into a first region of the strained semiconductor layer, and converting a portion of the crystalline semiconductor material in the second region of the strained semiconductor layer into amorphous material such that the second region of the strained semiconductor layer includes an amorphous region and an underlying crystalline region. The amorphous region is real-crystallized and elements are diffused from one portion of the second region of the strained semiconductor layer into another portion of the strained semiconductor layer to enrich the concentration of diffused elements in the other portion of the second region of the strained semiconductor layer and to alter the stress state of the second region of the strained semiconductor layer such that the second region of the strained semiconductor layer is in a stress state different from the stress state of the first region of the strained semiconductor layer. A first plurality of transistor channel structures each including a portion of the first region of the semiconductor layer and a second plurality of transistor channel structures each including a portion of the second region of the semiconductor layer are formed.In additional aspects, the present disclosure includes semiconductor structures fabricated using methods disclosed herein. For example, in some aspects, the present disclosure includes a semiconductor structure including a base substrate, a buried oxide layer over a surface of the base substrate, and a first plurality of transistor channel structures and a second plurality of transistor channel structures disposed over the buried oxide layer in a common plane on a side thereof opposite the base substrate. Each transistor channel structure of the second plurality of transistor channel structures includes a compressed strained semiconductor layer comprising two or more elements. Each transistor channel structure of the first plurality of transistor structures includes an uncompressed strained semiconductor layer. The transistor channel structures of the second plurality of transistor channel structures have a crystallographic voltage that is different from the crystallographic voltage of the transistor channel structures of the first plurality of transistor channel structures.Brief Description of the DrawingsWhile the specification concludes with claims particularly pointing out and distinctly claiming embodiments of the invention, the advantages of embodiments of the disclosure may be more readily ascertained from the description of certain exemplary embodiments of the disclosure in conjunction with the accompanying drawings, in which: FIG. 1 is a simplified, schematically depicted cross-sectional view illustrating a multilayer substrate including a strained semiconductor layer that may be used in accordance with embodiments of the present disclosure; FIG. 2 illustrates the substrate of FIG. 1 after a mask layer is applied to a portion of the multilayer substrate and illustrates implanting ions into the strained semiconductor layer in an unmasked portion of the multilayer substrate; FIG. 3 is an enlarged view of a portion of the substrate of FIGS. 1 and 2, showing a portion of the semiconductor layer after ions are implanted therein, such that an amorphous portion is formed in the semiconductor layer; FIG. 4 is similar to FIG. 3 and illustrates the portion of the semiconductor layer after recrystallization of the amorphous region therein; FIG. 5 is similar to FIGS. 3 and 4 and illustrates the portion of the semiconductor layer after removing an oxide layer from the surface of the semiconductor layer; FIG. 6 is comparable to FIGS. 3 to 5 and illustrates the partial region of the semiconductor layer after epitaxial deposition of additional semiconductor material on the semiconductor layer for thickening the semiconductor layer; FIG. 7 is similar to FIGS. 3-6 and illustrates the portion of the semiconductor layer after diffusion of elements from one of its regions to another of its regions to enrich a region of the semiconductor layer with one or more elements and to alter the stress state of the region of the semiconductor layer; FIG. 8 is a simplified, schematically depicted cross-sectional view showing a semiconductor structure fabricated using the methods described with reference to FIGS. 1-7 including a semiconductor on an insulator (SeOl) substrate including a semiconductor layer having regions of different voltage states over a buried oxide layer on a base substrate; FIG. 9 is a simplified, schematically depicted cross-sectional view showing a semiconductor structure that may be fabricated from the SeOI substrate shown in FIG. 8, and that includes a first plurality of fin structures formed in a region of the semiconductor layer having a first stress state and a second plurality of fin structures formed in a region of the semiconductor layer having a different second stress state; FIG. 10 is a simplified, schematically depicted cross-sectional view illustrating another semiconductor structure that may be fabricated from the SeOI substrate shown in FIG. 8, and that includes a trench isolation structure formed between the regions having different stress states; FIG. 11 is a simplified, schematically depicted cross-sectional view showing another multilayer substrate, such as that of FIG. 1, including a strained semiconductor layer that may be utilized in accordance with embodiments of the present disclosure; FIG. 12 illustrates a plurality of fin structures formed from a strained semiconductor layer of the substrate of FIG. 11 ; FIG. 13 illustrates the implantation of ions into some but not all of the fin structures; FIG. 14 is an enlarged view of a portion of the substrate of FIG. 13, showing some of the fin structures after ions are implanted into the fin structures and amorphous regions are formed within the fin structures; FIG. 15 is similar to FIG. 14 and illustrates the fin structures after crystallization of the amorphous regions therein; FIG. 16 is similar to FIGS. 14 and 15 and illustrates the fin structures after diffusing elements from one region thereof into another region thereof such that a region of the fin structures is enriched with one or more elements and the stress state of the fin structures is changed; and FIG. 17 illustrates an example structure of a finFET transistor.Detailed DescriptionThe drawings depicted herein are not intended to be actual views of a particular semiconductor structure, semiconductor element, semiconductor system, or method, but are merely idealized representations used to describe aspects of the disclosure.Any keywords used herein should not be considered to limit the scope of embodiments of the invention as defined by the claims below and their legal equivalents. Concepts described in any specific language are generally applicable in other sections throughout the specification.The terms first / r and second / r in the description and the claims are used to distinguish similar elements.As used herein, the term "fin" and "fin structure" refers to an elongated, three-dimensional, finite, and limited volume of semiconductor material having a length, a width, and a height, the length being greater than the width. The width and height of the fin may vary along the length of the fin in some embodiments.Hereinafter, with reference to the drawings, methods that can be used to produce semiconductor structures and semiconductor structures that can be produced using such methods will be described.Referring to FIG. 1, a multilayer substrate 100 may be provided that includes a base substrate 102, a buried oxide (BOX) layer 104 over a surface of the base substrate 102, and a strained semiconductor layer 106 over the BOX layer 104 on a side thereof opposite the base substrate 102. The strained semiconductor layer 106 may include a strained silicon layer and the multilayer substrate 100 may include a 'strained silicon on insulator' (SSOI) substrate.The base substrate 102 may include a chip or wafer of, for example, semiconductor material (e.g., silicon, silicon carbide, germanium, a III-V semiconductor material, etc.), a ceramic material (e.g., silicon oxide, aluminum oxide, silicon carbide, etc.), or a metallic material (e.g., molybdenum, etc.). The base substrate 102 may have a monocrystalline or polycrystalline microstructure in some embodiments. In other embodiments, the base substrate 102 may be amorphous. The base substrate 102 may have a thickness that may range between about 400 μm and about 900 μm (e.g., about 750 μm), for example, although thicker or thinner base substrates 102 may also be used.The layers overlying the base substrate 102, such as the BOX layer 104, may be deposited, "grown", or otherwise epitaxially formed over the substrate using any of a number of different processes, such as chemical vapor deposition (CVD), atomic facility deposition (ALD), physical vapor deposition (PLD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), and thermal oxidation. In additional embodiments, they may be transferred from another donor substrate to the base substrate 102 using known processes.By way of example only, the multilayer substrate 100 may be formed by the process known in the art as the SMART CUT® process in which a layer of semiconductor material is transferred from a donor structure to a receiving substrate (e.g., the base substrate) such that an oxide layer (e.g., the BOX layer 104) is disposed between the receiving substrate and the transferred semiconductor layer. The SMART CUT® process is described, for example, in U.S. Patent No. RE 39,484 to Bruel (issued February 6, 2007), U.S. Patent No. 6,303,468 to Aspar et al. (issued October 16, 2001), U.S. Patent No. 6,335,258 to Aspar et al. (issued January 1, 2002), U.S. Patent No. 6,756,286 to Moriceau et al. (issued June 29, 2004), U.S. Patent No. 6,809,044 to Aspar et al. (issued October 26, 2004) and U.S. Patent No. 6,946,365 to Aspar et al. (September 20, 2005).The BOX layer 104 may include, for example, an oxide (e.g., silicon dioxide, aluminum oxide, hafnium oxide, etc.), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), or a combination of such dielectric materials. The BOX layer 104 may be crystalline or amorphous. For example, the BOX layer 104 may have an average layer thickness between about 10 nm to about 200 nm, although thicker or thinner BOX layers 104 may also be used in embodiments of the present disclosure.The stressed semiconductor layer 106 may include a (compressive or tensile) stressed crystalline semiconductor material, such as a layer of stressed silicon (Si). In other embodiments, the layer of stressed semiconductor 106 may include stressed germanium (Ge), stressed silicon germanium (SiGe), or a stressed III-V semiconductor material. Consequently, the stressed semiconductor material 106 may have a crystal structure having lattice constants that are either above (tensile-strained) or below (compressive-strained) the relaxed lattice constants normally exhibited by the crystal structure of the corresponding solid-state free-standing semiconductor material in the equilibrium state. The strained semiconductor layer 106 may have an average layer thickness of about 50 nm or less, or even about 10 nm or less. The strained semiconductor layer 106 may have an average layer thickness below the critical thickness of a strained semiconductor layer 106. In embodiments where the stressed semiconductor layer 106 includes a stressed silicon layer transferred from a donor substrate to the base substrate 102 and where the stressed semiconductor layer 106 is epitaxially grown on a SiGe buffer layer prior to the layer transfer process, the critical thickness of the stressed semiconductor layer may be a function of germanium concentration in the SiGe buffer layer, with a critical thickness that decreases with increasing germanium concentration. Thicker layers of stressed semiconductor material 106 may also be used in embodiments of the present disclosure. The stressed semiconductor layer 106, after being transferred to the base substrate 102, may be thickened to a thickness greater than its critical thickness using epitaxial deposition techniques as disclosed, for example, in Thean et al., "Uniaxial Bi-axial Stress Hybridization for Supercritically Stressed Silicon directly on an insulator (SC-SSOI) PMOS having different channel orientations" (Uniaxial Bi-axial Stress Hybridization for Super-Critical Strained-Si Directly On Insulator (SC-SSOI) PMOS With Different Channel Orientations), IEEE International (Electron Devices Meeting, Washington DC, 2005), pp. 509-512, without degrading stress relaxation.As a specific example, the base substrate 102 of the donor substrate 101 may include monocrystalline silicon substrate, the BOX layer 104 may include silicon dioxide (SiO 2) and the strained semiconductor layer 106 may include strained strained monocrystalline silicon (sSi) having a thickness below its respective critical thickness, such that the onset of relaxations and the formation of local defects in its crystal structure is avoided.In some embodiments, an oxide layer 108, which may be a native oxide layer or a deposited oxide, may be present over the major surface of the strained semiconductor layer 106 on the side thereof opposite the BOX layer 104. In other embodiments, the oxide layer 108 may not be present.Referring to FIG. 2, a patterned mask layer 110 may be provided over the strained semiconductor layer 106. The patterned mask layer 110 may cover one or more regions of the strained semiconductor layer 106, while other regions of the strained semiconductor layer 106 may be uncovered by the patterned mask layer 110. As an example, FIG. 2 illustrates a first portion of the strained semiconductor layer 106A covered by the patterned mask layer 110 and a second portion of the strained semiconductor layer 106B uncovered by the patterned mask layer 110.The patterned mask layer 110 may comprise a hard mask layer material such as one or more of an oxide layer, a nitride layer, or an oxynitride layer. The patterned mask layer 110 may be formed by depositing or otherwise providing a continuous layer of a hard mask material over the multilayer substrate 100, and then patterning the hard mask material using a lithographic masking and etching process to form openings in the hard mask material at locations where it is desired to remove portions of the hard mask material to expose portions of the strained semiconductor layer 106. In other embodiments, the patterned mask layer 110 may include a photoresist mask material.Still referring to FIG. 2, after the formation of the patterned mask layer 110, ions may be implanted into the region or regions of the strained semiconductor layer 106 exposed by the patterned mask layer 110 (indicated by the directional arrows), such as the second region of the strained semiconductor layer 106B, without implanting ions into the region or regions of the strained semiconductor layer 106 covered by the patterned mask layer 110, such as the first region of the strained semiconductor layer 106A. The ions may traverse the openings in the mask layer 110 and transition into the first region of the strained semiconductor layer 106A, while the mask layer 110 shields the second region of the strained semiconductor layer 106B and prevents the ions from being implanted therein.In some embodiments, the oxide layer 108, if present, may be removed from as the strained semiconductor layer 106 such that a surface of the strained semiconductor layer is exposed. However, in other embodiments, the ions may be implanted into the strained semiconductor layer through the oxide layer 108.The ion implantation may convert a portion of the crystalline semiconductor material of the strained semiconductor layer 106 into amorphous material. Thus, the region or regions of the semiconductor layer 106 into which the ions have been implanted may include an amorphous region 112 and an underlying crystalline region 114, as shown in the enlarged view of FIG. 3.The implanted ions may be ions of elements different from at least one element present in the crystal structure of the semiconductor layer 106. For example, in embodiments where the strained semiconductor layer comprises strained silicon (sSi), the implanted ions may comprise, for example, germanium ions different from silicon. This is because the implanted ions having different atomic radii with respect to different elements in the semiconductor layer 106 may be used to subsequently change a stress state of the semiconductor layer 106 in subsequent processes, as described in more detail below.Table 1 below illustrates examples of germanium concentration and germanium content in a tensile strained strained silicon semiconductor layer 106 for layer thicknesses of the semiconductor layer 106 for each of the five (5) different doses of a germanium ion implantation process performed at ion implantation energies of 40-50 KeV. Table 1 Table 1(1)1.00E+151.00E+190,02%100 nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm(2)5.00E+155.00E+190,10%(3)1.00E+161.00E+200,20%(4)5.00E+165.00E+201,00%(5)1.00E+171.00E+212,00%(1)1.00E+152.00E+190,04%50 nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm(2)5.00E+151.00E+200,20%(3)1.00E+162.00E+200,40%(4)5.00E+161.00E+212,00%(5)1.00E+172.00E+214,00%(1)1.00E+153.33E+190,07%30 nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm(2)5.00E+151.67E+200,33%(3)1.00E+163.33E+200,67%(4)5.00E+161.67E+213,33%(5)1.00E+173.33E+216,67%(1)1.00E+155.00E+190,10%20 nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm(2)1.00E+152.50E+200,50%(3)1.00E+165.00E+201,00%(4)1.00E+162.50E+215,00%(5)1.00E+175.00E+2110,00%(1)1.00E+151.00E+200,20%10 nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm(2)1.00E+155.00E+201,00%(3)1.00E+161.00E+212,00%(4)1.00E+165.00E+2110,00%(5)1.00E+171.00E+2220,00%Referring to FIG. 4, after ions are implanted into the region or regions of the strained semiconductor layer 106, the amorphous regions 112 of the semiconductor layer 106 may be recrystallized such that the region or regions include an amorphous region 112 and an underlying crystalline region 114 (as shown in FIG. 3 ). For example, an annealing process performed in an oven at elevated temperatures may be used to re-crystallize the amorphous regions 112 and form re-crystallized regions 120 as shown in FIG. 4. After recrystallization, the recrystallized regions 120 may be in a different stress state from a stress state of the first region of the strained semiconductor layer 106A (FIG. 2 ) due to the implanted ions (e.g., germanium ions) having different atomic radii with respect to at least one element (e.g., silicon) present in the originally formed semiconductor layer 106.Thus, in embodiments where the originally formed strained semiconductor layer 106 comprises tensile-strained silicon and the implanted ions comprise germanium ions, the recrystallized regions 120 may comprise Si y Ge 1-y where y is between about 0.01 and about 0.50, or in other embodiments between about 0.10 and 0.20.During the recrystallization process, the recrystallization of the amorphous regions 112 of the semiconductor layer 106 may be seeded by the underlying crystalline regions 114 of the semiconductor layer 106. Since the underlying crystalline region 114 of the semiconductor layer 106 may include silicon and the recrystallized region 120 may include Si y Ge 1-y the recrystallized region 114 is formed of Si y Ge 1-y on the underlying Si and the crystal lattice of Si y Ge 1-y may be constrained by the underlying silicon such that the recrystallized regions of Si y Ge 1-y are in a compressive stress state (the lattice parameters of Si y Ge 1-y are larger than the lattice parameters of Si because the atomic radius of Ge is larger than that of Si).Referring to FIG. 5, the optional oxide layer 108, if present, may be removed after recrystallization of the amorphous regions 112 of the semiconductor layer 106 to form the crystallized regions 120 by utilizing one or more of a chemical etching process, a mechanical polishing process, or a chemical mechanical polishing (CMP) process.As shown in FIG. 6, in some embodiments, additional semiconductor material 124 may be selectively epitaxially grown on the second region of the semiconductor layer 106B without epitaxially growing additional semiconductor material on the first region of the semiconductor layer 106A. The additional semiconductor material 124 may include, for example, silicon or Si 1-y Ge y.In some embodiments, the growth of additional semiconductor material 124 may be performed after the recrystallization of the amorphous regions to form the recrystallized regions 120, as shown in the sequence of the figures. However, in other embodiments, the growth of additional semiconductor material 124 may be performed prior to implanting ions into the second region of the semiconductor layer 106B and prior to forming the amorphous regions 112 (FIG. 3 ). When performed prior to the ion implantation process described with reference to FIG. 2, the selective epitaxial growth of additional semiconductor material 124 discussed with reference to FIG. 6 may also allow for the implantation of a larger number of ions, which allows for the achievement of higher concentrations of the implanted ions in the second region of the semiconductor layer 106B as well as the fulfilment of a longer thermal diffusion process as described below with reference to FIG. 7, and thus allows for a larger deviation of a stress state of the second region of the semiconductor layer 106B.The thickness of the additional semiconductor material 124 selectively epitaxially grown over the second region of the semiconductor layer 106B may be selected such that, subsequent to a diffusion and accumulation process described below with reference to FIG. 7, a thickness of the second region of the semiconductor layer 106B is at least substantially equal to a thickness of the first region of the semiconductor layer 106A that is not subjected to the diffusion and accumulation process described with reference to FIG. 7.Referring to FIG. 7, after recrystallizing the amorphous regions 112 of the second region of the semiconductor layer 106B to form recrystallized regions 120, elements may be diffused from one portion of the recrystallized region 120 of the second region of the semiconductor layer 106B into another portion of the second region of the semiconductor layer 106B to enrich a concentration of the diffused elements in the other portion of the second region of the semiconductor layer 106B and change the voltage state of the second region of the semiconductor layer 106B.For example, a compaction process (often referred to as a "thermal mixing" process) or other type of process may be utilized to diffuse elements within the second region of the semiconductor layer 106B such that they are concentrated and enriched within a portion of the second region of the semiconductor layer 106B to selectively reduce tensile stress, increase compressive stress, and / or relieve stress in the second region of the semiconductor layer 106B relative to stress level in the first region of the semiconductor layer 106A. In such embodiments, the elements may not be diffused in any substantial manner within the first region of the semiconductor layer 106A. In other words, the compaction process may be performed only on the second region of the semiconductor layer 106B, but not on the first region of the semiconductor layer 106A. Such a compaction process is described below.FIG. 7 is similar to FIGS. 3-6 and illustrates a multilayer substrate 100 after a compaction process is performed on the second region of the semiconductor layer 106B. The densification process may involve subjecting the second region of the semiconductor layer 106B to an oxidation process in a furnace at elevated temperatures (e.g., between about 900° C. and about 1150° C.) in an oxidizing atmosphere (e.g., dry O 2 with or without HCL). The oxidation process may result in the formation of an oxide layer 122 on the surface of the second region of the semiconductor layer 106B and may cause diffusion of elements from within an upper region of the second region of the semiconductor layer 106B into a lower region of the second region of the semiconductor layer 106B.In embodiments in which the strained semiconductor layer 106 comprises strained silicon (sSi), the ions implanted into the second region of the semiconductor layer 106B may comprise germanium ions as described with reference to FIG. 2, and the germanium atoms may continue to diffuse into the second region of the semiconductor layer 106B during the densification process. An oxide layer 122 may form on the surface of the second region of the semiconductor layer 106B and grow in thickness into the second region of the semiconductor layer 106B. As the thickness of the oxide layer 122 increases during the germanium densification process, the thickness of the Si y Ge 1-y semiconductor layer 106 decreases and the concentration of germanium in the semiconductor layer 106 increases until the Si y Ge 1-y semiconductor layer 106 has a desired concentration of germanium. The diffusion and accumulation of germanium within the second region of the semiconductor layer 106B may result in a reduction of any tensile stress within the strained semiconductor layer 106 and may result in relaxation of the stress and / or generation of compressive stress within the strained semiconductor layer 106.As a result, the first portion of the semiconductor layer 106A may be in a first voltage state and the second portion of the semiconductor layer 106B may be in a second voltage state different from the first voltage state.The oxide layer 122 formed in the diffusion and accumulation process (i.e., densification process) may be removed above the second region of the semiconductor layer 106B prior to subsequent processing.As mentioned above, the first region of the semiconductor layer 106A may include a strained silicon layer. The tensile stress in the first region of the semiconductor layer 106A may allow for improved electron mobility within the first region of the semiconductor layer 106A, which may be desirable for forming n-type FET transistors with channel regions comprising portions of the first region of the semiconductor layer 106. The ion implantation and crystallization process, as well as the densification process applied in the second region of the semiconductor layer 106B, may result in improved hole mobility within the second region of the semiconductor layer 106B, which may be desirable for forming p-type FET transistors with channel regions comprising portions of the second region of the semiconductor layer 106B.The oxide layer 108 shown in FIG. 8 and the mask layer 110 overlying the semiconductor layer 106 may be removed from a semiconductor structure 130. The semiconductor structure 130 shown in FIG. 8, formed using the methods described with respect to FIGS. 1-7, includes a base substrate 102, a BOX layer 108 over a surface of the base substrate 102, and a first portion of a semiconductor layer 106A and a second portion of a semiconductor layer 106B located over the BOX layer 104 in a common plane on a side of the BOX layer 104 opposite the base substrate 102. The semiconductor structure 130 may then be processed to complete the fabrication of a semiconductor device including both n-type and p-type transistors. The n-type transistors may be formed on and / or in the first region of the semiconductor layer 106, and the p-type transistors may be formed on and / or in the second region of the semiconductor layer 106.FIG. 9, for example, illustrates the formation of a first plurality of fin structures 132A each including a portion of the first region of the semiconductor layer 106A and a second plurality of fin structures 132B each including a portion of the second region of the semiconductor layer 106B. Each of the fin structures 132A, 132B is designed and configured for use as a transistor channel structure in finFET-type transistors. As an example, each of the fin structures 132A, 132B may be formed with an average width of about 15 nm or less.The fin structures 132B of the second plurality of fin structures 132B have a crystallographic voltage that is different than the crystallographic voltage of the fin structures 132A of the first plurality of fin structures 132A. Each fin structure 132A of the first plurality of fin structures 132A includes a non-densified stressed semiconductor material. Each fin structure 132B of the second plurality of fin structures 132B includes a densified stressed semiconductor material including two or more elements (e.g., silicon and germanium).After forming the first and second pluralities of fin structures 132A, 132B, a first plurality of n-type finFET transistors comprising the first plurality of fin structures 132A and a second plurality of p-type finFET transistors comprising the second plurality of fin structures 132B may be formed.In additional embodiments, the semiconductor structure 130 of FIG. 8 may be subsequently processed to form a plurality of conventional planar n-type metal oxide semiconductor field effect transistors (NMOS FETs) on and / or in the first region of the semiconductor layer 106A, and to form a plurality of conventional planar p-type metal oxide semiconductor field effect transistors (PMOS FETs) on and / or in the second region of the semiconductor layer 106B, as shown in FIG. 10. For example, one or more trench isolation (STI) structures 134 may be partially or completely formed through the semiconductor layer 106 to electrically isolate the transistor channel regions still to be formed in the semiconductor layer 106. To define transistor channel structures in the semiconductor layer 106, conventional STI processing may be used. In such processing, a masking and etching process may be used to form trenches between the adjacent transistor channel structures, and dielectric material may be provided in the trenches to form the STI structures 134 between the transistor channel structures. Consequently, the STI structures 134 in the semiconductor layer 106 may be used to electrically isolate the transistor channel structures to be defined in the semiconductor layer 106. Although only one STI structure 134 is shown in FIG. 10, a plurality of such STI structures 134 may be used to define the transistor channel structures in the semiconductor layer 106.After forming the STI structures 134 in the semiconductor layer 106, a first plurality of transistor channel structures each including a portion of the first region of the semiconductor layer 106A and a second plurality of transistor channel structures each including a portion of the second region of the semiconductor layer 106B may be formed. The transistor channel structures may be designed and configured for use as transistor channel structures in MOS FET type transistors.The NMOS FET transistor channel structures formed in the first region of the semiconductor layer 106A have a crystallographic voltage that is different from the crystallographic voltage of the PMOS FET transistor channel structures formed in the second region of the semiconductor layer 106B. After forming the first and second pluralities of transistor channel structures, a first plurality of NMOS FET transistors may be formed including a first plurality of transistor channel structures, and a second plurality of PMOS FET transistors may be formed including a second plurality of transistor channel structures.Before the STI structures 134 are formed, in additional embodiments, a first plurality of NMOS FET transistors may be formed that includes the first plurality of transistor channel structures and a second plurality of PMOS FET transistors may be formed that includes the second plurality of transistor channel structures. FIGS. 11 through 16 illustrate an additional embodiment of a method that may be used to fabricate coplanar n-type and p-type finFET transistors similar to those described above with reference to FIGS. 1 through 9.FIG. 11 illustrates a multilayer substrate 140 that includes a base substrate 102, a buried oxide layer 104, and a strained semiconductor layer 106 as previously described herein with reference to FIG. 1.As shown in FIG. 12, the strained semiconductor layer 106 may be formed, for example, by applying a masking and etching process to form fin structures 142 each including a portion of the strained semiconductor layer 106. The fin structures 142 may be formed using finFET fabrication processes known in the art and may be spacer-defined double patterning (SDDP) processes (also known in the art as side-wall image transfer (SDDP) processes). The fin structures 142 may include a second plurality of fin structures 142B and a first plurality of fin structures 142A.Referring to FIG. 13, one or more mask layers may be deposited over the fin structures 142. The mask layers may include, for example, a passivating oxide layer 144, a nitride layer 146, and a mask layer 148. The mask layer 148 may include, for example, a photoresist mask material that may be configured to form passages therethrough over the second plurality of fin structures 142B. One or both of the oxide layer 144 and the nitride layer 146 may be removed using one or more etching processes in which they are exposed to an etchant through the passages in the mask layer 148, while the mask layer 148 protects the remainder of the structure from the etchant. As shown in FIG. 13, in some embodiments, portions of the nitride layer 146 overlying the second plurality of fin structures 142B may be removed by applying an etching process, wherein at least a portion of the oxide layer 144 overlying the second plurality of fin structures 142B may be left in place. However, in other embodiments, the portions of the oxide layer 144 overlying the second plurality of fin structures 142B may be at least substantially completely removed. The mask layer 148 may optionally be removed prior to subsequent processing or left in place as shown in FIG. 13.As shown in FIG. 13, ions may be implanted into the second plurality of fin structures 142B through the openings in one or both of the mask layer 148 and the nitride layer 146 in a process as described above with reference to FIG. 2 to form amorphous regions 150 in portions of the second plurality of fin structures 142B as shown in FIG. 14. The second plurality of fin structures 142B may include crystalline regions 114 of the strained semiconductor layer 106 remaining under the amorphous regions 150 substantially as described above with reference to FIG. 3.Referring to FIG. 15, after the formation of the amorphous regions 150, the amorphous regions 150 may be recrystallized to form recrystallized regions 154. The recrystallization process may be performed as described above with reference to FIG. 4.Referring to FIG. 16, a diffusion and accumulation process (e.g., a compaction process) may be performed on the second plurality of fin structures 142B after forming the recrystallized regions 154 (FIG. 15 ) in a manner as described above with reference to FIG. 7. The diffusion and accumulation process may result in the formation of an oxide layer 156 over each of the fin structures 142B of the second plurality.Optionally, prior to performing the diffusion and accumulation process as described above with reference to FIGS. 5 and 6, epitaxial growth of additional semiconductor material may also be performed on the second plurality of fin structures 142B.Thus, the second plurality of fin structures 142B may include transistor channel structures configured and arranged to form p-type finFET transistors, and the first plurality of fin structures 142A may include transistor channel structures configured and arranged to form n-type finFET transistors.After forming the first and second pluralities of fin structures 142A, 142B, as described above with reference to FIGS. 11-16, a first plurality of NMOS finFET transistors including the first plurality of fin structures 142A and a second plurality of PMOS finFET transistors including a second plurality of fin structures 142B may be formed.FIG. 17 illustrates a simplified, example embodiment of a finFET transistor die that may be fabricated using the second plurality of fin structures 142B and / or the first plurality of fin structures 142A in accordance with embodiments of the present disclosure (the fin structures of FIG. 9 ). It should be appreciated that many different finFET designs are known in the art and may be used in accordance with embodiments of the disclosure, and that the finFET structure shown in FIG. 17 is presented merely as an example of such finFET structures.As shown in FIG. 17, a finFET transistor 160 includes a source region 162, a drain region 164, and a channel extending between the source region 162 and the drain region 164. The channel is defined by and includes a fin, such as either a first fin structure 142A or a second fin structure 142B. In some embodiments, the source region 162 and the drain region 164 may include or be defined by longitudinal end portions of a fin structure 142. A conductive gate 166 extends over and adjacent at least a portion of the fin structure 142 between the source region 142 and the drain region 164. The gate 166 may be separated from the fin structure 142 by a dielectric material 168. The gate 166 may include a multilayer structure and may include semiconducting and / or conductive layers. A low-resistance layer including a metal, a metal compound, or both, such as conductive silicide, may be deposited over the source region 162 and / or the drain region 164 to form electrical contacts therewith.Advantageously, tensile stress / strain in the channel may increase the performance of NMOS finFET transistors and decrease the threshold voltage, while decreased tensile stress / strain (e.g., lower tensile stress, no tensile, or compressive stress, or compressive stress) in the channel may increase the performance of PMOS finFET transistors and decrease the threshold voltage. For some tasks, strained packages are advantageous because high power is needed and for some other tasks, power is less significant, but a high threshold voltage is advantageous. With embodiments of the present disclosure, the manufacturer may selectively integrate differing stress and strain levels into the crystal lattices of different finFETs or MOSFET transistors in a common FET transistor level of the same package.Additional exemplary embodiments of the disclosure are set forth below.Aspect 1: A method of manufacturing a semiconductor structure, comprising: providing a multilayer substrate comprising: a base substrate, a buried oxide layer over a surface of the base substrate, and a strained semiconductor layer over the buried oxide layer on a side thereof opposite the base substrate, the strained semiconductor layer comprising crystalline semiconductor material; implanting ions into a second region of the strained semiconductor layer without implanting ions into a first region of the strained semiconductor layer, and converting a portion of the crystalline semiconductor material in the second region of the strained semiconductor layer into amorphous material such that the second region of the strained semiconductor layer comprises an amorphous region and an underlying crystalline region; recrystalizing the amorphous region; diffusing elements from a portion of the second region of the strained semiconductor layer into another portion of the strained semiconductor layer, so that a concentration of the diffused elements is enriched in the other portion of the second region of the strained semiconductor layer and the strain state of the second region of the strained semiconductor layer is changed such that the second region of the strained semiconductor layer is in a strain state different from the strain state of the first region of the strained semiconductor layer; and forming a first plurality of transistor channel structures each including a portion of the first region of the semiconductor layer and a second plurality of transistor channel structures each including a portion of the second region of the semiconductor layer.Embodiment 2: The method of Embodiment 1, further comprising selecting a strained semiconductor layer comprising strained silicon.Embodiment 3: The method of Embodiment 2, further comprising selecting a strained semiconductor layer comprising strained silicon.Embodiment 4: The method of Embodiment 2 or Embodiment 3, wherein implanting ions into the second region of the strained semiconductor layer comprises implanting germanium ions into the second region of the strained semiconductor layer to form Si y Ge 1-y where y is between about 0.10 and about 0.5, and wherein diffusing elements from one portion of the second region of the strained semiconductor layer into another portion of the strained semiconductor layer comprises diffusing germanium into the other portion of the second region of the strained semiconductor layer.Aspect 5: The method of any of Aspects 1 to 4, wherein forming the first plurality of transistor channel structures and the second plurality of transistor structures comprises forming a first plurality of fin structures (fin structures) each comprising a portion of the first region of the semiconductor layer and a second plurality of fin structures each comprising a portion of the second region of the semiconductor layer.Embodiment 6: The method of Embodiment 5, further comprising forming a plurality of n-type finFET transistors comprising the first plurality of fin structures, and forming a p-type finFET transistor comprising the second plurality of fin structures.Embodiment 7: The method of any one of Embodiments 1 to 6, further comprising forming the transistor channel structures of the first and second pluralities of transistor channel structures having an average width of about 15 nm or less.Embodiment 8: The method of any of Embodiments 1 to 8, wherein diffusing elements from one portion of the second region of the strained semiconductor layer into another portion of the strained semiconductor layer comprises relaxing stresses in the second region of the strained semiconductor layer.Embodiment 9: The method of Embodiment 8, wherein relaxing stresses in the second region of the strained semiconductor layer comprises increasing hole mobility within the second region of the strained semiconductor layer.Embodiment 10: The method of any of Embodiments 1 to 9, wherein diffusing elements from one portion of the second region of the strained semiconductor layer into another portion of the strained semiconductor layer comprises performing a compression process on the second region of the strained semiconductor layer.Aspect 11: The method of Aspect 10, wherein performing a compression process on the second region of the strained semiconductor layer comprises oxidizing a portion of the second region of the strained semiconductor layer.Embodiment 12: The method of any of Embodiments 1 to 11, wherein recrystalizing the amorphous region comprises seeding the recrystallizing the amorphous region with the underlying crystalline region.Embodiment 13: The method of any of Embodiments 1 to 12, further comprising epitaxially growing additional semiconductor material on the second region of the semiconductor layer without growing additional semiconductor material on the first region of the semiconductor layer prior to diffusing elements from one portion of the second region of the strained semiconductor layer into the other portion of the strained semiconductor layer.Embodiment 14: A semiconductor structure comprising: a base substrate; a buried oxide layer over a surface of the base substrate; first and second pluralities of transistor channel structures disposed over the buried oxide layer in a common plane on a side thereof opposite the base substrate, each transistor channel structure of the second plurality of transistor channel structures comprising a compressed strained semiconductor layer including two or more elements, each transistor channel structure of the first plurality of transistor channel structures comprising an uncompressed strained semiconductor layer; wherein the transistor channel structures of the second plurality of transistor channel structures have a crystallographic voltage different from the crystallographic voltage of the transistor channel structures of the first plurality of transistor channel structures.Embodiment 15: The semiconductor structure of Embodiment 14, wherein the uncompressed strained semiconductor layer of each transistor channel structure of the first plurality of transistor channel structures comprises strained silicon.Embodiment 16: The semiconductor structure of Embodiment 14 or Embodiment 15, wherein the compressed stressed semiconductor layer of each transistor channel structure of the second plurality of transistor channel structures comprises Si x Ge 1-x where x is between about 0.01 and about 0.50.Embodiment 17: The semiconductor structure of any of embodiments 14 to 16, wherein the transistor channel structures of the first plurality of transistor channel structures are in a state of tensile stress and the transistor channel structures of the first plurality of transistor channel structures are relaxed or in a state of compressive stress.Embodiment 18: The semiconductor structure of any of Embodiments 14 to 17, wherein the transistor channel structures of the first plurality of transistor channel structures and the second plurality of transistor channel structures have an average width of about 15 nm or less.Embodiment 19: The semiconductor structure of any of Embodiments 14 to 18, wherein the transistor channel structures of each of the first plurality of transistor channel structures and the second plurality of transistor channel structures comprise fin structures.Embodiment 20: The semiconductor structure of Embodiment 19, further comprising a first plurality of n-type finFET transistors comprising the first plurality of transistor channel structures, and a second plurality of p-type finFET transistors comprising the second plurality of transistor channel structures.

Claims

A method of manufacturing a semiconductor structure (130), comprising: providing a multilayer substrate (140) comprising: a base substrate (102), a buried oxide layer (104) over a surface of the base substrate (102), and a strained semiconductor layer (106) over the buried oxide layer (104) on a side thereof opposite the base substrate (102), the strained semiconductor layer (106) comprising crystalline semiconductor material; implanting ions into a second region of the strained semiconductor layer (106B) without implanting ions into a first region of the strained semiconductor layer (106A), and converting a portion of the crystalline semiconductor material in the second region of the strained semiconductor layer (106B) into amorphous material such that the second region of the strained semiconductor layer (106B) includes an amorphous region and an underlying crystalline region; re-crystallizing the amorphous region; diffusing elements from a portion of the second portion of the strained semiconductor layer (106B) into another portion of the strained semiconductor layer (106), so that a concentration of the diffused elements is enriched in the other portion of the second portion of the strained semiconductor layer (106B), and the strain state of the second portion of the strained semiconductor layer (106B) is changed such that the second portion of the strained semiconductor layer is in a strain state different from the strain state of the first portion of the strained semiconductor layer (106A); and forming a first plurality of transistor channel structures each including a portion of the first region of the semiconductor layer and a second plurality of transistor channel structures each including a portion of the second region of the semiconductor layer (106B).The method of claim 1, further comprising selecting a strained semiconductor layer (106) comprising strained silicon.The method of claim 2, further comprising selecting a strained semiconductor layer (106) comprising strained silicon.The method of claim 2, wherein implanting ions into the second region of the strained semiconductor layer (106B) comprises implanting germanium ions into the second region of the strained semiconductor layer (106B) to form SiyGe1-y, where y is between about 0.10 and about 0.5, and wherein diffusing elements from one portion of the second region of the strained semiconductor layer (106B) into another portion of the strained semiconductor layer (106) comprises diffusing germanium into the other portion of the second region of the strained semiconductor layer (106B).The method of claim 1, wherein forming the first plurality of transistor channel structures and the second plurality of transistor structures comprises forming a first plurality of fin structures (142) each comprising a portion of the first region of the semiconductor layer (106A) and a second plurality of fin structures (142) each comprising a portion of the second region of the semiconductor layer (106B).The method of claim 1, wherein diffusing elements from one portion of the second portion of the strained semiconductor layer (106B) into another portion of the strained semiconductor layer (106) comprises relaxing stresses in the second portion of the strained semiconductor layer (106B).The method of claim 1, wherein diffusing elements from a portion of the second portion of the strained semiconductor layer (106B) into another portion of the strained semiconductor layer (106) comprises performing a compression process on the second portion of the strained semiconductor layer (106).The method of claim 7, wherein performing a compression process on the second region of the strained semiconductor layer (106B) comprises oxidizing a portion of the second region of the strained semiconductor layer (106B).The method of claim 1, wherein the crystallizing the amorphous region comprises seeding the recrystallization of the amorphous region with the underlying crystalline region.The method of claim 1, further comprising epitaxially growing additional semiconductor material on the second region of the semiconductor layer (106B) without growing additional semiconductor material on the first region of the semiconductor layer (106A) prior to diffusing elements from one portion of the second region of the strained semiconductor layer (106B) into the other portion of the strained semiconductor layer (106).

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