CIRCUIT AND METHOD WITH A SINGLE CELL WITH INTERNAL CLOCK GATING

Abstract

Circuit, showing: a latch (120) configured to generate a gating control signal (Q) in response to a latch enable signal (EB) and an input clock signal (CP), wherein the latch (120) has a pair of logic gates (210, 220) each configured to perform a complex logic function at multiple levels; and a logic circuit (130) configured to receive the gating control signal (Q) and the input clock signal (CP) and to generate an output clock signal (CPQ) in response to the gating control signal (Q) and the input clock signal (CP), where the logic gates (210, 220) are: at least one header switch (M1) and at least one footer switch (M3), each configured to be controlled by the input clock signal (CP); a first (M5), a second (M13) and a third switch (M7) which are coupled in series with at least one header switch (M1); a fourth (M6), a fifth (M14) and a sixth switch (M8) coupled in series with at least one header switch (M1); and a pair of cross-coupled inverters (310, 320) coupled to at least one footer switch (M3), wherein the second (M13) and fifth switches (M14) are configured to be controlled by outputs of the inverters (310, 320); wherein the first (M5) and third switches (M7) are configured to be controlled by the latch release signal (EB), and the fourth (M6) and sixth switches (M8) are configured to be controlled by a logical complement of the latch release signal (EB).

Description

BACKGROUND

[0001] In a digital system comprising various synchronous circuits, a clock signal is used to synchronize all components. With the advancement of semiconductor technologies, the frequency of clock signals increases, and consequently, so does the power consumption of the clock network. In this situation, internal clock gating (ICG) is a technique for reducing the overall clock network power loss. In some methods, internal clock gating is used to block the clock signal for certain circuits within the digital system when they are not in use for a certain number of clock cycles.

[0002] Document US 6,204,695 B1 relates to a clock gate circuit for a logic device. The clock gate circuit comprises an input terminal for receiving an input clock signal, an input terminal for receiving a clock enable signal, a storage latch coupled to receive the input clock signal and the clock enable signal and, in response, provide a clock gate control signal, and a logic gate coupled to receive the input clock signal and the clock gate control signal. The logic gate selectively passes the input clock signal in response to the clock gate control signal, thereby providing an output clock signal.

[0003] Document US 2012 / 0286824 A1 concerns a clock gate circuit for supplying either a clock signal or a predetermined gate value to a plurality of synchronous elements within an integrated circuit. The clock gate circuit is configured to receive a clock signal and output a signal containing either the clock signal or the predetermined gate value.The clock gate circuit unit receives a clock signal, a clock enable signal which either has an enable value indicating that the majority of synchronous elements are currently functional and should be clocked, or an undo value indicating that the majority of synchronous elements are currently not needed and should not be clocked, and a power mode signal which either has a low-power value indicating entry into a low-power mode in which at least some of the plurality of synchronous elements are energized to hold data and are not clocked, and at least another plurality of synchronous elements are energized, or a function mode value indicating that the plurality of synchronous elements should be energized.The clock gate unit has a logic circuit configured to output the clock signal in response to the enable signal with the enable value and the low-power mode signal with the function mode value, and to output the predetermined gate value in response to at least one of the enable signal with the block value and the low-power mode signal with the low-power value. Document US 7,265,599 B1 relates to an edge-triggered flip-flop that uses complex gates with weighted transistors to electrically isolate a master latch from data inputs before the master latch and a slave latch are electrically connected, and to electrically isolate the master latch from the slave latch before the master latch and the data inputs are electrically connected.Document US 2010 / 0174933 A1 concerns a method comprising the following steps: determining when a particular logic block is inactive, determining the power supply state of the particular logic block, isolating the particular logic block from a main processor core, and shutting down the particular logic block. A system execution includes software and a processor coupled with a clock control module, an isolation control module, and a head / foot module, which operate to isolate and shut down a particular logic block.

[0004] Document US 2014 / 0184271 A1 concerns an integrated clock gate cell in which a latch is coupled to a NOR gate. The NOR gate receives an enable signal. The latch is configured to produce a latch output in response to the state of the enable signal. A buffer contains a three-state inverter. A NAND gate is coupled to the latch, and the NAND gate is configured to produce an inverted clock signal in response to the latch output and a clock input.

[0005] Document US 2010 / 0109707 A1 concerns a clock gate cell containing a latch circuit, a comparator circuit, a first logic circuit, and a second logic circuit. An input signal is fed to the latch circuit. An input clock signal is fed to the first logic circuit. The first logic circuit switches the input clock signal based on a comparator signal generated by the comparator circuit, thereby generating a latch clock signal. The latch clock signal switches between a first state and a second state when the input signal switches between the first and second states.

[0006] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It is emphasized that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be enlarged or reduced arbitrarily for the sake of clarity. Fig. Figure 1 is a schematic representation of a cell with internal clock gating according to some embodiments of the present disclosure. Fig. 2 is a circuit diagram of the latch in Fig. 1 according to some embodiments of the present disclosure. Fig. Figure 3 is a detailed circuit diagram of the circuit described in Fig. 2 Latches shown according to some embodiments of the present disclosure. Fig. 4 is a detailed circuit diagram of the [device / system] in [section / document]. Fig. 2 Latches shown according to different embodiments of the present disclosure. Fig. Figure 5 is a timing diagram of various signals of the cell with internal clock gating. Fig. 1 according to some embodiments of the present disclosure. Fig. 6 and Fig. 7 are each a flowchart of a procedure that performs cell operations with internal clock-gating in Fig. 1 and of the latch in Fig. 4 according to some embodiments of the present disclosure. Fig. Figure 8 is a circuit diagram of the latch in Fig. 1 according to various embodiments of the present disclosure. Fig. Figure 9 is a detailed circuit diagram of the latch in Fig. 8 according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0008] The following disclosure provides many different embodiments or examples for implementing various features of the intended subject matter. Specific examples of components and arrangements are described subsequently for the sake of simplicity. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition serves for simplicity and clarity and does not itself establish any relationship between the various designs and / or configurations discussed.

[0009] The terms used in this patent specification generally have their usual meanings in the field and in the specific context in which each term is used. The use of examples in this patent specification, including examples of any terms discussed herein, serves only for illustration and in no way limits the scope and meaning of the disclosure or of any term explained. Likewise, the present disclosure is not limited to the various embodiments described in this patent specification.

[0010] Although the terms "first," "second," etc., may be used here to describe different elements, these elements should not be limited by these terms. The terms are used to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element, without altering the scope of the embodiments. As used here, the term "and / or" encompasses all combinations of one or more of the related points listed.

[0011] With increasing clock frequencies used in synchronous integrated circuit (IC) devices, dynamic power consumption is a constant concern. In some IC devices, the majority of dynamic power consumption is attributed to clock distribution networks. To reduce the dynamic power consumption of these networks, circuits with internal clock gating (ICG) are used, which perform selective gating of clock signals within the IC devices.

[0012] To illustrate, the circuit with internal clock gating selectively truncates the clock tree of an IC device by blocking portions of the clock tree when clock signals are not in use for certain circuits. Accordingly, circuit elements, including, for example, latches and / or flip-flops, associated with the blocked portions of the clock tree, do not switch between logic high and logic low states. Put another way, the circuit elements, including, for example, latches and / or flip-flops, are prevented from switching between different logic states. As a result, the dynamic power consumption of the IC device, caused by switching circuit elements between different logic states, is reduced.

[0013] Fig. Figure 1 is a schematic representation of a cell with internal clock gating 100 according to some embodiments of the present disclosure. As exemplified in Fig. As shown in Figure 1, the cell with internal clock gating 100 comprises a latch control circuit 110, a latch 120 and a logic circuit 130.

[0014] The latch control circuit 110 is configured to receive a test enable signal TE and an enable signal ES and to generate a latch enable signal EB in response to the test enable signal TE and the enable signal ES. In some embodiments, the latch control circuit 110 includes a NOR gate 112. The NOR gate 112 has inputs that receive the test enable signal TE and the enable signal ES and an output that is coupled to an input of the latch 120. The NOR gate 112 performs a NOR operation on the test enable signal TE and the enable signal ES and outputs the latch enable signal EB.

[0015] Latch 120 is configured to receive the latch enable signal EB and an input clock signal CP, and to generate a gating control signal Q in response to the latch enable signal EB and the input clock signal CP. In some embodiments, Latch 120 is implemented by a set / reset (SR) latch. Various types of latches for implementing Latch 120 are within the scope of this disclosure.

[0016] The logic circuit 130 is configured to receive the input clock signal CP and the gating control signal Q and to generate an output clock signal CPQ in response to the gating control signal Q and the input clock signal CP. To illustrate operation, the logic circuit 130 selectively passes the input clock signal CP on as the output clock signal CPQ in response to the gating control signal Q.

[0017] In some embodiments, the logic circuit 130 comprises a NAND gate 132 and an inverter 134. As shown, the NAND gate 132 has one input that receives the input clock signal CP and another input that is coupled to an output of the latch 120 and receives the gating control signal Q. The inverter 134 has one input that is coupled to an output of the NAND gate 132 and one output for outputting the output clock signal CPQ. In operation, the NAND gate 132 performs a NAND operation on the input clock signal CP and the gating control signal Q. Then, the inverter 134 performs a logic inversion operation on a signal from the output of the NAND gate 132 and accordingly outputs the output clock signal CPQ.

[0018] The configurations of the latch control circuit 110 and the logic circuit 130 are shown for illustrative purposes. Various logic gates for implementing the latch control circuit 110 and the logic circuit 130 are included within the planned scope of this disclosure.

[0019] Fig. Figure 2 is a circuit diagram of the Latch 120 in Fig. 1 according to some embodiments of the present disclosure. As in Fig. As shown in Figure 2, Latch 120 is an SR latch and comprises a pair of logic gates, which in some embodiments are complex logic gates, each configured to perform a complex logic function at multiple levels. In some embodiments, the complex logic gates are OR-AND-Invert (OAI) logic gates 210 and 220, as shown in Figure 2. Fig. Figure 2 is shown. Typically, an OAI logic gate executes complex logic functions on two levels, consisting of a combination of one or more OR gates followed by a NAND gate.

[0020] As in Fig. As shown in Figure 2, the OAI logic gates 210 and 220 are cross-coupled. The OAI logic gate 210 comprises three inputs. One input of an OR gate of the OAI logic gate 210 is connected to the output of a latch control circuit 110. Fig. One input of the OR gate of OAI logic gate 210 is coupled to receive the latch enable signal EB. The other input of the OR gate of OAI logic gate 210 is configured to receive the input clock signal CP. One input of a NAND gate of OAI logic gate 210 is coupled to an output of OAI logic gate 220 to receive an output signal QN from OAI logic gate 220.

[0021] Furthermore, the OAI logic gate 220 comprises three inputs. One input of an OR gate of the OAI logic gate 220 is coupled to an output of an inverter 230 to receive a logical complement of the latch enable signal EB, the signal EBN, from the inverter 230. The other input of the OR gate of the OAI logic gate 220 is configured to receive the input clock signal CP. One input of a NAND gate of the OAI logic gate 220 is coupled to an output of the OAI logic gate 210 to receive an output signal from the OAI logic gate 210. The output of the OAI logic gate 210 is further connected to the logic circuit 130 in Fig. 1 coupled to connect the gating control signal Q to the logic circuit 130 in Fig. to spend 1.

[0022] To illustrate operation, when the input clock signal CP and the latch enable signal EB are both at a logic low level, the output of the OR gate of OAI logic gate 210 is at a logic low level and is fed into the NAND gate of OAI logic gate 210. Furthermore, the output of the OR gate of OAI logic gate 220 is at a high-low level and is fed into the NAND gate of OAI logic gate 220. When an input is at a logic low level, the NAND gate of OAI logic gate 210 outputs the gating control signal Q, which is at a logic high level.

[0023] When the input clock signal CP goes to a logic high level and the latch enable signal EB remains at a logic low level, the output of the OR gate of OAI logic gate 210 is at a logic high level and is fed into the NAND gate of OAI logic gate 210. Furthermore, the output of the OR gate of OAI logic gate 220 remains at a high-low level. Under such conditions, there is no change at the inputs of the NAND gate of OAI logic gate 210. Accordingly, the gating control signal Q remains at a logic high level.

[0024] Then, when the input clock signal CP transitions from a logic high level to a logic low level, and the latch enable signal EB transitions from a logic low level to a logic high level, the output of the OR gate of OAI logic gate 210 is at a logic high level and is fed into the NAND gate of OAI logic gate 210. Furthermore, the output of the OR gate of OAI logic gate 220 is at a logic low level and is fed into the NAND gate of OAI logic gate 220. When an input is at a logic low level, the NAND gate of OAI logic gate 220 outputs the signal QN, which is at a logic high level. Upon receiving the logic-high output from the OR gate of the OAI logic gate 210 and the signal QN, which is at a logic-high level, the NAND gate of the OAI logic gate 210 outputs the gating control signal Q, which is at a logic-low level.

[0025] When the input clock signal CP transitions from a logic low to a logic high level, and the latch enable signal EB remains at a logic high level, the output of the OR gate of OAI logic gate 210 remains at a logic high level. Furthermore, the output of the OR gate of OAI logic gate 220 also remains at a logic high level. Under these conditions, there is no change at the output of the NAND gate of OAI logic gate 210. Consequently, the gating control signal Q remains at a logic low level.

[0026] The diagrams above illustrate exemplary operations in a sequence, but the operations are not necessarily performed in the order shown. Different sequences of operations for Latch 120 in Fig. 2. These are within the planned scope of the present disclosure. Furthermore, operations may be added, replaced, reordered and / or eliminated as needed, according to the nature and scope of different embodiments of the present disclosure.

[0027] Fig. Figure 3 is a detailed circuit diagram of the circuit described in Fig. Latch 120 shown in 2 according to some embodiments of the present disclosure. As exemplified in Fig. Figure 3 shows two header switches, which in some embodiments are PMOS transistors M1 and M2, with gates configured to receive the input clock signal CP. The sources of transistors M1 and M2 are connected to a voltage supply, which in some embodiments is VDD. Two footer switches, which in some embodiments are NMOS transistors M3 and M4, also have gates configured to receive the input clock signal CP. The sources of transistors M3 and M4 are connected to another voltage supply, which in some embodiments is ground. In such a configuration, transistors M1, M2, M3, and M4 are controlled by the input clock signal CP to be turned on and off.

[0028] Furthermore, a pair of switches, which in some embodiments are PMOS transistors M5 and M6, as in Fig. Figure 3 shows transistors coupled in series with transistors M1 and M2, respectively. A pair of switches, which in some embodiments are NMOS transistors M7 and M8, as shown in Figure 3, are connected in series with transistors M1 and M2, respectively. Fig. 3 shown, is coupled in parallel with transistors M3 and M4.

[0029] As shown, the source of transistor M5 is coupled to the drain of transistor M1, and the gate of transistor M5 is configured to receive the latch enable signal EB. The source of transistor M6 is coupled to the drain of transistor M2, and the gate of transistor M6 is coupled to the output of inverter 230 and receives the logic complement of the latch enable signal EB. The gate of transistor M7 is configured to receive the latch enable signal EB; the drain of transistor M7 is coupled to the drain of transistor M3, and the source of transistor M7 is, for example, coupled to ground. The gate of transistor M8 is configured to receive the logic complement of the latch enable signal EB; the drain of transistor M8 is coupled to the drain of transistor M4, and the source of transistor M8 is, for example, coupled to ground.In such a configuration, transistors M5 and M7 are controlled by the latch enable signal EB, and transistors M6 and M8 are controlled by the logical complement of the latch enable signal EB to switch on and off in operational readiness.

[0030] Furthermore, a pair of cross-coupled inverters 310 and 320 is coupled between transistors M5 and M6. As shown, inverter 310 comprises a pair of switches, which in some embodiments are PMOS transistor M9 and NMOS transistor M10. Inverter 320 additionally comprises a pair of switches, which in some embodiments are PMOS transistor M11 and NMOS transistor M12. The gates of transistors M9 and M10 are jointly coupled to the drains of transistors M11 and M12, which are coupled to the drain of transistor M6. The gates of transistors M11 and M12 are jointly coupled to the drains of transistors M9 and M10, which are coupled to the drain of transistor M5. The sources of transistors M9 and M11 are, for example, coupled to VDD. The source of transistor M10 is coupled to the drains of transistors M3 and M7. The source of transistor M12 is coupled to the drains of transistors M4 and M8.In such a configuration, the output of inverter 310 is configured as the input of inverter 320 and the output of inverter 320 is configured as the input of inverter 310.

[0031] In some embodiments of this document, at least one of the switches is implemented with at least one MOS transistor. In other embodiments, each of the at least one MOS transistor is implemented with stacked or cascaded MOS transistors. In various embodiments, each of the at least one MOS transistor is controlled by one or more control signals.

[0032] Furthermore, the MOS transistors used to implement the switches described in this document are shown for illustrative purposes. Various types of transistors for implementing the switches are within the scope of this disclosure. For example, in various embodiments, a bipolar junction transistor (BJT) is used to implement the switches shown in this document.

[0033] Fig. 4 is a detailed circuit diagram of the [device / system] in [section / document]. Fig. 2 illustrated latches 120 according to various embodiments of the present disclosure. With regard to the embodiments of Fig. 3 are identical elements in Fig. 4 is designated with the same reference symbols for better explanation.

[0034] Compared to those in Fig. The Latch 120 in the 3 illustrated embodiments comprises Fig. 4. Transistors M1 and M3 without transistors M2 and M4. In such embodiments, the drain of transistor M1 is coupled to the sources of transistors M5 and M6, and the drain of transistor M3 is coupled to the sources of transistors M10 and M12.

[0035] Furthermore, compared to the in Fig. 3 illustrated embodiments, the Latch 120 in Fig. 4. Furthermore, a pair of switches, which in some embodiments are NMOS transistors M13 and M14. As shown, transistors M5, M13 and M7 are coupled in series with transistor M1, and transistors M6, M14 and M8 are coupled in series with transistor M1.

[0036] As in Fig. As shown in Figure 4, transistor M13 is connected in series between transistors M5 and M7. The drain of transistor M13 is connected to the drain of transistor M5, and the source of transistor M13 is connected to the drain of transistor M7. Furthermore, transistor M14 is connected in series between transistors M6 and M8. The drain of transistor M14 is connected to the drain of transistor M6, and the source of transistor M14 is connected to the drain of transistor M8.

[0037] Additionally, the gates of transistors M13 and M14 are coupled to the outputs of inverters 310 and 320, respectively. As shown, the gates of transistors M9, M10, and M13 are coupled together to the drains of transistors M11 and M12. The gates of transistors M11, M12, and M14 are coupled together to the drains of transistors M9 and M10. In such configurations, transistor M13 is controlled by the output of inverter 320, represented as node QN in [reference missing]. Fig. 4, and transistor M14 is controlled by the output of inverter 310, represented as node Q in Fig. 4.

[0038] The configuration of the Latch 120 is in Fig. Figure 4 is shown for illustration. Different configurations of the Latch 120 in Fig. 4 are within the planned scope of the present disclosure. For example, in various embodiments, the Latch 120 comprises Fig. 4 the transistors M1 and M3 and further includes the one in Fig. 3 shown transistor M2. In further embodiments, the latch comprises 120 in Fig. 4 the transistors M1 and M3 and further includes the one in Fig. 3 transistor M4 shown. In alternative embodiments, the latch comprises 120 in Fig. 4 the transistors M1 and M3 and further includes the in Fig. 3 transistors M2 and M4 shown.

[0039] Fig. Figure 5 is a timing diagram of various signals of the cell with internal clock gating 100 in Fig. 1 according to some embodiments of the present disclosure. Fig. 6 and Fig. Figure 7 is a flowchart of a procedure 600, which describes operations of the cell with internal clock gating 100. Fig. 1 and the Latch 120 in Fig. 4 according to some embodiments of the present disclosure shows. The method 600 in Fig. 6 and Fig. Section 7 includes operations S602-S624, which are subsequently described for illustration purposes with reference to Fig. 1, Fig. 4 and Fig. 5 are described.

[0040] For the sake of simplicity, in the following operations the logic high level or high voltage level of the signals and nodes is referred to as logic "1" and the logic low level or low voltage level of the signals and nodes is referred to as logic "0".

[0041] First, at time T0 in Fig. 5 the cell with internal clock gating 100 in Fig. 1 is configured in the locked state, in which the input clock signal CP and the output clock signal CPQ are both at logical "0". Between time T0 and time T1, the latch enable signal EB does not affect any other signals of the cell with internal clock gating 100.

[0042] In Operation S602, at time T1 in Fig. 5. The cell with internal clock gating 100 changes from a locked state to an enabled state. As in Fig. As shown in Figure 5, the latch enable signal EB of the cell with internal clock gating 100 is presented and goes to a logic "0" at time T1 and is stable for an establishment time Tsu (not labeled). In some embodiments, the establishment time Tsu represents a minimum duration for which the latch enable signal EB is valid before the input clock signal CP changes its logic state, for example, from a logic "0" to a logic "1".

[0043] Although the latch enable signal EB presented to the cell with internal clock gating 100 is set to be stable at least for the establishment time Tsu before the clock edge, it is not limited to the latch enable signal EB arriving at earlier times. Various timing configurations for presenting the latch enable signal EB are within the planned scope of this disclosure.

[0044] At time T2 in Fig. In operation S604, the latch enable signal EB is stable at logical "0", and the input clock signal CP is also stable at logical "0". Fig. As shown in Figure 4, transistor M1 is switched on according to the input clock signal CP, and transistor M5 is switched on according to the latch enable signal EB. Transistor M8 is switched on by inverter 230 according to the complement of the latch enable signal EB. When both transistors M1 and M5 are switched on, node Q (which also displays the gating control signal Q) is in Fig. 4 is pulled up to VDD. Based on node Q being pulled up to VDD, transistor M14 is also turned on, causing node QN (which also displays the output signal QN) to be in Fig. 4 is pulled down to the mass.

[0045] If node Q in Fig. When VDD is pulled down to 4, the gating control signal Q goes into Fig. 5 at time T2 becomes a logical "1". In other words, Latch 120 in Fig. NAND gate 1 outputs a logical "1" as the gating control signal Q. If the input clock signal CP is a logical "0" and the gating control signal Q is a logical "1", the NAND gate 132 outputs a logical "1". Fig. 1 outputs a logical "1" signal. In response to the signal output by NAND gate 132, inverter 134 outputs the CPQ clock signal, a logical "0", as shown in Fig. 5 shown.

[0046] Operation S606 begins at time T3 in Fig. 5 the input clock signal CP from a logical “0” to a logical “1” and the latch enable signal EB remains at a logical “0”.

[0047] At time T4 in Fig. In operation S608, the latch enable signal EB remains at a logical "0" and the input clock signal CP is stable at a logical "1". Fig. As shown in Figure 4, transistor M3 is switched on according to the input clock signal CP. Furthermore, if node Q previously operated at a logic "1" and node QN previously operated at a logic "0", transistor M9 is switched on according to node QN's logic "0", and transistor M12 is switched on according to node Q's logic "1". Transistor M14 is also switched on according to node Q's logic "1". Additionally, transistor M8 is switched on by inverter 230 according to the logic complement of the latch enable signal EB, which is at logic "0". Node Q is effectively latched at a logic "1", and node QN is latched at a logic "0".

[0048] Based on the prediction, the in Fig. Figure 5 shows the gating control signal Q at time T4 at a logic "1". With the input clock signal CP at a logic "1" and the gating control signal Q at a logic "1", the NAND gate 132 outputs Fig. 1 outputs a logical "0" signal. In response to the signal output by NAND gate 132, inverter 134 outputs Fig. 1 the output clock signal CPQ, which goes to a logical "1", as in Fig. 5 shown.

[0049] At time T5 in Fig. In step 5, the input clock signal CP remains at a logic "1" and the gating control signal Q is locked at a logic "1". Accordingly, the output of NAND gate 132 remains at Fig. 1 at a logical "0" and the inverter 134 in Fig. 1 outputs the CPQ clock signal, which is stable at a logical "1", as shown in Fig. 5 shown.

[0050] When the gating control signal Q is locked at a logic "1", the latch release signal EB does not affect any other signals, including the gating control signal Q and the output clock signal CPQ of the cell with internal clock gating 100. As in Fig. As shown in Figure 5, the latch enable signal EB is irrelevant for the operation of latch 120 between time T5 and time T1'.

[0051] Operation S610 begins at time T6 in Fig. 5 the input clock signal CP from a logical “1” to a logical “0”, which leads to a change in the output clock signal CPQ at time T7.

[0052] At time T7 in Fig. In operation S612, with the input clock signal CP being a logical "0" and the gating control signal Q remaining at a logical "1", the NAND gate 132 outputs... Fig. 1 outputs a logical "1" signal. In response to the signal output by NAND gate 132, inverter 134 outputs Fig. 1 the output clock signal CPQ, which goes to a logical “0”, as in Fig. 5 shown.

[0053] At time T8 in Fig. At time 5, the input clock signal CP remains at a logical "0". The output clock signal CPQ is stable at a logical "0" due to the operations at time T7. With the input clock signal CP of a logical "0", NAND gate 132 outputs Fig. Inverter 1 outputs a logical "1" signal, regardless of the logic of the gating control signal Q. Accordingly, inverter 134 outputs... Fig. 1 the output clock signal CPQ a logical “0”, as in Fig. 5 is shown, where the gating control signal Q is irrelevant for the output clock signal CPQ. As in Fig. As shown in Figure 5, the gating control signal Q between time T8 and time T2' is irrelevant for the output clock signal CPQ.

[0054] In Operation S614, at time T1', in Fig. 5 the input clock signal CP at a logical “0” and the latch enable signal EB goes to a logical “1”, so that it is stable for the setup time Tsu as described above.

[0055] At time T2' in Fig. In operation S616, as in... Fig. As shown in Figure 4, transistor M1 is switched on according to the input clock signal CP, and transistor M7 is switched on according to the latch enable signal EB. Transistor M6 is switched on by inverter 230 according to the complement of the latch enable signal EB. When both transistors M1 and M6 are switched on, node QN is in Fig. 4 is pulled up to VDD. Since node QN is pulled up to VDD, transistor M10 is also switched on, which causes node Q to be in Fig. 4 is pulled down to the mass.

[0056] If node Q in Fig. When 4 is pulled down to ground, the gating control signal Q goes into Fig. 5 at time T2' to the logical "0". In other words, Latch 120 in Fig. 1 outputs the gating control signal Q at a logical "0". If the input clock signal CP is at a logical "0" and the gating control signal Q is at a logical "0", the NAND gate 132 outputs Fig. 1 outputs a logical "1" signal. In response to the signal output by NAND gate 132, inverter 134 outputs the CPQ clock signal, a logical "0", as shown in Fig. 5 shown.

[0057] Operation S618 begins at time T3' in Fig. 5 the input clock signal CP from a logical “0” to a logical “1” and the latch enable signal EB remains at a logical “1”.

[0058] At time T4' in Fig. In operation S620, the latch enable signal EB remains at a logical "1" and the input clock signal CP is stable at a logical "1". Fig. As shown in Figure 4, transistor M3 is switched on according to the input clock signal CP. Furthermore, if node Q was previously operating at a logic "0" and node QN was previously operating at a logic "1", transistor M10 is switched on according to node QN's logic "1", and transistor M11 is switched on according to node Q's logic "0". Transistor M13 is also switched on according to node QN's logic "1". Additionally, transistor M6 is switched on by inverter 230 according to the logic complement of the latch enable signal EB, which is at a logic "0". Node Q is effectively latched at a logic "0", and node QN is latched at a logic "1".

[0059] Based on the prediction, the situation remains unchanged. Fig. Figure 5 shows the gating control signal Q at time T4' at a logical "0". With the input clock signal CP at a logical "1" and the gating control signal Q at a logical "0", the NAND gate 132 outputs Fig. 1 outputs a logical "1" signal. In response to the signal output by NAND gate 132, inverter 134 outputs Fig. 1 the output clock signal CPQ, which goes to a logical “0”, as in Fig. 5 shown.

[0060] At time T5' in Fig. In step 5, the input clock signal CP remains at a logical "1" and the gating control signal Q is locked at a logical "0". Accordingly, the output of NAND gate 132 remains at Fig. 1 with a logical "1" and the inverter 134 in Fig. 1 outputs the CPQ clock signal, which is stable at a logical "0", as shown in Fig. 5 shown.

[0061] When the gating control signal Q is locked at a logic "0", the latch release signal EB does not affect any other signals, including the gating control signal Q and the output clock signal CPQ of the cell with internal clock gating 100. As in Fig. As shown in Figure 5, the latch enable signal EB is irrelevant for the operation of latch 120 between time T5' and time T7'.

[0062] Operation S622 begins at time T6' in Fig. 5 the input clock signal CP from a logical “1” to a logical “0”.

[0063] At time T7' in Fig. In operation S612, with the input clock signal CP at a logical "0" and the gating control signal Q at a logical "0", the NAND gate 132 outputs... Fig. 1 outputs a logical "1" signal. In response to the signal output by NAND gate 132, inverter 134 outputs Fig. 1 the output clock signal CPQ, which goes to a logical “0”, as in Fig. 5 shown.

[0064] As described above, there are only a few transistors that switch or change their state in response to the input clock signal CP. As in Fig. 1 and Fig. Figure 4 shows that when the enable signal ES is at logic "0", transistors M1 and M3 are switched on. Fig. 4 and two transistors of the NAND gate 132 in Fig. 1 is switched in response to the input clock signal CP. With the reduced number of devices that are switched when the enable signal ES is at logic "0", the energy consumption of the cell with internal clock gating 100 is reduced accordingly.

[0065] Additionally, due to the configurations and operations of Latch 120 shown above, Latch 120 is capable of functionally guiding and locking the signal by, for example, using the rising or falling edge of the input clock signal CP. In other words, Latch 120 is capable of functionally guiding and locking the signal using a phase of the input clock signal CP.

[0066] Compared to some methods that use a latch with an internal clock inverter to operate with two phases of a clock signal, the internal clock inverter in the Latch 120 shown in this document is unnecessary. Without the internal clock inverter used in related methods, the power consumption of the Latch 120 can be reduced and its operating speed improved.

[0067] The above illustrations depict exemplary operations in a sequence, but the operations are not necessarily performed in the order shown. Different sequences of the operations shown are possible. Fig. 6 and Fig. The operations described in section 7 are within the planned scope of this disclosure. Furthermore, operations may be added, replaced, reordered, and / or eliminated as needed, depending on the nature and scope of different embodiments of this disclosure.

[0068] Fig. Figure 8 is a circuit diagram of the Latch 120 in Fig. 1 according to various embodiments of the present disclosure. As in Fig. As shown in Figure 8, the Latch 120 is an SR latch. Compared to the embodiments in Figure 8, the following applies: Fig. 2 includes the Latch 120 in Fig. 8 a pair of logic gates, which in some embodiments are complex logic gates, each of which is capable of performing a complex logic function at multiple levels. In some embodiments, the AND-OR-Invert (AOI) logic gates are logic gates 810 and 820, as in Fig. Figure 8 illustrates this. Typically, an AOI logic gate, configured from a combination of one or more AND gates followed by a NOR gate, performs complex logic functions at two levels.

[0069] As in Fig. As shown in Figure 8, the AOI logic gates 810 and 820 are cross-coupled. The AOI logic gate 810 comprises three inputs. One input of an AND gate of the AOI logic gate 810 is connected to the output of the latch control circuit 110 in Figure 8. Fig. One input of the AND gate of the AOI logic gate 810 is coupled to receive the latch enable signal EB. The other input of the AND gate of the AOI logic gate 810 is configured to receive a logical complement of the input clock signal CP from an inverter 830. One input of a NOR gate of the AOI logic gate 810 is coupled to an output of the AOI logic gate 820 to receive an output signal QN from the AOI logic gate 820.

[0070] Furthermore, the AOI logic gate 820 comprises three inputs. One input of an AND gate of the AOI logic gate 820 is coupled to the output of inverter 230 to receive the logical complement of the latch enable signal EB, the signal EBN, from inverter 230. The other input of the AND gate of the AOI logic gate 820 is configured to receive the logical complement of the input clock signal CP. One input of a NOR gate of the AOI logic gate 820 is coupled to an output of the AOI logic gate 810 to receive an output signal from the AOI logic gate 810. The output of the AOI logic gate 810 is further connected to logic circuit 130 in Fig. 1 coupled to connect the gating control signal Q to the logic circuit 130 in Fig. to spend 1.

[0071] The configurations of the in Fig. 2 and Fig. The eight logic gates shown are for illustrative purposes. Various logic gates for implementing Latch 120 are included in the planned scope of this disclosure.

[0072] Fig. Figure 9 is a detailed circuit diagram of the Latch 120 in Fig. 8 according to some embodiments of the present disclosure. With regard to the embodiments of Fig. Four are the same elements for better understanding. Fig. 9 with the same reference symbols. Compared with Fig. 4, as in Fig. As illustrated in Figure 9, the gates of transistors M1 and M3 are coupled to the output of inverter 830, which receives the input clock signal CP. Furthermore, compared to Fig. 4. The sources of transistors M5 and M6, for example, are coupled to VDD. Additionally, compared to... Fig. 4 the transistors M13 and M14 in the in Fig.The nine illustrated embodiments are PMOS transistors. Transistor M13 is coupled in series between transistors M5 and M7, with its source coupled to the drain of transistor M5 and its drain coupled to the drain of transistor M7. Transistor M14 is coupled in series between transistors M6 and M8, with its source coupled to the drain of transistor M6 and its drain coupled to the drain of transistor M8.

[0073] In this document, the term "coupled" can also mean "electrically coupled," and the term "connected" can also mean "electrically connected." "Coupled" and "connected" can also be used to indicate that two or more elements work together or interact with each other.

[0074] In some embodiments, a circuit is disclosed that includes a latch and a logic circuit. The latch is configured to generate a gating control signal in response to a latch enable signal and an input clock signal. The latch includes a pair of logic gates, each configured to perform a complex, multi-level logic function. The logic circuit is configured to receive the gating control signal and the input clock signal and to generate an output clock signal in response to the gating control signal and the input clock signal.

[0075] A circuit is also disclosed comprising a latch control circuit, a latch, and a logic circuit. The latch control circuit is configured to generate a latch enable signal in response to a test enable signal and an enable signal. The latch is configured to generate a gating control signal in response to the latch enable signal and an input clock signal. The latch includes a pair of logic gates, each configured to perform a complex, multi-level logic function. The logic circuit is configured to selectively route the input clock signal as an output clock signal in response to the gating control signal.

[0076] Likewise, a method is disclosed that includes the following operations: In response to an input clock signal and a latch enable signal, a gating control signal is generated by a latch, wherein the latch comprises a pair of logic gates, each configured to perform a complex logic function at multiple levels. In response to the gating control signal, the input clock signal is selectively passed as an output clock signal through a logic circuit.

Claims

[1] Circuit comprising: a latch (120) configured to generate a gating control signal (Q) in response to a latch enable signal (EB) and an input clock signal (CP), wherein the latch (120) has a pair of logic gates (210, 220) each configured to perform a complex logic function at multiple levels; and a logic circuit (130) configured to receive the gating control signal (Q) and the input clock signal (CP) and to generate an output clock signal (CPQ) in response to the gating control signal (Q) and the input clock signal (CP), where the logic gates (210, 220) are: at least one header switch (M1) and at least one footer switch (M3), each configured to be controlled by the input clock signal (CP); a first (M5), a second (M13) and a third switch (M7) which are coupled in series with at least one header switch (M1); a fourth (M6), a fifth (M14) and a sixth switch (M8) coupled in series with at least one header switch (M1); and a pair of cross-coupled inverters (310, 320) coupled to at least one footer switch (M3), wherein the second (M13) and fifth switches (M14) are configured to be controlled by outputs of the inverters (310, 320); wherein the first (M5) and third switches (M7) are configured to be controlled by the latch release signal (EB), and the fourth (M6) and sixth switches (M8) are configured to be controlled by a logical complement of the latch release signal (EB). [2] Circuit according to claim 1, wherein the at least one footer switch (M3), at least one header switch (M1), the first (M5), the second (M13), the third (M7), the fourth (M6), the fifth (M14) and the sixth switch (M8) and the pair of cross-coupled inverters (310, 320) are configured to provide: a pair of OR-AND-Invert, OAI, logic gates. [3] Circuit according to claim 1, wherein the at least one footer switch (M3), at least one header switch (M1), the first (M5), the second (M13), the third (M7), the fourth (M6), the fifth (M14) and the sixth switch (M8) and the pair of cross-coupled inverters (310, 320) are configured to provide: two OR-AND inverting logic gates (OAI) that are cross-coupled; wherein one of the OAI logic gates is configured to receive the input clock signal (CP) and the latch enable signal (EB) and output the gating control signal (Q) and the other of the OAI logic gates is configured to receive the input clock signal (CP) and a logical complement of the latch enable signal (EB). [4] Circuit according to one of claims 1 to 3, wherein the at least one header switch (M1) and the at least one footer switch (M3), each of which is configured to be controlled by a logical complement of the input clock signal (CP). [5] Circuit, comprising: a latch control circuit (110) configured to generate a latch enable signal (EB) in response to a test enable signal (TE) and an enable signal (ES); a latch (120) configured to generate a gating control signal (Q) in response to the latch enable signal (EB) and an input clock signal (CP), wherein the latch (120) comprises a pair of logic gates (210, 220) each configured to perform a complex logic function at multiple levels; and a logic circuit (130) configured to selectively route the input clock signal (CP) as the output clock signal (CPQ) in response to the gating control signal (Q), wherein the logic gates (210, 220) have: a first (M5), a second (M13) and a third switch (M7) coupled in series with at least one footer switch (M3) configured to be controlled by a logical complement of the input clock signal (CP); a fourth (M6), a fifth (M14) and a sixth switch (M8) coupled in series with at least one footer switch (M3); and a pair of cross-coupled inverters coupled to at least one header switch (M1), wherein the second (M13) and fifth switches (M14) are configured to be controlled by outputs of the inverters; wherein the first (M5) and third switches (M7) are configured to be controlled by the latch release signal (EB), and the fourth (M6) and sixth switches (M8) are configured to be controlled by a logical complement of the latch release signal (EB). [6] Circuit according to claim 5, wherein the logic gates (210, 220) comprise OR-AND-Invert, OAI, logic gates or AND-OR-Invert, AOI, logic gates. [7] Circuit according to claim 5 or claim 6, wherein one of the logic gates (210, 220) is configured to receive the latch enable signal (EB) and a logical complement of the input clock signal (CP) and to output the gating control signal (Q) and the other of the logic gates (210, 220) is configured to receive a logical complement of the latch enable signal (EB) and the logical complement of the input clock signal (CP). [8] Circuit according to one of claims 5 to 7, wherein the at least one footer switch (M3) and the at least one header switch (M1) are further configured to be controlled by the received input clock signal (CP). [9] Circuit according to any one of claims 5 to 8, wherein the latch control circuit (110) has a NOR gate with inputs configured to receive the test enable signal (TE) and the enable signal (ES). [10] Circuit according to any one of claims 5 to 9, wherein the logic circuit comprises: a NAND gate with inputs configured to receive the gating control signal (Q) and the input clock signal (CP); and an inverter with an input coupled to an output of the NAND gate and an output configured to output the output clock signal (CPQ). [11] Methods, comprising: In response to an input clock signal (CP) and a latch enable signal (EB), a latch (120) generates a gating control signal (Q), wherein the latch (120) has a pair of logic gates (210, 220) each configured to perform a complex logic function at multiple levels; and In response to the gating control signal (Q), the input clock signal (CP) is selectively passed through a logic circuit (130) as an output clock signal (CPQ). where the logic gates (210, 220) are: at least one header switch (M1) and at least one footer switch (M3), each configured to be controlled by the input clock signal (CP); a first (M5), a second (M13) and a third switch (M7) which are coupled in series with at least one header switch (M1); a fourth (M6), a fifth (M14) and a sixth switch (M8) coupled in series with at least one header switch (M1); and a pair of cross-coupled inverters (310, 320) coupled to at least one footer switch (M3), wherein the second (M13) and fifth switches (M14) are configured to be controlled by outputs of the inverters (310, 320); wherein the first (M5) and third switches (M7) are configured to be controlled by the latch release signal (EB), and the fourth (M6) and sixth switches (M8) are configured to be controlled by a logical complement of the latch release signal (EB). [12] Method according to claim 11, wherein the logic gates (210, 220) comprise OR-AND-Invert (OAI) logic gates. [13] Method according to claim 11 or 12, wherein the logic circuit (130) comprises: a NAND gate with inputs configured to receive the gating control signal (Q) and the input clock signal (CP); and an inverter with an input coupled to an output of the NAND gate and an output configured to output the output clock signal (CPQ). [14] Method according to any one of claims 11 to 13, wherein the latch (120) is a set / reset SR latch.

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