Method for operating a semiconductor device

Abstract

A method of operating a semiconductor device, comprising: receiving a video stream (10) comprising a first frame, a second frame, a third frame and a fourth frame encoded in a hierarchical manner, wherein the first frame and the third frame are classified as a first level, and the second frame and the fourth frame are classified as a second level; where the first frame is a parent frame of the second frame, and the third frame is a parent frame of the fourth frame, where the first frame, the second frame, the third frame and the fourth frame are in chronological order; decoding the first frame and the third frame in a chronological order; storing the decoded first frame and the decoded third frame in a decoded frame buffer (DPB (200)) in chronological order; decoding the fourth frame; storing the decoded fourth frame in the DPB (200); displaying the fourth frame by reading the DPB (200); decoding the second frame after displaying the fourth frame; and overwriting the fourth frame in the DPB with the second frame after the fourth frame has been displayed.

Description

TECHNICAL FIELD

[0001] Example embodiments of the present disclosure relate to a method of operating a semiconductor device. DISCUSSION OF THE STATE OF THE ART

[0002] An encoded digital video stream may comprise a plurality of groups of pictures (GOPs), each of which comprises one or more video frames. Typically, random access is possible among GOPs, whereas sequential access is performed among video frames. Since sequential access takes longer than random access when searching, video frames of a video stream may be encoded in a hierarchical manner.

[0003] US 2014 / 0 185 681 A1 discloses a method for encoding a video sequence in a scalable video encoder to generate a scalable bitstream, comprising encoding the video sequence in a first-layer encoder of the scalable video encoder to generate a first sub-bitstream, encoding the video sequence in a second-layer encoder of the scalable video encoder to generate a second sub-bitstream, wherein portions of the video sequence encoded in the second-layer encoder are predicted using reference portions of the video sequence encoded in the first-layer encoder, combining the first sub-bitstream and the second sub-bitstream in the scalable bitstream, and signaling an indication of a highest temporal level of the first sub-bitstream comprising at least one of the reference portions in the scalable bitstream.

[0004] US 2001 / 0 005 398 A1 discloses that a decoded image and parameters of a sequence level, a GOP level, and an image level for displaying the decoded image are stored as a set in each of the image banks and parameter banks of a frame memory. The parameters of each level are read out, which are stored as a set with an immediately previously decoded image. Parameters attached to an image to be decoded are overwritten during decoding. In this way, the parameters of each level are generated, which are stored as a set with the image to be decoded.

[0005] US 6,154,603 A discloses a method for image decoding and display in an apparatus for reproducing a digital disc. The method comprises the steps of converting a digitally encoded signal from the disc, storing the digitally encoded signal in a first memory, decoding the digitally encoded signal to generate an image, storing the image in a second memory, and extracting the image from the second memory for display. Controlling the storage in the second memory and the coupling for display occurs substantially simultaneously. SUMMARY

[0006] Exemplary embodiments of the present disclosure provide a method of operating a semiconductor device by which decoding and reverse playback can be efficiently performed on a video stream encoded in a hierarchical manner.

[0007] The invention is defined in the appended independent claims. Further developments of the invention are specified in the dependent claims.

[0008] According to an exemplary embodiment of the present disclosure, a method of operating a semiconductor device comprises receiving a video stream comprising a first frame, a second frame, a third frame, and a fourth frame encoded in a hierarchical manner, wherein the first frame and the third frame are classified as a first level, and the second frame and the fourth frame are classified as a second level; wherein the first frame is a parent frame of the second frame, and the third frame is a parent frame of the fourth frame, wherein the first frame, the second frame, the third frame, and the fourth frame are in a chronological order; decoding the first frame and the third frame in a chronological order; storing the decoded first frame and the decoded third frame in a decoded frame buffer (DPB (200)) in chronological order;decoding the fourth frame; storing the decoded fourth frame in the DPB (200); displaying the fourth frame by reading the DPB (200); decoding the second frame after displaying the fourth frame; and overwriting the fourth frame in the DPB with the second frame after the fourth frame has been displayed.

[0009] According to an exemplary embodiment of the present disclosure, a method of operating a semiconductor device comprises receiving a video stream (10) comprising a plurality of groups of pictures (GOPs) encoded in a hierarchical manner; storing the video stream (10) in a first memory area; retrieving a first GOP, which is the most recent one of the plurality of GOPs, from the video stream (10) stored in the first memory area, wherein the first GOP comprises a first frame, a second frame, a third frame, and a fourth frame, wherein the first frame and the third frame are classified as a first level and the second and fourth frames are classified as a second level; wherein the first frame is a parent frame of the second frame, and the third frame is a parent frame of the fourth frame;wherein the first frame, the second frame, the third frame, and the fourth frame are in a chronological order; decoding the first frame and the third frame in a chronological order; storing the decoded first frame and the decoded third frame in a second memory area; decoding the fourth frame; storing the decoded fourth frame in the second memory area; displaying the fourth frame by reading the second memory area; decoding the second frame after displaying the fourth frame; overwriting the fourth frame in the second memory area with the second frame after the fourth frame has been displayed; and retrieving a second GOP, which is a second-most recent one of the plurality of GOPs, from the video stream (10) stored in the first memory area.

[0010] According to an exemplary embodiment of the present disclosure, a method of operating a semiconductor device comprises receiving a video stream (10) comprising a first frame, a second frame, a third frame, a fourth frame, a fifth frame, and a sixth frame encoded in a hierarchical manner, wherein the first frame and the third frame are classified as a first level, the second frame and the fourth frame are classified as a second level, and the fifth frame and the sixth frame are classified as a third level; wherein the first frame, the second frame, the fifth frame, the third frame, the sixth frame, and the fourth frame are in a chronological order; wherein the first frame is a parent frame of the second frame, and the third frame is a parent frame of the fourth frame;the second frame is a parent frame of the fifth frame, and the fourth frame is a parent frame of the sixth frame; decoding the first frame and the third frame in a chronological order; storing the decoded first frame and the decoded third frame in a decoded frame buffer (DPB (200)) in a chronological order; decoding the second frame and the fourth frame; storing the decoded second frame and the decoded fourth frame in the DPB (200); decoding the sixth frame; storing the decoded sixth frame in the DPB (200); retrieving the fifth frame; determining whether the second frame, a hierarchical parent frame of the fifth frame, is stored in the DPB (200); decoding the fifth frame if the hierarchical parent frame is stored in the DPB (200);and decoding the hierarchical parent frame and subsequently decoding the fifth frame and storing the fifth frame in the DPB (200) if the second frame is not stored in the DPB (200), wherein the fifth frame overwrites the sixth frame stored in the DPB (200) after it has been decoded and the sixth frame has been displayed; BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other features of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which: Fig. 1 is a block diagram schematically illustrating a semiconductor system according to an exemplary embodiment of the present disclosure. Fig. 2 is a block diagram schematically illustrating a semiconductor system according to an exemplary embodiment of the present disclosure. Fig. 3 is a diagram schematically illustrating an encoded video stream used in various exemplary embodiments of the present disclosure. Fig. 4 is a view schematically illustrating an exemplary operation of a semiconductor device according to an exemplary embodiment of the present disclosure. Fig. 5 is a diagram illustrating a design scheme of the decoded frame buffer (DPB) which varies depending on the operation of the semiconductor device described above with reference to Fig. 4 according to an exemplary embodiment of the present disclosure. Fig. 6 is a view schematically illustrating an exemplary operation of a semiconductor device according to an exemplary embodiment of the present disclosure. Fig. Fig. 7 is a diagram illustrating a design scheme of the decoded frame buffer (DPB) which varies depending on the operation of the semiconductor device described above with reference to Fig. 6 according to an exemplary embodiment of the present disclosure. Fig. 8 is a view schematically illustrating an exemplary operation of a semiconductor device according to an exemplary embodiment of the present disclosure. Fig. 9A and Fig. 9B are diagrams illustrating design schemes of the DPB which vary depending on the operation of the semiconductor device described above with reference to Fig. 8 according to exemplary embodiments of the present disclosure. Fig. 10 is a view schematically illustrating an exemplary operation of a semiconductor device according to an exemplary embodiment of the present disclosure. Fig. 11A to 11C are diagrams illustrating design schemes of the DPB which vary depending on the operation of the semiconductor device described above with reference to Fig. 10 according to exemplary embodiments of the present disclosure. Fig. 12 is a flowchart illustrating a method of operating a semiconductor device according to an exemplary embodiment of the present disclosure. Fig. 13 is a block diagram of an electronic system that may employ the method of operating a semiconductor device and a semiconductor system according to any of the exemplary embodiments of the present disclosure. Fig. 14 to 16 show examples of semiconductor systems that may employ the method of operating a semiconductor device according to example embodiments of the present disclosure. DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

[0012] Example embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals may refer to like elements throughout the accompanying drawings.

[0013] It will be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Accordingly, a first element, component, region, layer, or section discussed below could be referred to as a second element, component, region, layer, or section without departing from the teachings of the inventive concept.

[0014] When used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0015] It will be understood that when an element or layer is referred to as being "on", "connected to", "coupled to", or "adjacent to" another element or layer, it may be directly on, connected to, coupled to, or adjacent to the other element or layer, or intervening elements or layers may be present.

[0016] As is traditional in the field of inventive concepts, exemplary embodiments are described and illustrated in the drawings in units of functional blocks, units, and / or modules. Those skilled in the art will appreciate that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring interconnects, etc., which may be formed using semiconductor-based manufacturing techniques or other manufacturing technologies.In the case of blocks, units, and / or modules implemented by microprocessors or the like, they may be programmed using software (microcode) to perform various functions discussed herein and may optionally be operated by firmware and / or software. Alternatively, each block, unit, and / or module may be implemented by dedicated hardware or as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and dedicated circuits) to perform other functions. Likewise, each block, unit, and / or module of the exemplary embodiments may be physically separated into two or more interacting and discrete blocks, units, and / or modules without departing from the scope of the inventive concept.Furthermore, the blocks, units and / or modules of the exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0017] It should be understood that the present inventive concept may be implemented in various forms of hardware, software, firmware, special-purpose processors, or a combination thereof. In one embodiment, the present inventive concept may be implemented in software as program instructions tangibly embodied on a computer-readable storage medium. The program instructions may be executable by a processor to cause the processor to perform operations according to exemplary embodiments of the present disclosure.

[0018] Example embodiments of the present disclosure provide a semiconductor system capable of efficiently decoding video frames encoded in a hierarchical manner at the time of reverse playback of an encoded video stream, and capable of allowing reverse playback on a display device.

[0019] Fig. 1 is a block diagram schematically illustrating a semiconductor system according to an exemplary embodiment of the present disclosure.

[0020] Referring to Fig. 1, a semiconductor system 1 according to an exemplary embodiment of the present disclosure may include an input unit 50 (e.g., an input circuit 50), a decoder 100, an output unit 150 (e.g., an output circuit 150), and a decoded picture buffer (DPB) 200.

[0021] The input unit 50 is, for example, an input interface that receives an encoded video stream 10. The input unit 50 provides the encoded video stream 10 to the decoder 100. In exemplary embodiments, the input unit 50 may include a buffer for storing (e.g., temporarily storing) at least a portion of the encoded video stream 10. The input unit 50 may divide the encoded video stream 10 into segments, called, for example, groups of pictures (GOPs), and may provide the GOPs to the decoder 100. Accordingly, the encoded video stream 10 may include a plurality of groups of pictures (GOPs), each of which may include a predetermined number of frames.

[0022] In this exemplary embodiment, the encoded video stream 10 comprises a video stream including a plurality of frames encoded in a hierarchical manner. Encoding a plurality of frames in a hierarchical manner will be briefly described herein. Some of a plurality of frames included in a video stream that are encoded first are referred to as parent frames (also referred to herein as reference frames). Some other frames, which are subsequently encoded according to the hierarchical structure, are referred to as child frames. The parent / reference frames and the child frames form a hierarchical tree structure in which child frames are linked to the respective parent frames at the same level. The encoding order is determined according to the hierarchical structure.

[0023] For example, if a video stream includes eight frames F0 to F7 arranged in chronological order, sequential encoding refers to encoding the frames in the order from frame F0 to frame F7. In contrast, in an example in which encoding is performed in a hierarchical manner, frame F0 is referred to as a parent / reference frame of frames F1 to F3, and frame F4 is referred to as a parent / reference frame of frames F5 to F7. Frames F0 and F4 are referred to as the same level (e.g., a first level). Hereinafter, the first level may also be referred to as a first hierarchical level or a first level.

[0024] Hereinafter, frame F2 is referred to as a parent / reference frame of frames F1 and F3, and frame F6 is referred to as a parent / reference frame of frames F5 and F7. Frames F2 and F6 are referred to as the same level (e.g., second level). Hereinafter, the second level may also be referred to as a second hierarchical level or a second level.

[0025] Accordingly, frames F1, F3, F5, and F7 are referred to as the same level (e.g., a third level). Hereinafter, the third level may also be referred to as a third hierarchical level or a third level. Coding performed on the frames in each of the levels according to the hierarchical structure is referred to as hierarchical coding.

[0026] Decoder 100 encodes the encoded video stream 10 received from input unit 50. For example, decoder 100 decodes a plurality of frames included in video stream 10 received from input unit 50. In exemplary embodiments, the plurality of frames may include at least one of, for example, intra-frames (I-frames), predicted frames (P-frames), and bidirectional prediction frames (B-frames).

[0027] Each of the plurality of frames is classified as one of the plurality of levels described above. For example, some of the plurality of frames may be classified as the first level, and others of the plurality of frames may be classified as the second level. The number of the plurality of levels may be determined when the plurality of frames are encoded in a hierarchical manner as described above. Although the example described above includes three levels, the number of levels according to exemplary embodiments of the present disclosure is not limited thereto.

[0028] The decoder 100 initially decodes the frames classified as the first level L1 among the plurality of frames in a chronological order and stores these decoded frames in the DPB 200, as described below. Subsequently, the decoder 100 decodes the most recent one of the frames classified as the second level L2 and stores this decoded frame in the DPB 200. Subsequently, the decoder 100 decodes the remaining frames classified as the second level L2 that have not yet been decoded while traversing the frames in the hierarchical structure described above in a reverse chronological order. As an example, assume that frames A, B, and C are classified as the first level L1, and frames D, E, F, and G are classified as the second level L2.In an exemplary embodiment, decoder 100 initially decodes frames A, B, and C in chronological order (e.g., decoder 100 decodes frame A, then decodes frame B, then decodes frame C) and stores the decoded frames A, B, and C in DPB200. Subsequently, decoder 100 decodes frame G (e.g., the most recent one of the frames classified as the second level L2) and stores the decoded frame G in DPB200. Subsequently, decoder 100 decodes the remainder of the frames classified as the second level L2 that have not yet been decoded (e.g., frames D, E, and F) in reverse chronological order (e.g., decoder 100 decodes frame F, then decodes frame E, then decodes frame E).

[0029] In addition, the decoder 100 reads the DPB200 to retrieve a previous frame, which is the second-most recent one of the frames classified as the second level, and determines whether the hierarchical parent frame of the previous frame is stored in the DPB200. If the hierarchical parent frame of the previous frame is stored in the DPB200, the previous frame is decoded immediately (e.g., the previous frame is decoded before any other frame). Alternatively, if the hierarchical parent frame of the previous frame is not stored in the DPB200, the hierarchical parent frame is decoded first, and then the previous frame is decoded.

[0030] A detailed description of the operations of decoder 100 will be made below with reference to various exemplary embodiments.

[0031] The output unit 150 outputs a plurality of frames decoded by the decoder 100. In exemplary embodiments, the output unit 150 may output the plurality of frames decoded by the decoder 100 in reverse chronological order. Thus, the output unit 150 outputs a reversed / decoded video stream 20. Accordingly, for example, the display device 300, which is shown in Fig. 2, allow reverse playback of the decoded video stream.

[0032] The DPB200 stores (e.g., temporarily stores) the plurality of frames decoded by the decoder 100. In exemplary embodiments, the DPB200 may include a plurality of unit buffer blocks (e.g., buffer circuits). Each unit buffer block corresponds to information on a respective frame. For example, if the DPB200 has a size of five, the DPB200 may store five decoded frames. After decoding the plurality of frames in the order described above, the decoder 100 stores the decoded frames in the DPB200. In addition, the display device 300 may read the DPB200 to display the decoded frames.

[0033] In exemplary embodiments, the number of unit buffer blocks required for operation of a semiconductor device can be determined by Equation 1 below: NB=NG / 2(NL−1)+NL, where NB denotes the number of unit buffer blocks, NG denotes the number of the plurality of frames, and NL denotes the number of levels.

[0034] In exemplary embodiments, a display delay taken for decoding a frame until the semiconductor device starts a display operation can be determined by Equation 2 below: DD=NG / 2(NL−1)+NL−1, where DD denotes the display delay, NG denotes the number of frames, and NL denotes the number of levels.

[0035] For example, if NG is 32 (e.g., a GPO has 32 frames), NB and DD can be determined depending on the number of levels as follows: [Table 1] Anzahl vonEbenen 2 3 4 5 NB 18 11 8 7 DD 17 10 7 6

[0036] In a comparative example, when the NG is 32, 33 unit buffer blocks are required, and the display delay has a value of 32. In contrast, in a method of operating a semiconductor device and a semiconductor system according to exemplary embodiments of the present disclosure, when a number of levels is three or more, the size of the DPB200 and the display delay can be reduced to approximately one-third compared to the comparative example.

[0037] Fig. 2 is a block diagram schematically illustrating a semiconductor system according to an exemplary embodiment of the present disclosure.

[0038] Referring to Fig. 2, a semiconductor system 2 according to an exemplary embodiment of the present disclosure may include a decoder 100, a memory 250, and a display device 300. The decoder 100, the memory 250, and the display device 300 may send / receive data to / from each other via a bus 400.

[0039] The decoder 100 may include a processor 110 and a buffer 120 disposed therein. The processor executes one or more instructions that cause the decoder 100 to perform the operations described above with respect to Fig. 1. In exemplary embodiments, the processor 110 may be, but is not limited to, a processor such as a central processing unit (CPU), a graphic processing unit (GPU), etc., or may be an integrated circuit such as, but not limited to, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc.

[0040] Buffer 120 is storage space for storing (e.g., temporarily storing) data while processor 110 executes instructions. For example, processor 110 may store (e.g., temporarily storing) a portion of encoded video stream 10 while decoding it.

[0041] The memory 250 may be a volatile memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). However, the memory 250 is not limited thereto. For example, the memory 250 may be implemented as a non-volatile memory such as a flash memory. In exemplary embodiments, the DPB200 described above with respect to Fig. 1, may be implemented in the memory 250. That is, the DPB200 may be located within the memory 250 according to exemplary embodiments of the present disclosure.

[0042] The display device 300 receives a decoded video stream from the DPB200 and displays the decoded video stream. In exemplary embodiments, the display device 300 may be implemented as, but is not limited to, a cathode ray tube (CRT) display, a liquid crystal display (LCD), a light-emitting diode (LED) display, etc.

[0043] Fig. 3 is a diagram schematically illustrating an encoded video stream used in various example embodiments of the present disclosure.

[0044] Referring to Fig. 3, an encoded video stream 10 may include a plurality of GOPs (e.g., GOP0, GOP1, ..., GOPn, where n is an integer equal to at least 2). Each of the GOPs may include a plurality of video frames. For example, GOP0 may include frames I0, P01, ..., P0m, GOP1 may include frames I1, P11, ..., P1m, GOP2 may include frames I2, I21, ..., P2m, and GOPn may include frames In, Pn1, ..., Pnm.

[0045] Since the GOPs have their own intraframes I0, I1, ... In, random access to the GOPs is possible in exemplary embodiments by using the intraframes as identification information. However, random access to the majority of frames contained in the GOPs may not be possible.

[0046] According to exemplary embodiments of the present disclosure, the decoder 100 receives the video stream 10 having a plurality of GOPs encoded in a hierarchical manner, stores the video stream in a first storage area (e.g., the buffer 120), and receives a first GOP that is the most recent one among the plurality of GOPs of the video stream 10 stored in the first storage area (e.g., GOPn).

[0047] After performing the operations described above with reference to Fig. 1, on the first GOP, to complete the decoding, the decoder 100 retrieves the second GOP, which is the second-newest one among the plurality of GOPs of the video stream 10 stored in the first storage area (for example, GOP(n-1)), and performs decoding thereon.

[0048] Decoder 100 can perform decoding on the remaining GOPs in this manner until GOP0 is decoded. Consequently, the majority of GOPs are displayed in reverse chronological order. Accordingly, the majority of frames in each GOP are also displayed in reverse chronological order.

[0049] For example, according to exemplary embodiments of the present disclosure, in the method of operating a semiconductor device and a semiconductor system, at least some of the plurality of frames in the first GOP may be displayed before all of the frames in the first GOP are decoded. A detailed description of this will be made below with reference to various exemplary embodiments.

[0050] Fig. 4 is a view schematically illustrating an exemplary operation of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0051] In the example shown in Fig. As shown in Figure 4, a single GOP comprises eight frames. Each of the eight frames, which is encoded in the hierarchical manner, is assigned to the first level L1 and the second level L2, as shown in Fig. 4. In this example, decoder 100 initially decodes the frames classified as the first level L1 in chronological order and stores them in DPB200. For example, decoder 100 initially decodes frames I, P2, P4, and P6, which are classified as the first level L1, sequentially and stores them in DPB200.

[0052] Subsequently, the decoder 100 decodes the most recent one of the plurality of frames classified as the second level L2 and stores this frame in the DPB200. For example, the decoder subsequently decodes the most recent frame among the frames classified as the second level L2 (for example, frame P7) and stores it in the DPB200.

[0053] Subsequently, the decoder 100 reads the DPB200 to display the frame P7.

[0054] Subsequently, decoder 100 sequentially decodes the remaining frames classified as the second level L2 that have not yet been decoded, while traversing the frames in reverse chronological order. For example, decoder 100 sequentially decodes frames P5, P3, and P1.

[0055] Fig. Fig. 5 is a diagram illustrating a design scheme of the decoded frame buffer (DPB) which is dependent on the operations of the semiconductor device described above with reference to Fig. 4 according to an exemplary embodiment of the present disclosure.

[0056] Referring to Fig. 5, the DPB200 has a first buffer area and a second buffer area. The first buffer areas store decoded frames of the plurality of frames, and the second buffer area stores frames for display among the decoded frames. Fig. 5, the first buffer areas are indexed with values ​​from 0 to 4, respectively, and the second buffer area is indexed with the value of 5 in the DPB200. For example, referring to column s4, the DPB200 stores decoded frames I, P2, P4, and P6 in the first buffer areas and a frame P7 for display in the second buffer area.

[0057] In the tables, which show a design scheme of the DPB200, which is Fig. 5 and other similar tables illustrated herein, the underlined number of a frame indicates that the frame is being decoded at that step. Additionally, the number of a frame marked with crossed lines (e.g., with an "X") indicates that the frame has been displayed. A block containing a dot refers to invalid data (e.g., a garbage value).

[0058] Referring to the Fig. 4 and Fig. 5, the decoder 100 decodes the frames I, P2, P4 and P2 classified as the first level L1 in this order and stores them in the blocks indexed by 0 to 4, respectively, in the DPB200 (for example, steps s0 to s3).

[0059] Subsequently, the decoder 100 decodes the latest one of the frames classified as the second level L2 (for example, the frame P7) and stores this frame in the block indexed by 5 in the DPB200 to indicate the frame P7 (for example, step s4).

[0060] Subsequently, the decoder 100 sequentially decodes the remaining frames P5, P3, and P1 classified as the second level L2 that have not yet been decoded, and overwrites the frames already displayed in the DPB200 with the remaining frames. For example, frame P7, which is already displayed in step s4, is overwritten with frame P5 in step s5, frame P6, which is already displayed in step s5, is overwritten with frame P3 in step s6, and frame P5, which is already displayed in step s6, is overwritten with frame P1 in step s7.

[0061] Accordingly, the decoding of the plurality of frames is completed by step s7, and the frames P3, P2, P1 and I which are not yet displayed are sequentially displayed from step s8 to step s11.

[0062] As can be seen from the foregoing description, according to exemplary embodiments of the present disclosure, the size of the DPB200 can be drastically reduced at the time of reverse playback of an encoded video stream. Additionally, at least some of the plurality of frames included in a GOP are displayed before all of the frames of the GOP are displayed, reducing display delay.

[0063] Fig. 6 is a view schematically illustrating an exemplary operation of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0064] In the example shown in Fig. As shown in Figure 6, a single GOP comprises eight frames. Each of the eight frames, which is encoded in the hierarchical manner, is classified as one of the first level L1 to the third level L3, as shown in Fig. 6. In this example, decoder 100 initially decodes the frames classified as the first level L1 in chronological order and stores them in DPB200. For example, decoder 100 initially decodes frames I and P4, classified as the first level L1, sequentially and stores them in DPB200.

[0065] Subsequently, the decoder 100 decodes the most recent of the plurality of frames classified as each of the second level L2 and the third level L3 and stores these frames in the DPB200. For example, the decoder subsequently decodes the most recent frame among the frames classified as the second level L2 (for example, frame P6) and stores this frame in the DPB200. Subsequently, the decoder 100 decodes the most recent frame among the frames classified as the third level L3 (for example, frame P7) and stores this frame in the DPB200.

[0066] Subsequently, the decoder 100 reads the DPB200 to display the frame P7.

[0067] Subsequently, the decoder 100 sequentially decodes the rest of the frames P5, P2, P3 and P1, which are classified as the second level L2 and the third level L3, which are not yet decoded, while stepping through in reverse chronological order.

[0068] Additionally, decoder 100 reads DPB200 to retrieve the previous frame P5, which is the second-most recent one of the frames classified as the third level L3, and determines whether the hierarchical parent frame P6 of the previous frame P5 is stored in DPB200. In this example, the hierarchical parent frame P6 of the previous frame P5 is stored in DPB200. Therefore, the previous frame P5 is decoded immediately (e.g., the previous frame P5 is decoded before any other frame).

[0069] Alternatively, when decoder 100 reads DPB200 to retrieve the previous frame P3, which is earlier than frame P5 of the frames classified as the third level L3, the hierarchical parent frame P2 of the previous frame P3 is not stored in DPB200. Therefore, the hierarchical parent frame P2 is decoded first, and then the previous frame P3 is decoded.

[0070] Fig. Fig. 7 is a diagram illustrating a design scheme of the decoded frame buffer (DPB) which is generated depending on the operation of the semiconductor device described above with reference to Fig. 6 according to an exemplary embodiment of the present disclosure.

[0071] Referring to the Fig. 6 and Fig. 7, the decoder 100 decodes the frames I and P4, which are classified as the first level L1, in this order and stores these frames in the blocks indexed by 0 and 1, respectively, in the DPB200 (steps s0 and s1).

[0072] Subsequently, the decoder 100 decodes the latest one of the frames classified as the second level L2 and the third level l3, respectively (for example, the frames P6 and P7), and stores these frames in the blocks indexed by 2 and 3, respectively, in the DPB200 to indicate the frame P7 (steps s3 and s4).

[0073] Subsequently, the decoder 100 sequentially decodes the remainder of frames P5, P3, and P1 of the frames classified as the third level L3 that have not yet been decoded, and overwrites the frames already displayed in the DPB200 with the remainder of these frames. For example, frame P7, which is already displayed in step s3, is overwritten with frame P5 in step s4, frame P6, which is already displayed in step s4, is overwritten with frame P2 in step s5, frame P5, which is already displayed in step s5, is overwritten with frame P3 in step s6, and frame P4, which is already displayed in step s6, is overwritten with frame P1 in step s7.

[0074] Accordingly, the decoding of the plurality of frames is completed by step s7, and the frames P2, P1 and I which are not yet displayed are sequentially displayed from step s8 to step s10.

[0075] As can be seen from the foregoing description, according to exemplary embodiments of the present disclosure, at the time of reverse playback of an encoded video stream, the size of the DPB 200 can be drastically reduced. Additionally, at least some of the plurality of frames included in a GOP are displayed before all of the frames of the GOP are displayed, reducing display delay.

[0076] Fig. 8 is a view schematically illustrating an exemplary operation of a semiconductor device according to an exemplary embodiment of the present disclosure. Fig. 9A and Fig. 9B are diagrams illustrating design schemes of the DPB depending on the operation of the semiconductor device described above with reference to Fig. 8 according to exemplary embodiments of the present disclosure.

[0077] In the example shown in the Fig. 8, Fig. 9A and Fig. As shown in Figure 9B, a single GOP comprises 16 frames. Each of the 16 frames, which is encoded in the hierarchical manner, is classified as one of the first level L1 to the fourth level L4, as shown in Fig. 8. In this example, the decoder 100 sequentially decodes frames 1 and P8, which are classified as the first level L1, and stores them in the DPB200.

[0078] Subsequently, decoder 100 decodes the most recent frames among the frames classified as the second level L2 through the fourth level L4 (for example, frames P12, P14, and P15) and stores these frames in DPB200. Subsequently, decoder 100 reads the DPB200 to display frame P15.

[0079] Subsequently, the decoder 100 sequentially decodes the rest of the frames among the frames classified as the fourth level L4 that are not yet decoded (for example, frames P13, P11, P9, P7, P5, P3, and P1) while passing through in reverse chronological order.

[0080] Additionally, decoder 100 reads DPB200 to retrieve the previous frame P13, which is the second-most recent one of the frames classified as the fourth level L4, and determines whether the hierarchical parent frame P14 of the previous frame P13 is stored in DPB200. In this example, the hierarchical parent frame P14 of the previous frame P13 is stored in DPB200. Therefore, the previous frame P13 is decoded immediately (e.g., the previous frame P13 is decoded before any other frame).

[0081] Alternatively, when decoder 100 reads DPB200 to retrieve the previous frame P11, which is the third-newest one of the frames classified as the fourth level L4, the hierarchical parent frame P10 of the previous frame P11 is not stored in DPB200. Therefore, the hierarchical parent frame P10 is decoded first, and then the previous frame P11 is decoded.

[0082] Similarly, when decoder 100 reads DPB200 to retrieve a preceding frame P7 that is earlier than frame P9 of the frames classified as the fourth level L4, the hierarchical parent frames P4 and P6 (e.g., the grandfather frame P4 and a parent frame P6 of the preceding frame P7) are not stored in DPB200. Therefore, the hierarchical parent frames P4 and P6 are decoded first, and then the preceding frame P7 is decoded.

[0083] Fig. 10 is a view schematically illustrating an exemplary operation of a semiconductor device according to an exemplary embodiment of the present disclosure. Fig. 11A to 11C are diagrams illustrating design schemes of the DPB which depends on the operation of the semiconductor device described above with reference to the Fig. 10 according to exemplary embodiments of the present disclosure.

[0084] In the example shown in the Fig. 10 and 11A to 11C, a single GOP comprises 32 frames. Each of the 32 frames, which is encoded in the hierarchical manner, is designated as one of the first level L1 to the fifth level L5, as shown in Fig. 10. In this example, decoder 100 sequentially decodes frames I and P16, which are classified as the first level L1, and stores these frames in DPB200.

[0085] Subsequently, the decoder 100 decodes the latest frames among the frames classified as the second level L2 to the fifth level L5 (for example, frames P24, P28, P30, and P3, respectively) and stores these frames in the DPB200. Subsequently, the decoder 100 reads the DPB200 to display the frame P31.

[0086] Subsequently, the decoder 100 sequentially decodes the rest of the frames among the frames classified as the fifth level L5 that are not yet decoded (for example, frames P29, P27, P25, P23, etc.) while passing through in a reverse chronological order.

[0087] Additionally, decoder 100 reads DPB200 to retrieve the previous frame P29, which is the second-most recent one of the frames classified as the fifth level L5, and determines whether the hierarchical parent frame P30 of the previous frame P31 is stored in DPB200. In this example, the hierarchical parent frame P30 of the previous frame P31 is stored in DPB200. Therefore, the previous frame P31 is decoded immediately (e.g., the previous frame P31 is decoded before any other frame).

[0088] Alternatively, when decoder 100 reads DPB200 to retrieve the previous frame P27, which is the third-most recent one of the frames classified as the fifth level L5, the hierarchical parent frame P26 of the previous frame P27 is not stored in DPB200. Therefore, the hierarchical parent frame P26 is decoded first, and then the previous frame P27 is decoded.

[0089] Similarly, when decoder 100 reads DPB200 to retrieve the previous frame P23, which is the fifth-newest one of the frames classified as the fifth level L5, the hierarchical parent frames P20 and P22 (e.g., the grandfather frame P20 and a parent frame P22) of the previous frame P23 are not stored in DPB200. Therefore, the hierarchical parent frames P20 and P22 are decoded first, and then the previous frame P23 is decoded.

[0090] Similarly, when decoder 100 reads DPB200 to retrieve the previous frame P15, which is the ninth-most recent one of the frames classified as the fifth level L5, the hierarchical parent frames P8, P12, and P14 of the previous frame P15 are not stored in DPB200. Therefore, the hierarchical parent frames P8, P12, and P14 are decoded first in that order, and then the previous frame P15 is decoded.

[0091] Fig. 12 is a flowchart illustrating a method of operating a semiconductor device according to an exemplary embodiment of the present disclosure.

[0092] Referring to Fig. 12, the method includes receiving a video stream having a plurality of GOPs encoded in a hierarchical manner. The method further includes retrieving a first GOP that is the most recent one of the plurality of GOPs (operation S1201).

[0093] The method further comprises decoding some of the plurality of frames of the first GOP classified as the first level L1 in a chronological order (operation S1203).

[0094] The method further comprises decoding the most recent one of the frames of each of the plurality of frames classified as upper levels (operation S1205).

[0095] As used herein, the term “upper levels” refers to all levels other than the first level.

[0096] The method further comprises decoding the remainder of the frames classified as each of the upper levels while traversing the frames in reverse chronological order (operation S1207). The method further comprises retrieving a second GOP that is the second most recent one of the plurality of GOPs (operation S1209) and performing encoding on the second GOP.

[0097] In the method of operating a semiconductor device and a semiconductor system according to various exemplary embodiments of the present disclosure, the size of the DPB200 is drastically reduced at the time of backward playback of an encoded video stream. Additionally, at least some of the plurality of frames included in a GOP are displayed before all of the frames of the GOP are displayed, reducing display delay.

[0098] Fig. 13 is a block diagram of an electronic system that may employ the method of operating a semiconductor device and a semiconductor device according to any of the exemplary embodiments of the present disclosure.

[0099] Referring to Fig. 13, the electronic system 1100 according to an exemplary embodiment of the present disclosure may include a controller 1110, an input / output (I / O) device 1120, a memory device 1130, an interface 1140, and a bus 1150. The controller 1110, the I / O device 1120, the memory device 1130, and / or the interface 1140 may be connected to each other via bus 1150. The bus 1150 may serve as a path over which data is transferred.

[0100] The controller 1110 may include at least one of, for example, a microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing similar functions. The I / O device 1120 may include, for example, a keypad, a keyboard, a display device, etc. The memory device 1130 may, for example, store data and / or instructions therein. The interface 1140 may be capable of transmitting / receiving data to / from a communications network. The interface 1140 may be a wired or wireless interface. For example, the interface 1140 may include an antenna, a wired / wireless transceiver, etc.

[0101] According to exemplary embodiments of the present disclosure, the electronic system 1100 is an operational memory for enhancing the operation of the controller 1100 and may further include, for example, a high-speed DRAM and / or SRAM.

[0102] Additionally, the processor according to any of the exemplary embodiments of the present disclosure may be provided in the memory device 1130 or may be provided as a part of the controller 1110, the I / O device 1120, etc.

[0103] The semiconductor system 1100 can be applied to, for example, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or any other electronic device capable of transmitting / receiving information in a wireless environment.

[0104] The Fig. 14 to 16 show examples of semiconductor systems that may employ the method of operating a semiconductor device according to example embodiments of the present disclosure.

[0105] Fig. 14 shows a Tablet PC 1200, Fig. 15 shows a laptop computer 1300 and Fig.16 shows a smartphone 1400. At least one of the processors according to the exemplary embodiments of the present disclosure may be employed by the tablet PC 1200, the laptop computer 1300, the smartphone 1400, etc.

[0106] As will be appreciated by those skilled in the art, the semiconductor devices fabricated according to exemplary embodiments of the present disclosure may be implemented by integrated circuit devices other than those mentioned above. For example, although the tablet PC 1200, the laptop computer 1300, and the smartphone 1400 are described as examples of semiconductor systems that may implement the method of operating a semiconductor device according to exemplary embodiments of the present disclosure, the examples of the semiconductor system are not limited thereto.

[0107] In exemplary embodiments of the present disclosure, the semiconductor system may be implemented as, for example, a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a PDA, a portable computer, a wireless phone, a mobile phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a three-dimensional television, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, etc.

[0108] While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present inventive concept as defined by the following claims.

Claims

[1] A method of operating a semiconductor device, comprising: receiving a video stream (10) comprising a first frame, a second frame, a third frame and a fourth frame encoded in a hierarchical manner, wherein the first frame and the third frame are classified as a first level, and the second frame and the fourth frame are classified as a second level; where the first frame is a parent frame of the second frame, and the third frame is a parent frame of the fourth frame, where the first frame, the second frame, the third frame and the fourth frame are in chronological order; decoding the first frame and the third frame in a chronological order; storing the decoded first frame and the decoded third frame in a decoded frame buffer (DPB (200)) in chronological order; decoding the fourth frame; storing the decoded fourth frame in the DPB (200); displaying the fourth frame by reading the DPB (200); decoding the second frame after displaying the fourth frame; and overwriting the fourth frame in the DPB with the second frame after the fourth frame has been displayed. [2] Method according to claim 1, wherein the DPB (200) comprises a plurality of unit buffer blocks, and each unit buffer block is associated with information about a respective frame, wherein a number of unit buffer blocks used for operation of the semiconductor device is determined by: NB=NG / 2(NL−1)+NL, where NB denotes the number of unit buffer blocks used for the operation of the semiconductor device, NG denotes a number of the plurality of frames, and NL denotes a number of the plurality of levels. [3] Method according to claim 2, wherein a display delay taken in decoding a frame until the semiconductor device starts a display operation is determined by: DD=NG / 2(NL−1)+NL-1, where DD denotes the display delay. [4] Method according to claim 1, wherein the DPB (200) has a first buffer area and a second buffer area, wherein the first buffer area stores a decoded frame among the plurality of frames, and the second buffer area stores a frame for display among the decoded frames. [5] The method of claim 1, wherein the first frame, the second frame, the third frame and the fourth frame are displayed in reverse chronological order. [6] The method of claim 1, wherein the first frame, the second frame, the third frame, and the fourth frame comprise at least one of an intra-frame (I-frame), a predicted frame (P-frame), and a bidirectional prediction frame (B-frame). [7] The method of claim 1, wherein decoding and displaying the second frame comprises: reading the DPB (200) to retrieve the second frame; and determining whether a hierarchical parent frame of the second frame is stored in the DPB (200). [8] The method of claim 7, wherein decoding and displaying the second frame further comprises: decoding the second frame if the hierarchical parent frame of the second frame is stored in the DPB (200). [9] The method of claim 7, wherein decoding and displaying the second frame further comprises: decoding the hierarchical parent frame of the second frame and subsequently decoding the second frame if the hierarchical parent frame is not stored in the DPB (200). [10] The method of claim 1, wherein the first and second levels are determined when the first frame, the second frame, the third frame and the fourth frame are encoded in the hierarchical manner. [11] A method of operating a semiconductor device, comprising: receiving a video stream (10) comprising a plurality of groups of pictures (GOPs) encoded in a hierarchical manner; storing the video stream (10) in a first memory area; retrieving a first GOP, which is the most recent one of the plurality of GOPs, from the video stream (10) stored in the first memory area, wherein the first GOP comprises a first frame, a second frame, a third frame, and a fourth frame, the first frame and the third frame being classified as a first level and the second and fourth frames being classified as a second level; wherein the first frame is a parent frame of the second frame, and the third frame is a parent frame of the fourth frame; where the first frame, the second frame, the third frame and the fourth frame are in chronological order; decoding the first frame and the third frame in a chronological order; storing the decoded first frame and the decoded third frame in a second memory area; decoding the fourth frame; storing the decoded fourth frame in the second memory area; displaying the fourth frame by reading the second memory area; decoding the second frame after displaying the fourth frame; overwriting the fourth frame in the second memory area with the second frame after the fourth frame has been displayed; and retrieving a second GOP, which is a second most recent one of the plurality of GOPs, from the video stream (10) stored in the first storage area. [12] The method of claim 11, wherein at least some of the first frame, the second frame, the third frame, and the fourth frame included in the first GOP are displayed before all of the frames of the first GOP are decoded. [13] The method of claim 11, wherein the first memory area comprises a buffer memory for storing the video stream (10), and the second memory area comprises a decoded image buffer (DPB (200)) for storing the decoded frames. [14] Method according to claim 11, wherein the second memory area comprises a plurality of unit buffer blocks, each unit buffer block being associated with information about a respective frame, wherein a number of unit buffer blocks used for operation of the semiconductor device is determined by: NB=NG / 2(NL−1)+NL, where NB denotes the number of unit buffer blocks used for the operation of the semiconductor device, NG denotes a number of the plurality of frames, and NL denotes a number of the plurality of levels. [15] The method of claim 11, wherein the plurality of GOPs are displayed in reverse chronological order. [16] The method of claim 11, wherein decoding the second frame comprises: reading the second memory area to retrieve the second frame; and determining whether a hierarchical parent frame of the second frame is stored in the second memory area. [17] The method of claim 16, wherein decoding the second frame further comprises: decoding the second frame if the hierarchical parent frame of the second frame is stored in the second memory area. [18] The method of claim 16, wherein decoding the second frame further comprises: decoding the hierarchical parent frame of the second frame and subsequently decoding the second frame if the hierarchical parent frame is not stored in the second memory area. [19] A method of operating a semiconductor device, comprising: receiving a video stream (10) comprising a first frame, a second frame, a third frame, a fourth frame, a fifth frame and a sixth frame encoded in a hierarchical manner, wherein the first frame and the third frame are classified as a first level, the second frame and the fourth frame are classified as a second level, and the fifth frame and the sixth frame are classified as a third level; where the first frame, the second frame, the fifth frame, the third frame, the sixth frame and the fourth frame are in chronological order; wherein the first frame is a parent frame of the second frame, and the third frame is a parent frame of the fourth frame; the second frame is a parent frame of the fifth frame, and the fourth frame is a parent frame of the sixth frame; decoding the first frame and the third frame in a chronological order; storing the decoded first frame and the decoded third frame in a decoded frame buffer (DPB (200)) in a chronological order; decoding the second frame and the fourth frame; storing the decoded second frame and the decoded fourth frame in the DPB (200); decoding the sixth frame; storing the decoded sixth frame in the DPB (200); a retrieval of the fifth frame; determining whether the second frame, a hierarchical parent frame of the fifth frame, is stored in the DPB (200); decoding the fifth frame if the hierarchical parent frame is stored in the DPB (200); and decoding the hierarchical parent frame and subsequently decoding the fifth frame and storing the fifth frame in the DPB (200) if the second frame is not stored in the DPB (200), wherein the fifth frame overwrites the sixth frame stored in the DPB (200) after it has been decoded and the sixth frame has been displayed. [20] Method according to claim 19, wherein the DPB (200) comprises a plurality of unit buffer blocks, each unit buffer block being associated with information about a respective frame, wherein a number of unit buffer blocks used for operation of the semiconductor device is determined by: NB=NG / 2(NL−1)+NL, where NB denotes the number of unit buffer blocks, NG denotes a number of the plurality of frames in the video stream (10), and NL denotes a number of the plurality of levels into which the plurality of frames are classified.

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