Computing system, non-volatile memory module and method for operating a memory device

Abstract

A method of operating a memory device (200), the method comprising: sending an internal operation request for granting an internal operation of the storage device (200) to an external device, the internal operation request comprising a message indicating an internal operation time and generated by the storage device (200); receiving an internal operation command in response to the internal operation request from the external device, the internal operation command indicating whether the internal operation request is granted or rejected; and performing the internal operation by the storage device (200) during the internal operation time granted by the internal operation command when the requested internal operation has been granted by the external device.

Description

BACKGROUND1. Area

[0001] One or more embodiments described herein relate to a computing system, a non-volatile memory module, and a method for a memory device. 2. Description of the state of the art

[0002] Attempts have been made to develop non-volatile memory compatible with various interfaces of an existing computing system. For example, attempts have been made to use flash memory as a data storage device or random access memory by mounting the flash memory (or random access memory) on the same slot or channel as a computer system's main memory or random access memory. However, these attempts have proven to have drawbacks.

[0003] US 2006 / 0 285 413 A1 discloses a method in which a refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier, reducing the access time. The access time can be further reduced by changing the end time of the refresh operation in accordance with the timing of the delivery of the access request. Since a test circuit is provided for communicating the status of the refresh operation to the outside, the operating margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development time of the semiconductor memory.

[0004] US 7,242,631 B2 discloses a refresh operation for a memory cell array that can be executed based on an external refresh request inputted externally or an internal refresh request generated internally by a refresh control unit. When the refresh operation is executed based on the external refresh request, it is possible to perform an access operation for the memory cell array within a time necessary to perform the operation according to the access request, without including a time necessary to perform the refresh operation.

[0005] US 6,724,675 B2 discloses a semiconductor memory device, such as a DRAM, which needs to be refreshed to hold data and is provided with a storage section for storing data and a busy signal output section that outputs a busy signal during the refresh operation.

[0006] US 2014 / 0 071 778 A1 discloses a method for refreshing a memory, comprising receiving a synchronization command at a memory device. An internal refresh timer is reset within the memory device based on receiving the synchronization command. An internal refresh trigger is generated within the memory device based on the internal refresh timer reaching a predetermined value. Refreshing a memory array is performed within the memory device based on the internal refresh trigger. SUMMARY

[0007] The object of the present invention is to provide a memory device that efficiently performs an internal operation and an operating method for efficiently performing an internal operation of a memory device. This object is achieved by an operating method according to claim 1 and a memory device according to claim 11. Further developments of the memory device and the operating method are the subject of the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing exemplary embodiments in detail with reference to the accompanying drawings, in which: Fig. 1 illustrates an embodiment of a computing system; Fig. 2 illustrates an embodiment of a memory device; Fig. 3 illustrates one embodiment of an internal operation time request and a computing system response; Fig. 4 illustrates another embodiment of a computing system; Fig. 5 illustrates an embodiment of a non-volatile memory module; Fig. 6 illustrates an embodiment of a host interface time selection; Fig. 7 illustrates another embodiment of a host interface time selection; Fig. 8 illustrates another embodiment of a computing system; Fig. 9 illustrates an embodiment of a time selection for multiple memory modules; Fig. 10 illustrates an embodiment of an internal operation instruction; Fig. 11 illustrates another embodiment of a computing system; Fig. 12 illustrates another embodiment of a computing system; Fig. 13 illustrates an embodiment of a dynamic random access memory; Fig. 14 illustrates another embodiment of a computing system; Fig. 15 illustrates one embodiment of a method of operation for a host; Fig. 16 illustrates an embodiment of an internal operating method for a memory device; and Fig. 17 illustrates an embodiment of a data server system. DETAILED DESCRIPTION

[0009] Fig. 1 illustrates one embodiment of a computing system 10, which may include a host 100 and a storage device 200. The computing system 10 may be, for example, a computer, a portable computer, an ultra-mobile personal computer (UPM), a workstation, a data server, a netbook, a personal digital assistant (PDA), a web tablet, a wireless telephone, a cellular phone, a smartphone, an e-book, a portable multimedia player (PMP), a digital camera, a digital audio recorder / player, a digital image / video recorder / player, a portable game machine, a navigation system, a black box, a 3D television, a device capable of transmitting and receiving information in a wireless setting, any of various electronic devices forming a home network, any of various electronic devices forming a computer network,one of various electronic devices forming a telematics network, a radio frequency identification (RFID) or one of various electronic devices forming a computing system.

[0010] Host 100 may control overall operation of computing system 10. In one embodiment, host 100 may include at least one processor, a central processing unit (CPU), a graphics processing unit (GPU), a memory controller, etc. In one embodiment, the processor may include a general-purpose microprocessor, a multi-core processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or a combination thereof. In one embodiment, the memory controller may be implemented to control memory device 200.

[0011] In one embodiment, host 100 may provide storage device 200 with information indicating the granting or denial of an internal operation time based on a request from storage device 200. The internal operation time may be a time to perform an internal operation of storage device 200.

[0012] In one embodiment, the internal operation time grant / reject information may be transmitted or determined based on the type of command or data. In another embodiment, the internal operation time grant / reject information may be transmitted through a separate line between the host 100 and the storage device 200.

[0013] In Fig. 1 illustrates an embodiment in which host 100 transmits an internal operation time to storage device 200 based on a request from storage device 200. In another embodiment, host device 100 may transmit the internal operation time grant / reject information to storage device 200 based on an internal rule without a request from storage device 200.

[0014] The storage device 200 may be connected to the host 100 to store data for an operation of the host 100. The storage device 200 may be at least one of volatile memory, non-volatile memory, or a combination thereof. For example, the storage device 200 may be a dual-in-line memory module (DIMM), a non-volatile dual-in-line memory module (NVDIMM), a solid-state drive (SSD), a universal flash memory (UFS), an embedded multimedia card (eMMC), a secure digital (SD) card, a dynamic random access memory (DRAM), a static RAM (SRAM), a NAND flash memory, a vertical NAND flash memory, a phase-change RAM (PRAM), or a resistive RAM (RRAM).

[0015] In one embodiment, the storage device 200 may be connected to the host 100 based on the Double Data Rate (DDR) interface standard. For example, the storage device 200 may be implemented with any of the DDRx series (where x is an integer). The storage device 200 may be connected to the host 100 through various types of communication interfaces other than the DDR interface. For example, the communication interface may conform to the following communication standard: Non-Volatile Memory Express (NVMe), Peripheral Component Interconnect Express (PCIe), Serial AT Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Universal Storage Bus (USB) Attached SCSI (UAS), Internet Small Computer System Interface (iSCSI), Fiber Channel, or Fiber Channel over Ethernet (FCoE).

[0016] In one embodiment, storage device 200 may request an internal operation time for an internal operation from host 100 when it determines that the internal operation is to be performed according to an internal rule. In one embodiment, an internal operation request may be transmitted to host 100 in the form of a message.

[0017] In one embodiment, a message including the internal operating time request may be transmitted to the host 100 via at least one data channel, at least one clock channel, at least one control channel, at least one dedicated message channel between the host 100 and the storage device 200, or a combination thereof. For example, when the internal operating time request is transmitted through the data channels, it may be included in a response message corresponding to an asynchronous command. The asynchronous command may include an asynchronous event request command. Asynchronous events may be used to inform software or a controller of the host 100 about status, error, and health information of the storage device 200.

[0018] The internal operation time request described above can be transmitted as a message. In another embodiment, the internal operation time request can be provided to host 100 as a signal requesting selection of a register corresponding to the internal operation time for the internal operation.

[0019] In one embodiment, the storage device 200 may be implemented to perform the internal operation after receiving the internal operation time grant / reject information from the host 100. The internal operation may include various operations associated with, for example, refresh, timer calibration, process voltage temperature (PVT) compensation, internal data transfer, or another operation. In one embodiment, all or part of the internal operation may be performed according to the internal operation time grant / reject information. In this regard, the internal operation time grant / reject information may further include information about the execution of all or part of the internal operation.

[0020] In the computing system 10 according to one embodiment, the storage device 200 may directly request the internal operation time for the internal operation of the storage device 200 from the host 100. The host 100 may transfer authority over a time to the storage device 200 during the internal operation time based on the request. As a result, it may be possible for the storage device 200 to sufficiently perform the internal operation. For example, the host 100 may grant the internal operation time for the internal operation with respect to the storage device 200.

[0021] Fig. 2 illustrates an embodiment of the memory device 200 implemented with a memory module. Referring to Fig. 2, the memory device 200 may include a plurality of DRAMs 211 to 214 and a memory module controller (RCD) 220. Each of the DRAMs 211 to 214 may input and output data DQ under the control of the memory module controller 220. The number of DRAMs 211 to 214 in Fig. 2 is four, but may be a different number in another embodiment.

[0022] The memory module controller 220 may receive a command and / or address from the host 100 and control input / output operations of the DRAMs 211 to 214. In one embodiment, the memory module controller 220 may send an internal operation time request for an internal operation to the host 100 based on the internal rule. In one embodiment, the memory module controller 220 may perform the internal operation based on the internal operation time grant / reject information transmitted from the host 100.

[0023] In one embodiment, memory device 200 may further include a DRAM 215 for parity. In one embodiment, memory device 200 may further include data buffers DBs to buffer the data DQ between host 100 and DRAMs 211 to 214. In one embodiment, memory device 200 may be implemented to meet a DDRx SDRAM specification. For example, memory device 200 may be implemented to meet a next-generation DDR4 SDRAM specification. The internal operation timing may be implemented, for example, in a register set path.

[0024] Fig. 3 illustrates an embodiment of an internal operation time request and response in the computing system 10 based on the register set path. Referring to Fig. 3, the memory device 200 may include a register set that stores a plurality of internal operation times RT1 to RTk (where k is a natural number of two or more). For example, a first internal operation time RT1 may be a time corresponding to 16 clock cycles, and a second internal operation time RT2 may be a time corresponding to 8 clock cycles.

[0025] The memory controller of the host 100 may send a register selection signal to the memory device 200 based on the internal operation time requirement of the memory device 200. The register selection signal may be a signal for selecting a register among registers of the register set that corresponds to the internal operation time requirement. For example, the register selection signal may include the internal operation time grant / reject information. In one embodiment, the register set in the memory module controller 220 may be Fig. 2 or in a different location.

[0026] The calculation system 10 in the Fig. Figures 1 to 3 describe one embodiment with respect to internal operation time. In another embodiment, the computing system may be described in the context of issuing an internal operation request and an internal operation command in response to the internal operation request.

[0027] Fig. 4 illustrates another embodiment of a computing system 20, which may include a host 100a and a non-volatile memory module (NVDIMM) 300. The host 100a may receive the internal operation request from the non-volatile memory module 300, issue an internal operation command IOP based on the internal operation request, and send the issued internal operation command IOP to the non-volatile memory module 300. The internal operation command IOP may include the internal operation time for the internal operation. In one embodiment, the internal operation command IOP may further include information corresponding to the granting or denial of the internal operation request.

[0028] In one embodiment, the internal operation request may be transmitted to host 100a, for example, via data ports, data strobe ports, address / command ports, control signal ports, message-dedicated ports, or a combination thereof. In one embodiment, the internal operation command IOP may be generated through the command / address ports, reserved for future use (RFU) ports, or a combination thereof.

[0029] The non-volatile memory module 300 can send the internal operation request to the host 100a when the internal operation is to be performed according to the internal policy. The internal operation request can be implemented, for example, in the form of a message / signal. For example, the internal operation request transmitted in the form of a message / signal can include the internal operation time for the internal operation.

[0030] In one embodiment, non-volatile memory module 300 may be connected to host 100a through the DDRx interface (where x is a natural number). For example, non-volatile memory module 300 may be implemented to meet a next-generation DDR4 SDRAM specification.

[0031] In one embodiment, the non-volatile memory module 300 may be implemented with a non-volatile dual-in-line memory module (NVDIMM) that meets the JEDEC standard. The NVDIMM may be a memory module that retains data even during an unexpected power outage or system failure, or even when power is interrupted during a normal system shutdown. The NVDIMM may be used to improve application performance, the recovery time of a data security system, and the durability and reliability of the SSD.

[0032] The NVDIMM can take various forms. One embodiment of the NVDIMM is a byte-addressable memory-mapped device that accesses at or near memory speed. The NVDIMM supporting DDR4 SDRAM can be commercially used by any of a variety of hardware vendors. Another embodiment of the NVDIMM is a flash device module residing on an interconnect channel. Such an NVDIMM can be accessed, for example, by a host's driver block. A flash device can be accessed when a front-end cache miss occurs. Another embodiment of the NVDIMM is a module that has all the virtues of fast-access DRAMs and high-capacity non-volatile memory.

[0033] The non-volatile memory module 300 may include a message channel through which an internal operation request message is transmitted to the host 100a. In one embodiment, a DQ channel, a DQS channel, a clock channel, a control signal channel, or a combination thereof may be used as the message channel. In another embodiment, the message channel may have a dedicated channel for transmitting the internal operation request message.

[0034] In one embodiment, the internal operation request message may include requesting an internal operation time from the non-volatile memory module 300 that will perform the internal operation, such that the host 100a does not send a new command to the non-volatile memory module 300 for a predetermined time. In another embodiment, even if the host 100a issues a new command for a predetermined time, the non-volatile memory module 300 that receives an internal operation command may ignore the new command.

[0035] In one embodiment, the internal operation time may vary, for example, based on the type of internal operation performed by the non-volatile memory module 300. For example, the internal operation time for a refresh operation may be approximately a few microseconds. The internal operation time for an internal data transfer operation may be approximately a few hundred microseconds, for example.

[0036] In one embodiment, host 100a may grant or reject the internal operation request upon receiving the internal operation request. For example, if host 100a grants the internal operation request, host 100a may issue an internal operation command IOP corresponding to the internal operation request and send it to non-volatile memory module 300. For example, if host 100a rejects the internal operation request, non-volatile memory module 300 may postpone the internal operation. In one embodiment, non-volatile memory module 300 may perform the internal operation during the internal operation time without an interrupt command from host 100a.

[0037] Fig. 5 illustrates another embodiment of a non-volatile memory module 300, which may include first and second non-volatile memories 310L and 310R, first and second volatile memories 320L and 320R, first and second data buffers 330L and 330, and a memory control circuit (MMCD) 330.

[0038] Each of the first and second non-volatile memories 310L and 310R may include at least one non-volatile memory. In one embodiment, the at least one non-volatile memory may be a NAND flash memory, a vertical NAND (VNAND) flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase-change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin-transfer torque random access memory (STT-RAM), or a thyristor random access memory (TRAM).

[0039] Furthermore, the non-volatile memory may be implemented to have a three-dimensional array structure. In one embodiment, a three-dimensional 3D memory array is provided. The 3D memory array may be monolithically formed into one or more physical levels of arrays of memory cells having an active area above a silicon substrate and circuitry associated with the operation of these memory cells, regardless of whether the associated circuitry is above or within the substrate. The associated circuitry is above or within such a substrate. The term "monolithic" may correspond to layers of each level of the array being deposited directly on the layers of each underlying level of the array.

[0040] In one embodiment, the 3D memory array comprises vertical NAND strings that are vertically oriented such that at least one memory cell is placed above another memory cell. The at least one memory cell may include a charge trapping layer. Each vertical NAND string may include at least one select transistor above memory cells. At least one select transistor may have the same structure as memory cells and be formed monolithically together with memory cells.

[0041] The three-dimensional memory array has a plurality of levels and has word lines or bit lines shared within levels. The following documents are hereby incorporated by reference with respect to exemplary configurations for three-dimensional memory arrays having a plurality of levels, which are employed by Samsung Electronic Co., with word lines and / or bit lines shared between levels: U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235, and U.S. Patent Laid-Open No. 2011 / 0233648. The non-volatile memory may be applicable to a charge-trapping flash memory (CTF) in which an insulating layer is used as a charge storage layer, and a flash memory device in which a conductive floating gate is used as a charge storage layer.

[0042] Each of the first and second volatile memories 320L and 320R may include at least one DRAM. In one embodiment, the at least one DRAM may be implemented with a dual-port DRAM. For example, first ports of the at least one DRAM may be connected to at least one of the first and second non-volatile memories 310L and 310R, and second ports thereof may be connected to a corresponding one of the first and second data buffers 330L and 330R.

[0043] The memory control circuit 340 may be implemented to receive a command or address from the host 100a and to generate a first command / address CAN for controlling the first and second non-volatile memories 310L and 310R or a second command / address CAD for controlling the first and second volatile memories 320L and 320R.

[0044] In one embodiment, memory control circuit 340 may issue an internal operation request for an internal operation and send it to host 100a. In one embodiment, memory control circuit 340 may receive the internal operation command IOP from host 100a and perform the internal operation based on the received internal operation command IOP. The internal operation command IOP may include the internal operation time for the internal operation.

[0045] The non-volatile memory module 300 in Fig. 5 may include at least one first non-volatile memory 310L, at least one first volatile memory 320L, and first data buffers 330L arranged on a left side with respect to the memory control circuit 340, and at least one second non-volatile memory 310R, at least one second volatile memory 320R, and second data buffers 330R arranged on a right side with respect to the memory control circuit 340. The non-volatile memory module 300 may have a different arrangement of memories, memory control circuits, buffers, etc. in another embodiment.

[0046] Fig. Figure 6 illustrates one embodiment of timing a host interface corresponding to the internal operation request of the non-volatile memory module 300. In this embodiment, the internal operation request IOP may be transmitted to the host 100a through a host interface between the host 100a and the non-volatile memory module 300. The host interface may be, for example, an internal memory channel. In one embodiment, the internal operation request may include an internal operation time to complete the internal operation or information about the internal operation time.

[0047] When a message including the internal operation request is transmitted to host 100a through a message port MSG, information corresponding to the internal operation time may also be sent to host 100a. The information corresponding to the internal operation time may be transmitted through data ports DQ0 to DQ7. In one embodiment, the information corresponding to the internal operation time may be transmitted through command / address ports CAs, such as a CKE port, a CS port, a CK port, or an ODT port.

[0048] Information related to the internal operation time can be selectively transmitted to host 100a by toggling the message port MSG. In one embodiment, a continuous toggling frequency of the message port MSG can indicate the internal operation time. For example, a continuous toggling frequency of the message port MSG can be a time for the internal operation.

[0049] In one embodiment, the internal operation request in the message may be an internal operation request for all or some banks. If the internal operation request for all banks is granted by the host 100a, the non-volatile memory module 300 may perform the internal operation with respect to all banks while the host 100a fails to access the non-volatile memory module 300. If the internal operation request for some of the banks is granted by the host 100a, the internal operation may be performed with respect to only one bank selected by the internal operation request among some of the banks. In this case, the remaining banks other than the selected bank may be accessed for a read / write operation.

[0050] In one embodiment, when the internal operation request and the information corresponding to the internal operation time are received, the host 100a may determine whether to grant or reject the internal operation request.

[0051] If the internal operation request is confirmed, the host 100a may issue the internal operation command IOP so that the non-volatile memory module 300 starts the internal operation. After that, the host 100a may not issue a new command to access the non-volatile memory module 300 during the internal operation time.

[0052] If the internal operation request is rejected, the host 100a may ignore the internal operation request by not executing an internal operation command and issue a command notifying the rejection of the internal operation request. The non-volatile memory module 300 may detect the rejection notification from the host 100a and defer or abandon the execution of the internal operation. In one embodiment, the internal operation time grant / reject information may not be included in the internal operation request of the non-volatile memory module 300.

[0053] Fig. 7 illustrates another embodiment of the host interface timing for the internal operation request of the non-volatile memory module 300. In this embodiment, the internal operation request may be provided in a two-operation procedure.

[0054] In a first operation, the non-volatile memory module 300 may send a signal for requesting the internal operation only to the host 100a through the message channel MSG and store internal operation time-related information (time information) in a buffer area of ​​the non-volatile memory module 300.

[0055] In a second operation, the host 100a may read the buffer area to issue a read command to extract the internal operation time for the internal operation. In one embodiment, the host 100a may issue the internal operation command IOP based on the read time information. Thereafter, the non-volatile memory module 300 may perform the internal operation during the internal operation time based on the internal operation command IOP.

[0056] Likewise, in the second operation, the host 100a issues a read command to extract the internal operation time of the buffer area. In another embodiment, the non-volatile memory module 300 may read the internal operation time grant / reject information stored in the buffer area based on the internal operation command IOP of the host 100a and perform the internal operation for the read internal operation time.

[0057] Fig. 8 illustrates another embodiment of a computing system having two memory modules connected to a memory channel. Referring to Fig. 8, a host may be connected to a first and second memory module DIMM1 and DIMM2 through a memory channel CH. Each of the first and second memory modules DIMM1 and DIMM2 may perform the internal operation. For descriptive convenience, it is assumed below that the second memory module DIMM2 performs the internal operation.

[0058] Fig. Figure 9 illustrates an embodiment of the timing of the first and second memory modules DIMM1 and DIMM2 when the second memory module DIMM2 of the computing system is in Fig. 8 performs the internal operation.

[0059] With reference to the Fig. 8 and Fig. 9, the second memory module DIMM2 can perform the internal operation during the internal operation time based on the internal operation command IOP. The internal operation can be a data transfer operation performed in the second memory module DIMM2. A host can prohibit access to the second memory module DIMM2 while the internal operation is being performed. Even if the host does not access the second memory module DIMM2, it can access the first memory module DIMM1 in an idle state. For example, in Fig. 9, the first memory module DIMM1 sequentially receives a precharge command PRE, an active command ACT, and a read command / address RD, and outputs data D0 to D7 corresponding to the read command / address RD. After that, the first memory module DIMM1 can proceed to perform the next read operation.

[0060] The computing system can conceal the internal operation of the second memory module DIMM2 after data communication between the host and the first memory module DIMM1. Because the internal operation of the second memory module DIMM2 is concealed, the system's performance can be improved.

[0061] Fig. 10 illustrates one embodiment of an internal operation command issued by a host of a computing system. Referring to Fig. 10, the host can issue internal operation commands IOPA and IOPB based on the internal operation request of the DIMM / NVDIMM memory module. The IOPA internal operation command can command internal operations for all banks of the DIMM / NVDIMM memory module. The second IOPB internal operation command can command internal operations for a single bank of the DIMM / NVDIMM memory module.

[0062] In one embodiment, an internal all-bank operation and an internal single-bank operation may be performed using an address port as in Fig. 10. In one embodiment, the internal operation commands IOPA and IOPB may be generated from a specific combination of command / address pins. Such combinations may be reserved for the reserved future use (RFU) of a typical DDR4 SDRAM. In one embodiment, command / address pins associated with the internal operation commands IOPA and IOPB may include CKE, CS, CAS, RAS, ACT, a bank address, and address pins.

[0063] In one embodiment, the internal operation instructions IOPA and IOPB may have an internal operation time that varies according to a programmed value applied to the address pins. For example, the programmed value may be programmed to correspond to address pins A0 through A9.

[0064] In the Fig. 8 and Fig. 9, a computing system connects two memory modules DIMM1 and DIMM2, which may be the same as each other, to a memory channel. In another embodiment, the computing system may connect the memory module DIMM and the non-volatile memory module NVDIMM to a memory channel.

[0065] Fig. 11 illustrates an embodiment of a server system. Referring to Fig. 11, the computing system can connect the DIMM memory module and the NVDIMM non-volatile memory module to a memory channel. The host can access the DIMM memory module while the internal operation described above is being performed on the NVDIMM non-volatile memory module, and vice versa. For example, the host can access the NVDIMM non-volatile memory module while the internal operation described above is being performed on the DIMM memory module.

[0066] In the calculation system in Fig. 11, the DIMM memory module and the NVDIMM non-volatile memory module are connected to one memory channel. In one embodiment, the computing system has the DIMM memory module and the NVDIMM non-volatile memory module each connected to two memory channels.

[0067] Fig. 12 illustrates another embodiment of a computing system. Referring to Fig. 12, the host may be connected to the DIMM memory module through a first channel CH1 and to the NVDIMM non-volatile memory module through a second channel CH2. The host may access the DIMM memory module while the above-described internal operation is performed on the NVDIMM non-volatile memory module. This embodiment may be applicable, for example, to a DRAM implemented in chip form instead of a memory module form.

[0068] Fig. 13 illustrates one embodiment of a DRAM 400, which may include a memory cell array 410 and a refresh controller 420. The memory cell array 410 may include a plurality of DRAM cells, each arranged at the intersection of word lines and bit lines. The refresh controller 420 may perform a refresh operation of the DRAM cells. In one embodiment, the refresh controller 420 may perform the refresh operation based on a refresh command from the host or external device.

[0069] In one embodiment, the refresh controller 420 may request an internal operation time from the host / external device when the internal operation is to be performed. The host / external device may send internal operation time grant / reject information to the refresh controller 420 based on the internal operation time request. The refresh controller 420 may receive the internal operation time grant / reject information to perform the refresh operation during the internal operation time. In one embodiment, the refresh controller 420 may perform the refresh operation with respect to all or some banks. This embodiment may be applicable, for example, to a 3D Xpoint memory in which electrical resistance is used as a bit.

[0070] Fig. 14 illustrates one embodiment of a computing system 40 that may include a processor 41, a memory module (DIMM) 42, and a non-volatile memory (NVM) 43. The processor 41 may control the memory module 42 and the non-volatile memory 43. In one embodiment, the processor 41 may issue an internal operation command based on an internal operation request of the memory module 42.

[0071] The memory module 42 can be connected to the processor 41 through the DDR interface. The memory module 42 can send the internal operation request to the processor 41 when the internal operation is to be performed. Likewise, the memory module 42 can be implemented to perform the internal operation based on an internal operation command from the processor 41.

[0072] Non-volatile memory 43 may be connected to processor 41 via the DDR-T (transaction) interface. In this case, memory module 42 may perform a caching function of non-volatile memory 43. In one embodiment, non-volatile memory 43 may be a 3D Xpoint memory. This embodiment is applicable, for example, to the internal operation of non-volatile memory 43.

[0073] Fig. 15 illustrates one embodiment of a method for operating a host. In this method, the host may receive the internal operation time request for performing the internal operation from various types of storage devices (DIMM, NVDIMM, DRAM, NVM, SSD, eMMC, SD card, UFS, etc.) connected to a storage channel (S110). The host may grant or reject the internal operation (e.g., a memory operation) based on the internal operation time request. The host may issue an internal operation command corresponding to the internal operation time request. The issued internal operation command may have an internal operation time (S120). The issued internal operation command may be transmitted to a storage device, and the storage device may perform the internal operation during the internal operation time based on the internal operation command.

[0074] Fig. 16 illustrates one embodiment of a method for operating a memory device. Referring to the Fig. 15 to 16, in this method, the storage device may determine whether to perform the internal operation according to an internal control and may send the internal operation time request for the internal operation to the host (S210). The internal operation time request may be transmitted to the host in various forms, such as message form or signal form. For example, the storage device may be implemented to send a message including the internal operation time request to the host.

[0075] Thereafter, the storage device may receive the internal operation command from the host, which includes information indicating the approval or rejection of the internal operation time (S220). The storage device may perform all or part of the internal operation based on the internal operation command (S230).

[0076] In one embodiment, when the internal operation command includes information indicating the granting of the internal operation time, the storage device may ignore a new command issued by the host while performing the internal operation. In one embodiment, when the internal operation command includes information indicating the rejection of the internal operation time, the storage device may receive a new command issued by the host. The storage device may receive and buffer a new command issued by the host while performing the internal operation. The storage device may first process a new command from the host after suspending the internal operation based on the new command. This embodiment may be applicable to, for example, a data server.

[0077] Fig. 17 illustrates an embodiment of a data server system 50, which may include a related database management system (RDBMS) 51, a cache server 52, and an application server 53. The cache server 52 may maintain and delete key and value pairs that are different from each other based on a deactivation message from the database management system 51. At least one of the related database management system 51, the cache server 52, or the application server 53 may be implemented with the host, the memory module DIMM, the non-volatile memory module NVDIMM, the DRAM, or the non-volatile memory as described with reference to FIG. Fig. 1 to 16 are described.

[0078] The methods, processes, and / or operations described herein may be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device may be those described herein or may include elements in addition to those described herein. Because the algorithms that form the basis of the methods (or operations of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments may transform the computer, processor, controller, or other signal processing device into a special-purpose processor for performing the methods described herein.

[0079] The controllers, processors, and other processing features of the embodiments disclosed herein may be implemented in logic, which may include, for example, hardware, software, or both. When implemented at least partially in hardware, the controllers, processors, or other processing features may be, for example, any one of a variety of integrated circuits, including but not limited to, an application-specific integrated circuit, a field-programmable gate array, a combination of logic gates, a system-on-chip, a microprocessor, or other type of processing or control circuit.

[0080] When implemented at least partially in software, the controllers, processors, and other processing features may include, for example, a memory or other storage device for storing code or instructions to be executed, for example, by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or may be an additional element to those described herein.Because the algorithms that form the basis of the methods (or operations of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments may convert the computer, processor, controller, or other signal processing device into a special-purpose processor for performing the methods described herein.

[0081] According to one or more of the aforementioned embodiments, a storage device may directly request an internal operation time for an internal operation of the storage device from a host, and the host may transfer authority for a time to the storage device during the internal operation time based on the request. Accordingly, it may be possible for the storage device to sufficiently perform the internal operation.

[0082] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some examples, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise indicated. Accordingly, it will be understood that various changes in form and details may be made without departing from the spirit and scope of the embodiments as set forth in the claims.

Claims

[1] A method of operating a memory device (200), the method comprising: sending an internal operation request for granting an internal operation of the storage device (200) to an external device, the internal operation request comprising a message indicating an internal operation time and generated by the storage device (200); receiving an internal operation command in response to the internal operation request from the external device, the internal operation command indicating whether the internal operation request is granted or rejected; and performing the internal operation by the storage device (200) during the internal operation time granted by the internal operation command when the requested internal operation has been granted by the external device. [2] The method of claim 1, further comprising sending a ready message signal to the external device and receiving a message read command to the storage device (200) prior to sending the internal operation request. [3] The method according to claim 1, wherein the internal operation time indicates a time period required to perform the internal operation. [4] The method of claim 1, wherein requesting the internal operation time comprises: storing the internal operation time in a buffer area of ​​the storage device (200); and transmitting the request to the external device using a message channel, wherein the method comprises reading the internal operation time stored in the buffer area and performing the internal operation for the read internal operation time when the internal operation command is received. [5] The method of claim 1, wherein receiving the internal operation command comprises receiving the internal operation command through at least one of at least one command port, at least one address port, or at least one reserved for future use (RFO) port. [6] The method of claim 1, wherein performing the internal operation comprises performing the internal operation with respect to all or some banks based on the internal operation command. [7] The method of claim 1, wherein: the internal operation command contains information indicating approval or rejection of the request, and the method comprises ignoring a new command issued by the external device if the internal operation command includes the information indicating the grant of the request. [8] The method of claim 1, wherein: the internal operation command contains information indicating approval or rejection of the request, and the method comprises processing a new command issued by the external device when the internal operation command includes the information indicating the rejection of the request. [9] The method of claim 1, wherein the internal operation comprises at least one of a refresh operation, a time dial calibration operation, or an internal data transfer operation. [10] The method of claim 1, wherein the memory device (200) comprises one of a dual in-line memory module (DIMM), a non-volatile dual in-line memory module (NVDIMM), a solid-state drive (SSD), a universal flash memory (UFS), an embedded multimedia card (eMMC), a secure digital (SD) card, a dynamic random access memory (DRAM), a static RAM (SRAM), a NAND flash memory, a vertical NAND flash memory, a phase shift random access memory (PRAM), or a resistive RAM (RRAM). [11] Non-volatile memory module (42) comprising: at least one volatile memory; at least one non-volatile memory (43); and a memory control circuit (340) for controlling the at least one volatile memory and the at least one non-volatile memory and for generating an internal operation request for granting an internal operation of the at least one volatile memory or the at least one non-volatile memory (43), wherein the memory control circuit (340) is to transmit an internal operation request message to an external device, receive an internal operation command indicating whether the internal operation request message is granted or rejected in response to the internal operation request message from the external device, and perform the internal operation by the memory control circuit (340) during an internal operation time when the internal operation has been granted by the external device, and where the internal operation request message has the internal operation time. [12] The non-volatile memory module (42) of claim 11, wherein the memory control circuit (340) is to ignore a new command issued by the external device while the internal operation is performed. [13] The non-volatile memory module (42) of claim 11, wherein the memory control circuit (340) is to process a new command issued by the external device when the internal operation command including information indicating a rejection of the internal operation request is received. [14] The non-volatile memory module (42) of claim 11, wherein the internal operation command comprises the internal operation time or information corresponding to the internal operation time. [15] The non-volatile memory module (42) of claim 11, wherein the memory control circuit (340) is to receive the internal operation command through at least one of at least one command port, at least one address port, or at least one RFU port. [16] The non-volatile memory module (42) of claim 11, wherein the memory module is to transmit the internal operation request message to the external device using at least one data port or at least one data strobe port. [17] The non-volatile memory module (42) of claim 11, wherein the memory control circuit (340) is to transmit the internal operation request message to the external device using signal switching via at least one message port. [18] The non-volatile memory module (42) according to claim 11, wherein the memory control circuit (340) is to store the internal operation time for the internal operation in a buffer area, transmit a signal corresponding to the internal operation request message to the external device through a message terminal, receive a read command corresponding to the signal from the external device, read the internal operation time stored in the buffer area based on the received read command, and receive the internal operation command corresponding to the internal operation time from the external device. [19] The non-volatile memory module (42) of claim 11, wherein the internal operation comprises a data transfer operation between the at least one volatile memory or the at least one non-volatile memory. [20] The non-volatile memory module (42) of claim 11, wherein the internal operation command comprises a first operation command indicating an internal operation with respect to all banks or a second internal operation command indicating an internal operation with respect to a single bank.

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