Data control circuit for flat panel display device and display device

Abstract

A data drive circuit for a flat panel display device is disclosed. Digital-to-analog control units (DACs) of a digital-to-analog conversion (DA conversion) unit and amplifiers of an output amplification unit are configured to have the same number, and a switch array is arranged between the output amplification unit and a contact pad. Therefore, by maintaining adjustment during a next horizontal period and performing superimposed driving, a settling time can be secured and distortion of a data signal can be prevented.

Description

Background of the inventionField of the invention

[0001] The present invention relates to a flat panel display device, and more particularly, to a data driving circuit of a flat panel display device for securing a setting time and preventing distortion of a data signal by maintaining the setting during a next horizontal period and performing superimposed driving. Discussion of the state of the art

[0002] US 2010 / 0 182 349 A1 discloses a display device with buffer sections and D / A converters.

[0003] Representative flat panel display devices for displaying images using digital data include liquid crystal displays (LCDs) that use liquid crystal and organic light-emitting diode displays (OLED displays) that use OLEDs.

[0004] Fig. 1 is a block diagram schematically illustrating a general LCD device.

[0005] In general, the LCD includes, as in Fig. 1, a timing control unit 130, a gate driver 140, a data driver 150, a liquid crystal panel 160, and a backlight unit 170. In the case of an OLED, there is a display panel comprising subpixels containing OLEDs. Thus, no backlight is required.

[0006] The timing control unit 130 outputs a gate timing control signal GDC for controlling an operation timing of the gate driver 140 and a data timing control signal DDC for controlling an operation timing of the data driver 150. The timing control unit 130 supplies a data signal DATA supplied from an image processor to the data driver 150 along with the data timing control signal DDC.

[0007] The gate driver 140 sequentially outputs a scanning pulse to each gate line GL in response to the gate timing control signal GDC supplied from the timing control unit 130. The gate driver 140 may be configured as an integrated circuit (IC) type or as a gate-in-panel (GIP) type mounted in the liquid crystal panel 160.

[0008] The data driver 150 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing control unit 130, and converts the sampled and latched data signal DATA into a gamma reference voltage. The data driver 150 inverts a polarity of a data voltage having the period of one frame and outputs it. The data driver 150 supplies the data voltage to the sub-pixels SP included in the liquid crystal panel 160 through each data line DL. The data driver 150 may be formed as an IC type.

[0009] The liquid crystal panel 160 displays images in accordance with the scanning signal supplied from the gate driver 140 and the data voltage supplied from the data driver 150. The liquid crystal panel 160 includes sub-pixels SP for controlling light provided by the backlight unit 170. Each sub-pixel includes a switching transistor, a storage capacitor, and a liquid crystal layer. A gate electrode of the switching transistor is connected to the gate line GL, and a source electrode of the switching transistor is connected to the data line DL. The storage capacitor is formed between a pixel electrode connected to a drain electrode of the switching transistor and a common electrode connected to a common voltage line.That is, the liquid crystal layer is formed between the pixel electrode connected to the drain electrode of the switching transistor and the common electrode connected to a common voltage line.

[0010] The liquid crystal panel 160 is implemented in a twisted nematic mode (TN mode), a vertical alignment mode (VA mode), an in-plane switching mode (IPS mode), a fringe field switching mode (FFS mode), or an electrically controlled birefringence mode (ECB mode) according to the structure of the pixel electrode and the common electrode.

[0011] The liquid crystal panel 160 may be implemented by red, green, and blue sub-pixels, or may be implemented by a white sub-pixel in addition to the red, green, and blue sub-pixels to reduce power consumption, each of which may be implemented by a color filter or, in the case of a white sub-pixel, by no color filter. In the case of an OLED, the colors may be implemented with or without a color filter.

[0012] The backlight unit 170 provides light to the liquid crystal panel 160 using a light source that emits light.

[0013] The data driver 150 will now be described in more detail.

[0014] Fig. 2 is a block diagram schematically illustrating an internal configuration of a general data driver.

[0015] The data driver contains, as in Fig. 2, a shift register SR, a first buffer LAT1, a second buffer LAT2, a digital-to-analog conversion unit (DA conversion unit) DAC, a switching array 143 and an output amplification unit 145.

[0016] The data driver converts a digital data signal into an analog data voltage and outputs the analog data voltage through its output channels CH1 to CHN according to operations of the shift register SR, the first and second latches LAT1 and LAT2, the conversion unit DAC, the switching array 143, and the output amplification unit 145. The configuration included in the data driver is briefly described below.

[0017] The shift register SR outputs a sampling signal in response to a source start pulse and a source sampling clock supplied from the timing control unit 130. The first and second latches LAT1 and LAT2 sequentially sample the digital data signal in response to the sampling signal output from the shift register SR and simultaneously output data signals corresponding to one scanned line in response to a source output enable signal SOE.

[0018] The DA conversion unit DAC converts the data signals corresponding to one line into analog data signals in response to first to n-th gamma gray voltages output from a gamma voltage generator (not shown).

[0019] The switching array 145 alternately outputs data voltages from two adjacent digital-to-analog converters (DACs) of the DA conversion unit DAC.

[0020] The output amplification unit 145 is located on the rear side of the switching array 143 and amplifies the data voltage outputs from the switching array 143.

[0021] A detailed configuration of the DA conversion unit DAC, the switching array 143 and the output amplification unit 145 will now be described.

[0022] Fig. 3 illustrates a detailed configuration of the DA conversion unit DAC, the switching array 143 and the output amplification unit 145 in the general data driver.

[0023] The DA conversion unit (DAC) contains as many DACs as there are channels. That is, if there are 3600 channels, the DA conversion unit (DAC) contains 3600 DACs (DAC1 to DAC3600).

[0024] The switching array 143 performs a switching operation such that data voltages from odd-numbered DACs and even-numbered DACs are alternately outputted among the plurality of DACs DAC1 to DAC3600.

[0025] The output amplification unit 145 includes a plurality of amplifiers AMP1 to AMP1800, which corresponds to half the number of channels. That is, if there are 3600 channels, the output amplification unit 145 includes 1800 amplifiers AMP1 to AMP1800. The amplifiers AMP1 to AMP1800 amplify a data voltage output from each pair of DACs corresponding to two adjacent DACs among the plurality of DACs.

[0026] However, such a conventional data drive circuit has the following problems.

[0027] Fig. 4 is a flowchart referred to to explain problems of a conventional data drive circuit.

[0028] That is, in order to implement superior loading characteristics even in a short horizontal period, since the loading characteristics are affected by the delay of the DA conversion unit DAC and since a fast slew rate during the short horizontal period should be secured only by an amplifier, it is difficult to guarantee a settling time.

[0029] Specifically, in the conventional data drive circuit, when a horizontal period is 2.7 µs, a settling time that reaches 99.3% of a target voltage is 2.11 µs. Therefore, the data drive circuit has difficulties in securing the settling time.

[0030] In addition, since the switching array 143 is located between the DA conversion unit DAC and the output amplification unit 145, ripples are generated in an output signal of the DA conversion unit DAC and an output signal of the output amplification unit 145, thereby causing distortion of data signals. Summary of the invention

[0031] Accordingly, the present invention is directed to a data drive circuit for a flat panel display device that substantially obviates one or more problems due to limitations and disadvantages of the related art.

[0032] An object of the present invention is to provide a data driving circuit for a flat panel display device to maintain setting during a next horizontal period, secure a setting time by superimposing driving, and prevent distortion of a data signal by configuring DACs of a DA conversion unit and amplifiers of an output amplification unit in equal numbers and configuring a switching array between the output amplification unit and a contact pad.

[0033] The object is achieved by the features of the independent claims. Preferred embodiments are given in the independent claims.

[0034] According to one embodiment of the present invention, a data drive circuit for a flat panel display device includes a shift register configured to output a sampling signal in response to a source start pulse and a source sampling clock from the timing control unit, a latch configured to sequentially sample a digital data signal in response to the sampling signal and simultaneously output data signals corresponding to a scanned line in response to a source output enable signal, a digital-to-analog conversion unit including a plurality of digital-to-analog converters and configured to convert the data signals corresponding to one line into analog data voltages in response to first to n-th gamma gray voltages, an output amplification unit including a plurality of amplifiers and configured to amplify analog data voltages, and a switching array configured toto alternately output output data voltages from two adjacent amplifiers of the output amplification unit such that the data voltages from two adjacent amplifiers of the output amplification unit are supplied to a contact pad.,

[0035] According to the invention, the digital / analog conversion unit and the output amplification unit contain digital / analog converters and amplifiers, each corresponding to the number of channels (CH).

[0036] Preferably, the switching array performs a switching operation such that data voltages from odd-numbered amplifiers and data voltages from even-numbered amplifiers are alternately outputted among the plurality of amplifiers.

[0037] Preferably, the number of digital / analog converters and amplifiers is the same.

[0038] Preferably, the switching array can be arranged between the output amplification unit and the contact pads of the liquid crystal panel.

[0039] Preferably, the number of contact pads is half the number of amplifiers or the number of digital / analog converters.

[0040] Preferably, the switching array alternately outputs data voltages from odd-numbered amplifiers and data voltages from even-numbered amplifiers.

[0041] Preferably, the data control circuit includes a shift register, a first buffer, a second buffer, a digital / analog conversion unit, an output amplification unit, and a switching array.

[0042] The object is also achieved by a display device which includes a timing control unit, a gate driver and a data control circuit according to the invention.

[0043] Preferably, the display device may further include a liquid crystal panel and a backlight unit.

[0044] Preferably, the display device may further include an OLED display panel.

[0045] It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. Brief description of the drawings

[0046] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

[0047] The drawings show: Fig. 1 is a block diagram schematically illustrating a general LCD device; Fig. 2 is a block diagram schematically illustrating an internal configuration of a general data driver; Fig. 3 shows a detailed configuration of a digital / analog converter, a switching array and an output amplifier of Fig. 2; Fig. 4 is a flowchart to which reference is made for explaining problems of a conventional data drive circuit; Fig. 5 is a block diagram schematically illustrating an internal configuration of a data driver according to the present invention; Fig. 6 shows a detailed configuration of a digital-to-analog converter, an output amplifier, and a switching array according to the present invention; and Fig. 7 is a waveform diagram of an output of a data drive circuit according to the present invention. Detailed description of the invention

[0048] A data drive circuit for a flat panel display device according to the present invention will now be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals are used throughout the drawings to refer to the same or similar parts.

[0049] A flat panel display device according to the present invention includes, as shown in Fig. 1, a timing control unit, a gate driver, a data driver and a flat panel display.

[0050] The timing control unit outputs a gate timing control signal for controlling an operation timing of the gate driver and a data timing control signal for controlling an operation timing of the data driver. The timing control unit supplies a data signal DATA, which is supplied from an image processor, to the data driver along with the data timing control signal.

[0051] The gate driver sequentially outputs a sampling pulse to each gate line GL in response to the gate timing control signal supplied from the timing control unit.

[0052] The data driver samples and latches the data signal DATA in response to the data timing control signal supplied from the timing control unit, and converts the sampled and latched data signal into a gamma reference voltage. The data driver supplies the data voltage through each data line DL to subpixels SP included in the flat panel display.

[0053] The flat panel display displays images in response to the scanning signal supplied by the gate driver and the data voltage supplied by the data driver.

[0054] The flat screen contains a liquid crystal panel or an OLED panel.

[0055] A configuration of the data driver according to the present invention will now be described in more detail.

[0056] Fig. 5 is a block diagram schematically illustrating an internal configuration of a data driver according to an embodiment of the present invention.

[0057] The data driver according to an embodiment of the present invention includes, as shown in Fig. 5, a shift register SR, a first buffer LAT1, a second buffer LAT2, a DA conversion unit DAC, an output amplification unit 145 and a switching array 143.

[0058] The shift register SR outputs a sampling signal in response to a source start pulse and a source sampling clock supplied from the timing control unit. The first and second latches LAT1 and LAT2 sequentially sample a digital data signal in response to the sampling signal output from the shift register SR and simultaneously output data signals corresponding to one scanned line in response to a source output enable signal SOE.

[0059] The DA conversion unit DAC converts the data signals corresponding to one line into analog data signals in response to first to n-th gamma gray voltages output from a gamma voltage generator (not shown).

[0060] The output amplification unit 145 is located on the rear side or downstream of the DA conversion unit DAC and amplifies and outputs the data voltage output from the DA conversion unit DAC.

[0061] The switching array 143 alternately outputs data voltages of the odd-numbered amplifiers AMP1, AMP3, ... AMP3599 and data voltages of the even-numbered amplifiers AMP2, AMP4, ... AMP3600 among the plurality of amplifiers AMP1 to AMP3600 of the output amplification unit 145. That is, the switching array 143 alternately outputs output data voltages from two adjacent amplifiers of the output amplification unit, so that the data voltages from two adjacent amplifiers of the output amplification unit are supplied to one contact pad.

[0062] A detailed configuration of the DA conversion unit DAC, the switching array 143 and the output amplification unit 145 will now be described.

[0063] Fig. 6 illustrates a detailed configuration of the DA conversion unit DAC, the output amplification unit 145, and the switching array 143 in the data driver according to the present invention.

[0064] The DA conversion unit DAC contains several DACs, equal to the number of channels. The output amplification unit 145 also contains several amplifiers AMP1 to AMP3600, equal to the number of channels.

[0065] That is, if there are 3600 channels, the DA conversion unit DAC and the output amplification unit 145 each contain 3600 DACs DAC1 to DAC3600 and 3600 amplifiers AMP1 to AMP3600. That is, the number of DACs is the same as the number of output amplification units.

[0066] The switching array 143 alternately outputs data voltages from odd-numbered amplifiers AMP1, AMP3, AMP5, ... and data voltages from even-numbered amplifiers AMP2, AMP4, AMP6, ... among the amplifiers AMP1 to AMP3600, so that the data voltages from two adjacent amplifiers among the amplifiers AMP1 to AMP3600 are supplied to one contact pad among contact pads PAD1 to PAD1800.

[0067] Fig.7 is a waveform diagram of an output of a data drive circuit according to the present invention.

[0068] Since the switching array 143 is not located between the DA conversion unit DAC and the output amplification unit 145, no ripples are generated in an output signal of the DA conversion unit DAC and an output signal of the output amplification unit 145.

[0069] Furthermore, in the data drive circuit according to the present invention, adjustment is maintained during a next horizontal period, and overlap is maintained in outputs of two adjacent amplifiers. Accordingly, since a adjustment time that achieves 99.3% of a target voltage is 0.97 µs, when a horizontal period is 2.7 µs, the adjustment time can be sufficiently secured.

[0070] The data driving circuit of the flat panel display device configured as described above according to the present invention has the following effects.

[0071] A virtual reality (VR) model display device requires a fast adjustment time within a short 1-horizontal (1H) period. According to the present invention, the number of DACs of the DA conversion unit is equal to the number of amplifiers of the output amplification unit, and the switching array is arranged between the output amplification unit and the contact pad. Therefore, since adjustment is maintained during a next horizontal period and superimposed driving is performed, an adjustment time within a short 1H period can be sufficiently secured, and distortion of a data signal can be prevented.

[0072] It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope of the invention. Thus, the present invention is intended to cover the modifications and variations of this invention within the scope of the appended claims and their equivalents.

Claims

[1] Data drive circuit for a flat panel display device, comprising: a shift register (SR) configured to output a sampling signal in response to a source start pulse and a source sampling clock from a timing control unit (130); a latch (LAT1, LAT2) configured to sequentially sample a digital data signal in response to the sampling signal and to simultaneously output data signals corresponding to a scanned line in response to a source output enable signal (SOE); a digital-to-analog conversion unit (DAC) including a plurality of digital-to-analog converters and configured to convert the data signals corresponding to one line into analog data voltages in response to first to n-th gamma gray voltages; an output amplification unit (145) containing a plurality of amplifiers (AMP) and configured to amplify analog data voltages, and a switching array (143) configured to alternately output output data voltages from two adjacent amplifiers (AMP1, AMP2) of the output amplification unit (145) such that the data voltages from two adjacent amplifiers (AMP1, AMP2) of the output amplification unit (143) are supplied to a contact pad (PAD1), wherein the digital-to-analog conversion unit (DAC) and the output amplification unit (145) include a number of digital-to-analog converters (DAC) and a number of amplifiers (AMP), each equal to a number of channels (CH) of the data drive circuit. [2] The data drive circuit according to claim 1, wherein the switching array (143) is configured to perform a switching operation such that data voltages from odd-numbered amplifiers (AMP1) and data voltages from even-numbered amplifiers (AMP2) are alternately outputted among the plurality of amplifiers. [3] Data drive circuit according to one of the preceding claims, wherein the switching array (143) is arranged between the output amplification unit (145) and the contact pads of the liquid crystal panel (100). [4] Data drive circuit according to one of the preceding claims, wherein the number of contact pads (PAD) is half the number of amplifiers (AMP) or the number of digital-to-analog converters (DAC). [5] Data drive circuit according to one of the preceding claims, wherein the switching array (143) alternately outputs data voltages from odd-numbered amplifiers (AMP1, AMP3, AMP5, ...) and data voltages from even-numbered amplifiers (AMP2, AMP4, AMP6, ...). [6] Data drive circuit according to one of the preceding claims, wherein the data drive circuit (150) includes a shift register (SR), a first buffer (LAT1), a second buffer (LAT2), a digital / analog conversion unit (DAC), an output amplification unit (145) and a switching array (143). [7] A display device comprising: a timing control unit (130), a gate driver (140), a data drive circuit (150) according to any one of the preceding claims, and a display panel (160). [8] The display device according to claim 7, further comprising a liquid crystal panel (160) and a backlight unit (170) or an OLED display panel without a backlight unit.

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