Repair circuit, display panel and display equipment

Abstract

The invention provides a repair circuit, a display panel and display equipment. The repairing circuit comprises a dedelay unit, an input end of which is connected with a grid electrode to-be-repaired signal and an output end of which is electrically connected with a first node; the input end of the shaping unit is electrically connected to the first node, and the output end is electrically connected to the second node; the input end of the inverting unit is electrically connected to the second node, and the output end is electrically connected to the third node. The de-delay unit is used for processing the grid signal to be repaired according to the clock signal and outputting a de-delay signal, so that the falling edge of the de-delay signal is consistent with the falling edge of the clock signal; the shaping unit is used for processing the rising edge waveform of the dedelayed signal and outputting a square wave signal opposite to the dedelayed signal in phase; and the inverting unit is used for performing inverting processing on the square wave signal and outputting a grid electrode repairing signal. The repairing circuit can effectively repair abnormal grid signals in the display panel, and the product yield is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a repair circuit, a display panel, and a display device. Background Art

[0002] During the display panel manufacturing process, various defective panels can be produced due to process defects. Among these defects, gate drive-related defects account for up to 30%. Poor gate drive results in abnormal output of the scan signal for that row, which manifests as dark or weak horizontal lines on the display. Typically, these products are downgraded or scrapped on the production line, increasing production costs. Summary of the Invention

[0003] The present application provides a repair circuit, a display panel and a display device, which aim to solve the problem of dark lines appearing on the display screen due to poor gate drive in the prior art.

[0004] In order to solve the above technical problems, the first technical solution provided by this application is to provide a repair circuit. The repair circuit is used to repair abnormal gate signals in a display panel. The repair circuit includes:

[0005] a de-delay unit, wherein the input terminal is connected to the gate repair signal and the output terminal is electrically connected to the first node; the de-delay unit is used to process the gate repair signal according to the clock signal and output the de-delay signal so that the falling edge of the de-delay signal is consistent with the falling edge of the clock signal;

[0006] A shaping unit, the input end of which is electrically connected to the first node, and the output end of which is electrically connected to the second node; the shaping unit is used to process the rising edge waveform of the de-delayed signal and output a square wave signal with a phase opposite to that of the de-delayed signal;

[0007] The inverting unit has an input end electrically connected to the second node and an output end electrically connected to the third node; the inverting unit is used to invert the square wave signal and output a gate repair signal.

[0008] In some embodiments, the delay removal unit includes a first voltage dividing unit and a first switching unit;

[0009] The input end of the first voltage divider unit is connected to the gate to be repaired signal, and the output end is electrically connected to the fourth node; the first voltage divider unit is used to perform voltage division processing on the gate to be repaired signal;

[0010] The control end of the first switch unit is electrically connected to the fourth node, the first end is connected to the clock signal, and the second end is electrically connected to the first node; after the gate to be repaired signal after voltage division controls the first switch unit to be turned on, the clock signal is output to the first node through the first switch unit to form a de-delay signal.

[0011] In some embodiments, the de-delay unit further includes a filtering unit and a pull-down unit;

[0012] The filtering unit is electrically connected to the fourth node and is used to filter out the noise signal with the same frequency as the clock signal in the gate repair signal after voltage division;

[0013] One end of the pull-down unit is electrically connected to the first node, and the other end is connected to the gate low level signal, so as to provide an initial potential to the second end of the first switch unit.

[0014] In some embodiments, the shaping unit includes a second switching unit and a first pull-up unit;

[0015] The control end of the second switch unit is electrically connected to the first node, the first end is electrically connected to the second node, and the second end is connected to the gate low level signal; one end of the first pull-up unit is electrically connected to the second node, and the other end is connected to the gate high level signal;

[0016] When the delay removal signal controls the second switch unit to be turned off, the second node outputs a high level; when the delay removal signal controls the second switch unit to be turned on, the second node outputs a low level.

[0017] In some embodiments, the inverting unit includes a second voltage dividing unit, a third switching unit, and a second pull-up unit;

[0018] The second voltage dividing unit is electrically connected to the second node and is used for performing voltage dividing processing on the square wave signal;

[0019] The control end of the third switch unit is electrically connected to the second node, the first end is electrically connected to the third node, and the second end is connected to the gate low level signal;

[0020] One end of the second pull-up unit is electrically connected to the third node, and the other end is connected to the gate high level signal;

[0021] When the square wave signal after voltage division controls the third switch unit to be turned off, the third node outputs a high level; when the square wave signal after voltage division controls the third switch unit to be turned on, the third node outputs a low level.

[0022] In order to solve the above technical problems, the second technical solution provided by this application is to provide a display panel. The display panel includes:

[0023] A driving substrate includes a pixel array region and two gate driving modules respectively disposed on either side of the pixel array region; the pixel array region is provided with a plurality of gate lines; the gate driving module includes a plurality of cascaded gate driving units, and opposite ends of the gate lines are respectively electrically connected to corresponding gate driving units;

[0024] A drive control board is provided on one side of the drive substrate and is coupled to the drive substrate;

[0025] Wherein, the driving control board includes the repair circuit provided in the above embodiment;

[0026] When the gate driving unit connected to one end of the gate line is abnormal, the opposite ends of the gate line are disconnected from the gate driving unit, and the normal gate driving unit at the other end of the gate line is electrically connected to the input end of the repair circuit, for providing a gate to be repaired signal to the repair circuit, and the opposite ends of the gate line are electrically connected to the output end of the repair circuit, for receiving the gate repair signal output by the repair circuit.

[0027] In some embodiments, the driving control board is coupled to the driving substrate through a plurality of chip-on-film (COF)s; the display panel further includes an input repair line and an output repair line;

[0028] The input repair line is electrically connected to the broken line on one side of the normal gate drive unit, and extends to the input end of the repair circuit through the chip on film (COF) and is electrically connected;

[0029] The two output repair lines are electrically connected to the two ends of the corresponding gate lines that are disconnected, and are extended to the output end of the repair circuit through the chip-on-film (COF) and electrically connected.

[0030] In some embodiments, the drive control board includes a first drive control unit and a second drive control unit disposed on the same side of the pixel array area; the repair circuit is disposed in the first drive control unit; an end of the gate line close to the first drive control unit is a first end, and an end of the gate line close to the second drive control unit is a second end;

[0031] The input repair line and the output repair line on one side of the first end extend to the repair circuit through the chip-on-film (COF) away from the outside of the second driving control unit;

[0032] The input repair line and the output repair line on one side of the second end extend to the second drive control unit through the chip-on-film COF away from the outside of the first drive control unit, extend along the second drive control unit to the position of the second drive control unit close to the first drive control unit, and then extend again to the drive substrate along the chip-on-film COF on the side of the second drive control unit close to the first drive control unit, extend in the direction close to the first drive control unit to the position of the chip-on-film COF on the side of the first drive control unit close to the second drive control unit, and extend along the chip-on-film COF to the first drive control unit, and be electrically connected to the repair circuit.

[0033] In some embodiments, the chip-on-film (COF) is divided into a data region and a gate region. The gate region is located on both sides of the data region. The data region is provided with a driver chip, and the gate region is used for wiring. The input repair line and the output repair line are located in the gate region and extend along the gate region.

[0034] In order to solve the above technical problems, the third technical solution provided by this application is to provide a display device. The display device includes:

[0035] A display panel, which is the display panel provided in the above embodiment;

[0036] The central control board is used to provide a driving control signal to the display panel so that the display panel displays a corresponding image.

[0037] Beneficial effects of the present application: Different from the prior art, the present application provides a repair circuit, display panel, and display device. The repair circuit is used to repair abnormal gate signals in the display panel. The repair circuit includes a de-delay unit, a shaping unit, and an inverting unit. The de-delay unit has an input terminal connected to the gate signal to be repaired, and an output terminal electrically connected to a first node. The de-delay unit is used to process the gate signal to be repaired according to the clock signal and output a de-delay signal so that the falling edge of the de-delay signal is aligned with the falling edge of the clock signal. The shaping unit has an input terminal electrically connected to the first node, and an output terminal electrically connected to the second node. The shaping unit is used to process the rising edge waveform of the de-delay signal and output a square wave signal with a phase opposite to that of the de-delay signal. The inverting unit has an input terminal electrically connected to the second node, and an output terminal electrically connected to the third node. The inverting unit is used to invert the square wave signal and output a gate repair signal. The present application achieves effective repair of the gate signal to be repaired through the coordinated operation of the de-delay unit, shaping unit, and inverting unit, thereby avoiding the problem of dark lines on the display screen caused by poor gate drive in the display panel, and effectively improving product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0039] Figure 1 is a structural diagram of a display panel provided in one embodiment of the present application;

[0040] Figure 2 This is a schematic structural diagram of a chip-on-film (COF) provided in one embodiment of the present application;

[0041] Figure 3 is a structural diagram of a repair circuit provided in one embodiment of the present application;

[0042] Figure 4 1 is a schematic structural diagram of a delay removal unit provided in one embodiment of the present application;

[0043] Figure 5 It corresponds to Figure 4 Schematic diagram of simulation waveform of the delay removal unit in FIG;

[0044] Figure 6 is a structural diagram of a delay removal unit provided in another embodiment of the present application;

[0045] Figure 7 It corresponds to Figure 6 Schematic diagram of simulation waveform of the delay removal unit in FIG;

[0046] Figure 8 This is a schematic structural diagram of a shaping unit provided in one embodiment of the present application;

[0047] Figure 9 It corresponds to Figure 8 Schematic diagram of simulation waveform of the shaping unit in;

[0048] Figure 10 1 is a schematic structural diagram of an inverting unit provided in one embodiment of the present application;

[0049] Figure 11 It corresponds to Figure 10 Schematic diagram of simulation waveform of the inverting unit in FIG;

[0050] Figure 12 This is a schematic diagram of the structure of an output module provided in one embodiment of the present application;

[0051] Figure 13 It corresponds to Figure 12 A schematic diagram of status output provided by an embodiment of the output module;

[0052] Figure 14 1 is a flow chart of a method for repairing a display panel provided in one embodiment of the present application;

[0053] Figure 15 It is a structural diagram of a display device provided in one embodiment of the present application.

[0054] Reference numerals:

[0055] 100, display panel; 10, driving substrate; 11, pixel array area; 12, gate driving module; 121, first gate driving module; 122, second gate driving module; 123, gate driving unit; 123nL, first side n-stage driving unit 123nL; 123nR, second side n-stage driving unit 123nR; 13, input repair line; 13L, first side input line 13L; 13R, second side input line 13R; 14, output repair line; 14L, first side output line 14L; 14R, second side output line 14R; 20, driving control board; 21, first driving control unit; 211, first connection Connector; 22, second drive control unit; 221, second connector; 30, repair circuit; 31, de-delay unit; 311, first voltage divider; 312, first switch unit; 313, filter unit; 314, pull-down unit; 32, shaping unit; 321, second switch unit; 322, first pull-up unit; 33, inverting unit; 331, second voltage divider; 332, third switch unit; 333, second pull-up unit; 41, driver chip; 401, data area; 402, gate area; 50, output module; 51, resistor-capacitor unit; 52, transmission channel; 53, target transistor; 200, central control board;

[0056] X, row direction; Y, column direction; COF, chip-on-film COF; G1~Gw, gate lines; Gn, gate line of the nth row; M1, first transistor; M2, second transistor; M3, third transistor; R1, first voltage-dividing resistor; R2, second voltage-dividing circuit; R3, pull-down resistor; R4, first pull-up resistor; R5, third voltage-dividing resistor; R6, second pull-up resistor; C1, filter capacitor; N1, first node; N2, second node; N3, third node; N4, fourth node; G, gate; D, drain; S, source; Gin, gate to be repaired signal; Gout, gate repair signal; CLK, clock signal; VGH, gate high signal; VGL, gate low signal; GND, ground. DETAILED DESCRIPTION

[0057] The following describes the embodiments of the present application in detail with reference to the accompanying drawings.

[0058] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0059] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0060] The terms "first," "second," and "third" in this application are used only for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of such features. In the description of this application, "multiple" means at least two, for example, two, three, etc., unless otherwise specifically defined. All directional indications in the embodiments of this application (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship, movement, etc. between the components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications also change accordingly. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products, or devices.

[0061] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0062] The present application will be described in detail below with reference to the accompanying drawings and embodiments.

[0063] See also Figure 1 , Figure 1 FIG2 is a schematic diagram of the structure of a display panel provided in one embodiment of the present application. In this embodiment, a display panel 100 is provided. The display panel 100 includes a drive substrate 10 and a drive control board 20. The drive control board 20 is coupled to the drive substrate 10 and is configured to provide a drive signal to the drive substrate 10, thereby controlling the display panel 100 to display an image.

[0064] The driving substrate 10 includes a pixel array area 11 and two gate driving modules 12 respectively arranged on both sides of the pixel array area 11; the pixel array area 11 is provided with a plurality of gate lines G1 to Gw; the gate driving module 12 includes a plurality of cascaded gate driving units 123, and the opposite ends of the gate lines G1 to Gw are respectively electrically connected to the corresponding gate driving units 123;

[0065] The driving control board 20 is disposed on one side of the driving substrate 10 and is coupled to the driving substrate 10 ; the driving substrate 10 includes a repair circuit 30 as provided in the following embodiment;

[0066] When the gate driving unit 123 connected to one end of the gate lines G1~Gw is abnormal, both ends of the gate lines G1~Gw are disconnected from the gate driving unit 123, and the normal gate driving unit 123 at the other end of the gate lines G1~Gw is electrically connected to the input end of the repair circuit 30, for providing the gate to-be-repaired signal Gin to the repair circuit 30, and the opposite ends of the gate lines G1~Gw are electrically connected to the output end of the repair circuit 30, for receiving the gate repair signal Gout output by the repair circuit 30.

[0067] The pixel array region 11 includes a plurality of sub-pixels (not shown) arranged in an array within the pixel region. A plurality of gate lines G1-Gw are arranged along the pixel column direction Y and disposed between pixel rows. Each gate line G1-Gw extends along the pixel row direction X and has both ends electrically connected to a corresponding gate driver unit 123.

[0068] The gate driver modules 12 are arranged on both sides of the pixel array area 11 along the pixel row direction X. Each gate driver module 12 includes multiple cascaded gate driver units 123. One end of each gate line G1-Gw is electrically connected to the corresponding gate driver unit 123 in the gate driver module 12 closest to that end, while the other end of each gate line G1-Gw is electrically connected to the corresponding gate driver unit 123 in the other gate driver module 12 closest to that end. In other words, the display panel 100 utilizes bilateral gate drive, with the gate driver modules 12 on both sides simultaneously driving both ends of the same gate line G1-Gw. Specifically, the gate driver modules 12 include a first gate driver module 121 and a second gate driver module 122. The first gate driver module 121 is electrically connected to the first end of each gate line G1-Gw, and the second gate driver module 122 is electrically connected to the second end of each gate line G1-Gw. During the drive scanning process of the gate driver modules 12, the first gate driver module 121 and the second gate driver module 122 simultaneously drive the same gate line G1-Gw, achieving bilateral drive.

[0069] The drive control board 20 is disposed on one side of the drive substrate 10 along the pixel column direction Y and is coupled to the drive substrate 10 via a chip on film (COF). It is used to provide the required drive signals and power signals to the pixel array area 11 and the gate drive unit 123. The drive control board 20 also includes a repair circuit 30 for repairing abnormal gate signals.

[0070] When a gate driver unit 123 on one side of the gate lines G1-Gw experiences an abnormality, the gate signal on the gate line G1-Gw will become abnormal, and the pixels in the corresponding row will be abnormally driven, resulting in an abnormal image on the display panel 100. Specifically, the gate driver unit 123 electrically connected to the n-th row of gate line Gn is defined as the n-th stage gate driver unit 123. The n-th stage gate driver unit 123 in the first gate driver module 121 and the n-th stage gate driver unit 123 in the second gate driver module 122 are electrically connected to the first end and the second end of the n-th row of gate line Gn, respectively, to simultaneously drive the n-th row of gate line Gn. When one of the n-th stage gate driver unit 123 in the first gate driver module 121 and the n-th stage gate driver unit 123 in the second gate driver module 122 experiences an abnormality, the gate signal on the n-th stage gate line Gn will become abnormal, resulting in an abnormal image on the display panel 100.

[0071] To solve the above technical problems, the two ends of the n-th row gate line Gn are respectively disconnected from the n-th level gate driving unit 123 in the first gate driving module 121 and the n-th level gate driving unit 123 in the second gate driving module 122, and the normal n-th level gate driving unit 123 among the n-th level gate driving unit 123 in the first gate driving module 121 and the n-th level gate driving unit 123 in the second gate driving module 122 is electrically connected to the input end of the repair circuit 30 to provide the gate to-be-repaired signal Gin to the repair circuit 30, and the two ends of the n-th row gate line Gn are electrically connected to the output end of the repair circuit 30. The gate signal in the normal n-th level gate driving unit 123 is transmitted to the input end of the repair circuit 30 through the wiring. Due to the influence of the in-plane wiring RC, there is a delay problem in the gate to-be-repaired signal Gin sent to the repair circuit 30. The gate to-be-repaired signal Gin is repaired by the repair circuit 30, and the gate repair signal Gout is output at the output end and the n-th row gate line Gn is driven simultaneously through both ends of the n-th row gate line Gn, thereby completing the effective repair of the abnormal gate signal of the n-th row.

[0072] For example, the following description uses the case where the gate signal output by the n-th gate driving unit 123 in the second gate driving module 122 is abnormal, resulting in abnormal driving of the n-th row of gate lines Gn. The n-th gate driving unit 123 in the first gate driving module 121 is a normal gate driving unit 123, and the gate signal it outputs is normal, serving as the gate to-be-repaired signal Gin. This example is used in the following embodiments.

[0073] Specifically, the drive control board 20 is coupled to the drive substrate 10 via several COFs. The display panel 100 also includes an input repair line 13 and an output repair line 14. The input repair line 13 is electrically connected to the broken line on the normal gate drive unit 123 side and extends through the COF to the input of the repair circuit 30 and is electrically connected thereto. The two output repair lines 14 are respectively electrically connected to the two ends of the corresponding gate line Gn that are broken and extend through the flip chip module to the output of the repair circuit 30 and are electrically connected thereto.

[0074] For example, if the n-th row gate line Gn is driven abnormally, the n-th level gate drive unit 123 in the second gate drive module 122 is abnormal, and the n-th level gate drive unit 123 in the first gate drive module 121 is normal. The two ends of the n-th row gate line Gn are disconnected from the corresponding gate drive unit 123, and the disconnected portion of the n-th level gate drive unit 123 in the first gate drive module 121 is electrically connected to the input repair line 13. The input repair line 13 is arranged between the gate drive module 12 and the pixel array area 11, and extends along the pixel column direction Y to a position on the side of the drive substrate 10 close to the drive control board 20, and then extends through the chip-on-film (COF) to the input end of the repair circuit 30 and is electrically connected to the input segment. The output repair line 14 is arranged between the gate drive module 12 and the pixel array area 11, and is spaced apart from the input repair line 13. Two output repair lines 14, one of which is arranged between the first gate driving module 121 and the pixel array area 11, and is electrically connected to the first end of the n-th row gate line Gn that is disconnected; the other output repair line 14 is arranged between the second gate driving module 122 and the pixel array area 11, and is electrically connected to the second end of the n-th row gate line Gn that is disconnected; the two output repair lines 14 extend along the column direction Y of the pixel to a side close to the drive control board 20, and extend to the output end of the repair circuit 30 through a suitable flip chip film COF and are electrically connected to the output end.

[0075] In some embodiments, the drive control board 20 further includes a first drive control unit 21 and a second drive control unit 22, which are disposed on the same side of the pixel array area 11. A repair circuit 30 is disposed within the first drive control unit 21. The ends of the gate lines G1-Gw closest to the first drive control unit 21 are designated as first ends, while the ends closest to the second drive control unit 22 are designated as second ends. The input repair line 13 and the output repair line 14 on the first end extend to the repair circuit 30 via a chip-on-film (COF) located outside the second drive control unit 22. The input repair line 13 and the output repair line 14 on one side of the second end extend to the second drive control unit 22 through the chip-on-film COF away from the outside of the first drive control unit 21, extend along the second drive control unit 22 to the position of the second drive unit close to the first drive control unit 21, and then extend again to the drive substrate 10 along the chip-on-film COF on the side of the second drive control unit 22 close to the first drive control unit 21, extend in the direction close to the first drive control unit 21 to the position of the chip-on-film COF on the side of the first drive control unit 21 close to the second drive control unit 22, and extend along the chip-on-film COF to the first drive control unit 21, and are electrically connected to the repair circuit 30.

[0076] Specifically, the drive control board 20 includes a first drive control unit 21 and a second drive control unit 22 arranged along the pixel row direction X; considering that the second drive control unit 22 may have insufficient flash memory space, the repair circuit 30 is set in the first drive control unit 21.

[0077] Exemplarily, the input repair line 13 and the output repair line 14 defined between the first gate driving module 121 and the pixel array area 11 are respectively the first side input line 13L and the first side output line 14L, and the input repair line 13 and the output repair line 14 defined between the second gate driving module 122 and the pixel array area 11 are respectively the second side input line 13R and the second side output line 14R. The first drive control unit 21 and the second drive control unit 22 are each coupled to the drive substrate 10 via a plurality of chip-on-film (COFs). The COFs are arranged sequentially from the first drive control unit 21 to the second drive control unit 22. The COFs coupled to the first drive control unit 21 are defined as COF1, COF2, ..., COFa, and the COFs coupled to the second drive control unit 22 are defined as COFb, COF(b+1), ..., COFc, along the direction from the first drive control unit 21 to the second drive control unit 22. Here, a, b, and c are positive integers, and b = a+1, meaning COFa is adjacent to COFb. Furthermore, the n-th gate driver unit 123 in the first gate driver module 121 is defined as the first-side n-th gate driver unit 123nL, and the n-th gate driver unit 123 in the second gate driver module 122 is defined as the second-side n-th gate driver unit 123nR.

[0078] When an abnormality occurs in the n-stage driving unit 123nR on the second side and the n-stage driving unit 123nL on the first side is normal, the driving of the n-th row gate line Gn may be abnormal. To correct the abnormality, the first and second ends of the n-th row gate line Gn are disconnected from the n-stage driving unit 123nL and the second-side n-stage driving unit 123nR on the first side, respectively. The disconnected end of the normal first-side n-stage driving unit 123nL is electrically connected to the first-side input line 13L, and the first and second ends of the n-th row gate line Gn are electrically connected to the first-side output line 14L and the second-side output line 14R, respectively.

[0079] Among them, the first side input line 13L and the second side output line 14R extend along the column direction Y of the pixel on the driving substrate 10, extend to the outermost COF1 through the fan-shaped area, and then extend to the first driving control unit 21 through COF1, and are electrically connected to the input and output ends of the repair circuit 30 respectively.

[0080] Among them, the second side input line 13R and the second side output line 14R extend along the column direction Y of the pixel on the driving substrate 10, extend to the outermost COFc through the fan-shaped area, and extend to the second driving control unit 22. In the second driving control unit 22, they extend to the position of COFb on the second driving control unit 22 closest to the first driving control unit 21, re-enter the driving substrate 10 through COFb, and then extend toward the first driving control unit 21 on the driving substrate 10, and then enter the first driving control unit 21 through COFa on the first driving control unit 21 closest to the second driving control unit 22, and are electrically connected to the input end and output end of the repair circuit 30 respectively.

[0081] When an abnormality occurs in the first-side n-stage driver unit 123nL and a normal second-side n-stage driver unit 123nR, the drive of the n-th row gate line Gn may also be abnormal. To correct this abnormality, the first and second ends of the n-th row gate line Gn are similarly disconnected from the first-side n-stage driver unit 123nL and the second-side n-stage driver unit 123nR, respectively. Then, the disconnected end of the normal second-side n-stage driver unit 123nR is electrically connected to the second-side input line 13R, and the first and second ends of the n-th row gate line Gn are electrically connected to the first-side output line 14L and the second-side output line 14R, respectively. Specifically, the wiring method of the first-side input line 13L, the first-side output line 14L, the second-side input line 13R, and the second-side output line 14R is the same as in the above example.

[0082] Taking into account the limited in-plane wiring space of the driving substrate 10 and the insufficient space for wiring the repair line, the above-mentioned wiring method of the first side input line 13L, the first side output line 14L, the second side input line 13R and the second side output line 14R is used, so that the second side input line 13R and the second side output line 14R are first connected to the second driving control unit 22 through the outermost COFc, and then re-enter the driving substrate 10 through the COFb on the side of the second driving control unit 22 closest to the first driving unit, and then enter the first driving control unit 21 through the COFa on the side of the first driving control unit 21 closest to the second driving control unit, and finally enter the repair circuit 30, thereby solving the problem of limited in-plane wiring space and difficult wiring of the driving substrate 10.

[0083] Moreover, compared to a method in which the second-side input line 13R and the second-side output line 14R are connected from the second connector 221 of the second drive control unit 22 through a central control board (CB) or a client system on a chip (SOC) to the corresponding signals of the second connector 221 and the first connector 211 of the first drive control unit 21, and finally enter the first drive control unit 21 from the first connector 211 and then connect to the repair circuit 30, this method of connecting the repair line through a connector, while relatively easy to implement, has a universality issue. The first connector 211 and the second connector 221 have a universal pin definition depending on the data transmission protocol. Using this repair line connection method, two new signals (input and output) need to be added to the pin definition of each connector. First, due to the limited number of pins, there may not be space for these new signals. Second, after the pin definition is changed, the client system on a chip (SOC) must also undergo separate design changes to match, which makes the SOC non-universal. In addition, the cost of redeveloping a dedicated SOC is significantly increased. In the embodiment of the present application, the second-side input line 13R and the second-side output line 14R are wired in the above-mentioned manner. No changes are required to the client SOC, and all repairs can be completed only on the panel (Open Cell, OC) side. This reduces the difficulty of introduction and greatly reduces the repair cost, thereby effectively reducing the production cost of the product.

[0084] Specifically, in this embodiment, the first-side input line 13L and the first-side output line 14L are connected to the repair circuit only through the outermost COF1. The second-side input line 13R and the second-side output line 14R are electrically connected to the repair circuit via a wiring scheme of COFc-second drive control unit 22-COFb-drive substrate 22-COFa-first drive control unit 21. Electrical connection to the repair circuit is achieved only through the chip-on-film (COF) that enters the drive control board. This means that repair can be completed within the display panel alone. Compared to routing signals through a connector in the second drive control unit, this wiring scheme does not need to consider issues such as insufficient universal connector pins and the need to redesign the client's SOC to match the connector after pin definition changes. This wiring scheme does not require changes to the pins of the connector on the drive control unit and is therefore compatible with existing client SOCs. No modifications are required to the client SOC, resulting in a simpler structure, lower implementation difficulty, and significantly reduced repair difficulty, resulting in better repair results. Furthermore, repair costs can be significantly reduced, effectively reducing product production costs.

[0085] See also Figure 2 , Figure 2 This is a schematic diagram of the structure of a chip-on-film (COF) according to one embodiment of the present application. Specifically, the COF is divided into a data region 401 and a gate region 402, with the gate regions 402 located on either side of the data region 401. The data region 401 houses a driver chip 41, while the gate region 402 is used for wiring. The input repair line 13 and the output repair line 14 are located in and extend along the gate region 402.

[0086] Specifically, the areas on either side of the COF are typically used to set up simple, direct connections between the upper and lower wiring, while the center area is used to set up the driver chip 41 and the wiring connected to the driver chip 41 (not shown). Based on the structural characteristics of the COF, the present embodiment further reduces wiring difficulty by placing the input repair line 13 and the output repair line 14 in the gate area 402 on both sides.

[0087] Combine Figure 1 Specifically, the routing portions of the second-side input line 13R and the second-side output line 14R on COFc can be arranged in the gate region 402 on the side of COFc away from COFb, the routing portions on COFb can be arranged in the gate region 402 on the side of COFb close to COFa, and the routing portions on COFa can be arranged in the gate region 402 on the side of COFa close to COFb. The routing portions of the first-side input line 13L and the first-side input line 13L on COF1 can be arranged in the gate region 402 on the side of COF1 away from COFa. Specifically, depending on the specific wiring situation, the routing portion of the repair line on the COF can be arranged in one or both of the two gate regions 402 to reduce the routing length and reduce the impact of the routing RC.

[0088] The specific structure of the repair circuit 30 and the signal repair process are shown in the following embodiments. Please refer to the following detailed description.

[0089] See also Figure 3 , Figure 3 : is a schematic diagram of the structure of a repair circuit 30 provided in an embodiment of the present application. In this embodiment, a repair circuit 30 is provided, which is used to repair abnormal gate signals in a display panel 100. The repair circuit 30 includes:

[0090] The de-delay unit 31 has an input terminal connected to the gate repair signal Gin and an output terminal electrically connected to the first node N1. The de-delay unit 31 is configured to process the gate repair signal Gin according to the clock signal CLK and output a de-delay signal such that the falling edge of the de-delay signal coincides with the falling edge of the clock signal CLK.

[0091] The shaping unit 32 has an input end electrically connected to the first node N1 and an output end electrically connected to the second node N2; the shaping unit 32 is used to process the rising edge waveform of the de-delayed signal and output a square wave signal with a phase opposite to that of the de-delayed signal;

[0092] The inverting unit 33 has an input terminal electrically connected to the second node N2 and an output terminal electrically connected to the third node N3. The inverting unit 33 is used to invert the square wave signal and output the gate repair signal Gout.

[0093] It should be noted that the n-th level gate driving unit 123 on the normal side in the above embodiment is electrically connected to the input end of the de-delay unit 31 through the input repair line 13 to provide the gate signal to be repaired Gin. When the gate signal output by the n-th level driving unit 123nL on the first side enters the input end of the de-delay unit 31 through the input repair line 13, there is a signal delay. If it is directly sent back to the other end of the n-th row gate line Gn through the wiring, due to the more serious delay of the in-plane wiring RC, the gate drive on the other side of the n-th row gate line Gn will have a mischarging problem. The repair circuit 30 provided in the embodiment of the present application can be used to align the falling edge of the gate signal to be repaired Gin with the corresponding normal clock signal CLK, so as to achieve effective repair of the gate signal.

[0094] The de-delay unit 31 receives the gate repair signal Gin at its input and performs de-delay processing on the gate repair signal Gin based on the corresponding clock signal CLK. The processed output signal is defined as the de-delay signal, which is then output to the first node N1. The de-delay unit 31 processes the gate repair signal Gin so that the falling edge of the output de-delay signal is aligned with the corresponding clock signal CLK, thereby eliminating the delay at the falling edge of the gate repair signal Gin.

[0095] The input end of the shaping unit 32 receives the de-delay signal from the first node N1 and processes the rising edge of the de-delay signal to output a square wave signal to the second node N2. The output square wave signal is inverted from the de-delay signal, meaning that the high and low levels of the square wave signal are opposite to those of the de-delay signal.

[0096] The input end of the inverting unit 33 receives the square wave signal from the second node N2 and inverts the square wave signal, causing the high-level portion of the square wave signal to become a low level and the low-level portion to become a high level. The signal output after the inversion conversion is defined as the gate repair signal Gout, which is then output to the third node N3, thereby completing the processing of the gate to-be-repaired signal Gin. The third node N3 is electrically connected to the output end of the repair circuit 30.

[0097] The embodiment of the present application realizes effective repair of the gate repair signal Gin through the coordinated work of the above-mentioned de-delay unit 31, the shaping unit 32 and the inverting unit 33, thereby avoiding the problem of dark lines appearing on the display screen due to poor gate drive in the display panel 100, and effectively improving the product yield.

[0098] See also Figure 4 and Figure 5 , Figure 4 is a schematic structural diagram of a delay removal unit 31 provided in an embodiment of the present application. Figure 5 It corresponds to Figure 4 Schematic diagram of simulation waveforms of the de-delay unit 31 in FIG. Specifically, the de-delay unit 31 includes a first voltage divider 311 and a first switch unit 312. The input end of the first voltage divider 311 is connected to the gate to-be-repaired signal Gin, and the output end is electrically connected to the fourth node N4. The first voltage divider 311 is used to divide the gate to-be-repaired signal Gin. The control end of the first switch unit 312 is electrically connected to the fourth node N4, the first end is connected to the clock signal CLK, and the second end is electrically connected to the first node N1. After the gate to-be-repaired signal Gin after voltage division controls the first switch unit 312 to turn on, the clock signal CLK is output to the first node N1 through the first switch unit 312, forming a de-delayed signal.

[0099] Among them, the voltage difference between the high level and the low level of the gate to be repaired signal Gin is △V, and due to the device specification limitation, the maximum voltage difference between the control end and the second end of the first switch unit 312 is less than △V. Therefore, the gate to be repaired signal Gin is voltage-divided by setting the first voltage divider unit 311. The processed gate to be repaired signal Gin is transmitted to the control end of the first switch unit 312 through the fourth node N4 to control the first switch unit 312.

[0100] The first end of the first switch unit 312 is connected to the clock signal CLK corresponding to the n-th gate driver unit 123, and the second end is electrically connected to the first node N1. When the gate repair signal Gin after voltage division is at a high level, the first switch unit 312 is turned on. After turning on, because the clock signal CLK at the first end is at a high level, the second end also outputs a high level. When the clock signal CLK transitions to a low level, the second end also switches to a low level, thereby achieving the effect of prematurely shutting off the gate repair signal Gin after voltage division. This ensures that the falling edge of the de-delay signal outputted from the second end is fully aligned with the falling edge of the corresponding clock signal CLK.

[0101] Specifically, the first voltage dividing unit 311 includes a first voltage dividing resistor R1 and a second voltage dividing resistor R2 connected in series.

[0102] One end of the first voltage-dividing resistor R1 is connected to the gate-to-repair signal Gin, and the other end is electrically connected to the fourth node N4.

[0103] One end of the second voltage-dividing resistor R2 is electrically connected to the fourth node N4 , and the other end thereof is connected to the gate low level signal VGL.

[0104] The first switch unit 312 includes a first transistor M1, wherein the control terminal of the first transistor M1 is electrically connected to the fourth node N4, the first terminal is connected to the corresponding clock signal CLK, and the second terminal is electrically connected to the fourth node N4. Specifically, the first transistor M1 can be an NMOS transistor, wherein the control terminal of the first transistor M1 is the gate G, the first terminal is the drain D, and the second terminal is the source S.

[0105] Because the maximum VGS specification of the first transistor M1 is 30V, and the high-level and low-level voltage difference ΔV of the gate-to-repair signal Gin reaches 37V, a first voltage divider unit 311 is provided to divide the gate-to-repair signal Gin to reduce the voltage difference ΔV. Specifically, after voltage division by the first voltage divider resistor R1 and the second voltage divider resistor R2, the voltage at the fourth node N4 is (Gin-VGL)·R2 / (R1+R2). In a specific application, the voltage dividing effect of the gate-to-repair signal Gin can be adjusted by adjusting the resistance values of the first voltage divider resistor R1 and the second voltage divider resistor R2, so that the voltage at the fourth node N4 meets the specification requirements of the first transistor M1.

[0106] When the signal at the fourth node N4 is at a high level, the first transistor M1 is turned on. After being turned on, the clock signal CLK of the drain D is at a high level, and the source S outputs a high level. When the clock signal CLK of the drain D is converted to a low level, the source S is also switched to a low level, so that the falling edge of the signal output by the source S is completely aligned with the falling edge of the clock signal CLK, thereby completing the de-delay effect on the falling edge of the gate to-be-repaired signal Gin.

[0107] See also Figure 6 and Figure 7 , Figure 6 is a structural diagram of a delay removal unit 31 provided in another embodiment of the present application. Figure 7 It corresponds to Figure 6 Schematic diagram of simulation waveforms of the de-delay unit 31 in FIG. Furthermore, in some embodiments, the de-delay unit 31 further includes a filtering unit 313 and a pull-down unit 314; the filtering unit 313 is electrically connected to the fourth node N4 and is configured to filter out noise having the same frequency as the clock signal CLK from the voltage-divided gate repair signal Gin; the pull-down unit 314 is electrically connected to the first node N1 at one end and connected to the gate low-level signal VGL at the other end to provide an initial potential to the second end of the first switch unit 312.

[0108] like Figure 5 As shown in the figure, since the first end of the first switch unit 312 is connected to the corresponding clock signal CLK, and the clock signal CLK has continuous pulses in one frame, while the gate repair signal Gin has only one pulse in one frame, due to the gate-drain parasitic capacitance Cgd of the first transistor M1, there will be noise at the gate G end with the same frequency as the clock signal CLK. The noise is the waveform spike that appears when the first node N1 signal (the signal at the gate G) is at a high level and is higher than the low level when the clock signal CLK is at a high level. Figure 7 As shown, in this embodiment, a filtering unit 313 is connected to the fourth node N4 to filter out the noise (i.e., waveform spikes) in the gate repair signal Gin after the above voltage division that is at the same frequency as the clock signal CLK, thereby effectively suppressing signal noise and improving the signal repair effect.

[0109] Furthermore, a pull-down unit 314 is connected to the first node N1 to provide an initial potential to the second end of the first switch unit 312. Specifically, when the first switch unit 312 is turned on, the pull-down unit 314 provides an initial potential to the second end of the first switch unit 312, allowing current to flow normally from the first end to the second end and the pull-down unit 314, thereby forming a current path and preventing a short circuit. When the first switch unit 312 is turned off, the gate low-level signal VGL at the other end of the pull-down unit 314 provides an initial potential to the second end of the first switch unit 312, allowing the first switch unit 312 to remain in a normally closed state, thereby preventing leakage current caused by incomplete closing of the first switch. In other words, by providing an initial signal to the second end of the first switch unit 312, the first switch unit 312 can switch normally, thereby improving the delay reduction effect of the delay reduction unit 31.

[0110] Specifically, if Figure 6 As shown, the filter unit 313 includes a filter capacitor C1, one end of which is electrically connected to the first node N1 and the other end is grounded GND. The pull-down unit 314 includes a pull-down resistor R3, one end of which is electrically connected to the second node N2 and the other end is connected to the gate low level signal VGL.

[0111] Among them, the filter capacitor C1 can be used to offset the gate-drain parasitic capacitance Cgd of the first transistor M1, thereby filtering out the noise (waveform protrusion) with the same frequency as the clock signal CLK in the gate repair signal Gin after voltage division, effectively suppressing signal noise and improving the signal repair effect.

[0112] See also Figure 8 and Figure 9 , Figure 8 is a structural diagram of the shaping unit 32 provided in one embodiment of the present application. Figure 9 It corresponds to Figure 8 Schematic diagram of the simulation waveform of the shaping unit 32 in FIG. In this embodiment, the shaping unit 32 includes a second switch unit 321 and a first pull-up unit 322. The control end of the second switch unit 321 is electrically connected to the first node N1, the first end is electrically connected to the second node N2, and the second end is connected to the gate low-level signal VGL. One end of the first pull-up unit 322 is electrically connected to the second node N2, and the other end is connected to the gate high-level signal VGH. When the de-delay signal controls the second switch unit 321 to be turned off, the second node N2 outputs a high level; when the de-delay signal controls the second switch unit 321 to be turned on, the second node N2 outputs a low level.

[0113] It should be noted that after the gate repair signal Gin is de-delayed by the de-delay unit 31, its falling edge is aligned with the falling edge of the corresponding clock signal CLK, forming a de-delayed signal, which is output to the first node N1. Figure 5 and Figure 7 As shown, the de-delay signal output to the first node N1 after being processed by the de-delay unit 31 does not meet the gate signal specification requirements due to the voltage division process. Therefore, the de-delay signal cannot be directly sent back to the gate line Gn of the nth row in the plane. Moreover, it can be seen from the figure that there is a climbing waveform at the front end of the pulse of the de-delay signal. If it is directly sent back to the gate lines G1~Gw in the plane to drive the sub-pixels, the switching effect of the driving transistor of the sub-pixel will be poor. Therefore, in the embodiment of the present application, the de-delay signal is further shaped by the shaping unit 32 to output a square wave signal, so that the pulse front end of the signal meets the square wave shape, so that the signal can normally drive the driving transistor of the sub-pixel in the corresponding row.

[0114] Among them, when the de-delay signal is at a low level, the second switch unit 321 is closed, and the potential of the first end of the second switch unit 321 will be pulled up to a high level by the gate high level signal VGH; when the de-delay signal is changed to a high level, the second switch unit 321 is turned on, and a path is formed from the gate high level signal VGH, the first pull-up unit 322, the second switch unit 321 to the gate low level signal VGL, so that the potential of the first end of the second switch unit 321 will be pulled down to a low level by the gate low level signal VGL, so that the first end of the second switch unit 321 outputs a square wave signal, thereby achieving a shaping effect on the de-delay signal.

[0115] By connecting the first pull-up unit 322 in series between the gate high signal VGH and the second switch unit 321 , the gate high signal VGH and the gate low signal VGL are not directly short-circuited when the second transistor M2 is turned on.

[0116] Specifically, the second switch unit 321 includes a second transistor M2, the control terminal of the second transistor M2 being electrically connected to the second node N2, the first terminal being electrically connected to the third node N3, and the second terminal being connected to a low-level signal. The first pull-up unit 322 includes a first pull-up resistor R4, one terminal of the first pull-up resistor R4 being electrically connected to the third node N3 and the other terminal being connected to a gate high-level signal VGH. Specifically, the second transistor M2 can be an NMOS transistor, the control terminal of the second transistor M2 being the gate G, the first terminal being the drain D, and the second terminal being the source S.

[0117] When the delay removal signal at the first node N1 is at a low level, the second transistor M2 is turned off. At this time, the drain D of the second transistor M2 is pulled up to a gate-high level by the gate-high signal VGH. When the delay removal signal at the first node N1 is at a high level, the second transistor M2 is turned on. The drain D is pulled down to a gate-low level by the gate-low signal VGL. Consequently, the drain D of the second transistor M2 outputs a square wave signal to the second node N2.

[0118] By connecting a first pull-up resistor R4 in series between the gate high signal VGH terminal and the drain D of the second transistor M2, a direct short circuit between the gate high signal VGH terminal and the gate low signal VGL terminal is prevented when the second transistor M2 is turned on. The resistance value of the first pull-up resistor R4 can be set based on the signal values of the repair circuit 30 and the specifications of the various components, and is not specifically limited thereto.

[0119] After the delay-removed signal has been shaped as above, Figure 9 As shown, it can be seen that when the de-delay signal at the gate G of the second transistor M2 is at a low level, the square wave signal output at the second node N2 is at a gate high level; when the de-delay signal is at a high level, the square wave signal output at the second node N2 is at a gate low level. That is, the shaping unit 32 shapes the de-delay signal and outputs a square wave signal to complete the shaping process of the signal's pulse rising edge climbing waveform, and makes the high-low level voltage difference of the output square wave signal the same as the high-low level voltage difference of the gate signal, thereby completing the shaping process of the de-delay signal. It can be seen that the square wave signal waveform output by the shaping unit 32 to the second node N2 is inversely proportional to the de-delay signal waveform. Therefore, the square wave signal needs to be inverted to obtain the gate repair signal Gout required for the n-th row gate line Gn.

[0120] See also Figure 10 and Figure 11 , Figure 10 is a structural diagram of the inverting unit 33 provided in one embodiment of the present application, Figure 11 It corresponds to Figure 10Schematic diagram of the simulation waveform of the inverting unit 33 in the embodiment. In this embodiment, the inverting unit 33 includes a second voltage divider unit 331, a third switch unit 332 and a second pull-up unit 333. The second voltage divider unit 331 is electrically connected to the second node N2 and is used to divide the square wave signal. The control end of the third switch unit 332 is electrically connected to the second node N2, the first end is electrically connected to the third node N3, and the second end is connected to the gate low level signal VGL. One end of the second pull-up unit 333 is electrically connected to the third node N3, and the other end is connected to the gate high level signal VGH. When the square wave signal after voltage division controls the third switch unit 332 to be turned off, the third node N3 outputs a high level; when the square wave signal after voltage division controls the third switch unit 332 to be turned on, the third node N3 outputs a low level.

[0121] Since the high- and low-level voltage difference of the square wave signal is ΔV, and the maximum voltage difference between the control terminal and the second terminal of the third switch unit 332 is less than ΔV due to device specification limitations, the second voltage divider unit 331 is provided to divide the square wave signal. The processed square wave signal is applied to the control terminal of the first switch unit 312 to control the first switch unit 312. Specifically, when the second switch unit 321 in the shaping unit 32 is closed, a path is formed between the first pull-up unit 322 and the second voltage divider unit 331. The first pull-up unit 322 and the second voltage divider unit 331 divide the gate high-level signal VGH, thereby achieving voltage division processing of the square wave signal.

[0122] The square wave signal after voltage division is applied to the control terminal of the third switch unit 332 to control the switching of the third switch unit 332. When the square wave signal after voltage division is at a high level, the third switch unit 332 is turned on, and the first terminal of the third switch unit 332 is pulled down to the gate low level. When the square wave signal after voltage division is at a low level, the third switch unit 332 is turned off, and the first terminal of the third switch unit 332 is pulled up to the gate high level. This causes the waveform of the signal output from the first terminal to be inversely proportional to the waveform of the square wave signal, and the high and low levels of the waveform output from the first terminal to be the same as the high and low levels of the gate signal, thereby forming the gate repair signal Gout and completing the repair of the gate to-be-repaired signal Gin.

[0123] The second pull-up unit 333 is connected in series between the gate high level signal VGH and the third switch unit 332 , so that the gate high level signal VGH and the gate low level signal VGL are not directly short-circuited when the third transistor M3 is turned on.

[0124] Specifically, the second voltage divider unit 331 includes a third voltage divider resistor R5; one end of the third voltage divider resistor R5 is electrically connected to the second node N2, and the other end is connected to the gate low signal VGL. The third switch unit 332 includes a third transistor M3; the control end of the third transistor M3 is electrically connected to the second node N2, the first end is electrically connected to the third node N3, and the second end is connected to the gate low signal VGL. The second pull-up unit 333 includes a second pull-up resistor R6; one end of the second pull-up resistor R6 is electrically connected to the third node N3, and the other end is connected to the gate high signal VGH.

[0125] The third voltage-dividing resistor R5 and the first pull-up resistor R4 work together to divide the square wave signal. After the voltage division, the high level at the second node N2 is (VGH-VGL)·R5 / (R4+R5). The resistance values of the first pull-up resistor R4 and the third voltage-dividing resistor R5 can be set according to the required voltage division requirements and the specifications of the various circuit components, and are not specifically limited thereto.

[0126] The third transistor M3 may be an NMOS transistor, with a control terminal of the third transistor M3 being the gate G, a first terminal being the drain D, and a second terminal being the source S. A square wave signal after voltage division acts on the gate G of the third transistor M3. When the square wave signal after voltage division is at a high level, the third transistor M3 is turned on, and the voltage at the drain D of the third transistor M3 is pulled down to a gate-low voltage level. When the square wave signal after voltage division is at a low level, the third transistor M3 is turned off, and the voltage at the drain D of the third transistor M3 is pulled up to a gate-high voltage level, thereby inverting the square wave signal. The desired gate repair signal Gout is generated and outputted at the drain D of the third transistor M3. The high and low levels of the gate repair signal Gout are identical to those of the desired gate signal, and the falling edge is aligned with the falling edge of the corresponding clock signal CLK, thereby effectively repairing the gate-to-repair signal Gin.

[0127] Furthermore, a knob resistor can be provided at the output end of the third node N3 and electrically connected thereto, so that the waveform of the gate signal to be repaired Gin passes through the knob resistor and is transmitted to the corresponding gate lines G1 to Gw through the output repair line 14 to complete the repair of the abnormal gate signal on the display panel 100. Since the routing path lengths of the output repair lines 14 corresponding to abnormal gate lines at different positions are different, their corresponding RCs are also different. In this application, a knob resistor is connected in series at the output end of the third node N3, thereby adjusting the resistance value to match the gate lines at different positions, thereby further improving the repair effect of the gate signal. Specifically, the longer the routing path length of the output repair line 14, the smaller the resistance value of the knob resistor.

[0128] In some high-precision application scenarios, on the one hand, impedance matching of abnormal gate lines at different locations through knob resistors requires manual adjustment of the knob resistors, and the adjustment accuracy cannot meet the requirements; on the other hand, during the manual adjustment of the knob resistors, frequent contact with the panel will inevitably cause friction, and it is also very likely to cause static damage to the display panel. To solve this technical problem, in some embodiments, an output module 50 (see FIG. 5 ) is provided at the output end of the third node N3. Figure 12 ), the output module 50 can perform impedance matching on abnormal gate lines Gn at different positions through a digitally adjustable impedance matching method, and the adjustment accuracy is adjustable to meet high-precision requirements. In addition, the digital adjustment method does not require manual adjustment and can improve the anti-static ability. For details, please refer to the detailed introduction below.

[0129] See also Figure 12 , Figure 12 1 is a schematic diagram of the structure of the output module provided in one embodiment of the present application. In this embodiment, the repair circuit further includes an output module 50, which includes a plurality of RC units 51 connected in series with the output end of the third level node N3 and a plurality of transmission channels 52 connected in parallel.

[0130] A transmission channel 52 is connected between every two adjacent RC units 51 , and each transmission channel 52 is electrically connected to the repair output terminal of the output module 36 . At least one target transistor 53 is connected in series to each transmission channel 52 .

[0131] The gate of the target transistor is used to input a target control signal, and the target control signal is used to control the conduction of a target transmission channel 52 among the multiple transmission channels 52, so as to transmit the gate repair signal Gout to the repair output end through the target transmission channel 52 after passing through at least one resistor-capacitor unit 51 between the target transmission channel 52 and the output end of the level conversion unit 35.

[0132] The position of the target transmission channel 52 among the multiple transmission channels 52 matches the position of the scanning line Gn where the abnormality occurs.

[0133] Here, the multiple transmission channels 52 can be arranged in multiple rows along the horizontal direction, and the multiple resistor-capacitor units 51 (i.e., RC units) can be arranged in a column along the vertical direction with the output end of the level conversion unit 35, and a transmission channel 52 is connected between every two adjacent resistor-capacitor units 51.

[0134] In one embodiment, the RC unit 51 includes a resistor and a capacitor, the resistor and the capacitor are connected in parallel, and one end of the capacitor is grounded GND.

[0135] In one embodiment, the number of the RC units 51 is the same as the number of the transmission channels 52 , for example, both are 8.

[0136] In one embodiment, each transmission channel 52 may include one or more target transistors 53. For example, the number of target transistors 53 included in multiple transmission channels 52 may be the same, and the target transistors 53 included in different transmission channels 52 may be controlled by different target control signals.

[0137] In one embodiment, the target transistor 53 may be an N-type metal-oxide-semiconductor field-effect transistor (NMOS) or a P-type metal-oxide-semiconductor field-effect transistor (PMOS). For example, the target transistor 53 is a PMOS transistor. When the target control signal is low, the target transistor 53 is turned on. When the target control signal is high, the target transistor 53 is turned off.

[0138] In one embodiment, in the case where an abnormality occurs at a target position (such as the position of the nth row gate line Gn), that is, in the impedance matching process of a normal signal, only one target transmission channel 52 is turned on, that is, the gate repair signal Gout at the output end of the level conversion unit 35 is only transmitted to the repair output end through one target transmission channel 52.

[0139] In one embodiment, different transmission channels 52 have different numbers of RC units 51 connected in series with the output end of the level conversion unit 35 . The lower the transmission channel 52 is, the more RC units 51 are connected in series with the output end of the level conversion unit 35 .

[0140] For example, one RC unit 51, R51C51, is connected in series between the first row of transmission channels 52 and the output of the level shifter 35. Two RC units 51, R51C51 and R52C52, are connected in series between the second row of transmission channels 52 and the output of the level shifter 35. Eight RC units 51, R51C51, R52C52 through R58C58, are connected in series between the eighth row of transmission channels 52 and the output of the level shifter 35. The greater the number of RC units 51 connected in series between a transmission channel 52 and the output of the third node N3, the greater the impedance corresponding to the transmission channel 52.

[0141] In one embodiment, the position of the target transmission channel 52 in the multi-row transmission channels 52 matches the target position where the abnormal gate signal occurs, which may refer to the position of the target transmission channel 52 in the multi-row transmission channels 52 corresponding to the position of the target row where the abnormal scan signal occurs in the pixel array area 11.

[0142] For example, the target row is located at the upper part in the pixel array area 11, and the selected target transmission channel 52 is also located at the upper part in the multi-row transmission channels 52, such as selecting the 1st row or the 2nd row; the target row is located in the middle part in the pixel array area 11, and the selected target transmission channel 52 is also located in the middle part in the multi-row transmission channels 52, such as selecting the 4th row; the target row is located in the lower part in the pixel array area 11, and the selected target transmission channel 52 is also located at the lower part in the multi-row transmission channels 52, such as selecting the 7th row or the 8th row.

[0143] In this way, based on the relative position of the abnormal gate signal in the pixel array area 11, a target transmission channel 52 with a matching position is selected. When the impedance matching requirements required for different abnormal positions are different, the impedances provided by the resistor-capacitor units 51 corresponding to different target transmission channels 52 are different, thereby achieving accurate and flexible impedance matching, improving accuracy, and avoiding low accuracy and electrostatic damage caused by manual adjustment of the variable resistor.

[0144] In some embodiments, the target control signal includes: a plurality of first control signals and a plurality of second control signals, the number of first control signals and second control signals is the same, and each second control signal is an inverted signal of a first control signal. For example, the plurality of first control signals include D2, D1, and D0, and the plurality of second control signals include an inverted signal of D2. The inverted signal of D1 and the inverted signal of D0

[0145] The gate of each target transistor 53 is used to input a first control signal or a second control signal; based on different combinations of multiple first control signals and multiple second control signals, a target transmission channel 52 is controlled to be turned on.

[0146] Here, controlling a target transmission channel 52 to be turned on may refer to controlling all target transistors 53 in the target transmission channel 52 to be turned on. A first control signal or a second control signal may be input to multiple target transistors 53 located in the same column, and the multiple target transistors 53 located in the same column may be located in different transmission channels 52.

[0147] For example, Figure 12 As shown, the first control signal and the second control signal are both 3, the first control signal includes, and the second control signal includes the inverted signal of D2 The inverted signal of D1 and the inverted signal of D0 R51C51, R52C52, ..., R58C58 are the first to eighth resistor-capacitor units 51, respectively.

[0148] In one embodiment, different combinations may refer to different phase combinations. By controlling the phase combinations of multiple first control signals, multiple second control signals can be controlled simultaneously. Each combination of multiple first control signals only corresponds to one transmission channel 52 being turned on.

[0149] Please refer to Figure 13 , Figure 13 It corresponds to Figure 13 For example, when the target position or target row where the abnormal scanning signal is located corresponds to the middle of the pixel array area 11, the phases of D2, D1 and D0 are controlled to be 1, 0 and 0 respectively, and the second control signals are 0, 1 and 1 respectively. Figure 13 As shown, when the target transistors 53 are PMOS transistors, only all target transistors 53 in the fourth transmission channel 52 among the multiple rows of transmission channels 52 are turned on, that is, the fourth transmission channel 52 serves as the target transmission channel 52, and at least one target transistor 53 in the remaining transmission channels 52 is turned off, that is, the remaining transmission channels 52 remain closed. At this time, the gate repair signal Gout at the output end of the level conversion unit 35 is transmitted to the repair output end through the first four RC units 51 and the fourth transmission channel 52.

[0150] In this way, by controlling the phase of the first control signal, the switching control of all target transistors 53 can be achieved, and then by combining different combinations of the first control signal, the switching control of different row transmission channels 52 can be accurately achieved, thereby further improving the accuracy and convenience of channel selection control.

[0151] Please refer to Figure 1 and Figure 14 , Figure 14 1 is a flow chart of a method for repairing a display panel 100 according to one embodiment of the present application. In this embodiment, a method for repairing a display panel 100 is provided for repairing abnormal gate signals in the display panel 100; wherein the display panel 100 may be the display panel 100 provided in the above embodiment. The method for repairing the display panel 100 includes:

[0152] S10: Determine the gate line Gn corresponding to the abnormal gate signal and the gate driving unit 123 on the abnormal side;

[0153] S20: Cutting off the electrical connection between the two ends of the abnormal gate line Gn and the gate driving unit 123;

[0154] S30: electrically connecting the gate broken line connected to the gate driving unit 123 on the normal side to the input repair line 13, and electrically connecting the output repair lines 14 on both sides to the two ends of the abnormal gate line Gn respectively;

[0155] S40: The repair circuit 30 receives the gate repair signal Gin collected by the input repair line 13, repairs the gate repair signal Gin, and transmits the gate repair signal Gout to both ends of the abnormal gate line Gn through the output repair lines 14 on both sides.

[0156] The specific wiring method of the input repair line 13 and the output repair line 14 is the same as Figure 1 The specific structure and function of the repair circuit 30 are the same or similar to those of the repair circuit 30 provided in the above embodiment, and can achieve the same technical effect.

[0157] In step S10, the gate line Gn corresponding to the abnormal gate signal and the gate driving unit 123 on the abnormal side are tested. Specifically, the gate lines G1 to Gw can be tested first to determine the gate line Gn with an abnormal signal, and then the gate driving units 123 connected to both ends of the gate line Gn with an abnormal signal are tested to determine the gate driving unit 123 on the abnormal side. Alternatively, the gate driving units 123 on both sides can be directly tested to determine the gate driving unit 123 with an abnormal signal, and then the corresponding gate line Gn with an abnormal signal can be determined based on the abnormal gate driving unit 123.

[0158] In step S20, the two ends of the abnormal gate line Gn are disconnected from the corresponding gate drive unit 123 so that the abnormal gate signal is no longer sent to the gate line Gn. Then, through step S30, the gate signal of the gate drive unit 123 on the normal side is transmitted to the repair circuit 30 through the input repair line 13 as the gate signal to be repaired Gin. Then, through step S40, the repair circuit 30 repairs the gate signal to be repaired Gin, and then transmits the gate repair signal Gout to the two ends of the abnormal gate line Gn respectively through the output repair line 14, so that the two ends of the abnormal gate line Gn are driven simultaneously by the gate repair signal Gout, so that the sub-pixels corresponding to the abnormal scanning line can be driven normally, avoiding the problem of mischarging.

[0159] Through the above-mentioned repair method, by collecting the gate repair signal Gin output by the normal gate driving unit 123 on one side of the abnormal gate line Gn, and making the repair circuit 30 repair the gate repair signal Gin, it is transmitted to the two ends of the abnormal gate line Gn through the output repair lines 14 on both sides, so that the gate repair signal Gout drives both ends of the gate line Gn at the same time to solve the problem that one end of the abnormal gate line Gn is normal and the other end is mischarged, thereby completing the effective repair of the abnormal gate signal in the display panel 100, which can effectively improve the product yield.

[0160] See also Figure 15 , Figure 15 FIG2 is a schematic diagram of the structure of a display device provided in one embodiment of the present application. In this embodiment, a display device is provided, which includes a display panel 100 and a central control board 200. The central control board 200 is coupled to the display panel 100 and is configured to provide a driving control signal to the display panel 100 so that the display panel 100 displays a corresponding image.

[0161] Among them, the specific structure and function of the display panel 100 are the same or similar to the structure and function of the display panel 100 provided in the above embodiment, and can achieve the same technical effects. For details, please refer to the detailed introduction above and will not be repeated here.

[0162] In some embodiments, the display device may further include peripheral components, which are electrically connected to the display panel to implement corresponding functions to expand the usage scenarios of the display device.

[0163] The above is only an implementation method of the present application and does not limit the scope of patent protection of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the scope of patent protection of the present application.

Claims

1. A repair circuit for repairing abnormal gate signals in a display panel, characterized in that: include: a de-delay unit, wherein the input terminal is connected to the gate to-be-repaired signal, and the output terminal is electrically connected to the first node; The de-delay unit is used to process the gate to-be-repaired signal according to the clock signal and output a de-delayed signal so that the falling edge of the de-delayed signal is consistent with the falling edge of the clock signal; a shaping unit, the input end of which is electrically connected to the first node, and the output end of which is electrically connected to the second node; the shaping unit is used to process the rising edge waveform of the de-delayed signal and output a square wave signal with a phase opposite to that of the de-delayed signal; An inverting unit, whose input end is electrically connected to the second node and whose output end is electrically connected to the third node; the inverting unit is used to invert the square wave signal and output a gate repair signal.

2. The repair circuit according to claim 1, characterized in that: The delay removal unit includes a first voltage dividing unit and a first switch unit; The input end of the first voltage divider unit is connected to the gate to be repaired signal, and the output end is electrically connected to the fourth node; the first voltage divider unit is used to perform voltage division processing on the gate to be repaired signal; The control end of the first switch unit is electrically connected to the fourth node, the first end is connected to the clock signal, and the second end is electrically connected to the first node; after the gate to be repaired signal after voltage division controls the first switch unit to be turned on, the clock signal is output to the first node through the first switch unit to form the de-delay signal.

3. The repair circuit according to claim 2, characterized in that: The de-delay unit further includes a filtering unit and a pull-down unit; The filtering unit is electrically connected to the fourth node, and is used to filter out noise signals having the same frequency as the clock signal in the gate repair signal after voltage division; One end of the pull-down unit is electrically connected to the first node, and the other end is connected to a gate low level signal, so as to provide an initial potential to the second end of the first switch unit.

4. The repair circuit according to claim 1, characterized in that: The shaping unit includes a second switch unit and a first pull-up unit; The control end of the second switch unit is electrically connected to the first node, the first end is electrically connected to the second node, and the second end is connected to the gate low level signal; one end of the first pull-up unit is electrically connected to the second node, and the other end is connected to the gate high level signal; When the delay removal signal controls the second switch unit to be turned off, the second node outputs a high level; when the delay removal signal controls the second switch unit to be turned on, the second node outputs a low level.

5. The repair circuit according to claim 1 or 4, characterized in that: The inverting unit includes a second voltage dividing unit, a third switch unit and a second pull-up unit; The second voltage dividing unit is electrically connected to the second node, and is used to perform voltage dividing processing on the square wave signal; The control end of the third switch unit is electrically connected to the second node, the first end is electrically connected to the third node, and the second end is connected to the gate low level signal; One end of the second pull-up unit is electrically connected to the third node, and the other end is connected to the gate high level signal; When the square wave signal after voltage division controls the third switch unit to be turned off, the third node outputs a high level; when the square wave signal after voltage division controls the third switch unit to be turned on, the third node outputs a low level.

6. A display panel comprising: A driving substrate comprising a pixel array area and two gate driving modules respectively arranged on both sides of the pixel array area; The pixel array area is provided with a plurality of gate lines; the gate driving module includes a plurality of cascaded gate driving units, and opposite ends of the gate lines are electrically connected to corresponding gate driving units respectively; a driving control board, disposed on one side of the driving substrate and coupled to the driving substrate; It is characterized in that the drive control board includes a repair circuit according to any one of claims 1 to 5; When the gate driving unit connected to one end of the gate line is abnormal, the opposite ends of the gate line are disconnected from the gate driving unit, and the normal gate driving unit at the other end of the gate line is electrically connected to the input end of the repair circuit to provide a gate to-be-repaired signal to the repair circuit, and the opposite ends of the gate line are electrically connected to the output end of the repair circuit to receive the gate repair signal output by the repair circuit.

7. The display panel according to claim 6, wherein: The drive control board is coupled to the drive substrate via a plurality of COFs; the display panel further includes an input repair line and an output repair line; The input repair line is electrically connected to the broken line on one side of the normal gate driving unit, and extends to the input end of the repair circuit through the chip on film (COF) and is electrically connected; The two output repair lines are respectively electrically connected to the disconnected ends of the corresponding gate lines, and extend to the output end of the repair circuit through the chip-on-film (COF) and are electrically connected.

8. The display panel according to claim 7, wherein: The drive control board includes a first drive control unit and a second drive control unit disposed on the same side of the pixel array area; the repair circuit is disposed in the first drive control unit; the end of the gate line close to the first drive control unit is a first end, and the end close to the second drive control unit is a second end; The input repair line and the output repair line on one side of the first end extend to the repair circuit through a chip-on-film (COF) away from the outside of the second driving control unit; The input repair line and the output repair line on one side of the second end extend to the second drive control unit through the chip-on-film COF away from the outside of the first drive control unit, extend along the second drive control unit to the position of the second drive control unit close to the first drive control unit, and then extend again to the drive substrate along the chip-on-film COF on the side of the second drive control unit close to the first drive control unit, extend in the direction close to the first drive control unit to the position of the chip-on-film COF on the side of the first drive control unit close to the second drive control unit, and extend along the chip-on-film COF to the first drive control unit, and be electrically connected to the repair circuit.

9. The display panel according to claim 7, wherein: The chip-on-film (COF) is divided into a data area and a gate area. The gate area is located on both sides of the data area. The data area is provided with a driver chip, and the gate area is used for wiring. The input repair line and the output repair line are located in the gate area and extend along the gate area.

10. A display device, characterized in that: include: A display panel, wherein the display panel is the display panel according to any one of claims 6 to 9; The central control board is used to provide a driving control signal to the display panel so that the display panel displays a corresponding image.

Images