Self-testing bus system and use of this self-testing capability to assign bus node addresses with detection of input and output swapping

Abstract

Procedure for assigning bus addresses within a serial data bus consisting of a chain of bus nodes (SL1, SL2, SL3) and a bus master (ECU) - where the bus nodes (SL1, SL2, SL3) can be auto-addressing bus nodes or standard bus nodes and - where the data bus has a bus master (ECU) and - wherein each bus node (SL2, SL3) has a preceding bus node (SL1, SL2) if it is not the first bus node (SL1) and - each bus node (SL2, SL3) being connected to its preceding bus node (SL1, SL2) by the data bus if it is not the first bus node (SL1) and - wherein the first bus node (SL1) is connected to the bus master (ECU) via the data bus and - wherein each bus node (SL2, SL3) sends a bus node output current (i2, i3) to its preceding bus node (SL1, Sl2) via a bus node output if it is not the first bus node (SL1), and - wherein the first bus node (SL1,) sends a bus node output current (i1) to the bus master (ECU) via a bus node output and - wherein each bus node (SL1, SL2) receives a bus node input current (i2, i3) from its subsequent bus nodes (SL2, Sl3) via a bus node input if it is not the last bus node (SL3), with the following steps - Determination of the maximum addressing current (I amax ); - Perform an initialization sequence with the following steps for each auto-addressing bus node of the bus nodes (SL1, SL2, SL3) that does not yet have a valid bus node address until all auto-addressing bus nodes of the bus nodes (SL1, SL2, SL3) have a valid bus node address: • Signaling that a bus address is to be assigned to all auto-addressing bus nodes by means of an auto-addressing command; • Execution of the following steps by all auto-addressing bus nodes (SL1, SL2, SL3), hereinafter referred to as the relevant auto-addressing bus node (SLj): • Reception of the said auto-addressing command, in particular from the bus master (ECU), by the relevant auto-addressing bus node (SLj); • Receipt of a start signal for the allocation of the bus address to be allocated from the bus master (ECU) by the relevant auto-addressing bus node (SLj) and start of a timer by the relevant auto-addressing bus node (SLj); • Feeding the bus input current (i) received from the subsequent bus nodes (SL(j+1), SL(j+2)...) (j+1) ) into the bus node output of the respective auto-addressing bus node (SLj) as part of the bus output current (i j ) of the relevant auto-addressing bus node (SLj); • Detecting the value of the bus node output current (i j) of the relevant auto-addressing bus node (SL j ) by means of measuring instruments (R2, D1, D3); • Checking the recorded value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) for plausibility and initiation of measures if the recorded value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) is not plausible; • Generation of a control signal (rw j ) from the recorded value of the bus node output current (i j ) of the relevant auto-addressing bus node (SLj) by means of regulating means (F); • Control of the bus node output current (i j ) by the respective auto-addressing bus node (SLj), by means of a regulated auto-addressing current source (Iqj), whose addressing current is a portion of the bus output current (i j ) to a given total current value (I ref) depending on the generated control signal (rwj), • wherein an increase in the addressing current of the regulated auto-addressing current source (Iqj) of the relevant auto-addressing bus node (SLj) takes place with a first time constant (τ1) and • wherein a reduction of the addressing current of the regulated auto-addressing current source (Iqj) of the relevant auto-addressing bus node (SLj) is carried out with a second time constant (τ2) and • where the second time constant (τ2) is smaller than the first time constant (τ1); • Comparing the control value (rj) of the relevant auto-addressing bus node (SLj) with a threshold value (SWj) of the relevant auto-addressing bus node (SLj); • Freezing the control of the addressing current source (Iqj) of the relevant auto-addressing bus node (SLj) at a first time (τ1) after the start of the timer; • Reception of the bus node address to be assigned from the bus master (ECU) by the relevant auto-addressing bus node (SLj); • Acceptance of the bus node address to be assigned from the bus master (ECU) as a valid bus node address of the relevant auto-addressing bus node (SLj) if a minimum time has elapsed since the start of the timer and if the comparison of the control value (rj) with a threshold value (SWj) shows that the addressing current of the addressing current source (Iqj) of the relevant auto-addressing bus node (SLj) is above a current threshold value and configuration of the relevant auto-addressing bus node (SLj) as a standard bus node without auto-addressing capability with the bus node address to be assigned as the bus node address of the relevant auto-addressing bus node (SLj) at a second time (t2) after the first time (t1), as a result of which this relevant auto-addressing bus node (SLj) no longer participates in subsequent initialization sequences until further notice. • Checking the successful address assignment by the bus master (ECU); • If necessary, deletion of the validity of the last assigned bus node address, whereby the relevant auto-addressing bus nodes (SLj) again behave like auto-addressing bus nodes (SLj) without a valid bus node address; • Check whether all auto-addressing bus nodes have received a valid bus node address; • Performing another initialization sequence if not all auto-addressing bus nodes have received a valid bus node address

Description

generic term

[0001] The proposal is directed to a self-testing serial data bus system and a method for assigning bus addresses within this serial data bus from a chain of bus nodes.

[0002] The proposal claims the priority of the German patent application DE 10 2017 122 364.9 of 26 September 2017. General introduction and state of the art

[0003] Various methods for address assignment in LIN bus systems are known from the state of the art. Examples include DE 10 2010 026 431 B1, DE 101 47 512 B4, EP 1 490 772 B1, US 2014 / 0 095 749 A1, and US 9 331 866 B2.

[0004] Such auto-addressing is also known, for example, from the Elmos product E521.31 (reference: Elmos: LIN Controller with Position Detection E521.31, PRODUCTION DATA - Oct. 6, 2015).

[0005] What all these documents have in common is that the number of bus nodes addressable by the bus master is limited, since each bus node introduces a defined current into the bus during auto-addressing. Shunt resistors (bus shunts) are inserted into the single-wire data bus at each bus node, where these currents cause a voltage drop on their way to the bus master, where a current sink is active during the address assignment process.

[0006] The bus nodes closest to the bus master register a higher voltage drop than those farther away. The voltage across the bus shunt is compared to a threshold. If this threshold is exceeded, the bus node whose bus shunt exceeds the threshold can assume that it is not the last bus node in the chain of bus nodes from the bus master. It then switches off its power source and waits for the next initialization run.

[0007] The bus node that is the last bus node in the bus node chain from the bus master does not switch off its power source. After a specified initialization time has elapsed, this bus node can assume that it is the last bus node in the chain of bus nodes. It then adopts the bus node address transmitted by the bus master and no longer participates in further initialization runs until the received bus address is invalidated by a reset command or other reset condition.

[0008] The problem is that, first, the electrical resistance of the bus shunt must be as small as possible. Second, as many bus nodes as possible should be addressable. Third, the addressing system must be capable of operating with a negative ground offset. Fourth, the level across the bus shunt must be maximized, which requires the largest possible addressing current. Fifth, the total current consumed by the bus master during the address assignment process must not exceed a specified value, currently 40 mA for LIN buses.

[0009] DE 10 2010 026 431 B1 discloses a method in which the individual bus nodes do not operate with a constant addressing current as in DE 101 47 512 B4 and EP 1 490 772 B1, but instead increase this addressing current continuously or in a stepped manner until the thresholds of the preceding bus nodes are exceeded. This has several disadvantages: Firstly, with a large number of bus nodes, this leads to a very long rise time. However, the time for performing auto-addressing is limited. Therefore, it is necessary to shorten this time until the bus node furthest from the bus master and not yet addressed is addressed. DE 10 2010 026 431 B1 therefore does not completely solve the problem of being able to address a large number of bus nodes and to be able to sufficiently reduce the resistance of the bus shunt resistor. Furthermore, the technical teaching disclosed in DE 10 2010 026 431 B1 does not lead to a self-testing capability.

[0010] A further disadvantage of DE 10 2010 026 431 B1 is that, for robustness reasons, a certain level range must be kept free to prevent overloading the master or incorrect addressing. To minimize bus shunt resistances and ensure compliance with the LIN bus, it is therefore advisable to maximize the DC component in the addressing current. However, in the technical teaching disclosed in DE 10 2010 026 431 B1, this value fluctuates around an addressing current level. This unnecessarily reduces the available addressing current level. Task

[0011] The proposal is therefore based on the task of creating a solution that eliminates the above-mentioned disadvantages of the prior art and offers further advantages. In particular, a self-testing device is required that can detect a loss of the bus shunt resistor or a malfunction of the addressing current source. In contrast to the prior art, the device should be able to detect a swapping of the bus input and bus output.

[0012] This object is achieved by a method according to claim 1. Solution to the task

[0013] For better orientation, the following directions on the data bus are initially defined: From a bus node, the viewing direction is such that everything on the data bus between the bus node and the bus master is located BEFORE the bus node, and everything between the bus node and the end of the data bus is located AFTER the bus node. These definitions apply to the entire following document.

[0014] The following describes the process for automatic address assignment using a standard-compliant LIN bus system. In contrast to the processes and devices described in DE 101 47 512 B4, EP 1 490 772 B1, and US Pat. No. 9 331 866 B2, the resistance of the bus shunt resistor is reduced to such an extent that standard compliance can be achieved again. The Local Interconnect Network (LIN), also known as the LIN bus, is a serial communication system for networking sensors and actuators, a fieldbus. LIN is used where the bandwidth and versatility of CAN are not required. Typical application examples include networking within the door or seat of a motor vehicle. The relevant standard is ISO 17987-1, "Road vehicles - Local interconnect network (LIN) - Part 1-7."

[0015] The basic idea of ​​the proposal presented here is to use the addressing current source for the self-test and thus to meet the requirements of ISO 26262. For this purpose, in deviation from the technical teaching of DE 10 2010 026 431 B1, it is not the bus current flowing into the respective bus node from the subsequent bus nodes that is measured, but rather the total current (i1, i2, i3) leaving the respective bus node, which is composed of the addressing current that is fed into the data line in this respective bus node by the addressing current source (Iq1, Iq2, Iq3) of this respective bus node, and the bus current flowing into the respective bus node from the subsequent bus nodes.Architecturally, this means that the bus shunt resistor (R2) of the respective bus node (SL1, SL2, SL3) is arranged in front of the respective auto-addressing current source (Iq1, Iq2, Iq3), so that the own addressing current of the respective bus node must flow through this bus shunt resistor (R2) to reach the bus master (ECU), where it is diverted to ground.

[0016] A further idea of ​​the proposal presented here is that, in contrast to all the aforementioned documents, an essentially constant output current (i j ) of the relevant bus node (SL j ) is fed into the preceding data bus towards the bus master (ECU).

[0017] One problem may be present with existing standard bus nodes (CS1, CS2) that do not have auto-addressing capability as defined in this document. This document assumes that there is no mixed installation with bus nodes with auto-addressing capabilities according to other auto-addressing methods. These bus nodes (CS1, CS2) without auto-addressing capability each feed a bus current, the bus node basic current, into the data bus in the direction of the bus master (ECU) with their bus current source (S1, R3, d1). Preferably, these are bus nodes (CS1, CS2) that are present only once in the data bus and are therefore easily visually distinguishable from one another by the assemblers due to their appearance, for example during the assembly of a motor vehicle. This eliminates the need for self-addressing when installing these bus nodes, for example in a motor vehicle during its assembly.Each of these standard bus nodes (CS1, CS2) feeds a base current component into the data bus using a pull-up current source (S1, R3, d1) in accordance with the LIN standard. These standard bus nodes (CS1, CS2) thus collectively generate a maximum base current. This base current can be estimated by the bus nodes with auto-addressing capability, hereinafter referred to as auto-addressing bus nodes, based on the output of the number of standard bus nodes without auto-addressing capability.

[0018] There are two extreme configurations that can be used to illustrate the resulting problem. In both extreme configurations, the number of standard bus nodes without auto-addressing capability is maximized, while the number of auto-addressing bus nodes with auto-addressing capability is minimized: Configuration A In configuration A, all n standard bus nodes that do not have auto-addressing capability are located, as seen from the bus master (ECU), behind only two auto-addressing bus nodes that have auto-addressing capability according to the proposal described here. The maximum number n of standard bus nodes behind the two auto-addressing bus nodes with auto-addressing capability is then (n+2). max / I k . Here I max The maximum current value that the bus master (ECU) can accept by default during the auto-addressing phase ISO. Preferably, the maximum current value I max slightly smaller than the actual maximum current value of the bus master (ECU) to compensate for manufacturing and operating parameter fluctuations. k ​is the upper limit value for the value of the bus node base current that each standard bus node without auto-addressing capability feeds into the data bus. Preferably, each of the standard bus nodes without auto-addressing capability feeds approximately the same bus node base current into the data bus. The standard bus nodes without auto-addressing capability then generate a maximum base current of I at the input of the second auto-addressing bus node with auto-addressing capability. G =n*I k . A current range of I remains for auto-addressing by the auto-addressing bus nodes with auto-addressing. amax =2*I kfor the maximum addressing current of each auto-addressing bus node. This current range for the maximum addressing current of each auto-addressing bus node can then be used for auto-addressing. To do this, the auto-addressing bus nodes in an upstream phase A can measure this base current through their respective bus shunt resistor (R2) and then determine the current range for the maximum addressing current of each auto-addressing bus node and subsequently use it for auto-addressing. This maximizes the voltage drop across the bus shunt resistors (R2). These can therefore be minimized. This is in contrast to DE 10 2010 026 431 B1, which does not solve this problem. Configuration B In configuration B, all n standard bus nodes that do not have auto-addressing capability are located, as seen from the bus master (ECU), in front of the only two auto-addressing bus nodes that do have auto-addressing capability according to the proposal described here. However, in contrast to configuration A, the auto-addressing bus nodes cannot receive any information about the number of standard bus nodes in front of them from the bus master (ECU). Thus, there is a risk that the maximum addressing current used by the auto-addressing bus nodes, combined with the base current arriving at the bus master from all preceding bus nodes in the data bus, is too high, which would lead to an error message. However, the maximum number n of standard bus nodes behind the two auto-addressing bus nodes with auto-addressing capability is again (n+2). max / I k . Here I max ​again the maximum current value that the bus master (ECU) can accept in the auto-addressing phase. Preferably, the maximum current value I max Here, too, the maximum current value is slightly smaller than the actual maximum current value of the bus master (ECU) to compensate for manufacturing and operating parameter fluctuations. k is the upper limit value for the value of the bus node base current that each standard bus node without auto-addressing capability feeds into the data bus. Preferably, each of the standard bus nodes feeds approximately the same bus node base current into the data bus. The standard bus nodes without auto-addressing capability then generate a maximum base current of I at the input of the bus master (ECU). G =n*I k . For auto-addressing by the subsequent auto-addressing bus nodes with auto-addressing, only a current range of 2*I remains. k for the addressing current (I a). However, the subsequent auto-addressing bus nodes with auto-addressing capability cannot receive information about this current range. Although this current range can be used for auto-addressing, it must now be communicated to the auto-addressing bus nodes with auto-addressing capability by the bus master (ECU). This can be done by the bus master informing all bus nodes of the number of standard bus nodes without auto-addressing capability using a message addressed to all bus nodes, or by communicating a suitable addressing current value in advance using such a command. This makes it possible to maximize the addressing current in the respective auto-addressing bus nodes. Configuration C Configuration C is a mixture of Configuration A and Configuration B Standard bus nodes without auto-addressing capability are then located upstream and downstream of the auto-addressing bus nodes with auto-addressing capability in the serial data bus. In this case, the bus master (ECU) only needs to transmit the number n of standard bus nodes located upstream of the auto-addressing bus nodes with auto-addressing capability. By measuring the base current through their bus shunt resistor relative to the downstream bus nodes, the auto-addressing bus nodes can thus calculate the total base current by summing this base current with n times the bus node base current I k Alternatively, the bus master (ECU) can, of course, also transmit a different value from which the basic bus current can be calculated. On this basis, each auto-addressing bus node can then determine the maximum addressing current I amax calculate and maximize.

[0019] Before the bus addresses are assigned, the bus master (ECU) preferably signals to all bus nodes which of the configurations specified above is present and how many standard bus nodes are present in the system that do not have auto-addressing capability and / or how large the expected basic bus current is.

[0020] When auto-addressing begins, the bus master (ECU) pulls the data line to ground using a switch (SB) or similar. The current sink used for this purpose can reach the maximum current value I max If the bus current flowing into the bus master (ECU) exceeds this value, the bus master (ECU) may assume a short circuit and generate corresponding signals and error messages. Therefore, this maximum current value I max may not be exceeded in normal operation.

[0021] Depending on the number of standard bus nodes without auto-addressing capability and the standard maximum permissible bus current I max Each bus node can then use the maximum addressing current I amax of its respective addressing current source (Iq1, Iq2, Iq3) which is still permissible without exceeding the maximum permissible addressing current (I max ). This value is preferably specified by the received number n of standard bus nodes without auto-addressing capability in the respective auto-addressing bus node with auto-addressing capability. A safety margin is preferably also taken into account so that the actually set auto-addressing current I amax the auto-addressing current sources of the auto-addressing bus nodes (SL1, SL2, SL3) is lower than the actual maximum permissible auto-addressing current.

[0022] It must now be ensured that the maximum permissible bus current I max is not exceeded. In contrast to DE 10 2010 026 431 B1, the base current and addressing current coming into the auto-addressing bus node from the subsequent bus nodes are not detected, and if there is a deviation from the base current, the addressing current source is deactivated.

[0023] Rather, the total current (i1, i2, i3) that leaves the respective bus node via the data bus toward the bus master (ECU) is recorded. This current consists of the bus current fed in by the subsequent bus nodes plus the self-generated addressing current.

[0024] For this purpose, the respective bus node (Sl1, SL2, SL3) measures the outgoing bus current (i1, i2, i3) coming from the subsequent bus nodes (Sl2, Sl3) and flowing through the bus shunt (R2) of the respective bus node (Sl1, SL2, SL3) and leaving the respective bus node at the output in the direction of the bus master (ECU). The respective auto-addressing bus node (SL1, SL2, SL3) now controls its own addressing current source (Iq1, Iq2, Iq3) such that the sum of the incoming bus current of the subsequent bus nodes (Sl2, Sl3) and the addressing current of its own addressing current source (Iq1, Iq2, Iq3) corresponds to a predetermined total current (I s ). The amplitude of the addressing current (I a ) is set so that the maximum bus current I maxcannot be exceeded by the amount of the outgoing bus current (i1, i2, i3). Thus, the bus current (i1, i2, i3) leaving the respective bus node (SL1, SL2, SL3) remains constant and is not increased above a maximum value by the respective bus node (SL1, SL2, SL3). This prevents overloading of the bus master current sink during the address assignment process.

[0025] In this method, each of the auto-addressing bus nodes participating in the address allocation process detects an additional current that deviates from the base current. This additional current is composed of the respective bus node's own addressing current and the addressing current of the bus node following the respective bus node (SL1, SL2, SL3).

[0026] To avoid an overdrive of the output current (i1, i2, i3) above I maxcomes, the respective bus node regulates its output current (i1, i2, i3) towards the bus master (ECU) in such a way that it always corresponds to the intended maximum value of the addressing current I amax plus the base current. For this purpose, the addressing current source (Iq1, Iq2, Iq3) within each auto-addressing bus node (SL1, Sl2, Sl3) is designed to be controllable. The addressing current of the respective addressing current source (Iq1, Iq2, Iq3) then depends on the previously determined maximum value (I amax ) and, on the other hand, from a control signal which is determined by means of a control system (F) and a measuring device (R2, D1) from the output current (i1, i2, i3) of the respective bus node (SL2) in the direction of the bus master (ECU).

[0027] The controlled system therefore begins with a measuring device, preferably a bus shunt resistor (R2), which is inserted into the data bus upstream of the respective bus node (SL1, SL2, SL3) as seen from the bus master (ECU). There, the bus current from the respective bus node towards the bus master (ECU) is converted into a voltage value. This voltage is detected by a measuring device, e.g., an operational amplifier (D1) and, if necessary, after filtering (F), converted into a control value with which the respective auto-addressing current source (Iq1, Iq2, Iq3) can then be controlled such that the bus current (i1, i2, i3) towards the bus master (ECU) is kept constant during this address assignment phase.

[0028] With a suitable design of the necessary control loop, a controlled variable, the control value, preferably appears within the respective bus node (SL1, SL2, SL3) as the output signal of the aforementioned filter (F). For simplicity, it is assumed here, as an example, that this controlled variable is directly proportional to the respective output current (i1, i2, i3) of the respective auto-addressing bus node (SL1, SL2, SL3) toward the bus master (ECU).

[0029] If this control value still exceeds a specified threshold (SW) after the specified initialization time has elapsed, i.e., if the internal addressing current source (Iq1, Iq2, Iq3) delivers the specified output current to the bus master (ECU), the respective auto-addressing bus node is the last in the chain of auto-addressing bus nodes as seen from the bus master (ECU). The respective auto-addressing bus node then adopts the bus node address previously transmitted by the bus master (ECU) to all auto-addressing bus nodes (SL1, SL2, SL3) as its now valid bus node address and no longer participates in further initialization runs until the received bus address is invalidated by a reset command or other reset condition.The other auto-addressing bus nodes that do not yet have a valid bus node address and are not the auto-addressing bus node that has just adopted the bus node address to be assigned as a valid bus node address, participate in the following initialization runs.

[0030] Preferably, the control of the output current value of the auto-addressing current sources (Iq1, Iq2, Iq3) within the auto-addressing bus nodes (SL1, SL2, SL3) is filtered by means of a filter (F). Preferably, the control loop forms a PI controller. This filtering is necessary to prevent overshoots when generating the addressing current by the entire set of auto-addressing bus nodes (SL1, SL2, SL3) at the bus master (ECU). If this were to happen, the maximum permissible bus current I max exceeded and the bus master (ECU) detects a short circuit, which must be avoided.

[0031] It is therefore advantageous and preferred to include at least one low-pass filter (F) in the control loop of each auto-addressing bus node (SL1, SL2, Sl3).

[0032] In a further preferred embodiment of the proposal, the filter (F) is designed to be nonlinear. Preferably, a first control time constant (τ1) of the nonlinear filter (F) for increasing the addressing current of the respective addressing current source (Iq1, Iq2, Iq3) of the respective bus node (SL1, SL2, SL3) should be greater than a second control time constant (τ2) of the nonlinear filter (F) for decreasing the addressing current of the respective addressing current source (Iq1, Iq2, Iq3) of the respective bus node (SL1, SL2, SL3). It has been shown that for m auto-addressing bus nodes, the second time constant (τ2) for a reduction of the addressing current of the respective addressing current source (Iq1, Iq2, Iq3) should be shorter by a factor m than the first time constant (τ1) for an increase of the addressing current of the respective addressing current source (Iq1, Iq2, Iq3).This results in the addressing current of the respective addressing current source (Iq1, Iq2, Iq3) of the respective bus node (SL1, SL2, SL3) being decreased faster than it is increased. Thus, subsequent auto-addressing bus nodes reduce their addressing current faster than it is increased by other auto-addressing bus nodes. Thus, a constant bus current, or at least a permanent undershoot of a maximum bus current value I, is ensured. max during the addressing phase. Simulations have shown that the first time constant (τ1), with which the addressing current source (Iq1, Iq2, Iq3) of the respective auto-addressing bus node (SL1, SL2, SL3) is regulated down, should preferably be a factor of 10, or even better, a factor of 100, faster (= smaller) than the second time constant (τ2), with which the addressing current source (Iq1, Iq2, Iq3) of the respective auto-addressing bus node (SL1, SL2, SL3) is regulated up.

[0033] However, as already described, experience has shown that a typical LIN bus also contains standard LIN bus nodes without auto-addressing capability. These supply a constant, continuous current to the bus master (ECU) during the addressing phase. Unlike other methods that rely on base current, the threshold for detecting the last bus position can now be set very high for the auto-addressing bus node, which is to be assigned a bus address during the respective initialization run.

[0034] After an auto-addressing bus node with auto-addressing capability has received a valid bus address in this way, it preferably uses its addressing current source like a bus node base current source and then behaves like a bus node without auto-addressing capability. Nevertheless, separate bus node base current sources (S1, R3, d1) in the auto-addressing bus nodes (SL1, SL2, SL3) are shown in the figures as a possible alternative. These could then be omitted. This state of an auto-addressing bus node after a valid bus node address has been assigned is preferably only changed by resetting the auto-addressing bus node or deleting the validity of the bus node address. In the next initialization run, the last auto-addressing bus node therefore receives a valid bus node address from the bus master (ECU) and from then on behaves like a standard bus node without auto-addressing capability.Auto-addressing bus nodes that have not yet received a valid bus node address continue to behave as auto-addressing bus nodes. This concludes an initialization run. The bus master then initiates another initialization run, during which the previously penultimate auto-addressing bus node, as seen by the bus master (ECU), which is now the last auto-addressing bus node from the bus master's perspective to behave as such, receives a valid bus node address, and so on. This repeated imitation of the initialization runs by the bus master (ECU) and the assignment of a valid bus node address in such an initialization run to the last auto-addressing bus node from the bus master's perspective to behave as such, continues until all auto-addressing bus nodes have received a valid bus node address from the bus master (ECU).To determine this, the bus master (ECU) preferably checks after each initialization run whether the addressed auto-addressing bus node, which is supposed to have just received a valid bus node address, responds. The addressed auto-addressing bus node then preferably sends a random number to the bus master (ECU) at the request of the bus master (ECU). If - for whatever reason - two auto-addressing bus nodes are active, bus collisions occur. These can be detected by the bus nodes and signaled to the bus master. In certain cases, if the response is predeterminable, the bus master (ECU) can also directly detect a bus collision. The bus master can thus detect a bus collision either directly or indirectly and, if necessary, repeat the initialization of the relevant bus address. For this purpose, it is useful if the bus master (ECU) can send a delete command for the last assigned bus address to all bus nodes.

[0035] During address assignment, the bus current through the bus shunt can now be checked for various conditions: a) If the voltage drop across the bus shunt resistor (R2) exceeds a maximum voltage drop threshold, a short circuit to the supply voltage on the downstream bus has occurred. In this case, the affected bus node will preferentially shut down all power sources to prevent damage to the system. However, the bus master (ECU) will usually also detect this short circuit. b) If the voltage drop across the bus shunt resistor is 0V, the measuring input is typically short-circuited. c) If the voltage drop across the bus shunt resistor (R2) is below the maximum voltage drop threshold but above a second voltage drop threshold, the bus shunt resistor is probably disconnected from the downstream bus nodes and the measurement input is still connected to the downstream bus nodes, which pull this measurement line high in potential towards the supply voltage. d) If the voltage drop across the bus shunt resistor is in the range of the voltage drop of the base current, the addressing current source (Iq1, Iq2, Iq3) of the respective bus node is not working, even though it is the last one. The bus node can signal this to the bus master (ECU), for example, by provoking a bus collision by adopting the bus node address to be assigned as a valid bus node address. This then leads to two auto-addressing bus nodes responding to the bus master when checking for correct bus node addressing, which the bus master can then recognize. Thus, a method for assigning bus node addresses within a serial data bus consisting of a chain of bus nodes (SL1, SL2, SL3) and a bus master (ECU) is proposed. In this method, the bus nodes (SL1, SL2, SL3) can be auto-addressing bus nodes or standard bus nodes, and the data bus has a bus master (ECU).Each bus node (SL2, SL3) has a preceding bus node (SL1, SL2) if it is not the first bus node (SL1). Each bus node (SL2, SL3) is connected to its preceding bus node (SL1, SL2) by the data bus if it is not the first bus node (SL1). The first bus node (SL1) is connected to the bus master (ECU) by the data bus. Each bus node (SL2, SL3) sends a bus node output current (i2, i3) to its preceding bus node (SL1, SL2) via a bus node output if it is not the first bus node (SL1). The first bus node (SL1) sends a bus node output current (i1) to the bus master (ECU) via a bus node output. Each bus node (SL1, SL2) receives a bus node input stream (i2, i3) from its subsequent bus nodes (SL2, SL3) via a bus node input, unless it is the last bus node (SL3). The method comprises the following steps: • Determination of the maximum addressing current (I amax ); • Perform an initialization sequence with the following steps for each auto-addressing bus node of the bus nodes (SL1, SL2, SL3) that does not yet have a valid bus node address until all auto-addressing bus nodes of the bus nodes (SL1, SL2, SL3) have a valid bus node address: ◯ Signalling of a bus address to be assigned to all auto-addressing bus nodes; ◯ Execution of the following steps by all auto-addressing bus nodes (SL1, SL2, SL3), hereinafter referred to as the relevant auto-addressing bus node (SLj): ▪ Reception of the said auto-addressing command from the bus master (ECU) by the relevant auto-addressing bus node (SLj); ▪ Reception of the bus address to be assigned from the bus master (ECU) by the relevant auto-addressing bus node (SLj); ▪ Switching off any existing bus node basic power sources (S1, R3, d1) within the respective auto-addressing bus node (SLj) ▪ Receipt of a start signal for the allocation of the bus address to be allocated from the bus master (ECU) by the relevant auto-addressing bus node (SLj) and start of a timer by the relevant auto-addressing bus node (SLj); ▪ Feeding the bus input current (i) received from the subsequent bus nodes (SL(j+1), SL(j+2)...) (j+1) ) into the bus node output of the respective auto-addressing bus node (SLj) as part of the bus output current (i j ) of the relevant auto-addressing bus node (SLj); ▪ Detecting the value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) by means of measuring instruments (R2, D1, D3); ▪ Generation of a control signal (rw j ) from the recorded value of the bus node output current (i j ) of the relevant auto-addressing bus node (SLj) by means of regulating means (F); ▪ Control of the bus node output current (i j) by the respective auto-addressing bus node (SLj), by means of a regulated auto-addressing current source (Iqj), whose addressing current is a portion of the bus output current (i j ) to a given total current value (I ref ) depending on the generated control signal (rwj), ▪ wherein an increase of the addressing current of the regulated auto-addressing current source (Iqj) of the respective auto-addressing bus node (SLj) takes place with a first time constant (τ1) and ▪ wherein a reduction of the addressing current of the regulated auto-addressing current source (Iqj) of the respective auto-addressing bus node (SLj) is carried out with a second time constant (τ2) and ▪ where the second time constant (τ2) is smaller than the first time constant (τ1); ▪ Comparing the control value (rj) of the relevant auto-addressing bus node (SLj) with a threshold value (SWj) of the relevant auto-addressing bus node (SLj); ▪ Freezing the control of the addressing current source (Iqj) of the relevant auto-addressing bus node (SLj) at a first time t1 after the start of the timer; ▪ Acceptance of the bus node address to be assigned from the bus master (ECU) as a valid bus node address of the relevant auto-addressing bus node (SLj) if a minimum time has elapsed since the start of the timer and if the comparison of the control value (rj) with a threshold value (SWj) shows that the addressing current of the addressing current source (Iqj) of the relevant auto-addressing bus node (SLj) is above a current threshold value and configuration of the relevant auto-addressing bus node (SLj) as a standard bus node without auto-addressing capability with the bus node address to be assigned as the bus node address of the relevant auto-addressing bus node (SLj) at a second time t2 after the first time t1, whereby this auto-addressing bus node (SLj) no longer participates in subsequent initialization sequences until further notice. ◯ Verification of successful address assignment by the bus master (ECU); ◯ If necessary, deletion of the validity of the last assigned bus node address, whereby the relevant auto-addressing bus nodes (SLj) behave again like auto-addressing bus nodes (SLj) without a valid bus node address; ◯ Check whether all auto-addressing bus nodes have received a valid bus node address; ◯ Performing another initialization sequence if not all auto-addressing bus nodes have received a valid bus node address

[0036] In one variant of the proposed method, the second time constant (τ2) is smaller than the first time constant (τ1) by a factor greater than 10, preferably greater than 100. In another variant of the method, the first time constant (τ1) within the respective auto-addressing bus node (SLj) depends on the value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j). For example, it is advantageous if the first time constant (τ1) is very short at the beginning, when the total current through the bus shunt resistor is still small, and thus the addressing current source of the respective auto-addressing bus node increases the current very quickly, while later the addressing current of the auto-addressing current source is increased slowly. It is therefore conceivable that the first time constant (τ1) within the respective auto-addressing bus node (SLj) depends on the value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j) in such a way that the value of the first time constant (τ1) has a first value below a threshold value and a second value above the threshold value. It is also conceivable that the second time constant (τ2) within the respective auto-addressing bus node (SLj) depends on the value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) depends.

[0037] In order to detect a swap of the LIN input with the LIN output, a variant of the method preferably includes checking the recorded value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) for plausibility and initiation of measures if the recorded value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) is not plausible.

[0038] In a further refinement, a countermeasure can then be taken to redetermine the feed point of the addressing current if the recorded value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) is not plausible.

[0039] In addition to these compensating measures, an error can also be signalled via the data bus upon request by a bus master (ECU) if the recorded value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) is not plausible.

[0040] A further measure necessary for the stability of the control loop can be a refinement of the implementation of the step of detecting the value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j) by means of measuring means (R2, D1, D3). Preferably, the value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) by means of measuring means (R2, D1, D3) with a first sign, if the detected value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) is plausible, and detecting the value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) by means of measuring means (R2, D1, D3) with a second sign which is inverted to the first sign if the detected value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) is plausible.

[0041] A further procedural measure may be the use of a predetermined error address as the valid bus node address of the relevant auto-addressing bus node (SLj) if the detected value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) is not plausible. This can be predetermined by design or, for example, specified via a broadcast message by the bus master (ECU).

[0042] Thus, a data bus system with bus nodes (SL1, SL2, SL2) for a serial data bus is proposed, each of which has a bus shunt resistor (R2) inserted into the data bus. Furthermore, they should have an addressing current source (Iq1, Iq2, Iq2) for determining the bus position of the bus node in the data bus, which can additionally feed an addressing current into the data bus in a controlled manner such that the total current (i1, i2, i3) through the bus shunt resistor (R2) of the bus node (Sl1, SL2, SL3) corresponds to a predetermined or calculated or otherwise determined total current (I ref). Control is achieved via the aforementioned control loop (R2, D1, D3, F, Iq1, Iq2, Iq3). The addressing current flows through the bus shunt resistor (R2) of the respective auto-addressing bus node. A variant of the proposed bus node has means (R2, D1) for detecting the current through the bus shunt resistor (R2), which may include recording a measured value. This detected current through the bus shunt resistor (R2) can be used for a self-test in such a way that the errors described above (e.g., bus shunt resistor break) can be detected.

[0043] In a further variant of the device, it has a detection device (DET) that checks internal signals (ds1, ds3) of the bus node (SLx) for plausibility. Reference is made to the description of the figures.

[0044] The bus node (SLx) or a sub-device (DET) of the bus node (SLx) is preferably designed to take action if the detection device (DET) detects implausible internal signals within the bus node. Reference is made to the following description of the figures for possible measures.

[0045] For example, a proposed bus node comprises a sub-device (MUX) that can change the feed point of the addressing current of the addressing current source (Iqx). Alternatively, instead of an addressing current source (Iqx) and a multiplexer (MUX), a proposed bus node (SLx) can also comprise a first addressing current source (Iqx1) and a second addressing current source (Iqx2), wherein the first addressing current source (Iqx1) feeds its current into a node connected to the first terminal of the bus shunt resistor (R2) when it feeds current, and wherein the second addressing current source (Iqx2) feeds its current into a node connected to the first terminal of the bus shunt resistor (R2) when it feeds current. To enable auto-addressing, only one of the two addressing current sources (Iqx1, Iqx2) supplies the auto-addressing current, while the other one preferentially supplies no current.Preferably, the two addressing current sources (Iqx1, Iqx2) feed their currents in such a way that the addressing current flows through the bus shunt resistor (R2) preferably in the direction of the bus master (ECU).

[0046] In a further particularly preferred variant of the auto-addressing bus node, the addressing current source (Iq1, Iq2, Iq2) feeding the addressing current increases the addressing current with a first time constant (τ1) and decreases it with a second time constant (τ2) which is smaller than the first time constant (τ1). Advantage of the proposal

[0047] The proposed method and device enable a partial self-test of the bus nodes and the data bus system.

[0048] In contrast to previous prior art devices and methods, the proposed method thus operates with a substantially constant bus node output current during the address assignment phase, which should be essentially the same for all auto-addressing bus nodes, except for manufacturing variations in design parameters. This avoids EMC emissions such as those shown in DE 10 2010 026 431 B1, which shows a sawtooth-like current waveform, from the outset.

[0049] In addition, this addressing current can now be set very high, or at least at its maximum. This allows a corresponding reduction in the resistance values ​​of the bus shunt resistors (R2), since only an addressing current flows through these resistors together with the base current. This ensures that, after all initialization runs have been successfully completed, a LIN bus system only comprises bus nodes that behave according to the LIN standard.

[0050] But the benefits are not limited to this. List of characters Fig. 1 shows a simplified, schematic representation of a proposed bus system, wherein the measurement of the total current is carried out by measuring the total current at a shunt resistor in the bus output of the respective auto-addressing bus node (SL1, SL2, Sl3). Fig. 2 to 4 show the course of the output currents (i1, i2, i3) of the bus nodes (SL1, SL2, Sl3) and the currents of the addressing current sources (lq1, Iq2, Iq3) for different time constants of the control. Fig. Figure 5 shows a simplified schematic of a Category A bus system with two standard bus nodes (CS1, CS2) that do not have auto-addressing capability. Fig. Figure 6 shows a simplified schematic of a Category B bus system with two standard bus nodes (CS1, CS2) that do not have auto-addressing capability. Fig. Figure 7 shows a simplified schematic of a Category C bus system with two standard bus nodes (CS1, CS2) that do not have auto-addressing capability. Fig. 8 shows the case of twisting the second bus node (SL2). Fig. 9 shows the situation of the Fig. 8 after detecting a swap of the LIN inputs and outputs and implementing countermeasures. Fig. 10 shows the second auto-addressing bus node (SL2), which Fig. 8 and Fig. 9 in detailed form now as the x-th auto-addressing bus node (SLx). Description of the figuresFigure 1

[0051] Fig. Figure 1 shows a simplified and schematic representation of a proposed bus system.

[0052] At the beginning of auto-addressing, the bus master (ECU) signals to all auto-addressing bus nodes that the bus node addresses are to be assigned. The subsequent address assignment is split into address assignment phases, whereby in each address assignment phase, preferably exactly one auto-addressing bus node, namely the last of the auto-addressing bus nodes (SL1, SL2, SL3) from the bus master (ECU) in the bus node chain that has not yet received a bus node address, receives a valid bus node address from the bus master (ECU) using an initialization run. Preferably, the bus master transmits to all auto-addressing bus nodes the number of standard bus nodes that are located upstream of the auto-addressing bus nodes (SL1, SL2, SL3), i.e., between them and the bus master (ECU), or a maximum addressing current level, using a so-called broadcast command. Of course, this maximum addressing current level can be I amaxalso be programmed into the bus node, since the bus topology is typically structural and not operational and is therefore predictable. This determines which total current (I ref ) should flow through the bus shunt resistor (R2).

[0053] At the beginning of each address allocation phase, the bus master (ECU) closes its switch (SB) again for a predetermined addressing time T AThis current sink (SB) of the bus master (ECU) is usually a more complex structure in reality, which can also detect a bus short circuit and is only shown here in a simplified manner. In this way, the bus master (ECU) provides a current sink for the addressing current of the auto-addressing current sources and the bus node base currents of the bus nodes in the subsequent address assignment phase. The auto-addressing-capable auto-addressing bus nodes (SL1), (SL2), and (SL3) register that the data bus is being pulled to ground and open their respective switches S1 and S2. The auto-addressing bus nodes (SL1, SL2, SL3) thus no longer feed any bus node base current into the data bus.

[0054] After a first period of time (dt1), the auto-addressing bus nodes determine the base current through the respective bus shunt resistor (R2) by measuring the voltage drop across this bus shunt resistor (R2). This voltage drop can, for example, be temporarily stored as an offset voltage value in a sample-and-hold circuit and subsequently subtracted from the subsequently measured voltage drop across the bus shunt resistor (R2) by a subtractor circuit. This ensures that only the bus current that deviates from the respective base current, which is based on the addressing current of the auto-addressing bus nodes, is used for address assignment and the control of the addressing current sources (Iq1, Iq2, Iq3).

[0055] This phase ends after a second period (dt2) has elapsed.

[0056] All auto-addressing bus nodes that do not yet have a valid bus node address detect the current that deviates from the base current through their respective bus shunt resistor (R2) and, on the basis of this measured bus current value, subsequently regulate their respective addressing current source (Iq1, Iq2, Iq3) so that the current through their respective bus shunt resistor (R2) corresponds to the previously determined or specified current sum (I ref). For this purpose, the respective auto-addressing bus node has measuring devices (R2, D1, D3) to determine the real current sum in the form of the respective bus node output current (i1, i2, i3) in the direction of the bus master (ECU). The voltage drop across the bus shunt resistor (R2) is recorded and, preferably after subtracting the voltage value for the basic bus current, further processed as a current sum signal. As already explained, the current sum signal thus generated is filtered in a preferably non-linear filter (F1) to form a control signal. This is compared with a reference value (Ref) by a differential amplifier stage, which corresponds to a comparison of the respective bus node output current (i1, i2, i3) with a reference current (I ref ) in its effect. When setting or calculating the reference current (I ref), this reference value (Ref) is typically actually determined. This comparison can be performed before and after filtering in the filter (F). Preferably, it involves calculating the difference. Further filtering, which is not shown in the figures, can also be performed after this comparison. The control value (rw1, rw2, rw3) determined in this way then controls the respective addressing current source (Iq1, Iq2, Iq3) of the respective auto-addressing bus node (SL1, SL2, SL3).

[0057] Since the current sum at the output of the respective auto-addressing bus node (SL1, Sl2, Sl3) should always be constant, only the last auto-addressing bus node (SL3) supplies electrical current to the data bus, while all other addressing current sources (Iq1, Iq2) of the other auto-addressing bus nodes (SL1, Sl2) are regulated down by the regulators (R2, D1, D3, F) of the other auto-addressing bus nodes (SL1, Sl2). This results in the control value (rw3) of the last bus node (SL3) differing from the control values ​​(rw1, rw2) of the other bus nodes (SL1, SL2) in that it fully controls the addressing current source (Iq3) of its bus node (SL3), while the control values ​​(rw1, rw2) of the preceding bus nodes (SL1, SL2) have values ​​such that they reduce their addressing current sources (Iq1, Iq2). Thus, each bus node (SL1, SL2, SL3) can compare this control value (rw1, rw2, rw3) with a preferably approximately equal threshold value (SW).

[0058] This phase ends after a third period (dt3).

[0059] The end of this addressing phase is preferably marked by the opening of the current sink switch (SB). This reconnects the data bus to the supply voltage. The bus nodes (SL1, SL2, SL3) then preferably freeze the status of their respective control value (rw1, rw2, rw3) and evaluate it against the aforementioned threshold value (SW). Based on this, they then decide whether they are the last auto-addressing bus node (here SL3) in the bus node chain (SL1, SL2, SL3) or a preceding auto-addressing bus node (SL1, SL2). If they are the last bus node (SL3), they adopt the bus address to be assigned, signaled by the bus master (ECU) at the very beginning, which they have preferably stored in a suitable memory for this purpose after receiving it. This auto-addressing bus node (SL3) then no longer participates in further addressing phases in the form of initialization runs.This means that this auto-addressing bus node (SL3) will then no longer feed any addressing current into the data bus via its addressing current source (Iq3). Naturally, it will then no longer accept the additional bus addresses offered by the bus master (ECU), since it already has a valid bus address and is intended to behave like a standard bus node until its valid bus node address becomes invalid. The bus node address of an auto-addressing bus node becomes invalid, for example, if the operating voltage drops below an operating voltage threshold, or due to a command from the bus master, or due to another signaling.

[0060] Preferably, the bus master checks the successful address assignment at the end of each initialization run.

[0061] This is followed by the addressing phase in the form of a subsequent initialization run, in which the next, now last, unaddressed auto-addressing bus node (SL2) receives its valid bus address in the same way. The process is analogous. This auto-addressing bus node (SL2), like the auto-addressing bus node (SL3) that was first assigned a valid bus node address, then no longer participates in further addressing phases in the form of subsequent initialization runs. It then behaves like a standard bus node. This means that it no longer feeds an addressing current into the data bus via its addressing current source (Iq2). Of course, it also no longer accepts the additional bus addresses to be assigned offered by the bus master (ECU), since it then has a valid bus address. This process continues until all auto-addressing bus nodes have received a valid bus node address. Figure 2

[0062] Fig. Figure 2 shows the output current (i1) of the first bus node (SL1), the output current (i2) of the second bus node (SL2), and the output current (i3) of the third bus node (SL3). It also shows the current (I1_internal) of the addressing current source (Iq1) of the first bus node (SL1), the current (I2_internal) of the addressing current source (Iq2) of the second bus node (SL2), and the current (I3_internal) of the addressing current source (Iq3) of the third bus node (SL3). Here, the time constants for the upregulation of the addressing current sources and the downregulation of the addressing current sources are approximately equal. This results in an overshoot.It is clearly visible that the current (I1_internal) of the addressing current source (Iq1) of the first bus node (SL1) and the current (I2_internal) of the addressing current source (Iq2) of the second bus node (SL2) are regulated down by the regulators of these auto-addressing bus nodes, while the current (I3_internal) of the addressing current source (Iq3) of the third bus node (SL3) is regulated to the reference value. Unlike in DE 102010 026 431 B1, the settling time is determined only by the first time constant (τ1). Figure 3

[0063] Fig. Figure 3 shows the output current (i1) of the first bus node (SL1), the output current (i2) of the second bus node (SL2), and the output current (i3) of the third bus node (SL3). It also shows the current (I1_internal) of the addressing current source (Iq1) of the first bus node (SL1), the current (I2_internal) of the addressing current source (Iq2) of the second bus node (SL2), and the current (I3_internal) of the addressing current source (Iq3) of the third bus node (SL3). Here, the time constants for regulating the addressing current sources up are approximately ten times as long as the time constants for regulating the addressing current sources down. A minimal overshoot occurs. Figure 4

[0064] Fig. Figure 4 shows the output current (i1) of the first bus node (SL1), the output current (i2) of the second bus node (SL2), and the output current (i3) of the third bus node (SL3). It also shows the current (I1_internal) of the addressing current source (Iq1) of the first bus node (SL1), the current (I2_internal) of the addressing current source (Iq2) of the second bus node (SL2), and the current (I3_internal) of the addressing current source (Iq3) of the third bus node (SL3). Here, the time constants for regulating the addressing current sources up are approximately 100 times longer than the time constants for regulating the addressing current sources down. No overshoot occurs. Figure 5

[0065] Fig. Figure 5 shows a simplified schematic of a Category A bus system with two standard bus nodes (CS1, CS2) that do not have auto-addressing capability. Figure 6

[0066] Fig. Figure 6 shows a simplified schematic of a Category B bus system with two standard bus nodes (CS1, CS2) that do not have auto-addressing capability. Figure 7

[0067] Fig. Figure 7 shows a simplified schematic of a Category C bus system with two standard bus nodes (CS1, CS2) that do not have auto-addressing capability. Figure 8

[0068] Fig. Figure 8 shows the case of the twisting of the second bus node (SL2). In this example, the LIN bus input and the LIN bus output of the second bus node (SL2) are swapped. This operating case should be recognized. The swapping results in the bus shunt current (i2R) through the bus shunt resistor (R2) of this twisted second bus node (SL2) being fed into its bus shunt resistor (R2) backwards compared to the normal position. This bus shunt current (i2R) through the bus shunt resistor (R2) in this example only includes the bus node output current (i3) of the subsequent, third auto-addressing bus node (SL3) or, in other cases, the subsequent bus nodes. This bus node output current (i3) of the third auto-addressing bus node (SL3) therefore now leads to a negative voltage drop (V R2) via the bus shunt resistor (R2). This can be detected by the first differential amplifier (D1) of the twisted second auto-addressing bus node (SL2) in this example. Its output (ds1) saturates due to the negative drive caused by the negative voltage drop (V R2) across the bus shunt resistor (R2) at the smallest possible output level of the output (ds1) of the differential amplifier (D1). This smallest possible output level of the output (ds1) of the differential amplifier (D1) can be a maximum value of a negative output value or a minimum value of a positive output value. Typically, depending on the design of the first differential amplifier (D1) and its power supply, this is close to 0V. Thus, the output (ds1) of the first differential amplifier (D1) is typically below the level of the reference value (Ref).This causes a large positive signal at the output (ds3) of the third differential amplifier (D3) and thus, at least after the nonlinear filter (F) of the twisted auto-addressing bus node (SL2) has settled, a maximization of the addressing current by the regulated addressing current source (iq2) of the second auto-addressing bus node (SL2), which is twisted in this exemplary fault case. The control loop thus increases the addressing current fed into the data bus by the addressing current source (Iq2). This creates the problem that this addressing current does not flow through its own bus shunt resistor (R2) as intended. Thus, the intended control loop is interrupted. The current transient through the bus node output current (i3) of the subsequent third auto-addressing bus node (SL3) therefore does not cause a positive current transient in the bus shunt resistor (R2) as intended, but rather a negative current transient.Additional auto-addressing bus nodes (SL2) located behind the second twisted-pair auto-addressing bus node (SL2) would further negatively bias the voltage drop across the bus shunt resistor (R2) of the second twisted-pair auto-addressing bus node (SL2).

[0069] However, the twisted second auto-addressing bus node (SL2) can be identified by the voltage drop (V R2 ) via its bus shunt resistor (R2), which supplies the voltage magnitude of |V R2 |=|i2R|*|R2|, recognize that there is a mismatch between the transient of the addressing current generated by its regulated addressing current source (Iq2) and the normally correlating transient of the voltage drop (V R2 ) across its bus shunt resistor (R2). In addition, a sign error is present. If an x-th auto-addressing bus node (SLx) at an x-th position in the chain of bus nodes detects a negative voltage drop (V R2) via its bus shunt resistor (R2) and if its addressing current source (Iq2) supplies a positive current, the corresponding auto-addressing bus node (SL2) can detect this constellation and initiate countermeasures.

[0070] In particular, the respective x-th auto-addressing bus node (SLx) must prevent the addressing current of its regulated addressing current source (Iqx) and thus the bus node output current (ix) of the respective x-th auto-addressing bus node (SLx) from increasing further in this fault case, since the bus node output current (ix), which is the sum of the bus input current and the addressing current of its regulated addressing current source (Iqx), would exceed the maximum LIN bus current (condition: i1= < 40mA).

[0071] In the simplest case, the xth auto-addressing bus node (SLx) switches off its addressing current source (Iqx) and adopts a predetermined fault address as the bus node address. After auto-addressing has been completed, the bus master (ECU) can send a test query to the bus nodes using this fault address as the bus node address, to which they respond with a standardized response.

[0072] In the simplest case, the bus master (ECU) can then signal a bus error to all bus nodes and / or users. The bus master (ECU) can also send a command to the bus nodes with this error address, whereupon they first change the feed point of their addressing stream, e.g., using a multiplexer (MUX), and secondly swap the polarity of the inputs or, alternatively, the output of the first differential amplifier (D1). The bus master (ECU) then reassigns the address. Only if this is still incorrect does it preferentially signal an error. If necessary, it shuts down the still affected bus nodes by sending a command (broadcast command) to the error address in question, since a different error is then obviously present. Figure 9

[0073] Fig. 9 shows the situation after a. detecting a swap of the LIN inputs and outputs, b. switching the feed point of the auto-addressing current of the addressing current source (Iq2) of the second auto-addressing bus node (SL2) which is rotated here as an example, and c. reversing the polarity of the inputs or alternatively reversing the output of the first differential amplifier (D1). Figure 10

[0074] Fig. 10 shows the second auto-addressing bus node (SL2), which Fig. 8 and Fig. 9 in more detail as an x-th auto-addressing bus node. Where x represents a position in the LIN bus chain of bus nodes in the form of a positive, integer, natural number. This is an x-th auto-addressing bus node (SLx) that is capable of • Firstly, to detect a swap of its LIN input with its LIN output and • Secondly, in this case, as an exemplary countermeasure, to position the feed point for the addressing current of its regulated addressing current source (Iqx) in front of or behind its bus shunt resistor (R2) so that auto-addressing is possible depending on the wiring.

[0075] In this regard, the Fig. 10, the x-th auto-addressing bus node (SLx) shown as an example has a detection device (DET) capable of detecting a swap of the LIN input of the x-th auto-addressing bus node (SLx) with the LIN output of the x-th auto-addressing bus node (SLx). To do so, the example detection device (DET) checks internal signals of the x-th auto-addressing bus node (SLx) for plausibility. If the internal signals of the x-th auto-addressing bus node (SLx) reliably indicate a swap of the LIN input of the x-th auto-addressing bus node (SLx) with the LIN output of the x-th auto-addressing bus node (SLx), the detection device can potentially take various exemplary measures. a. Signaling the error to a user; b. Signalling the error to a bus master (ECU) by responding to a diagnostic request (broadcast message); c. Use of an error address as bus node address; d. Reconfiguration of the internal topology to neutralize the fault; e. Reparameterization of internal sub-devices such as current sources to neutralize the fault; Further measures are conceivable.

[0076] In the example of Fig. 10, a reconfiguration of the internal topology is planned to neutralize the error. In the Fig. 10, for example, the detection device (DET) changes the feed point for the addressing current of the regulated addressing current source (Iqx) of the x-th auto-addressing bus node (SLx), for example with the aid of an analog multiplexer (MUX), and swaps the polarity of the inputs or the output of the first differential amplifier (D1) by means of the polarity signal (pol).

[0077] Alternatively to the example of Fig.10, a reparameterization of internal sub-devices such as current sources for neutralizing the error is possible if, instead of an addressing current source (Iqx) of the x-th auto-addressing bus node (SLx) and a multiplexer (MUX), a first addressing current source (Iqx1) of the x-th auto-addressing bus node (SLx) and, for example, a second addressing current source (Iqx2) of the x-th auto-addressing bus node (SLx) are used, of which the first addressing current source (Iqx1) of the x-th auto-addressing bus node (SLx) feeds its addressing current upstream of the bus shunt resistor (R2) and the second addressing current source (Iqx2) of the x-th auto-addressing bus node (SLx) feeds its addressing current downstream of the bus shunt resistor (R2).In this case, the detection device (DET) would set the addressing current of one of the two current sources (Iqx1, Iqx2) to zero, so that the equivalent effect is achieved as when combining an addressing current source (Iqx) of the x-th auto-addressing bus node (SLx) with the switching by a multiplexer (MUX).

[0078] For example, the detection device (DET) can detect that the control value (rwx) of the x-th auto-addressing bus node (SLx) maximizes the addressing current of the addressing current source (iqx). This can be done, for example, with a suitable design, by comparing the control value (rwx) with a second threshold value (Ref2). If the derivative of the addressing current of the auto-addressing current source (iqx) with respect to the control value (rwx) is positive, this means that the control value (rwx) is above the second threshold value (Ref2). Furthermore, the detection device (DET) can simultaneously compare the output (ds1) of the first differential amplifier (D1) with a third reference value. If the output (ds1) of the first differential amplifier (D1) is below a third reference value (Ref3), the detection device can react to a negative voltage drop (V R2 ) via the bus shunt resistor (R2) or to a voltage drop (V R2) across the bus shunt resistor (R2) close to zero. This condition is illegal because the auto-addressing current source supplies a positive addressing current, which, if correctly mounted, should flow through the bus shunt resistor (R2), but this obviously does not happen.

[0079] The detection device (DET) can signal such a detected error, for example, via an error signal (er) to a bus node internal computer or a suitable controller. List of reference symbols D1 first differential amplifier; d1 first reverse polarity protection diode D2 second differential amplifier; d2 second reverse polarity protection diode D3 third differential amplifier; DET detection device; ds1 Output of the first differential amplifier (D1); ds2 Output of the second differential amplifier (D2); ds3 Output of the third differential amplifier (D3); ECU Busmaster; the error signal to the bus node internal optional processor; F nonlinear filter of an auto-addressing bus node (SL1, SL2, SL3); Iq1 regulated addressing current source of the first auto-addressing bus node (SL1), which supplies the addressing current of the first auto-addressing bus node (SL1); i1 Bus node output current of the first auto-addressing bus node (SL1); Iq2 regulated addressing current source of the second auto-addressing bus node (SL2), which supplies the addressing current of the second auto-addressing bus node (SL2); i2 Bus node output current of the second auto-addressing bus node (SL2); i2R bus shunt current through the bus shunt resistor (R2) of the second auto-addressing bus node (SL2); Iq3 regulated addressing current source of the third auto-addressing bus node (SL3), which supplies the addressing current of the third auto-addressing bus node (SL3); i3 Bus node output current of the third auto-addressing bus node (SL3); Iqx regulated addressing current source of the x-th auto-addressing bus node (SLx), which supplies the addressing current of the x-th auto-addressing bus node (SLx); ix Bus node output current of the x-th auto-addressing bus node (SLx); ixR bus shunt current through the bus shunt resistor (R2) of the x-th auto-addressing bus node (SLx); I ref specified current sum for the bus node output currents; pol Signal with which the detection device (DET) switches the polarity of the two inputs of the first differential amplifier (D1) or the polarity of the output of the first differential amplifier (D1) if the plausibility check results in implausible internal signals (ds1, ds3). R1 Auxiliary shunt resistor of an auto-addressing bus node (SL1, SL2, SL3) R2 Bus shunt resistor of an auto-addressing bus node (SL1, SL2, SL3) R3 Slave pull-up resistor Ref Reference value rw1 Control value of the first auto-addressing bus node (SL1) rw2 Control value of the second auto-addressing bus node (SL2) rw3 Control value of the third auto-addressing bus node (SL3) rwx Control value of the x-th auto-addressing bus node (SLX) S1 first switch of an auto-addressing bus node (SL1, SL2, SL3) S2 second switch of an auto-addressing bus node (SL1, SL2, SL3) S3 third switch of an auto-addressing bus node (SL1, SL2, SL3) Self-service counter SL1 first auto-addressing bus node SL2 second auto-addressing bus node SL3 third auto-addressing bus node SLx x-th auto-addressing bus node V R2 Voltage drop across the bus shunt resistor (R2) of the respective auto-addressing bus node (SL1, SL2, SL3); List of cited writings DE 10 2010 026 431 B1, DE 10 147 512 B4, EP 1490 772 B1, US 9 331 866 B2

Claims

[1] Procedure for assigning bus addresses within a serial data bus consisting of a chain of bus nodes (SL1, SL2, SL3) and a bus master (ECU) - where the bus nodes (SL1, SL2, SL3) can be auto-addressing bus nodes or standard bus nodes and - where the data bus has a bus master (ECU) and - wherein each bus node (SL2, SL3) has a preceding bus node (SL1, SL2) if it is not the first bus node (SL1) and - each bus node (SL2, SL3) being connected to its preceding bus node (SL1, SL2) by the data bus if it is not the first bus node (SL1) and - wherein the first bus node (SL1) is connected to the bus master (ECU) via the data bus and - wherein each bus node (SL2, SL3) sends a bus node output current (i2, i3) to its preceding bus node (SL1, Sl2) via a bus node output if it is not the first bus node (SL1), and - wherein the first bus node (SL1,) sends a bus node output current (i1) to the bus master (ECU) via a bus node output and - wherein each bus node (SL1, SL2) receives a bus node input current (i2, i3) from its subsequent bus nodes (SL2, Sl3) via a bus node input if it is not the last bus node (SL3), with the following steps - Determination of the maximum addressing current (I amax ); - Perform an initialization sequence with the following steps for each auto-addressing bus node of the bus nodes (SL1, SL2, SL3) that does not yet have a valid bus node address until all auto-addressing bus nodes of the bus nodes (SL1, SL2, SL3) have a valid bus node address: • Signaling that a bus address is to be assigned to all auto-addressing bus nodes by means of an auto-addressing command; • Execution of the following steps by all auto-addressing bus nodes (SL1, SL2, SL3), hereinafter referred to as the relevant auto-addressing bus node (SLj): • Reception of the said auto-addressing command, in particular from the bus master (ECU), by the relevant auto-addressing bus node (SLj); • Receipt of a start signal for the allocation of the bus address to be allocated from the bus master (ECU) by the relevant auto-addressing bus node (SLj) and start of a timer by the relevant auto-addressing bus node (SLj); • Feeding the bus input current (i) received from the subsequent bus nodes (SL(j+1), SL(j+2)...) (j+1) ) into the bus node output of the respective auto-addressing bus node (SLj) as part of the bus output current (i j ) of the relevant auto-addressing bus node (SLj); • Detecting the value of the bus node output current (i j ) of the relevant auto-addressing bus node (SLj ) by means of measuring instruments (R2, D1, D3); • Checking the recorded value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) for plausibility and initiation of measures if the recorded value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) is not plausible; • Generation of a control signal (rw j ) from the recorded value of the bus node output current (i j ) of the relevant auto-addressing bus node (SLj) by means of regulating means (F); • Control of the bus node output current (i j ) by the respective auto-addressing bus node (SLj), by means of a regulated auto-addressing current source (Iqj), whose addressing current is a portion of the bus output current (i j ) to a given total current value (I ref ) depending on the generated control signal (rwj), • wherein an increase in the addressing current of the regulated auto-addressing current source (Iqj) of the relevant auto-addressing bus node (SLj) takes place with a first time constant (τ1) and • wherein a reduction of the addressing current of the regulated auto-addressing current source (Iqj) of the respective auto-addressing bus node (SLj) is carried out with a second time constant (τ2) and • where the second time constant (τ2) is smaller than the first time constant (τ1); • Comparing the control value (rj) of the relevant auto-addressing bus node (SLj) with a threshold value (SWj) of the relevant auto-addressing bus node (SLj); • Freezing the control of the addressing current source (Iqj) of the relevant auto-addressing bus node (SLj) at a first time (τ1) after the start of the timer; • Reception of the bus node address to be assigned from the bus master (ECU) by the relevant auto-addressing bus node (SLj); • Acceptance of the bus node address to be assigned from the bus master (ECU) as a valid bus node address of the relevant auto-addressing bus node (SLj) if a minimum time has elapsed since the start of the timer and if the comparison of the control value (rj) with a threshold value (SWj) shows that the addressing current of the addressing current source (Iqj) of the relevant auto-addressing bus node (SLj) is above a current threshold value and configuration of the relevant auto-addressing bus node (SLj) as a standard bus node without auto-addressing capability with the bus node address to be assigned as the bus node address of the relevant auto-addressing bus node (SLj) at a second time (t2) after the first time (t1), as a result of which this relevant auto-addressing bus node (SLj) no longer participates in subsequent initialization sequences until further notice. • Checking the successful address assignment by the bus master (ECU); • If necessary, deletion of the validity of the last assigned bus node address, whereby the relevant auto-addressing bus nodes (SLj) again behave like auto-addressing bus nodes (SLj) without a valid bus node address; • Check whether all auto-addressing bus nodes have received a valid bus node address; • Performing another initialization sequence if not all auto-addressing bus nodes have received a valid bus node address [2] Method according to claim 1 - Execution of the following step by the relevant auto-addressing bus node (SLj): • Switching off any existing bus node basic current sources (S1, R3, d1) within the relevant auto-addressing bus node (SLj). [3] Method according to one or more of the preceding claims - Where the second time constant (τ2) is smaller than the first time constant (τ1) by a factor greater than 10. [4] Method according to one or more of the preceding claims - wherein the second time constant (τ2) within the respective auto-addressing bus node (SLj) depends on the value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) depends. [5] Method according to one or more of the preceding claims - wherein the first time constant (τ1) within the respective auto-addressing bus node (SLj) depends on the value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) depends. [6] Method according to one or more of the preceding claims - wherein the first time constant (τ1) within the respective auto-addressing bus node (SLj) depends on the value of the bus node output current (ij ) of the relevant auto-addressing bus node (SL j ) in such a way that the value of the first time constant (τ1) has a first value below a threshold value and a second value above the threshold value. [7] Method according to one or more of the preceding claims comprising the additional step - Redetermination of the addressing current injection point if the detected value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) is not plausible; [8] A method according to claim 7 comprising the additional step - Signaling of an error via the data bus upon request by a bus master (ECU) if the recorded value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) is not plausible; [9] Method according to one or more of claims 1 to 8 comprising the additional step - performing the step of detecting the value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) using measuring instruments (R2, D1, D3) as: • Detecting the value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) by means of measuring means (R2, D1, D3) with a first sign, if the detected value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) is plausible, and • Detecting the value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) by means of measuring means (R2, D1, D3) with a second sign which is inverted to the first sign if the detected value of the bus node output current (i j) of the relevant auto-addressing bus node (SL j ) is plausible. [10] Method according to one or more of claims 1 to 9 comprising the additional step - Use of an error address as a valid bus node address of the relevant auto-addressing bus node (SLj) if the detected value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) is not plausible; [11] Bus nodes (SL1, SL2, SL2) for a serial data bus - with a bus shunt resistor (R2) inserted into the data bus and - with an addressing current source (Iq1, Iq2, Iq3, Iqx) for determining the bus position of the bus node in the data bus, which can additionally feed an addressing current into the data bus in a controlled manner such that the total current (i1, i2, i3, ix) through the bus shunt resistor (R2) of the bus node (Sl1, SL2, SL3, SLx) corresponds to a predetermined or calculated or otherwise determined total current (I ref ) and - with means (R2, D1, Iq1, Iq2, Iq2, Iqx, DET) for detecting a swap of bus node input and bus node output, wherein the addressing current of its addressing current source (Iq1, Iq2, Iq2, Iqx) is provided to flow through the bus shunt resistor (R2) during normal operation. [12] Bus node according to the preceding claim, - wherein the bus node has means (R2, D1) to detect the current through the bus shunt resistor (R2). [13] Bus node according to the preceding claim, - where the detected current through the bus shunt resistor (R2) is used for a self-test. [14] Bus node according to claim 12, - with a detection device (DET) that checks internal signals (ds1, ds3) of the bus node (SLx) for plausibility. [15] Bus node according to the preceding claim, - wherein the bus node (SLx) or a sub-device (DET) of the bus node (SLx) takes measures if the detection device (DET) detects implausible internal signals within the bus node. [16] Bus node according to one or more of claims 11 to 15, - wherein the bus node comprises a sub-device (MUX) which can change the feed point of the addressing current of the addressing current source (Iqx). [17] Bus node according to one or more of claims 11 to 16, - wherein the bus node has a first addressing current source (Iqx1) and a second addressing current source (Iqx2) instead of an addressing current source (Iq1, Iq2, Iq2, Iqx), and - wherein the first addressing current source (lqx1) injects its current into a node connected to the first terminal of the bus shunt resistor (R2) when it injects current, and - wherein the second addressing current source (Iqx2) injects its current into a node connected to the second terminal of the bus shunt resistor (R2) when it injects current, and - where the two addressing current sources (Iqx1, Iqx2) feed their currents in such a way that the addressing current flows through the bus shunt resistor (R2). [18] Bus node according to one or more of the preceding claims 11 to 17, - wherein the addressing current source (Iq1, Iq2, Iq2) increases the addressing current with a first time constant (τ1) and decreases it with a second time constant (τ2) which is smaller than the first time constant (τ1).

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