Backside deep trench insulating (BDTI) structure for image sensor with pinned photodiode

Abstract

CMOS image sensor, including: a substrate (102) having a front (122) and a back (124) opposite the front (122); a plurality of pixel regions (103a, 103b) arranged in the substrate (102), each comprising a photodiode (104) configured to convert radiation entering the substrate (102) from the rear (124) into an electrical signal; and a BDTI structure (111) arranged in a deep trench (802) between adjacent pixel regions (103a, 103b) extending from the back (124) of the substrate (102) to a position in the substrate (102); wherein the BDTI structure (111) comprises a doped layer (114) having a first doping type and a dielectric filling layer (112), wherein the doped layer (114) lines a side wall surface of the deep trench (802) and the dielectric filling layer (112) fills the remaining space of the deep trench (802), and wherein the doped layer (114) and the dielectric filling layer (112) of the BDTI structure (111) extend upwards from the deep trench (802) and are arranged laterally along the rear side (124) of the substrate (102).

Description

BACKGROUND

[0001] Digital cameras and optical imaging devices use image sensors. Image sensors convert optical images into digital data that can be displayed as digital images. An image sensor comprises a pixel matrix (or grid) for detecting the light intensity and recording intensity (brightness) of the detected light. The pixel matrix responds to the light by accumulating a charge. The accumulated charge is then used (for example, by other circuitry) to provide a color and brightness signal for use in a suitable application, such as a digital camera. One type of image sensor is a back-illuminated (BSI) image sensor device.Back-side illumination (BSI) image sensor devices are used to sample a volume of light projected onto the back side of a substrate (facing a front side of the substrate on which interconnection structures comprising multiple metallic and dielectric layers are mounted). BSI image sensor devices provide reduced destructive interference compared to front-side illumination (FSI) image sensor devices.

[0002] Publication US 2015 / 0243694A1 discloses image sensors comprising a substrate that defines multiple pixel regions. The substrate defines a deep trench extending from a second surface of the substrate toward a first surface, separating the multiple pixel regions. A photoelectric conversion region is provided within each of the multiple pixel regions of the substrate. The image sensors also include a flat device insulation layer on the first surface of the substrate. The flat device insulation layer defines an active region within each of the pixel regions, and the negative fixed charge layer contacts the flat device insulation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The aspects of this revelation are best understood from the following detailed description, when read with the accompanying figures. It should be noted that, as is common practice in the field, several features are not drawn to scale. Indeed, the dimensions of the various features may have been enlarged or reduced at will for the sake of clarity of discussion. Fig. Figure 1 shows a cross-sectional view of some embodiments of a CMOS (complementary metal oxide semiconductor) image sensor having a photodiode surrounded by a backside deep trench insulation (BDTI) structure. Fig. Figure 2 shows a cross-sectional view of some additional embodiments of a CMOS image sensor comprising a photodiode surrounded by a backside deep trench insulation (BDTI) structure. Fig. Figure 3 shows a cross-sectional view of some additional embodiments of a CMOS image sensor comprising a photodiode surrounded by a backside deep trench insulation (BDTI) structure. Fig. Figure 4 shows a cross-sectional view of some additional embodiments of a CMOS image sensor comprising a photodiode surrounded by a backside deep trench insulation (BDTI) structure. Fig. Figure 5A shows a cross-sectional view of some embodiments of an integrated chip comprising an image sensor having a photodiode surrounded by a backside deep trench insulation (BDTI) structure. Fig. Figure 5B shows a cross-sectional view of some additional embodiments of an integrated chip comprising an image sensor having a photodiode surrounded by a backside deep trench insulation (BDTI) structure. Fig. Figures 6 to 11 depict some embodiments of cross-sectional views showing a method for forming a CMOS image sensor comprising a photodiode surrounded by a backside deep trench insulation (BDTI) structure. Fig. Figure 12 shows a flow diagram of some embodiments of a method for forming a CMOS image sensor comprising a photodiode surrounded by a backside deep trench insulation (BDTI) structure. DETAILED DESCRIPTION

[0004] Improved CMOS image sensors and an improved manufacturing process are provided according to claims 1, 13, and 18. The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first feature above or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features can be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various embodiments and / or the configurations discussed.

[0005] Furthermore, spatial reference terms, such as "below," "under," "lower," "above," "over," "upper," and the like, can be used here for easier description of the relationship between an element or feature and one or more other elements or features, as illustrated in the figures. These spatial reference terms are intended to accommodate different orientations of the device during use or operation, in addition to the orientation shown in the figures. The device can be oriented differently (rotated by 90 degrees or in other orientations), and the spatial reference terms used here can be interpreted accordingly.

[0006] Integrated circuit (IC) technologies are constantly being improved. These improvements often necessitate the reduction of component geometries to achieve lower manufacturing costs, higher component density, increased speeds, and improved performance. Due to component scaling, the pixels of an image sensor's pixel matrix are smaller and positioned closer together. Improved electrical and optical isolation between adjacent image sensor pixels is required to reduce glare and overlap. Dielectric trenches and implantation wells can be fabricated as insulating structures to isolate image sensor pixels.

[0007] Furthermore, pinned photodiode (PPD) CMOS image sensors, driven by low-noise applications, have become the main image sensor technology for both commercial and scientific applications. The PPD is formed by a double pn impurity junction, at which a p +A surface implant, also known as a pinning implant, is formed on the surface of the substrate. This double pn defect junction structure not only reduces the dark current (by isolating the buried collector channel from the charges generated at the SiO2-Si interface) but also limits the maximum PPD channel potential, often referred to as the pinning voltage, which corresponds to the totally depleted state. One type of current fabrication process for image sensors involves a series of implantation steps to form the pinned implant for a PPD structure and implantation wells as insulating walls. However, in addition to the complexity of the fabrication, these implantation steps necessitate a thick photoresist layer, which reduces the exposure resolution.The full-well capacity of the photodiode is also limited, and a higher pinning voltage is created by the implantation profile, which negatively affects the performance of the image sensor.

[0008] The present disclosure relates to a CMOS image sensor comprising a backside deep trench insulation (BDTI) structure surrounding a photodiode, and an associated formation method. In some embodiments, the CMOS image sensor has a pixel region arranged in a substrate. The pixel region includes a photodiode configured to convert radiation into an electrical signal. A backside deep trench insulation (BDTI) structure, arranged in the pixel region of the substrate, extends from a rear face of the substrate to a position within the substrate. The BDTI structure comprises a doped layer and a dielectric layer, the doped layer lining one sidewall face of a deep trench and the dielectric layer filling the remaining space of the deep trench.The BDTI structure can be formed from the back side of the substrate and serves as an insulating structure between adjacent pixels, while also acting as a doped well for depletion. This, combined with the disclosed BDTI structure acting as a doped well, simplifies the implantation process from the front side of the substrate, thereby improving the exposure resolution, the photodiode's full-well capacitance, and the pinning voltage. Furthermore, the disclosed BDTI structure, acting as a deep insulating structure, reduces overexposure and overlap.

[0009] Fig. Figure 1 shows a cross-sectional view 100 of some embodiments of a CMOS image sensor comprising a photodiode surrounded by a backside deep trench insulation (BDTI) structure. The CMOS image sensor comprises a substrate 102 having a front side 122 and a back side 124. In the various embodiments, the substrate 102 can comprise any type of semiconductor body (e.g., silicon / CMOS bulk, SiGe, SOI, etc.), such as a semiconductor wafer or one or more dies on a wafer, as well as any other type of semiconductor and / or epitaxial layers formed on it and / or otherwise associated with it. The substrate 102 comprises a plurality of pixel regions arranged in the substrate 102 in a matrix, the rows and / or columns being such as those shown in Fig. The pixel regions 103a and 103b shown in Figure 1 can be arranged as follows: Each pixel region 103a and 103b comprises a photodiode 104 configured to convert incident radiation or light 120 (e.g., photons) into an electrical signal. In some embodiments, the photodiode 104 comprises a first region 104a in the substrate 102, which has a first doping type (e.g., p-type doping), and an adjacent second region 104b in the substrate 102, which has a second doping type (e.g., n-type doping) that is different from the first doping type.

[0010] A backside deep trench insulation (BDTI) structure 111 is arranged in the substrate 102, extending from the backside 124 to a position within the substrate 102. The BDTI structure 111 is located between and insulates the adjacent pixel regions 103a and 103b. In some embodiments, the BDTI structure 111 comprises a doped layer 114 with the first doping type (e.g., a p-type doping) and a dielectric filler layer 112 (e.g., an oxide layer). The doped layer 114 lines a sidewall surface of a deep trench, and the dielectric filler layer 112 fills a remaining space of the deep trench.

[0011] In some embodiments, a doped insulating layer 110 is arranged in the substrate 102, extending from the front face 122 to a position within the substrate 102. The doped insulating layer 110 can have the first doping type (e.g., p-type doping). The doped insulating layer 110 can comprise a lateral section 110a and a perpendicular section 110b that extends deeper into the substrate. The lateral section 110a extends along the front face 122 of the substrate 102. The lateral section 110a can contact a lateral surface of the photodiode 104 and serves as a pinned implantation layer for the photodiode 104. The perpendicular section 110b extends from the front face 122 of the substrate 102 to a position within the substrate 102 between the adjacent pixel regions 103a, 103b. The lateral section 110a may be heavily doped (e.g.with a low resistivity in the milliohm / cm range) and a doping concentration greater than that of the perpendicular section 110b. In some embodiments, the perpendicular section 110b is oriented perpendicularly to the BDTI structure 111 (e.g., sharing a common centerline 126 with it). The perpendicular section 110b can meet the BDTI structure 111 in the substrate 102. A lower section of the BDTI structure 111 can be arranged in a recessed upper surface of the perpendicular section 110b of the doped insulating layer 110. The BDTI structure 111 and the doped insulating layer 110 together serve as insulators for the pixel regions 103a, 103b, thus reducing overlap and overexposure between the pixel regions 103a, 103b.The BDTI structure 111 and the doped insulating layer 110 also enable an overall depletion of the photodiode 104 during operation, thus improving the full-well capacitance and the pinning voltage.

[0012] In some embodiments, a plurality of color filters 116 is arranged over the back surface 124 of the substrate 102. Each plurality of color filters 116 is configured to transmit specific wavelengths of incident radiation or incident light 120. For example, a first color filter (e.g., a red color filter) may transmit light having wavelengths in a first range, while a second color filter may transmit light having wavelengths in a second range that is different from the first range. In some embodiments, the plurality of color filters 116 may be arranged in a grid structure superimposed on the substrate 102. In some embodiments, the grid structure may comprise a stacked grid having a metallic frame surrounded by a dielectric material.In some embodiments, a layer of dielectric material and the stacking grid can have the same dielectric material (e.g. silicon dioxide (SiO2)).

[0013] A plurality of microlenses 118 is arranged above the plurality of color filters 116. The individual microlenses 118 are oriented laterally towards the color filters 116 and lie above the pixel regions 103a, 103b. In some embodiments, the plurality of microlenses 118 has a substantially flat lower surface that abuts the plurality of color filters 116 and a curved upper surface. The curved upper surface is configured to focus the incident radiation or incident light 120 (e.g., light directed towards the underlying pixel regions 103a, 103b). During operation of the CMOS image sensor, the incident radiation or incident light 120 is focused by the microlens 118 onto the underlying pixel regions 103a, 103b. When an incident radiation or incident light with sufficient energy strikes the photodiode 104, it generates an electron hole pair that produces a photocurrent.In particular, it is understood that, although the microlenses 118 in . Fig. 1 shown as fixed to the image sensor, the image sensor may not include a microlens, and the microlens may be attached to the image sensor later in a separate manufacturing activity.

[0014] Fig. Figure 2 shows a cross-sectional view of some additional embodiments of a CMOS image sensor comprising the photodiode 104 surrounded by the BDTI structure 111. In addition to similar features previously described for Fig. As shown and described in Figure 1, the BDTI structure 111 comprises, in some embodiments, as in Fig. Figure 2 shows a high K-value dielectric lining 113 arranged between the doped layer 114 and the dielectric filler layer 112. The high K-value dielectric lining 113 can serve as a passivation layer, separating the doped layer 114 from the dielectric filler layer 112. The high K-value dielectric lining 113 can, for example, comprise aluminum oxide (A1O), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfA1O), or hafnium tantalum oxide (HfTaO). In some embodiments, which differ from those shown in Figure 2, the following applies: Fig. Figure 1 shows that the doped layer 114 and the dielectric filler layer 112 have upper surfaces that are coplanar to a lateral surface of the back side 124 of the substrate 102, and can be in Fig. 2. The doped layer 114, the high K-value dielectric lining 113, and the dielectric filler layer 112 extend upwards from the deep trench over the back side 124 of the substrate 102 and are arranged laterally along the back side of the substrate 102. The doped layer 114 and the high K-value dielectric lining 113 can be conformal layers. The in Fig. The image sensor shown in Figure 2 can be an intermediate structure, and the doped layer 114, the high K-value dielectric lining 113, and the dielectric filler layer 112 may or may not be subjected to a planarization process, so that the upper surfaces of the layers could be changed.

[0015] In some embodiments, a floating diffusion tray 204 is arranged between the adjacent pixel regions 103a, 103b, extending from the front face 122 of the substrate to a position within the substrate 102. A transfer gate 202 is located on the front face 122 of the substrate 102, positioned laterally between the photodiode 104 and the floating diffusion tray 204. During operation, the transfer gate 202 controls the charge transfer from the photodiode 104 to the floating diffusion tray 204. If the charge level in the floating diffusion tray 204 is sufficiently high, a source-follower transistor (not shown) is activated, and the charges are selectively output according to the operation of a row-select transistor (not shown), which is used for addressing. A reset transistor (not shown) can be used to reset the photodiode 104 between exposure periods.

[0016] Fig. Figure 3 shows a cross-sectional view of some additional embodiments of a CMOS image sensor comprising the photodiode 104 surrounded by the BDTI structure 111. In addition to similar features previously described for Fig. 1 and Fig. 2 shown and described, in some embodiments, as in Fig. Figure 3 shows a shallow trench insulation (STI) structure 302 arranged between the adjacent pixel regions 103a, 103b from the front face 122 of the substrate 102 to a position within the substrate 102. The STI structure 302 and the BDTI structure 111 are perpendicularly oriented (e.g., they have a common centerline 304, which may or may not share a common centerline with the perpendicular section 110b of the doped insulating layer 110). In some embodiments, the perpendicular section 110b of the doped insulating layer 110 extends from the front face 122 of the substrate 102 to a position within the substrate 102 and surrounds the STI structure 302. The perpendicular section 110b of the doped insulating layer 110 can separate the STI structure 302 from the BDTI structure 111.Thus, the BDTI structure 111, the doped insulating layer 110, and the STI structure 302 together serve as insulation for the pixel regions 103a and 103b, thereby reducing overlap and overexposure between these regions. The BDTI structure 111 and the doped insulating layer 110 also enable the depletion of the photodiode 104 during operation, thus improving the full-well capacitance and the pinning voltage.

[0017] Fig. Figure 4 shows a cross-sectional view of some additional embodiments of a CMOS image sensor comprising the photodiode 104 surrounded by the BDTI structure 111. As an alternative embodiment to Fig. 3, in which the doped insulating layer 110 separates the STI structure 302 from the BDTI structure 111, as in Fig. As shown in Figure 4, the BDTI structure extends deeper into the substrate 102 and meets the STI structure 302. In some embodiments, the doped layer 114 of the BDTI structure 111 ends up on a flat or recessed upper surface of the STI structure 302, while the high K-value dielectric lining 113 and / or the dielectric filler layer 112 of the BDTI structure 111 extend further downwards to a concave recess of the STI structure 302.

[0018] Fig. Figure 5A shows a cross-sectional view of some embodiments of an integrated chip comprising an image sensor having the photodiode 104 surrounded by the BDTI structure 111. In addition to similar features previously shown and described, some embodiments, as in Fig. Figure 5A shows a back-end-of-line (BEOL) metallization stack 108 arranged on the front face 122 of the substrate 102. The BEOL metallization stack 108 comprises a plurality of metallic interconnection layers arranged in one or more dielectric intermediate layer (ILD) layers 106. The ILD layers 106 may comprise one or more of a low K-value dielectric layer (i.e., a dielectric with a dielectric constant of less than about 3.9), a particularly low K-value dielectric layer, or an oxide (e.g., silicon oxide). A logic gate device 502 may be arranged on the same integrated chip of the image sensor and isolated by a logic STI structure 504. Conductive contacts 506 are arranged in the ILD layers 106.The conductive contacts 506 extend from the transfer gate 202 and the floating diffusion tray 204 to one or more layers of metal wire 508. In various embodiments, the conductive contacts 506 can comprise a conductive metal, such as copper or tungsten.

[0019] Fig. Figure 5B shows a cross-sectional view of some additional embodiments of an integrated chip comprising an image sensor having the photodiode 104 surrounded by the BDTI structure 111. As an alternative to the previously disclosed embodiments, the image sensor can have the second region 104b of the photodiode 104 with a lateral dimension smaller than that of the first region 104a. The floating diffusion tray 204 is arranged between the STI structures 302 on the far side of the transfer gate 202 opposite the photodiode 104. The logic STI structure 504 can have the same or different dimensions as the STI structure 302.

[0020] Fig. Figures 6 to 11 depict some embodiments of cross-sectional views showing a method for forming a CMOS image sensor having a photodiode surrounded by a backside deep trench insulation (BDTI) structure.

[0021] As shown in the cross-sectional view 600 from Fig. As shown in Figure 6, dopants are implanted into a substrate 102 to form a doped region comprising a photodiode 104 and a doped insulating layer 110 in a front face 122 of the substrate 102. In various embodiments, the substrate 102 can comprise any type of semiconductor body (e.g., silicon / CMOS bulk, SiGe, SOI, etc.), such as a semiconductor wafer or one or more dies on a wafer, as well as any other type of semiconductor and / or epitaxial layers formed on it and / or otherwise associated with it. The substrate 102 can be prepared by comprising a first region 104a of the photodiode to be formed with a first doping type (e.g., p-type). Then a cover implant or a graded epitaxial growth process can be performed to form a second region 104b of the photodiode, which is to be formed with a first doping type (e.g. p-type).A dopant is then implanted into the substrate 102 to form a doped insulating layer 110. In some embodiments, the dopant may comprise the first conducting type (e.g., a p-type dopant, such as boron), which is implanted into the front face 122 of the substrate 102. In other embodiments, the dopant may comprise an n-type dopant (e.g., phosphorus). In some embodiments, the dopant may be implanted as a deck implantation (i.e., as an unmasked implantation) to form a lateral section 110a extending to a first depth of the substrate 102 from the front face 122, followed by selective implantation (i.e., a masked implantation) to form a perpendicular section 110b comprising a plurality of clefts extending to a second depth of the substrate 102, which is deeper than the first depth.The lateral section 110a can have a higher doping concentration than the vertical section 110b.

[0022] As shown in the cross-sectional view 700 from Fig. As shown in Figure 7, a transfer gate 202 is formed over a front face 122 of the substrate 102. The transfer gate 202 can be formed by depositing a dielectric gate layer and a gate electrode layer over the substrate 102. The dielectric gate layer and the gate electrode layer are then patterned to form a dielectric gate layer and a gate electrode. Sidewall spacers can be formed on the outer sidewalls of the gate electrode. In some embodiments, the sidewall spacers can be formed by depositing nitride onto the front face 122 of the substrate 102 and selectively etching the nitride to form the sidewall spacers. Implantation processes are carried out in the front face 122 of the substrate 102 to form a floating diffusion trough 204 along one side of the transfer gate 202 or opposite sides of a pair of transfer gates 202, as shown in Fig. Figure 7 shows that in some embodiments, the substrate 102 can be selectively implanted according to a structured masking layer (not shown) comprising a photoresist.

[0023] In some embodiments, as shown in cross-sectional view 1000 from Fig. As shown in Figure 10, one or more insulating structures 302 (e.g., shallow trench insulating regions) can be formed on the front face 122 of the substrate 102 on opposite sides of a pixel region 103a, 103b. The one or more insulating structures 302 can be formed by selectively etching the front face 122 of the substrate 102 to form shallow trenches and subsequently forming an oxide in the shallow trenches. The one or more insulating structures 302 can be formed before or after the formation of the transfer gate 202 and / or the floating diffusion trough 204.

[0024] Although this in Fig. 6 or Fig. Not shown in Figure 10, a BEOL metallization stack comprising a variety of metallic interconnection layers arranged in an ILD layer (see, for example, Figure 10) can be used. Fig. 5A or Fig. 5B for the BEOL metallization stack 108 and the ILD layer 106) are formed over the front face 122 of the substrate 102. In some embodiments, the BEOL metallization stack can be formed by forming the ILD layer, comprising one or more layers of ILD material, over the front face 122 of the substrate 102. The ILD layer is subsequently etched to form contact holes and / or metal grooves. The contact holes and / or metal grooves are then filled with a conductive material to form the plurality of metallic interconnection layers. In some embodiments, the ILD layer can be deposited by a physical vapor deposition technique (e.g., PVD, CVD, etc.). The plurality of metallic interconnection layers can be formed using a deposition process and / or an electroplating process (e.g., electroplating, chemical plating, etc.).In various embodiments, the multiple metallic interconnection layers can include, for example, tungsten, copper, or aluminum-copper. The ILD layer can then be bonded to a handling substrate (not shown). In some embodiments, the bonding process can utilize a bonding oxide interlayer positioned between the ILD layer and the handling substrate. In some embodiments, the bonding process can include a melt bonding process.

[0025] As shown in the cross-sectional view 800 from Fig. As shown in Figure 8, the substrate 102 is flipped over to a back surface 124, which faces the front surface 122, for further processing. The substrate 102 is selectively etched to form deep trenches 802 in the back surface 124. In some embodiments, the substrate 102 can be etched by forming a masking layer on the back surface 124. The substrate 102 is then exposed to an etchant in the regions not covered by the masking layer. The etchant etches the substrate 102 to form deep trenches 802 that extend down to the substrate 102. In various embodiments, the masking layer can comprise a photoresist or a nitride (e.g., SiN) that is patterned using a photolithography process. In various embodiments, the etchant can be a dry etchant with an etching chemical containing a fluorine doping agent (e.g. CF4, CHF3, C4F8, etc.).The deep grooves 802 extend through the doped insulating layer 110 to a position in the substrate 102 and laterally separate the photodiode 104. The substrate 102 can be thinned to reduce its thickness before the deep grooves are formed and to allow radiation to pass through the back surface 124 of the substrate 102 to the photodiode 104. In some embodiments, the substrate 102 can be thinned by etching the back surface 124 of the semiconductor substrate. In other embodiments, the substrate 102 can be thinned by mechanically grinding the back surface 124 of the semiconductor substrate.

[0026] As shown in the cross-sectional view 900 Fig. 9 or the cross-sectional view 1100 from Fig. As shown in Figure 11, a self-aligned doped layer 114 is formed along the sidewalls of the deep grooves 802. The doped layer 114 can be formed by an implantation process, a plasma doping process, an epitaxial growth process, an atomic layer deposition process, or other suitable techniques. The deep grooves 802 are then filled with dielectric material. In some embodiments, a high K-value dielectric lining 113 is formed in the deep grooves 802 on top of the doped layer 114. The high K-value dielectric lining 113 can be formed by deposition techniques and can comprise aluminum oxide (A10), hafnium oxide (HfO), tantalum oxide (TaO), or other dielectric materials that have a dielectric constant greater than that of silicon oxide.The doped layer 114 and the high-K dielectric lining 113 line the side walls and lower surfaces of the deep trenches 802. In some embodiments, the doped layer 114 and the high-K dielectric lining 113 can extend across the back surface 124 of the substrate 102 between the deep trenches 802. A dielectric filler layer 112 is formed to fill the remainder of the deep trenches 802. In some embodiments, a planarization process is performed after the formation of the dielectric filler layer 112 to create a planar surface extending along an upper surface of the high-K dielectric lining 113 and the dielectric filler layer 112. In some embodiments, the high-K dielectric lining 113 and the dielectric filler layer 112 can be deposited using a physical vapor deposition technique.This results in the formation of the BDTI structure 111 in the substrate 102, which extends from the back side 124 to a position within the substrate 102. The BDTI structure 111 is located between and isolates the adjacent pixel regions 103a and 103b.

[0027] Although not shown in the figure, a variety of color filters (see, for example, the one in Fig. The color filter 116 shown in Figure 1 is subsequently formed over the back surface 124 of the substrate 102. In some embodiments, the plurality of color filters can be formed by forming a color filter layer and structuring the color filter layer. The color filter layer is formed from a material that transmits radiation (e.g., light) having a specific wavelength range while blocking light with wavelengths outside the specified range. Furthermore, in some embodiments, the color filter layer is planarized after formation. A plurality of microlenses (see, for example, the one shown in Figure 1) can be formed by structuring the color filter layer. Fig. The microlenses shown in Figure 118 can be formed over a plurality of color filters. In some embodiments, the plurality of microlenses can be formed by depositing a microlens material over the plurality of color filters (e.g., by a spin-deposition or deposition process). A microlens template having a curved upper surface is patterned over the microlens material. In some embodiments, the microlens template can comprise a photoresist material that is exposed using a distributed exposure dose (e.g., in a negative photoresist, the lower part of the curvature is more exposed and the upper part of the curvature is less exposed), developed, and cured to form a rounded shape. The plurality of microlenses is then formed by selectively etching the microlens material according to the microlens template.

[0028] Fig. Figure 12 shows a flow diagram of some embodiments of a method 1200 for forming a CMOS image sensor comprising a photodiode surrounded by a backside deep trench insulation (BDTI) structure.

[0029] Although the disclosed method 1200 is depicted and described here as a series of steps or events, it is understood that the depicted sequence of these steps and events is not to be interpreted as restrictive. For example, some steps may occur in different sequences and / or simultaneously with other steps or events than those depicted and / or described here. Furthermore, it may be that not all of the depicted steps are necessary to implement one or more aspects or embodiments of the present description. Additionally, one or more of the steps depicted here may be carried out in one or more separate steps and / or phases.

[0030] In 1202, a photodiode and a doped insulating layer are formed in the front face of the substrate. In some embodiments, part of the photodiode and / or the doped insulating layer can be formed by implanting dopants in the front face of the substrate. The doped insulating layer can be implanted as a deck implant to form a lateral section, followed by selective implantation to form a perpendicular section comprising a plurality of slits that extend further into the substrate than the lateral section. The lateral section can have a higher doping concentration than the perpendicular section. Fig. Figure 6 shows a cross-sectional view corresponding to some embodiments that correspond to step 1202.

[0031] At 1204, a floating diffusion well and a transfer gate are formed on the front side of the substrate. A BEOL metallization stack is formed above the transfer transistor on the front side of the substrate. Fig. Figure 7 shows a cross-sectional view corresponding to some embodiments that correspond to step 1204.

[0032] In 1206, a shallow trench isolation region can be formed on the front face of the substrate by selectively etching the substrate to create shallow trenches and subsequently forming a dielectric (e.g., an oxide) within these shallow trenches. The one or more isolation structures can be formed before or after the formation of the transfer gate and / or the floating diffusion trough. Fig. Figure 10 shows a cross-sectional view corresponding to some embodiments that correspond to step 1206.

[0033] At step 1208, the substrate is turned over for further processing. One side of the substrate is selectively etched to form deep trenches extending into the substrate. The deep trenches may have a centerline aligned with that of the vertical section of the doped insulating layer and / or the shallow trench insulating region. Fig. Figure 8 shows a cross-sectional view corresponding to some embodiments that correspond to step 1208.

[0034] At 1210, the deep trenches are filled to form backside deep trench insulation (BDTI) structures that are separated from the photodiode by the doped insulating layer. Fig.Figure 9 shows a cross-sectional view corresponding to some embodiments that correspond to step 1210. In 1212, a doped layer is formed along the sidewalls of the deep trenches. In 1214, a high K-value dielectric lining is formed in the deep trenches on top of the doped layer. In 1216, a dielectric filler layer is formed to fill the remainder of the deep trenches.

[0035] In 1218, color filters and microlenses are formed on the back side of the semiconductor substrate.

[0036] Therefore, the present disclosure relates to a CMOS image sensor comprising a photodiode surrounded by a backside deep trench insulation (BDTI) structure, and an associated formation method. The BDTI structure includes a doped layer, wherein the doped layer lines one sidewall face of a deep trench, and a dielectric layer that fills the remaining space of the deep trench. By forming the disclosed BDTI structure, which serves as a doped well, and an insulation structure, the implantation processes are simplified from a front-side position on the substrate, thus improving the exposure resolution, the full-well capacitance of the photodiode, and the pinning voltage, while reducing overexposure and overlap.

[0037] In some embodiments, the present disclosure relates to a CMOS image sensor. The image sensor comprises a substrate having a front and a back side opposite the front. A plurality of pixel regions are arranged in the substrate, each comprising a photodiode configured to convert radiation entering the substrate from the back side into an electrical signal. A backside deep trench insulation (BDTI) structure is arranged between adjacent pixel regions, extending from the back side of the substrate to a position within the substrate.The BDTI structure comprises a doped layer with a first doping type and a dielectric filler layer, wherein the doped layer lines a sidewall surface of a deep trench and the dielectric filler layer fills the remaining space of the deep trench, and wherein the doped layer and the dielectric filler layer of the BDTI structure extend upwards from the deep trench and are arranged laterally along the back side of the substrate.

[0038] In some alternative embodiments, the present disclosure relates to a CMOS image sensor. The image sensor comprises a substrate having a front and a back opposite the front. A photodiode is arranged in the substrate. A back-side deep trench insulation (BDTI) structure extends from the back of the substrate to positions in the substrate on opposite sides of the photodiode. A doped insulating layer with a first doping type comprises a lateral section and a perpendicular section in direct contact with each other, the lateral section extending over the photodiodes of the pixel regions along the front of the substrate.The BDTI structure comprises a doped layer with a first doping type and a dielectric filler layer, wherein the doped layer lines a sidewall surface of a deep trench and the dielectric filler layer fills the remaining space of the deep trench, and a plurality of metallic interconnection layers arranged in a dielectric interplane layer.

[0039] In other embodiments, the present disclosure relates to a method for forming an image sensor. The method comprises forming doped layers corresponding to photodiodes of a plurality of pixel regions from a front face of a substrate. The method further comprises forming a doped insulating layer from the front face of the substrate by implanting a dopant into the substrate through a plurality of implantation processes, wherein the doped insulating layer comprises a perpendicular section between adjacent pixel regions. The method further comprises inverting the substrate and etching from a rear face of the substrate to form a deep trench between adjacent pixel regions and extending into the substrate, wherein the rear face of the substrate faces the front face of the substrate.The process further includes filling the deep trench with a doped layer and a dielectric filler layer to form a backside deep trench insulation (BDTI) structure that is positioned between the adjacent pixel regions and separates photodiodes from the adjacent pixel regions.

Claims

[1] CMOS image sensor, comprising: a substrate (102) having a front (122) and a back (124) opposite the front (122); a plurality of pixel regions (103a, 103b) arranged in the substrate (102), each comprising a photodiode (104) configured to convert radiation entering the substrate (102) from the rear (124) into an electrical signal; and a BDTI structure (111) arranged in a deep trench (802) between adjacent pixel regions (103a, 103b) extending from the back (124) of the substrate (102) to a position in the substrate (102); wherein the BDTI structure (111) comprises a doped layer (114) having a first doping type and a dielectric filling layer (112), wherein the doped layer (114) lines a side wall surface of the deep trench (802) and the dielectric filling layer (112) fills the remaining space of the deep trench (802), and wherein the doped layer (114) and the dielectric filling layer (112) of the BDTI structure (111) extend upwards from the deep trench (802) and are arranged laterally along the rear side (124) of the substrate (102). [2] CMOS image sensor according to claim 1, further comprising: a doped insulating layer (110) of the first doping type comprising a lateral section (110a) and a perpendicular section (110b) in direct contact with each other, wherein the lateral section (110a) extends along the front side (122) of the substrate (102) and the perpendicular section (110b) extends between the adjacent pixel regions (103a, 103b) from the front side (122) of the substrate (102) to a position in the substrate (102). [3] CMOS image sensor according to claim 2, wherein the photodiode (104) comprises a first region (104a) with the first doping type and a second region (104b) with a second doping type which is different from the first doping type; and wherein the opposite sides of the first region (104a) touch the second region (104b) and the doped insulating layer (110). [4] CMOS image sensor according to claim 2 or 3, wherein the doped insulating layer (110) and the BDTI structure (111) meet in the substrate (102). [5] CMOS image sensor according to any one of the preceding claims 2 to 4, wherein a lower section of the BDTI structure (111) is arranged in a recessed upper surface of the vertical section (110b) of the doped insulating layer (110). [6] CMOS image sensor according to one of the preceding claims, wherein the BDTI structure (111) further comprises a high K-value dielectric lining (113) arranged between the doped layer (114) and the dielectric filler layer (112). [7] CMOS image sensor according to any of the preceding claims, wherein the doped layer (114) is a conformal layer and / or wherein the doped layer (114) is formed by an implantation process, a plasma doping process, an epitaxial growth process, or an atomic layer deposition process. [8] CMOS image sensor according to any of the preceding claims, further comprising: a floating diffusion tray (204) arranged between the adjacent pixel regions (103a, 103b) from the front (122) of the substrate (102) to a position in the substrate (102); and a transfer gate (202) which is arranged on the front side (122) of the substrate (102) in a position laterally between the photodiode (104) and the floating diffusion tray (204). [9] CMOS image sensor according to any of the preceding claims, further comprising: an STI structure (302, 504) that is arranged between the adjacent pixel regions (103a, 103b) from the front (122) of the substrate (102) to a position in the substrate (102); where the STI structure (302, 504) and the BDTI structure (111) are aligned perpendicularly. [10] CMOS image sensor according to claim 9, further comprising: a doped insulating layer (110) of the first doping type extending from the front (122) of the substrate (102) to a position in the substrate (102). [11] CMOS image sensor according to claim 10, wherein the doped insulating layer (110) separates the STI structure (302, 504) from the BDTI structure (111). [12] CMOS image sensor according to any one of the preceding claims 9 to 11, wherein the doped layer (114) of the BDTI structure (111) is located on a planar upper surface of the STI structure (302, 504), while the dielectric filler layer (112) of the BDTI structure (111) extends further downwards to a concave recess of the STI structure (302, 504). [13] CMOS image sensor according to any of the preceding claims, further comprising: a BEOL metallization stack arranged on the front (122) of the substrate (102) comprising a plurality of metallic interconnection layers arranged with one or more dielectric interlayer layers. [14] CMOS image sensor, comprising: a substrate (102) having a front (122) and a back (124) opposite the front (122); a photodiode (104) arranged in the substrate (102); a BDTI structure (111) extending from the back (124) of the substrate (102) to positions in the substrate (102) on opposite sides of the photodiode (104); and a doped insulating layer (110) with a first doping type and comprising a lateral section (110a) and a perpendicular section (110b) in direct contact with each other, wherein the lateral section (110a) extends over the photodiodes of the pixel regions (103a, 103b) along the front side (122) of the substrate (102); wherein the BDTI structure (111) comprises a doped layer (114) of the first doping type and a dielectric filling layer (112), wherein the doped layer (114) lines a side wall surface of a deep trench (802) and the dielectric filling layer (112) fills a remaining space of the deep trench (802). [15] CMOS image sensor according to claim 14, wherein the BDTI structure (111) is laterally attached to the side walls of the photodiode (104). [16] CMOS image sensor according to claim 14 or 15, wherein the perpendicular section (110b) of the doped insulating layer (110) in the substrate (102) meets the BDTI structure (111). [17] CMOS image sensor according to claim 16, further comprising: an STI structure (302, 504) extending from the front (122) of the substrate (102) to a position in the doped insulating layer (110); where the STI structure (302, 504) and the BDTI structure (111) are aligned perpendicularly. [18] CMOS image sensor according to any one of the preceding claims 14 to 17, wherein the BDTI structure (111) further comprises: a dielectric lining (113) with a high K-value, which is arranged between the doped layer (114) and the dielectric filler layer (112). [19] Method for forming an image sensor, comprising the following steps: Forming doping layers corresponding to the photodiodes of a plurality of pixel regions (103a, 103b) from a front side (122) of a substrate (102); Forming a doped insulating layer (110) from the front (122) of the substrate (102) by implanting a dopant into the substrate (102) via a plurality of implantation processes, wherein the doped insulating layer (110) comprises a perpendicular section (110b) between adjacent pixel regions (103a, 103b); Rotating the substrate (102) and etching from a back side (124) of the substrate (102) to form a deep trench (802) between adjacent pixel regions (103a, 103b) extending into the substrate (102), with the back side (124) of the substrate (102) facing the front side (122) of the substrate (102); and Filling the deep trench (802) with a doped layer (114) and a dielectric filler layer (112) to form a BDTI structure (111) that is positioned between the adjacent pixel regions (103a, 103b) and separates the photodiodes of the adjacent pixel regions (103a, 103b). [20] Method according to claim 19, further comprising, before turning over the substrate (102): forming a BEOL metallization stack on the front side (122) of the substrate (102), wherein the BEOL metallization stack comprises a plurality of metallic interconnection layers arranged in one or more dielectric interlayer layers.

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