Semiconductor device and method for its manufacture

Abstract

Semiconductor device comprising the following: first and second fin structures (212-1, 212-2) arranged on a substrate (102, 202) each extending parallel to an axis; a first gate structural element (260-1) that crosses the first fin structure (212-1) to lie over a central section (231) of the first fin structure (212-1); a second gate structural element (260-2) that crosses the second fin structure (212-2) to lie over a central section (231) of the second fin structure (212-2); a first spacer (236) comprising the following: a first section (236a, 246a) comprising two layers, each extending from the side walls of the first gate structural element (260-1) in opposite directions along the axis; and a second section (236b, 246b) comprising two layers, each extending from the side walls of the first section (236a, 246a) of the first spacer (236) in opposite directions along the axis; and a second spacer (246) comprising the following: a first section (236a, 246a) comprising two layers, each extending from the side walls of the second gate structural element (260-2) in opposite directions along the axis; and a second section (236b, 246b) comprising two layers, each extending from the side walls of the first section (236a, 246a) of the second spacer (246) in opposite directions of the axis, wherein the thickness of the first section (236a, 246a) of the second spacer (246) is thinner than the thickness of the first section (236a, 246a) of the first spacer (236).

Description

BACKGROUND

[0001] Integrated circuits (ICs) typically contain a large number of components, especially transistors. One type of transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET). MOSFET devices generally contain a gate structure on a semiconductor substrate. Both sides of the gate structure are doped to form source and drain regions. A channel is formed between the source and drain regions beneath the gate. Based on a bias voltage applied to the gate, electric current can either be allowed to flow through the channel or prevented from doing so.

[0002] In some cases, the channel can be configured as a fin-like structure (referred to as a "fin" in this text). Such a fin projects beyond a top surface of the substrate and is perpendicular to the gate structure and the fin formed on the substrate. Generally, a field-effect transistor that uses such a fin as a channel is called a fin-type field-effect transistor ("FinFET"). The FinFET typically includes a gate structure element that traverses a central portion of the projecting fin and a pair of source / drain structures along the fin, positioned laterally on the sides of the gate structure element.

[0003] Although the FinFET offers several advantages over a planar MOSFET when constructed in such a three-dimensional manner (for example, better gate controllability, higher scalability, etc.), the FinFET generally exhibits a higher parasitic capacitance coupled between the gate element and each of the drain / source elements compared to a planar MOSFET. This higher parasitic capacitance generally results from increased electromagnetic coupling induced between a sidewall of the gate element and each of the drain / source elements. Several performance characteristics of the FinFET are negatively impacted by this higher parasitic capacitance, such as a reduced cutoff frequency, which in turn can limit the FinFET's application range (for example, making it unsuitable for high-frequency (RF) applications).

[0004] Accordingly, conventional FinFETs and methods for their manufacture are not satisfactory in every respect.

[0005] Publication US 2015 / 0014788A1 discloses a semiconductor device comprising a gate on a substrate, a gate insulating layer along a side wall and bottom surface of the gate, and an L-shaped spacer structure on both side walls of the gate.

[0006] Publication US 2015 / 0236131A1 discloses a FinFET device structure comprising a first transistor formed on a fin structure. The first transistor includes a first gate dielectric layer conformally formed on the first fin structure and a first gate electrode formed on the first gate dielectric layer. The FinFET also includes an interlayer dielectric (ILD) structure formed adjacent to the first transistor. The first gate electrode is in direct contact with a sidewall of the ILD structure.

[0007] Publication US 2017 / 0069737A1 discloses a semiconductor device and a method for its fabrication. The method comprises forming a dummy gate pattern on an active fin and forming a spacer on at least one side of the dummy gate pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of this revelation are best understood with the help of the following detailed description, when read in conjunction with the accompanying figures. It should be noted that various features are not necessarily drawn to scale. Rather, the dimensions of the various features may be enlarged or reduced as desired to enhance clarity. Fig. 1A, Fig. 1B and Fig. Figures 1C together illustrate a flowchart of an embodiment of a method for forming a semiconductor device according to some embodiments. Fig. 2A, Fig. 3A, Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A and Fig. Figure 18A illustrates perspective views of an exemplary semiconductor device produced by the method of Fig. 1A-1C is manufactured during various manufacturing stages according to some embodiments. Fig. 2B, Fig. 3B, Fig. 4B, Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8B, Fig. Figures 9B / 9C, 10B, 11B / 11C / 11D, 12B / 12C / 12D, 13B / 13C, 14B / 14C, 15B / 15C, 16B / 16C, 17B / 17C and 18B / 18C illustrate corresponding cross-sectional views of the Fig. 2A, Fig. 3A, Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 104, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A and Fig. 18A according to some embodiments. Fig. Figure 19A illustrates a perspective view of an exemplary semiconductor device according to some embodiments. Fig. Figures 19B / 19C illustrate corresponding cross-sectional views of Fig. 18A according to some embodiments. DETAILED DESCRIPTION OF EXAMPLES OF EXECUTION

[0009] Improved structures and a method relating to the problems described above are provided according to independent claims 1, 9, and 17. The following disclosure describes various exemplary embodiments for implementing different features of the subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact.Furthermore, this disclosure may repeat reference numbers and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not automatically establish a relationship between the various embodiments and / or configurations discussed.

[0010] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or structural element to one or more other elements or structural elements, as illustrated in the figures. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also other orientations of the device during use or operation. The device may also be oriented differently (rotated 90 degrees or otherwise), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0011] The present disclosure provides various embodiments of a semiconductor device comprising a spacer formed from multiple dielectric layers, as well as a method for its fabrication. For example, the present disclosure provides various embodiments of a fin field-effect transistor (FinFET) comprising a multilayer spacer extending along the respective sidewalls of the gate structure element of the FinFET, and methods for fabricating the FinFET. By forming such a multilayer spacer located between the gate structure element and each of the respective source / drain structure elements of the FinFET, a corresponding electromagnetic coupling (the parasitic capacitance) between the gate and the source / drain structure element can be significantly suppressed, for example, due to the increased distance between them.Accordingly, the cutoff frequency of the disclosed FinFET can be advantageously improved. Furthermore, the present disclosure provides, in some embodiments, several embodiments for the simultaneous formation of multiple FinFETs, a first subset of which each have a single-layer spacer or a relatively thin multilayer spacer, and a second subset of which each have a multilayer spacer. Therefore, the first subset of FinFETs, which is less sensitive to parasitic capacitance, may be suitable for use in logic applications (for example, logic gates), and the second subset of FinFETs, which is more sensitive to parasitic capacitance, may be suitable for use in high-frequency (HF) applications (for example, HF transistors).

[0012] Fig. 1A, Fig. 1B and Fig. Figures 1C and 1C together illustrate a flowchart of a method 100 for forming a semiconductor device according to one or more embodiments of the present disclosure. It should be noted that method 100 is merely an example and is not intended to limit the present disclosure. In some embodiments, the semiconductor device includes two FinFETs or at least respective sections thereof. For the purposes of the present disclosure, FinFET means any fin-based multi-gate transistor. It should be noted that the method of Fig. 1A-1C does not produce a complete FinFET. A complete FinFET can be fabricated using complementary metal-oxide-semiconductor (CMOS) technology processing. Accordingly, it is understood that additional operations before, during, and after process 100 of the Fig. 1A-1C can be performed and that some other operations may only be briefly described in the present text.

[0013] We turn first Fig. 1A. The process 100 begins with operation 102, in which a semiconductor substrate is provided. The process 100 proceeds to operation 104, in which several fins are formed. The process 100 proceeds to operation 106, in which an insulating dielectric layer is formed over the several fins. The process 100 proceeds to operation 108, in which the respective upper boundaries of the several fins are exposed. The process 100 proceeds to operation 110, in which the respective upper fins are exposed. The process 100 proceeds to operation 112, in which an oxide layer is formed so that it lies over each of the upper fins.

[0014] The next step in the process is 100. Fig. Procedure 100 progresses to Operation 114, in which several dummy stacks are formed to lie over respective central sections of the upper fins. Procedure 100 progresses to Operation 116, in which a first spacer dielectric layer is formed to lie over each of the several dummy stacks. Procedure 100 progresses to Operation 118, in which a logic region and a radio frequency (RF) region are each defined over the semiconductor region. Procedure 100 progresses to Operation 120, in which the one or more first spacer dielectric layers in the logic region are each etched to form a first section of a first spacer extending along sidewalls of each dummy stack in the logic region.After the etching process, in some embodiments the first portion of the first spacer may have a substantially thin thickness in the logic region, and in some other embodiments the first spacer dielectric layers in the logic region may be completely removed (i.e., there is no first portion of the first spacer). For the sake of consistency, the following discussion of Method 100 continues with the embodiments in which the first portion of the first spacer remains. Method 100 proceeds to Operation 122, in which a second spacer dielectric layer is formed to lie over each of the multiple dummy stacks in the logic and RF regions.

[0015] We now turn Fig. 1C, where Procedure 100 progresses to Operation 124, in which one or more second spacer dielectric layers in the logic region are etched to form a second section of the first spacer, and simultaneously the first and second spacer dielectric layers in the RF region are etched to form a second spacer extending along sidewalls of each dummy stack in the RF region. Procedure 100 progresses to Operation 126, in which respective source / drain structural elements are formed on sides of each of the multiple dummy stacks in the logic and RF regions. Procedure 100 progresses to Operation 128, in which an intermediate layer dielectric (ILD) or intermediate metal dielectric (IMD) layer is formed over the respective source / drain structural elements.The process 100 progresses to operation 130, in which the multiple dummy stacks are removed to form several cavities. The process progresses to operation 132, in which each of the multiple cavities is filled with a respective gate structural element. The process progresses to operation 134, in which respective contact connectors are formed to couple the gate and source / drain structural elements.

[0016] In some embodiments, operations of the method 100 can be performed with perspective views of a semiconductor device 200 at various manufacturing stages, as in the Fig. 2A, Fig. 3A, Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A and 18A respectively, and corresponding cross-sectional views, as shown in the Fig. 2B, Fig. 3B, Fig. 4B, Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B / 9C, 10B, 11B / 11C / 11D, 12B / 12C / 12D, 13B / 13C, 14B / 14C, 15B / 15C, 16B / 16C, 17B / 17C and 18B / 18C are shown and linked. In some embodiments, the semiconductor device 200 can contain at least two FinFETs. The semiconductor device 200 can be integrated into a microprocessor, a memory cell and / or other integrated circuit (IC). Furthermore, the Fig. Figures 2A to 18C have been simplified to facilitate understanding of the concepts presented in this disclosure. For example, while the figures illustrate semiconductor device 200, it is understood that the IC may also include a number of other devices, including resistors, capacitors, inductors, fuses, etc., as detailed in the Fig. 2A to 18C are not shown for the sake of clarity in the illustration.

[0017] According to Operation 102 of Fig. 1A, is Fig. 2A a perspective view of the semiconductor device 200 containing a substrate 202, at one of the various manufacturing stages according to some embodiments, and Fig. 2B is a cross-sectional view of the semiconductor device 200 along line aa (the X-axis) of Fig. 2A. As shown, the substrate 202 is covered by a contact pad layer 204, a mask layer 206, and a photosensitive layer 208, which is structured with one or more openings 210. The photosensitive layer 208 is structured to form one or more fins of the at least two FinFETs contained in the semiconductor device 200, which is discussed in the following operations.

[0018] In some embodiments, the substrate 202 comprises a crystalline silicon substrate (for example, a wafer). In some alternative embodiments, the substrate 202 can be made from another suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon-germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Furthermore, the substrate 202 can include an epitaxial layer (epi-layer), can be stretched for the purpose of increasing performance, and / or can incorporate a silicon-on-insulator (SOI) structure.

[0019] In some embodiments, the contact pad layer 204 can be a thin film comprising silicon oxide, formed, for example, by a thermal oxidation process. The contact pad layer 204 can act as an adhesion layer between the semiconductor substrate 202 and the mask layer 206. The contact pad layer 204 can also act as an etch stop layer during the etching of the mask layer 206. In some embodiments, the mask layer 206 is formed from silicon nitride, for example, using low-pressure galvanic vapor deposition (LPCVD) or plasma-enhanced galvanic vapor deposition (PECVD). The mask layer 206 is used as a hard mask during subsequent photolithography processes. The photosensitive layer 208 is formed on the mask layer 206 and then patterned, thereby forming the openings 210 in the photosensitive layer 208.

[0020] According to Operation 104 of Fig. 1A, is Fig. 3 A a perspective view of the semiconductor device 200, which contains several fins 212-1 and 212-2 at one of the various manufacturing stages, according to some embodiments, and Fig. Figure 3B is a cross-sectional view of the semiconductor device 200 along line aa (the X-axis) of Fig. 3 A. As shown, the fins 212-1 and 212-2 are separated from each other by a central groove 213. It should be noted that although only two fins 212-1 and 212-2 are shown in the illustrated embodiments of the Fig. 3A and Fig. Figure 3B (and the following figures) shows that any desired number of fins can be placed on the semiconductor substrate 202 using the photosensitive layer 208 ( Fig. 2A and Fig. 2B) can be formed with a corresponding structure. Thus, the left and right trenches 213 can be incorporated into the Fig. 3A and Fig. 3B is coupled between one of the fins shown, 212-1 and 212-2, and another fin not shown. For the sake of clarity, fins 212-1 and 212-2 will be referred to as "left fin 212-1" and "right fin 212-2" in the following discussions.

[0021] In some embodiments, the fins 212 are formed by at least some of the following processes. The mask layer 206 and the contact pad layer 204 are etched through openings 210 ( Fig. 2A and Fig. 2B) to expose the underlying semiconductor substrate 202. Using the remaining contact pad layer 204 and the mask layer 206, as shown in the Fig. 3A and Fig. As shown in Figure 3B, the exposed semiconductor substrate 202 is then etched to form the grooves 213, such that a main surface 203 of the semiconductor substrate 202 is exposed. Sections of the semiconductor substrate 202 arranged between the grooves 213 are thus formed as the fins 212. The fins 212 each extend upwards from the main surface 203. The grooves 213 can be strips (in a top view of the semiconductor device 200) that run parallel to each other and are spaced apart. After the fins 212 have been formed, the photosensitive layer 208 (in the Fig. 3A and Fig. (3B omitted for clarity) removed. Subsequently, a cleaning process can be performed to remove any native oxide of the semiconductor substrate 202. The cleaning can be carried out using dilute hydrogen fluoride (DHF) acid or the like.

[0022] According to Operation 106 of Fig. 1A, is Fig. 4A a perspective view of the semiconductor device 200, which includes an insulating dielectric material 214 formed over the substrate 202, the left and right fins 212-1 and 212-2, the contact pad layer 204 and the mask layer 206, at one of the various manufacturing stages according to some embodiments, and Fig. 4B is a cross-sectional view of the semiconductor device 200 along line aa (the X-axis) of Fig. 4A. As shown, the insulating dielectric material 214 is formed over the entire semiconductor device 200 (for example, over the left and right fins 212-1 and 212-2) such that the entire grooves 213 are filled by the insulating dielectric material 214.

[0023] In one embodiment, the insulating dielectric material 214 can be deposited over the substrate 202 using a high-density plasma (HDP) CVD process with reaction precursors, for example, silane (SiH4) and oxygen (O2). In another embodiment, the insulating dielectric material 214 can be deposited over the substrate 202 using a subatmospheric ACVD (SACVD) process or a high-aspect-ratio process (HARP), wherein the process gases used in such processes may include tetraethyl orthosilicate (TEOS) and ozone (O3). In a further embodiment, the insulating dielectric material 214 can be deposited over the substrate 202 using a spin-on dielectric (SOD) process, such as hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), or the like.

[0024] According to Operation 108 of Fig. 1A, is Fig. 5 A a perspective view of the semiconductor device 200, in which the respective uppermost limits 215-1 and 215-2 of the left and right fins 212-1 and 21-2 are exposed at one of the various manufacturing stages, according to some embodiments, and Fig. 5B is a cross-sectional view of the semiconductor device 200 along line aa (the X-axis) of Fig. 5 A. In some embodiments, the upper limits 215-1 and 215-2 are formed by performing a polishing process (for example, a chemical-mechanical polishing process) on the insulating dielectric material 214 ( Fig. 4A and Fig. 4B) exposed until the mask layer 206 is again exposed. The mask layer 206 and the contact pad layer 204 are then removed to expose the top boundaries 215-1 and 215-2. In some embodiments, if the mask layer 206 is formed of silicon nitride, the mask layer 206 can be removed using a wet process with hot phosphoric acid (H3PO4), and if the contact pad layer 204 is formed of silicon oxide, the contact pad layer 204 can be removed using dilute hydrofluoric acid (HF). In some alternative embodiments, the removal of the mask layer 206 and the contact pad layer 204 can be carried out after a recessing process performed on the insulating dielectric material 214, as described in the Fig. 6A and Fig. 6B is discussed below.

[0025] According to Operation 110 of Fig. 1A, is Fig. 6A a perspective view of the semiconductor device 200, in which the respective upper fins 218-1 and 218-2 of the left and right fins 212-1 and 212-2 are exposed, at one of the various manufacturing stages according to some embodiments, and Fig. Figure 6B is a cross-sectional view of the semiconductor device 200 along line aa (the X-axis) of Fig. 6A. As in the Fig. 6A and Fig. As shown in Figure 6B, an insulating structural element 220 is formed between the respective lower sections of the left and right fins 212-1 and 212-2, such that it exposes the respective upper fins 218-1 and 218-2. Similarly, the upper fin 218-1 of the left fin 212-1 and the upper fin 218-2 of the right fin 212-2 are referred to in the following discussion as "left upper fin 218-1" and "right upper fin 218-2". In some embodiments, after the left and right upper fins 218-1 and 218-2 have been exposed, the respective side walls 219-1 and 219-2 of the left and right upper fins 218-1 and 218-2 are further exposed.

[0026] In some embodiments, the insulating structural element 220 can be formed by performing at least one etching process to recess an upper section of the insulating dielectric material 214 ( Fig. 5A and Fig. 5B). In one embodiment, the etching process may involve performing a wet etching process, such as immersing the substrate 202 in a hydrofluoric acid (HF) solution to remove the upper portion of the insulating dielectric material 214 until the left and right upper fins 218-1 and 218-2 are exposed. In another embodiment, the etching process may involve performing a dry etching process, such as using the etching gases fluoroform (CHF3) and / or boron trifluoride (BF3) to remove the upper portion of the insulating dielectric material 214 until the left and right upper fins 218-1 and 218-2 are exposed.

[0027] According to Operation 112 of Fig. 1A, is Fig. 7A a perspective view of the semiconductor device 200, which contains an oxide layer 222 over each of the left and right upper fins 218-1 and 218-2, at one of the various manufacturing stages according to some embodiments, and Fig. Figure 7B is a cross-sectional view of the semiconductor device 200 along line aa (the X-axis) of Fig. 7A. What's next in Fig. As shown in Figure 7B, the oxide layer 222 is formed such that it extends along the side wall 219-1 / 219-2 and lies above the upper boundary 215-1 / 215-2 of each of the left and right upper fins 218-1 and 218-2. In some embodiments, the oxide layer 222 can be formed using a thermal oxidation process, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or the like. In embodiments in which the left and right upper fins 218-1 and 218-2 are formed from silicon, the oxide layer 222 can contain silicon oxide.

[0028] According to Operation 114 of Fig. 1B, is Fig. 8A a perspective view of the semiconductor device 200, which contains several dummy stacks 230-1 and 230-2 formed at one of the various manufacturing stages, according to some embodiments, and Fig. Figure 8B is a cross-sectional view of the semiconductor device 200 along line aa (the X-axis) of Fig. 8A. In some embodiments, the dummy stacks 230-1 and 230-2 are spatially separated from each other. More precisely, dummy stack 230-1 lies above a central section 231-1 of the left upper fin 218-1, with a central section of the oxide layer 222 between them, which is referred to in this text as the “left dummy stack 230-1”, and dummy stack 230-2 lies above a central section 231-2 of the right upper fin 218-2, with a central section of the oxide layer 222 between them, which is referred to in this text as the “right dummy stack 230-1”.

[0029] As mentioned above, the semiconductor device 200 contains at least two FinFETs. According to some embodiments, the central section 231-1 of the left upper fin 218-1, above which the left dummy stack 230-1 lies, can serve as a respective conduction channel for one of the at least two FinFETs; and the central section 231-2 of the right upper fin 218-2, above which the right dummy stack 230-2 lies, can serve as a respective conduction channel for the other of the at least two FinFETs, as will be discussed below. Furthermore, the sections on the respective sides of the superimposed central section of the left and right upper fins 218-1 and 218-2 (for example, side sections 233-1 and 233-2, as shown in Figure 1) can serve as a respective conduction channel for the other of the at least two FinFETs. Fig. 8A shown), above which only the oxide layer 222 in Fig. 8A lies, is partially covered by spacers and partially removed to be formed as respective source / drain structural elements in the following processing steps, which is also discussed below.

[0030] In some embodiments, the left and right dummy stacks 230-1 and 230-2 can each comprise a polysilicon material. Furthermore, each of the left and right dummy stacks 230-1 and 230-2 can be a polysilicon material doped with a uniform or non-uniform doping concentration. The left and right dummy stacks 230-1 and 230-2 can be formed by performing at least some of the following processes: using a suitable process, such as LD, CVD, physical vapor deposition (PVD), plating, or combinations thereof, to deposit the polysilicon material described above over the left and right upper fins 218-1 and 218-2 (with the respective oxide layer 222 between them); and use at least one wet and / or dry etching process to define the left and right dummy stacks 230-1 and 230-2, respectively.

[0031] According to Operation 116 of Fig. 1B, is Fig. 9A a perspective view of the semiconductor device 200, which includes a first spacer dielectric layer 234 formed at one of the various manufacturing stages, according to some embodiments, and Fig. 9B and Fig. Figure 9C shows cross-sectional views of the semiconductor device 200 along line bb and line cc (the Y-axis) respectively. Fig. 9A. In some embodiments, the first spacer dielectric layer 234 is essentially thin and conformal, such that the first spacer dielectric layer 234 can follow the respective geometric profiles of the left and right dummy stacks 230-1 and 230-2, as shown in the cross-sectional views of the Fig. 9B and Fig. 9C is easier to see.

[0032] In Fig. 9B the first spacer dielectric layer 234 lies above a top boundary 235a of the left dummy stack 230-1 and extends along side walls 235b of the left dummy stack 230-1. As above in Fig. As addressed in 8 A, the central section 231-1 of the left upper fin 218-1 is superimposed by the left dummy stack 230-1, with the oxide layer 222 in between, and the side sections 233-1 (on the sides of the central section 231-1, extending parallel to the Y-axis) are only superimposed by the oxide layer 222. In some embodiments, the first spacer dielectric layer 234 can also lie over the side sections 233-1, with the oxide layer 222 in between. Similarly, in Fig. 9C The integrally formed first spacer dielectric layer 234 lies over a top boundary 237a of the right dummy stack 230-2 and extends along side walls 237b of the right dummy stack 230-2. As mentioned above, the central section 233-1 of the right upper fin 218-2 is superimposed on the right dummy stack 230-2, with the oxide layer 222 in between, and the side sections 233-2 (on the sides of the central section 233-1, extending parallel to the Y-axis) are only superimposed on the oxide layer 222. In some embodiments, the first spacer dielectric layer 234 may also lie over the side sections 233-2, with the oxide layer 222 in between.

[0033] In some embodiments, the first spacer dielectric layer 234 may contain silicon oxide (SiO₂), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or another suitable material. In some embodiments, the first spacer dielectric layer 234 may be formed by depositing at least one of the above-mentioned materials over the left and right dummy stacks 230-1 and 230-2 (and the oxide layer 222) using CVD, PVD, ALD, or other suitable techniques.

[0034] According to Operation 118 of Fig. 1B, is Fig. 10A a perspective view of the semiconductor device 200, in which respective logic and RF regions above the substrate 202 are identified at one of the various manufacturing stages, according to some embodiments, and Fig. 10B is a cross-sectional view of the semiconductor device 200 along line aa (the X-axis) of Fig. 10A. As mentioned above, the semiconductor device 200 contains at least two FinFETs, one of which is configured to be used as a logic gate device, and the other of which is configured to be used as an RF transistor. In this respect, the substrate 202 is divided into the logic region, where the logic gate device is to be formed, and the RF region, where the RF transistor is to be formed. In the illustrated embodiments of the Fig. 10A and Fig. In Figure 10B (and the following figures), the left part of the substrate 202, containing the left fin 212-1, the left upper fin 218-1, and the left dummy stack 230-1, is defined as the logic region; and the right part of the substrate 202, containing the right fin 212-2, the right upper fin 218-2, and the right dummy stack 230-2, is defined as the RF region. Although the logic and RF regions in the illustrated embodiments of the Fig. 10A and Fig. 10B (and the following figures) are spatially separated by the insulation structure element 220 (for example, a shallow trench insulation (STI) structure element), it should be noted that any number of different structural elements can be formed between the logic and RF regions without leaving the scope of this disclosure.

[0035] According to operation 120 of Fig. 1B, is Fig. 11A a perspective view of the semiconductor device 200, which includes a first section 236a of a first spacer 236 formed at one of the various manufacturing stages, according to some embodiments; Fig. Figure 11B is a cross-sectional view of the semiconductor device 200 along line aa (the X-axis) of Fig. 11A; Fig. Figure 11C is a cross-sectional view of the semiconductor device 200 along line bb (the Y-axis) of Fig. 11A; and Fig. Figure 11D is a cross-sectional view of the semiconductor device 200 along the line cc (the Y-axis) of Fig. 11A.

[0036] In some embodiments, the first section 236a of the first spacer 236 is formed by performing at least one dry and / or wet etching process on the first spacer dielectric layer 234 in the logic region, while the RF region is covered by a structureable layer 240 (for example, a hard mask layer, a photoresist layer, etc.), as shown in the Fig. 11A and Fig. Figure 1B illustrates this. Therefore, the first section 236a of the first spacer 236, which is a remaining section of the first spacer dielectric layer 234 after at least one dry and / or wet etching process, extends along the side wall 235b of the left dummy stack 230-1 in the logic region (as shown in the Fig. 11A and Fig. 11C illustrated), while in the HF region (as in Fig. (Figure 11D illustrates) the first spacer dielectric layer 234 remains intact (i.e., it continues to extend above the top boundary 237a and along the side walls 237b). Furthermore, in some embodiments, after the at least one dry and / or wet etching process, the first section 236a of the first spacer 236 may have a thickness that is substantially thinner than the original thickness of the first spacer dielectric layer 234 or substantially close to zero (i.e., such a first section 236a of the first spacer 236 is absent), as discussed above. For the sake of consistency, the following discussions mainly describe the embodiments with the presence of the first section 236a of the first spacer 236. In some embodiments, the structurable layer 240 is removed after the first section 236a of the first spacer 236 has been formed.

[0037] We turn again Fig. 11C. In some embodiments, the first section 236a of the first spacer 236 has two layers, each extending along the side walls 235b of the left dummy stack 230-1 in the logic region, these two layers each extending further from the side walls 235b in opposite directions along the Y-axis (i.e., parallel to the left fin 212-1 and the left upper fin 218-1). That is, one of the two layers extends to the left along the Y-direction, while the other of the two layers extends to the right along the -Y-direction. Accordingly, the two layers of the first section 236a of the first spacer 236 each lie over a portion of the side sections 233-1 (with the oxide layer 222 between them) that are located immediately adjacent to the central section 231-1, as shown.Furthermore, due to at least one dry and / or wet etching process, each of the two layers may extend unevenly laterally (for example, a rounded upper edge). For example, a respective upper section of each layer extends laterally less farther from the side wall 235b (at a distance 236a-1), and a respective lower section of this layer extends laterally farther from the side wall 235b (at a distance 236a-2), where the distance 236a-2 is greater than the distance 236a-1.

[0038] According to Operation 122 of Fig. 1B, is Fig. 12A a perspective view of the semiconductor device 200, which includes a second spacer dielectric layer 244 formed at one of the various manufacturing stages, according to some embodiments; Fig. Figure 12B is a cross-sectional view of the semiconductor device 200 along line aa (the X-axis) of Fig. 12A; Fig. Figure 12C is a cross-sectional view of the semiconductor device 200 along line bb (the Y-axis) of Fig. 12A; and Fig. 12D is a cross-sectional view of the semiconductor device 200 along the line cc (the Y-axis) of Fig. 12A. As in the Fig. 12A and Fig. As shown in Figure 12B, the second spacer dielectric layer 244 is configured to lie over both the logic and RF regions. More precisely, according to some embodiments, the second spacer dielectric layer 244 is essentially thin and conformal, such that the second spacer dielectric layer 244 can follow the respective geometric profiles of the left and right dummy stacks 230-1 (with the first section 236a of the first spacer 236 between them) and 230-2 (with the first and second spacer dielectric layers 234 and 244 together between them), as shown in the cross-sectional view of the Fig. 12C and Fig. 12D is easier to see.

[0039] In Fig. In Figure 12C, where the logic region is shown, the second spacer dielectric layer 244, which is integrally formed, lies over the top boundary 235a of the left dummy stack 230-1 and extends along side walls of the first section 236a of the first spacer 236. Furthermore, the second spacer dielectric layer 244 can lie over part of the side sections 233-1, with the oxide layer 222 in between. Fig. In Figure 12D, where the RF region is shown, the second spacer dielectric layer 244, which is formed integrally over the first spacer dielectric layer 234, extends along the top boundary 237a and the respective side walls 237b of the right dummy stack 230-2. Furthermore, the second spacer dielectric layer 244 can lie over part of the side sections 233-2, with the oxide layer 222 in between. As mentioned above, in some embodiments the first section 236a of the first spacer 236 is significantly thinner than the original thickness of the first spacer dielectric layer 234. Thus, it is understood that a lateral distance 244-1 in the logic region, by which the second spacer dielectric layer 244 extends from the side wall 235b, is significantly shorter than a lateral distance 244-2 in the RF region, by which the second spacer dielectric layer 244 extends from the side wall 237b.

[0040] In some embodiments, the second spacer dielectric layer 244 can contain silicon oxide (SiO₂), silicon nitride (SiN), silicon oxynitride (SiON₂), silicon oxycarbonitride (SiOCN), or another suitable material. In some embodiments, the second spacer dielectric layer 244 can be formed using CVD, PVD, ALD, or other suitable techniques to deposit at least one of the above-mentioned materials over the left dummy stack 230-1, wherein the first section 236a of the first spacer 236 is arranged on the sides of the left dummy stack 230-1, and the right dummy stack 230-2 with the first spacer dielectric layer 234 is arranged between them.

[0041] According to Operation 124 of Fig. 1C, is Fig. 13A a perspective view of the semiconductor device 200, which includes a second section 236b of the first spacer 236 in the logic region and a second spacer 246 in the RF region, which are formed at one of the various manufacturing stages, according to some embodiments; Fig. 13B is a cross-sectional view of the semiconductor device 200 along line bb (the Y-axis) of Fig. 13 A; and Fig. Figure 13C is a cross-sectional view of the semiconductor device 200 along the line cc (the Y-axis) of Fig. 13A. As in each case in the Fig. 13B and Fig. As shown in Figure 13C, in the logic region, the second section 236b of the first spacer 236 extends along the side wall of the first section 236a; and in the RF region, the second spacer 246 contains respective first and second sections 246a and 246b, each of which extends along the side wall 237b of the right dummy stack 230-2. In some embodiments, the first and second sections 246a and 246b are remaining sections of the first and second spacer dielectric layers 234 and 244, respectively, which will be discussed below.

[0042] In some embodiments, the first spacer 236 (including the second section 236b) and the second spacer 246 are formed by simultaneously performing at least one dry and / or wet etching process on the second spacer dielectric layer 244 in the logic region and on the first and second spacer dielectric layers 234 and 244 in the RF region. More precisely, in the logic region, the first section 236a of the first spacer 236 can remain essentially intact during the simultaneous etching process, which is primarily performed on the second spacer dielectric layer 244. Therefore, the thickness of the first section 236a of the first spacer 236 can remain essentially unchanged.In the HF region, the first section 246a of the second spacer 246 can remain essentially intact during the simultaneous etching process, which is mainly carried out on the second spacer dielectric layer 244, such that the thickness of the first section 246a of the second spacer 246 can remain essentially unchanged (i.e. the original thickness of the first spacer dielectric layer 234).

[0043] Furthermore, as above with reference to the Fig. 12C and Fig. As described in Figure 12D, the lateral distance 244-1 in the logic region is significantly shorter than the lateral distance 244-2 because the first section 236a of the first spacer 236 is significantly thinner than the original thickness of the first spacer dielectric layer 234. Accordingly, after at least one simultaneous dry and / or wet etching process in which the respective thicknesses of the first sections 236a of the first spacer 236 and the second spacer 246 remain substantially unchanged, a lateral distance 248-1 in the logic region, by which the first spacer 236 extends from the side wall 235b, is significantly shorter than a lateral distance 248-2 in the RF region, by which the second spacer 246 extends from the side wall 237b.

[0044] In Fig. In some embodiments, the second section 236b of the first spacer 236 has two layers, each extending along the side walls of the first section 236a, with each of these two layers extending further from the side walls in opposite directions along the Y-axis (i.e., parallel to the left fin 212-1 and the left upper fin 218-1). Accordingly, the two layers of the second section 236b of the first spacer 236 each lie over a portion of the side sections 233-1 (with the oxide layer 222 in between) that are located immediately adjacent to the portion of the left upper fin 218-1 over which the first section 236a lies, as shown. Fig. 13C the first and second sections 246a and 246b of the second spacer 246 each have two layers extending along the side walls 237b of the right dummy stack 230-2, with the two layers of the first section 246a and the two layers of the second section 246b each extending further from the side walls 237b in opposite directions of the Y-axis (i.e. parallel to the right fin 212-2 and the right upper fin 218-2).Accordingly, the two layers of the first section 246a of the second spacer 246 each lie over a part of the side sections 233-2 (with the oxide layer 222 in between) which are located immediately next to the central section 231-2 of the right upper fin 218-2, and the two layers of the second section 246b of the second spacer 246 each lie over a part of the side sections 233-2 (with the oxide layer 222 in between) which are located immediately next to the section of the right upper fin 218-2 over which the first section 246a lies, as shown.

[0045] According to Operation 126 of Fig. 1C, is Fig. 14A a perspective view of the semiconductor device 200, which includes source / drain structural elements 250 formed in the logic region and source / drain structural elements 252 formed in the RF region, at one of the various manufacturing stages according to some embodiments; Fig. Figure 14B is a cross-sectional view of the semiconductor device 200 along line bb (the Y-axis) of Fig. 14A; and Fig. 14C is a cross-sectional view of the semiconductor device 200 along the line cc (the Y-axis) of Fig. 14A. In some embodiments, which brings us back to Fig. Turning to 13B (in the logic region), a portion of the side sections 233-1 of the left upper fin 218-1, and the overlying oxide layer 222 not covered by the left dummy stack 230-1 and the first spacer 236, are each removed (for example, etched) before the source / drain structural elements 250 are formed. Similarly, in some embodiments, which we will discuss again Fig. Turning towards 13C (in the HF region), a portion of the side sections 233-2 of the right upper fin 218-2, and the overlying oxide layer 222, which are not covered by the right dummy stack 230-2 and the second spacer 246, are each removed (for example, etched) before the source / drain structural elements 252 are formed. For the sake of clarity, these removed sections are shown in Fig. 14A each shown in dashed lines.

[0046] To form the source / drain structural element 250 in the logic region, in some embodiments, after removing the sections described above, recesses 253 are made ( Fig. 14A) on the sides of the left dummy stack 230-1 and the first spacer 236. In some embodiments, such a recess 237 can be extended downwards below a top boundary 220' of the insulating structure element 220. Subsequently, the source / drain structure elements 250 are grown epitaxially from the left fin 212-1 using a low-pressure chemical vapor deposition (LPCVD) process and / or a metal-organic chemical vapor deposition (MOCVD) process. The formation of the source / drain structure elements 252 in the RF region is carried out in a similar manner, so the discussions are not repeated here. Accordingly, the source / drain structure elements 250 are each arranged immediately adjacent to the remaining sections 233-1a of the side sections 233-1 located below the first spacer 236, as in Fig. 14B illustrated; and the source / drain structural elements 252 are each arranged immediately adjacent to the remaining sections 233-2a of the side sections 233-2 located below the second spacer 246, as shown in Fig. 14C illustrated.

[0047] According to Operation 128 of Fig. 1C, is Fig. 15A a perspective view of the semiconductor device 200 containing an interlayer dielectric (ILD) or intermetal dielectric (IMD) layer 256 formed at one of the various manufacturing stages according to some embodiments; Fig. 15B is a cross-sectional view of the semiconductor device 200 along line bb (the Y-axis) of Fig. 15A; and Fig. 15C is a cross-sectional view of the semiconductor device 200 along the line cc (the Y-axis) of Fig. 15 A. As shown, the ILD or IMD layer 256 is formed over the source / drain structural elements 250 in the logic region and the source / drain structural elements 252 in the RF region such that it protects the formed source / drain structural elements 250 / 252 in at least some of the subsequent processes. In some embodiments, the ILD or IMD layer 256 can also fill a space between the left and right dummy stacks 230-1 and 230-2, as shown in Fig. 15A shown.

[0048] In some embodiments, the ILD or IMD layer 256 may contain a dielectric material selected from at least one of the following: silicon dioxide, a material with a low dielectric constant (low k-value), or a combination thereof. The low k-value material may include: fluorinated fused silica (FSG), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), carbon-doped silicon dioxide (SiOxCy), Black Diamond ® (Applied Materials from Santa Clara, California), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutene), SiLK (Dow Chemical, Midland, Michigan), polyimide and / or other dielectric materials with low k-values ​​developed in the future.

[0049] According to Operation 130 of Fig. 1C, is Fig. 16A a perspective view of the semiconductor device 200, which contains a vacancy 258-1 formed in the logic region and a vacancy 258-2 formed in the RF region, at one of the various manufacturing stages according to some embodiments; Fig. 16B is a cross-sectional view of the semiconductor device 200 along line bb (the Y-axis) of Fig. 16A; and Fig. Figure 16C is a cross-sectional view of the semiconductor device 200 along the line cc (the Y-axis) of Fig. 16A.

[0050] In some embodiments, the vacancy 258-1 is created by removing (for example, by etching) the left dummy stack 230-1 ( Fig. 15B), and each or simultaneously the vacancy 258-2 is created by removing (for example, etching) the right dummy stack 230-2 ( Fig. 15C). During the removal of the left and right dummy stacks 230-1 and 230-2, the first and second spacers 236 and 246 can remain intact. In some embodiments, either a wet or a dry etching process can be used to remove the left and right dummy stacks 230-1 and 230-2. The wet etching process involves the use of dilute hydrofluoric acid (DHF) and / or an amine derivative etchant (for example, NH4OH, NH3(CH3)OH, tetramethylammonium hydroxide (TMAH), etc.); and the dry etching process involves the use of a plasma of reactive gas selected from: fluorocarbons, oxygen, chlorine, boron trichloride, nitrogen, argon, helium, or a combination thereof.After removing the left and right dummy stacks 230-1 and 230-2, the sections of the oxide layer 220, which each lie above the central section 231-1 of the left upper fin 218-1 and the central section 231-2 of the right upper fin 218-2, are exposed, as shown in the . Fig. 16B and Fig. 16C shown. In some other embodiments, these sections of the oxide layer 220 can optionally be removed, simultaneously with, or after, the removal of the left and right dummy stacks 230-1 and 230-2.

[0051] According to Operation 132 of Fig. 1C, is Fig. 17A a perspective view of the semiconductor device 200, which includes a gate structural element 260-1 formed in the logic region and a gate structural element 260-2 formed in the RF region, at one of the various manufacturing stages according to some embodiments; Fig. 17B is a cross-sectional view of the semiconductor device 200 along line bb (the Y-axis) of Fig. 17A; and Fig. 17C is a cross-sectional view of the semiconductor device 200 along line cc (the Y-axis) of Fig. 17A. In some embodiments, the gate structural element 260-1 “replaces” the left dummy stack 230-1 ( Fig. 15B) by filling in the blank space 258-1 ( Fig. 16B); and the gate structural element 260-2 “replaces” the right dummy stack 230-2 ( Fig. 15C) by filling in the blank space 258-2 ( Fig. 16B). Accordingly, the respective side walls of the left dummy stack 230-1 then become the side walls of the gate structure element 260-1; and the respective side walls of the right dummy stack 230-2 then become the side walls of the gate structure element 260-2. In some embodiments, the gate structure element 260-1 includes a gate electrode 262-1 and a high k-value dielectric layer 264-1 over which the gate electrode 262-1 is located; and the gate structure element 260-2 includes a gate electrode 262-2 and a high k-value dielectric layer 264-2 over which the gate electrode 262-2 is located, as shown in the cross-sectional views of the Fig. 17B and Fig. 17C is easier to see.

[0052] In some embodiments, the high k-value dielectric layers 264-1 and 264-2 each contain a material with a k-value (dielectric constant) greater than approximately 4.0 or even greater than approximately 7.0. In such embodiments, the high k-value dielectric layers 264-1 and 264-2 can each be formed from at least one material selected from: Al2O3, HfAlO, HfAlON, AlZrO, HfO2, HfSiOx, HfAlOx, HfZrSiOx, HfSiON, LaAlO3, ZrO2, or a combination thereof. The high k-value dielectric layers 264-1 and 264-2 can be formed using a suitable process, such as LD, CVD, PVD, plating or combinations thereof, such that they lie above the central section 231-1 of the left upper fin 218-1 (with the oxide layer 222 above it) or above the central section 231-2 of the right upper fin 218-2 (with the oxide layer 222 above it).

[0053] In some embodiments, the gate electrodes 262-1 and 262-2 can each contain a metal material, such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, CoSi, or combinations thereof. In some alternative embodiments, the gate electrodes 262-1 and 262-2 can each contain a polysilicon material, wherein the polysilicon material can be doped with a uniform or non-uniform doping concentration. The gate electrodes 262-1 and 262-2 can be formed using a suitable process, such as LD, CVD, PVD, plating or a combination thereof, such that they are located above the central section 231-1 of the left upper fin 218-1 (with the high k-value dielectric layer 264-1 and the oxide layer 222 above it) or above the central section 231-2 of the right upper fin 218-2 (with the high k-value dielectric layer 264-2 and the oxide layer 222 above it).

[0054] According to Operation 134 of Fig. 1C, is Fig. 18A a perspective view of the semiconductor device 200, which includes contact connectors 280-1, 282-1, 280-2 and 282-2, formed at one of the various manufacturing stages, according to some embodiments; Fig. Figure 18B is a cross-sectional view of the semiconductor device 200 along line bb (the Y-axis) of Fig. 18A; and Fig. 18C is a cross-sectional view of the semiconductor device 200 along the line cc (the Y-axis) of Fig. 18A. In some embodiments, the contact plugs 280-1, 282-1, 280-2 and 282-2 are configured to extend through an IMD or ILD layer 284 (in the Fig. 18B and Fig. 18C), which is located above the IMD or ILD layer 256. More precisely, as shown in the cross-sectional views of Fig. 18B and Fig. As can be seen better in 18C, the contact plug 280-1 extends through the IMD or ILD layer 284 to touch the gate electrode 262-1; the contact plugs 282-1 each extend through the IMD or ILD layer 284 to touch the respective source / drain structural elements 250; the contact plug 280-2 extends through the IMD or ILD layer 284 to touch the gate electrode 262-2; and the contact plugs 282-2 each extend through the IMD or ILD layer 284 to touch the respective source / drain structural elements 252.

[0055] In some embodiments, the contact connectors 280-1, 282-1, 280-2, and 282-2 can each contain a metal material such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, CoSi, or combinations thereof. The contact connectors 280-1, 282-1, 280-2, and 282-2 can each be formed by performing at least some of the following processes: forming a structureable layer (for example, a hard mask layer, a photoresist layer, etc.).) above the IMD or ILD layer 284, wherein the structurable layer has openings that are directed towards the respective areas where the contact connectors are to be formed; using the structurable layer as a mask for performing at least one dry / wet etching process to etch through the IMD or ILD layer 284 such that the respective conductive structural elements (for example, the gate electrode 262-1, the source / drain structural elements 250, the gate electrode 262-2, the source / drain structural elements 252) are exposed; and using a suitable process such as LD, CVD, PVD, plating or a combination thereof to fill the etched sections of the IMD or ILD layer 284 with the aforementioned metallic material (for example, W).

[0056] In some embodiments, after the formation of the contact connectors 280-1, 282-1, 280-2 and 282-2, the at least two FinFETs, as mentioned above, can be formed in the logic and RF regions respectively.More precisely, the upper left fin 218-1, the oxide layer 222, the source / drain structural elements 250, the first spacer 236, the gate stack 260-1 and the contact plugs 280-1 and 282-1 form a FinFET in the logic region (hereinafter referred to as the “logic FinFET”), wherein the upper left fin 218-1 serves as the conduction channel and the contact plugs 208-1 and 282-1 serve as gate and source / drain contacts respectively; and the upper right fin 218-2, the oxide layer 222, the source / drain structural elements 252, the second spacer 246, the gate stack 260-2 and the contact plugs 280-2 and 282-2 form another FinFET in the RF region (hereinafter referred to as “RF FinFET”), wherein the upper right fin 218-2 serves as the conduction channel and the contact plugs 208-2 and 282-2 each serve as gate and source / drain contacts.

[0057] As with regard to the Fig. 13B and Fig. As described in Figure 13C5, the lateral distance 248-1 in the logic region, by which the first spacer 236 extends from the side wall 235b, is significantly shorter than the lateral distance 248-2 in the RF region, by which the second spacer 246 extends from the side wall 237b. We turn again to the Fig. 18B and Fig. 18C, where accordingly the source / drain structural elements 252 and the gate structural element 260-2 of the RF FinFET can be separated laterally by the second spacer 246 by a longer distance 248-2 than in comparison to the separation distance 248-1 between the source / drain structural elements 250 and the gate structural element 260-1 of the logic FinFET.

[0058] Therefore, the problems mentioned above (for example, the high parasitic capacitance induced between the gate and source / drain structural elements) that are observed in conventional FinFETs can be avoided. For example, the second spacer 246 of the RF FinFET contains several dielectric layers, at least one of which is maintained at its original thickness (for example, the layers of 246a), such that parasitic capacitance between the respective gate and source / drain structural elements can be advantageously suppressed. Furthermore, using the disclosed method 100 for fabricating a semiconductor device (for example, the semiconductor device 200), two FinFETs, each with different spacer thicknesses, can be formed simultaneously.For example, the logic FinFET, which is usually less sensitive to parasitic capacitance, and the RF FinFET, which is usually more sensitive to parasitic capacitance, can be designed to have appropriate spacer thicknesses.

[0059] Fig. Figure 19A is a perspective view of the semiconductor device 200', which includes contact connectors 280-1, 282-1, 280-2 and 282-2 formed at one of the various manufacturing stages, according to some embodiments. Fig. 19B is a cross-sectional view of the semiconductor device 200' along line bb (the Y-axis) of Fig. 19A; and Fig. 18C is a cross-sectional view of the semiconductor device 200' along line cc (the Y-axis) of Fig. 19A. As discussed previously, the first section 236a of the first spacer 236 can have a thickness essentially close to zero (i.e., without such a first section 236a of the first spacer 236). As in Fig. As shown in Figure 19B, the first spacer 236 of the semiconductor device 200' contains only section 236b and does not have section 236a. In contrast, as shown in Fig. As shown in Figure 19C, the second spacer 246 of the semiconductor device 200' further comprises two sections (246a, 246b). As discussed previously, each of the sections 236b, 246a, 246b may contain one or more of the following: silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or any other suitable material.

[0060] In this case, the width of the first spacer 236 (i.e., 236b in this embodiment), which extends along the Y-axis in the logic region, is as shown in Fig. 19B, significantly shorter than the width of the second spacer 246, which extends along the Y-axis in the HF region, as shown in Fig. Figure 19C shows that the source / drain structural elements 252 and the gate structural element 260-2 of the RF FinFET can be separated laterally by the second spacer 246 at a greater distance than the separation distance between the source / drain structural elements 250 and the gate structural element 260-1 of the logic FinFET. Therefore, the problems mentioned above (for example, the high parasitic capacitance induced between the gate and source / drain structural elements) that are observed in conventional FinFETs can be avoided.

[0061] In one embodiment as described in the Fig. 19B and Fig.As shown in Figure 19C, there is a protective layer 293 that forms outside the gate electrode 262-1 in the logic region, and there is a protective layer 294 that forms outside the gate electrode 262-2 in the RF region. The protective layer 293 and the protective layer 294 may contain silicon oxide (SiOx) to repair damage from poly-etching. In one example, the protective layer 293 and the protective layer 294 are formed after operation 130, in which the multiple dummy stacks are removed to form multiple cavities, and before operation 132, in which each of the multiple cavities is filled with a respective gate structural element. In another example, the protective layer 293 and the protective layer 294 are part of the gate structural element 260-1 and the gate structural element 260-2, respectively. This means that the protective layer 293 and the protective layer 294 can be formed with the gate structural element 260-1 and the gate structural element 260-2, respectively.In one embodiment, while the width of the protective layer 293, which extends along the Y-axis in the logic region, is the same or similar to the width of the protective layer 294, which extends along the Y-axis in the RF region, the source / drain structural elements 252 and the gate structural element 260-2 of the RF FinFET are again laterally separated by a longer distance than compared to the separation distance between the source / drain structural elements 250 and the gate structural element 260-1 of the logic FinFET.

[0062] Although the method 100 described above relates to the fabrication of a semiconductor device containing at least one logic FinFET and one RF FinFET, it should be noted that method 100 can also be used to fabricate a combination of logic and RF FinFETs without departing from the scope of this disclosure. For example, to form an RF FinFET, operations 118 and 120 of method 100 can be omitted; to form a logic FinFET (with only one section of the spacer), operations 118, 122, and 124 of method 100 can be omitted.

[0063] In one embodiment, a semiconductor device comprises: first and second fin structures arranged on a substrate, each extending parallel to an axis; a first gate structure element traversing the first fin structure to lie over a central section of the first fin structure; a second gate structure element traversing the second fin structure to lie over a central section of the second fin structure; a first spacer comprising: a first section comprising two layers, each extending from the side walls of the first gate structure element in opposite directions of the axis; and a second section comprising two layers, each extending from the side walls of the first section of the first spacer in opposite directions of the axis;and a second spacer comprising: a first section comprising two layers, each extending from the side walls of the second gate structural element in opposite directions of the axis; and a second section comprising two layers, each extending from the side walls of the first section of the second spacer in opposite directions of the axis, wherein the thickness of the first section of the second spacer is substantially thinner than the thickness of the first section of the first spacer.

[0064] In another embodiment, a semiconductor device comprises: first and second fin structures arranged on a substrate, each extending parallel to an axis; a first gate structure element traversing the first fin structure to lie over a central section of the first fin structure; a second gate structure element traversing the second fin structure to lie over a central section of the second fin structure; a first spacer comprising: a first section comprising two layers, each extending from the side walls of the first gate structure element in opposite directions of the axis; and a second section comprising two layers, each extending from the side walls of the first section of the first spacer in opposite directions of the axis;and a second spacer comprising: a first section comprising two layers, each extending from the side walls of the second gate structural element in opposite directions of the axis; and a second section comprising two layers, each extending from the side walls of the first section of the second spacer in opposite directions of the axis, wherein the thickness of the first section of the second spacer is substantially thinner than the thickness of the first section of the first spacer.

[0065] In a further embodiment, a method for forming a fin field-effect transistor (FinFET) comprises: forming first and second fin structures, each projecting from an upper interface of an insulating structure element; forming a first dummy stack traversing a central section of the first fin structure and a second dummy stack traversing a central section of the second fin structure; forming a first dielectric layer over the first and second dummy stacks; etching a section of the first dielectric layer over the first dummy stack; and forming a second dielectric layer over the first and second dummy stacks.and etching the second dielectric layer to form a first spacer extending along a side wall of the first dummy stack, and to form a second spacer extending along a side wall of the second dummy stack, wherein the first and second spacers each comprise both the first and second dielectric layers, wherein the first dielectric layer of the first spacer is substantially thinner than the first dielectric layer of the second spacer.

Claims

[1] Semiconductor device comprising the following: first and second fin structures (212-1, 212-2) arranged on a substrate (102, 202) each extending parallel to an axis; a first gate structural element (260-1) that crosses the first fin structure (212-1) to lie over a central section (231) of the first fin structure (212-1); a second gate structural element (260-2) that crosses the second fin structure (212-2) to lie over a central section (231) of the second fin structure (212-2); a first spacer (236) comprising the following: a first section (236a, 246a) comprising two layers, each extending from the side walls of the first gate structural element (260-1) in opposite directions along the axis; and a second section (236b, 246b) comprising two layers, each extending from the side walls of the first section (236a, 246a) of the first spacer (236) in opposite directions along the axis; and a second spacer (246) comprising the following: a first section (236a, 246a) comprising two layers, each extending from the side walls of the second gate structural element (260-2) in opposite directions along the axis; and a second section (236b, 246b) comprising two layers, each extending from the side walls of the first section (236a, 246a) of the second spacer (246) in opposite directions of the axis, wherein the thickness of the first section (236a, 246a) of the second spacer (246) is thinner than the thickness of the first section (236a, 246a) of the first spacer (236). [2] Semiconductor device according to claim 1, wherein the first and second gate structural elements (260-1, 260-2) each comprise a gate dielectric layer (264-1, 264-2) and at least one conductive gate layer (262-1, 262-2) arranged above the gate dielectric layer (264-1, 264-2). [3] Semiconductor device according to claim 2, wherein the gate dielectric layer (264-1, 264-2) comprises a dielectric layer (264) with a high k-value and the conductive gate layer (262-1, 262-2) comprises at least one metal layer or a polysilicon layer. [4] Semiconductor device according to one of the preceding claims, wherein the two layers of the first section (236a, 246a) of the first spacer (236) lie over first side sections of the first fin structure (212-1), each of which lies next to the central section (231). [5] Semiconductor device according to claim 4, wherein the two layers of the second section (236b, 246b) of the first spacer (236) lie over second side sections of the first fin structure (212-1), each of which lies next to the first side sections. [6] Semiconductor device according to any of the preceding claims, further comprising: a pair of first source / drain structural elements (250) along the first fin structure (212-1), which are arranged on the outer sides of the second section (236b, 246b) of the first spacer (236); and a pair of second source / drain structural elements (252) along the second fin structure (212-2) which are arranged on outside sides of the second section (236b, 246b) of the second spacer (246). [7] Semiconductor device according to claim 6, wherein the pair of first source / drain structural elements (250) is electromagnetically isolated from the first gate structural element (260-1) by at least the first spacer (236) and the pair of second source / drain structural elements (252) is electromagnetically isolated from the second gate structural element (260-2) by at least the second spacer (246). [8] Semiconductor device according to one of the preceding claims, wherein the first and second spacers (246) are each formed from a dielectric material (214). [9] Semiconductor device comprising the following: first and second fin structures (212-1, 212-2) arranged on a substrate (102, 202) each extending parallel to an axis; a first gate structural element (260-1) that crosses the first fin structure (212-1) to lie over a central section (231) of the first fin structure (212-1); a second gate structural element (260-2) that crosses the second fin structure (212-2) to lie over a central section (231) of the second fin structure (212-2); a first spacer (236) comprising the following: a first section (236a, 246a) comprising two layers, each extending from the side walls of the first gate structural element (260-1) in opposite directions along the axis; and a second section (236b, 246b) comprising two layers, each extending from the side walls of the first section (236a, 246a) of the first spacer (236) in opposite directions along the axis; and a second spacer (246) comprising the following: a first section (236a, 246a) comprising two layers, each extending from the side walls of the second gate structural element (260-2) in opposite directions along the axis; and a second section (236b, 246b) comprising two layers, each extending from the side walls of the first section (236a, 246a) of the second spacer (246) in opposite directions of the axis, wherein the thickness of the first section (236a, 246a) of the second spacer (246) is thinner than the thickness of the first section (236a, 246a) of the first spacer (236). [10] Semiconductor device according to claim 9, wherein the first and second gate structural elements (260-1, 260-2) each comprise a gate dielectric layer (264-1, 264-2) and at least one conductive gate layer (262-1, 262-2) arranged over the gate dielectric layer (264-1, 264-2). [11] Semiconductor device according to claim 10, wherein the gate dielectric layer (264-1, 264-2) comprises a dielectric layer (264) with a high k-value and the conductive gate layer (262-1, 262-2) comprises at least one metal layer or a polysilicon layer. [12] Semiconductor device according to claim 9 or 10, further comprising: a first source / drain structural element (250) along the first fin structure (212-1), which is arranged on one side of the second section (236b, 246b) of the first spacer (236); and a second source / drain structural element (252) along the second fin structure (212-2) which is arranged on one side of the second section (236b, 246b) of the second spacer (246). [13] Semiconductor device according to claim 12, wherein the first source / drain structural element (250) is electromagnetically isolated from the first gate structural element (260-1) by at least the first spacer (236) and the second source / drain structural element (252) is electromagnetically isolated from the second gate structural element (260-2) by at least the second spacer (246). [14] Semiconductor device according to any one of the preceding claims 9 to 13, wherein the first gate structure element (260-1) lies over side walls and a top boundary of the central section (231) of the first fin structure (212-1) and the second gate structure element (260-2) lies over side walls and a top boundary of the central section (231) of the second fin structure (212-2). [15] Semiconductor device according to any one of the preceding claims 9 to 14, wherein the first section (236a, 246a) of the first spacer (236) lies over side walls and a top boundary of a first side section of the first fin structure (212-1) and the first section (236a, 246a) of the second spacer (246) lies over side walls and a top boundary of a first side section of the second fin structure (212-2). [16] Semiconductor device according to claim 15, wherein the second section (236b, 246b) of the first spacer (236) lies over side walls and a top boundary of a second side section of the first fin structure (212-1) which is located immediately adjacent to the first side section of the first fin structure (212-1), and the second section (236b, 246b) of the second spacer (246) lies over side walls and a top boundary of a second side section of the second fin structure (212-2) which is located immediately adjacent to the first side section of the second fin structure (212-2). [17] Method for forming a fin field-effect transistor (FinFET) comprising the following: Forming first and second fin structures (212-1, 212-2), each projecting from an upper boundary surface of an insulation structure element (220); Forming a first dummy stack (230-1) that crosses a central section (231) of the first fin structure (212-1), and a second dummy stack (230-2) that crosses a central section (231) of the second fin structure (212-2); Forming a first dielectric layer (234) over the first and second dummy stacks (230-1, 230-2); Etching a section of the first dielectric layer (234) that lies above the first dummy stack (230-1); Forming a second dielectric layer (244) over the first and second dummy stacks (230-1, 230-2); and Etching the second dielectric layer (244) to form a first spacer (236) extending along a side wall of the first dummy stack (230-1) and to form a second spacer (246) extending along a side wall of the second dummy stack (230-2), wherein the first and second spacers (246) each comprise both the first and second dielectric layers (234, 244), wherein the first dielectric layer (234) of the first spacer (236) is thinner than the first dielectric layer (234) of the second spacer (246). [18] Method according to claim 17, wherein the first spacer (236) surrounds a side section of the first fin structure (212-1), wherein the side section is located immediately next to the central section (231) of the first fin structure (212-1), and the second spacer (246) surrounds a side section of the second fin structure (212-2), wherein the side section is located immediately next to the central section (231) of the second fin structure (212-2). [19] The method of claim 17 or 18, further comprising: Forming a first source / drain structural element (250) along the first fin structure (212-1) and laterally next to an outer wall of the first spacer (236) and a second source / drain structural element (252) along the second fin structure (212-2) and laterally next to an outer wall of the second spacer (246); Remove the first and second dummy stacks (230-1, 230-2) to create respective cavities; Form first and second gate structural elements (260-1, 260-2) in the respective cavities. [20] The method of claim 19, further comprising: Forming respective contact structures that are coupled to the first and second source / drain structure elements (250, 252) and the first and second gate structure elements (260-1, 260-2).

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