Semiconductor device and methods for its manufacture

Abstract

Method for manufacturing a semiconductor device comprising the following steps: Providing a first semiconductor structure with first integrated circuit components (100.1, 402.1, 412.1, 432.1), wherein the first integrated circuit components (100.1, 402.1, 412.1, 432.1) each have an active region (100A) and a peripheral region (100B) that surrounds the active region (100A); Fabricating a first redistribution layer (104.1, 204.1) over the first semiconductor structure, wherein the first redistribution layer (104.1, 204.1) comprises a dielectric layer (206, 206.1) and matrices of first conductive contacts (302, 302.1, 302.2, 312, 312.1, 312.2, 324, 324.1, 324.2) embedded in the dielectric layer (206, 206.1), wherein the matrices of first conductive contacts (302, 302.1, 302.2, 312, 312.1, 312.2, 324, 324.1, 324.2) are each arranged on a first region of the peripheral area (100B) and along a first direction (D1) wherein any two nearest adjacent matrices of first conductive contacts (302, 302.1, 302.2, 312, 312.1, 312.2, 324, 324.1, 324.2) are aligned to each other in a second direction (D2) and each connect to two adjacent first integrated circuit components (100.1, 402.1, 412.1, 432.1) are arranged, spaced apart from each other by a first distance (DS1), wherein the first distance (DS1) is greater than a first dimension (DM1) of the active area (100A) in the second direction (D2), wherein the second direction (D2) is substantially perpendicular to the first direction (D1), wherein no other matrix of conductive contacts is arranged between any two nearest adjacent matrices of first conductive contacts (302, 302.1, 302.2, 312, 312.1, 312.2, 324, 324.1, 324.2); . Providing a second semiconductor structure; Creating a second redistribution layer (104.2, 204.2) over the second semiconductor structure; and Performing a bonding process to bond the first and second redistribution layers (104.2, 204.2) to produce a bonded structure (210).

Description

background

[0001] Continuous improvements in semiconductor manufacturing processes have enabled manufacturers and developers to create smaller and more powerful electronic components. Semiconductor manufacturing has evolved from a 10 µm semiconductor manufacturing process achieved around 1971 to a 22 nm semiconductor manufacturing process achieved around 2012. Semiconductor manufacturing is expected to evolve to a 5 nm semiconductor manufacturing process around 2019. With each advancement in semiconductor manufacturing processes, semiconductor elements in integrated circuit components have become smaller, allowing more components to be fabricated on the semiconductor substrate. Multiple integrated circuit components can be bonded together to create even more powerful electronic components.However, with every advancement in the semiconductor manufacturing process, new challenges have arisen in the bonding of integrated circuit components. One such new challenge concerns the avoidance of air bubbles that arise during bonding between the integrated circuit components. A semiconductor circuit package and a sensor device are known from US 2014 / 0015084 A1. Further semiconductor devices are known from US 2016 / 0155724 A1 and US 2017 / 0200756 A1. A method for bonding two substrates is known from WO 2017 / 140348. Short description of the drawings

[0002] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. The Fig. 1A and Fig. 1B illustrate an exemplary integrated circuit component or a semiconductor device with bonded integrated circuit components, according to exemplary embodiments of the present invention. The Fig. 2A to 2C illustrate exemplary semiconductor wafers including exemplary integrated circuit components, according to exemplary embodiments of the present invention. The Fig. 3A to 3B and 3E to 3J show exemplary redistribution layers of the exemplary integrated circuit components, according to exemplary embodiments of the present invention, wherein the Fig. 3C and Fig. 3B do not belong to the invention. The Fig. 4A to 4B and 4D to 4I show exemplary redistribution layers for the exemplary semiconductor wafers, according to exemplary embodiments of the present invention, wherein the Fig. The exemplary redistribution layer shown in Figure 4C does not belong to the invention. Fig. 5 shows a flowchart of exemplary steps for manufacturing the exemplary semiconductor wafers with the exemplary integrated circuit components, according to an exemplary embodiment of the present invention. Detailed description

[0003] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to facilitate the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed. Overview

[0004] Example embodiments for redistribution layers fabricated on integrated circuit components are disclosed. The redistribution layers on the integrated circuit components of the present invention include one or more arrays of conductive contacts configured and arranged such that a bonding wave can displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimizes discontinuities, such as air pockets (i.e., voids), between the redistribution layers during bonding. Example integrated circuit

[0005] The Fig. 1A and Fig. 1B show an exemplary integrated circuit component or a semiconductor device with bonded integrated circuit components, according to exemplary embodiments of the present invention. As in Fig. 1A, an exemplary integrated circuit component 100 includes a semiconductor substrate 101 with electronic circuitry fabricated therein and an interconnect structure 102 disposed on the semiconductor substrate 101. In some embodiments, the integrated circuit component 100 includes an active area 100A in which the electronic circuitry is fabricated and a peripheral area 100B surrounding the active area 100A. In a back end of line (BEOL) process, a redistribution layer 104 is fabricated on the interconnect structure 102 of the integrated circuit component 100. The redistribution layer 104 fabricated on the interconnect structure 102 of the integrated circuit component 100 may serve as a bonding layer when the integrated circuit component 100 is bonded to other components. In the exemplary embodiment shown in Fig. 1A, the electronic circuits fabricated in the substrate 101 include analog and / or digital circuits arranged in a semiconductor stack with one or more conductive layers, also referred to as metal layers, and interdigitated with one or more non-conductive layers, also referred to as insulating layers. However, one skilled in the art will recognize that the electronic circuits may include one or more mechanical and / or electromechanical components without departing from the spirit and scope of the present invention.

[0006] The semiconductor substrate 101 may be made of silicon or other semiconductor materials. Alternatively, the semiconductor substrate 101 may include other elemental semiconductor materials, such as germanium. In some embodiments, the semiconductor substrate 101 is made of a compound semiconductor, such as sapphire, silicon carbide, gallium arsenic, indium arsenide, or indium phosphide. In some embodiments, the semiconductor substrate 101 is made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 includes an epitaxial layer over a bulk semiconductor.

[0007] The semiconductor substrate 101 may further include isolation elements (not shown), such as shallow trench isolation (STI) or local oxidation of silicon (LOCOS) elements. The isolation elements may define and separate different semiconductor elements. The semiconductor substrate 101 may also include doped regions (not shown). The doped regions may be doped with p-type dopants, such as boron or BF2, and / or n-type dopants, such as phosphorus (P) or arsenic (As). The doped regions may be formed directly on the semiconductor substrate 101 in a p-well structure, an n-well structure, or a double-well structure.

[0008] Electronic circuits comprising the aforementioned isolation elements and semiconductor elements, for example, transistors such as metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS transistors), bipolar transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field-effect transistors (PFETs / NFETs), etc., diodes, and / or other suitable elements, can be fabricated over the semiconductor substrate 101. Various processes can be performed to fabricate the isolation elements and semiconductor elements, such as deposition, etching, implantation, photolithography, annealing, and / or other suitable processes. In some embodiments, the electronic circuits comprising the isolation elements and semiconductor elements are fabricated in the semiconductor substrate 101 using a front-end-of-line (FEOL) process.

[0009] In some embodiments, the interconnect structure 102 includes dielectric layers, conductive vias embedded in the dielectric layers, and conductive wiring formed between the dielectric layers, with different layers of the conductive wiring being electrically connected to each other via the conductive vias. Furthermore, the interconnect structure 102 is electrically connected to the electronic circuits formed in the semiconductor substrate 101.In some embodiments, at least one sealing ring and at least one alignment mark are formed in the interconnect structure 102, wherein the sealing ring and the alignment mark are formed in the peripheral region 100B of the integrated circuit component 100, the sealing ring encloses the active area 100A of the integrated circuit component 100, and the alignment mark is formed in a region outside the sealing ring. In some embodiments, a plurality of alignment marks are formed around corners of the integrated circuit component 100. The number of the aforementioned sealing rings and alignment marks is not limited in the present invention.

[0010] In the exemplary embodiment shown in Fig. 1A, the redistribution layer 104 represents a conductive layer (e.g., a metal layer) of the one or more conductive layers of the semiconductor stack that is used to electrically connect the electronic circuits to other electrical, mechanical, and / or electromechanical components. For example, the redistribution layer 104 may be used to electrically connect the electronic circuits to an integrated circuit package, such as a via package, a surface mount package, a pin array package, a low-profile package, a small footprint package, a chip-scale package, and / or a ball grid array.

[0011] As another example, which Fig. 1B, a semiconductor device comprises a first integrated circuit component 100.1, a first redistribution layer 104.1, a second integrated circuit component 100.2, and a second redistribution layer 104.2, wherein the first redistribution layer 104.1 and the second redistribution layer 104.2 are arranged between the first integrated circuit component 100.1 and the second integrated circuit component 100.2. An exemplary first integrated circuit component 100.1 comprises a first semiconductor substrate 101.1 with first electronic circuits fabricated therein and a first interconnect structure 102.1 arranged on the first semiconductor substrate 101.1. An exemplary second integrated circuit component 100.2 comprises a second semiconductor substrate 101.2 with second electronic circuits fabricated therein and a second interconnect structure 102.2 formed on the second semiconductor substrate 101.2 is arranged. The first redistribution layer 104.1 of a first semiconductor stack associated with the first electronic circuits may be electrically and / or mechanically connected to the second redistribution layer 104.2 of a second semiconductor stack associated with the second electronic circuits to electrically connect the first electronic circuits to the second electronic circuits. In this exemplary embodiment, the first redistribution layer 104.1 is configured and arranged to be electrically and / or mechanically connected to the second redistribution layer 104.2. In an exemplary embodiment, the first redistribution layer 104.1 is connected to the second redistribution layer 104 using the following methods.2: hybrid bonding, direct bonding, surface-activated bonding, plasma-activated bonding, anodic bonding, eutectic bonding, thermocompression bonding, reactive bonding, transient liquid-phase diffusion bonding, and / or any other known bonding method known to those skilled in the art without departing from the spirit and scope of the present invention. In this exemplary embodiment, the aforementioned bonding methods utilize a bonding wave to electrically and / or mechanically connect the first redistribution layer 104.1 to the second redistribution layer 104.2. As will be explained in more detail later, the first redistribution layer 104.1 and the second redistribution layer 104.2 are configured and arranged to eliminate discontinuities, such as air bubbles, between the first redistribution layer 104.1 and the second redistribution layer 104.2 during bonding of the first redistribution layer 104.1 to the second redistribution layer 104.2. Example semiconductor wafers

[0012] The Fig. 2A to 2C show exemplary semiconductor wafers with exemplary integrated circuit components, according to exemplary embodiments of the present invention. In Fig. 2A, a semiconductor device manufacturing step is used to fabricate a plurality of integrated circuit components 100.1 to 100.n in a semiconductor wafer 200. The semiconductor wafer 200 comprises a plurality of integrated circuit components 100.1 to 100.n arranged in a matrix. In some embodiments, the semiconductor wafer 200 comprises a semiconductor substrate 202 with electronic circuits fabricated therein and an interconnect structure 203 arranged on the semiconductor substrate 202. In some embodiments, the integrated circuit components 100.1 to 100.n in the semiconductor wafer 200 each comprise an active region 100A in which the electronic circuits are fabricated, and a peripheral region 100B surrounding the active region 100A.In the semiconductor device manufacturing step, a predetermined sequence of photographic and / or chemical processing steps is used to manufacture the plurality of integrated circuit components 100.1 to 100.n in the semiconductor wafer 200. The predetermined sequence of photographic and / or chemical processing steps may include deposition, removal, patterning, and modification. Deposition is a process used to grow, deposit, or otherwise transfer a material onto a semiconductor substrate and may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), and / or molecular beam epitaxy (MBE). Removal is a process used to remove material from the semiconductor substrate and may include, for example, wet etching, dry etching, and / or chemical mechanical planarization (CMP).Patterning, often referred to as lithography, is a process for shaping or altering the material of the semiconductor substrate to create various geometric shapes of the analog and / or digital circuits for the electronic device. Electrical property modification is a process for changing the physical, electrical, and / or chemical properties of the semiconductor substrate material, typically through ion implantation. In an exemplary embodiment, this manufacturing process can be used in a semiconductor fabrication facility to fabricate the analog and / or digital circuits for the electronic device on the semiconductor substrate.

[0013] In the exemplary embodiment shown in Fig. As shown in Figure 2A, the integrated circuit components 100.1 to 100.n are manufactured in and / or on the semiconductor substrate 202 with a first series of manufacturing steps referred to as front-end-of-line processing and a second series of manufacturing steps referred to as back-end-of-line processing. The front-end-of-line processing represents a first series of photographic and / or chemical processing steps for producing corresponding electronic circuits of the plurality of integrated circuit components 100.1 to 100.n in and / or on the semiconductor substrate 202. The back-end-of-line processing represents a second series of photographic and / or chemical processing steps for producing a corresponding interconnect structure 203 of the plurality of integrated circuit components 100.1 to 100.n on the semiconductor substrate 202 for producing the semiconductor wafer 200.In an exemplary embodiment, the integrated circuit components 100.1 to 100.n included in the semiconductor wafer 200 may be similar to and / or different from each other.

[0014] As in Fig. 2A, the semiconductor substrate 202 is a portion of the semiconductor wafer 200. The semiconductor substrate 202 may be made of silicon or other semiconductor materials. In addition, the semiconductor substrate 202 may include other elemental semiconductor materials, such as germanium. In some embodiments, the semiconductor substrate 202 is made of a compound semiconductor, such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide. In some embodiments, the semiconductor substrate 202 is made of an alloy semiconductor, such as sapphire, silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the semiconductor substrate 202 includes an epitaxial layer. For example, the semiconductor substrate 202 includes an epitaxial layer over a bulk semiconductor.

[0015] The semiconductor substrate 202 may further include isolation elements (not shown), such as STI elements or LOCOS elements. The isolation elements may define and separate various semiconductor elements. The semiconductor substrate 202 may also include doped regions (not shown). The doped regions may be doped with p-type dopants, such as boron or BF2, and / or n-type dopants, such as phosphorus (P) or arsenic (As). The doped regions may be formed directly on the semiconductor substrate 202 in a p-well structure, an n-well structure, or a double-well structure.

[0016] In some embodiments, the interconnect structure 203 includes dielectric layers, conductive vias embedded in the dielectric layers, and conductive interconnections between the dielectric layers, wherein different layers of the conductive interconnections are electrically connected to each other via the conductive vias.

[0017] A redistribution layer 204 is formed over the semiconductor wafer 200. In some embodiments, the process for forming the redistribution layer 204 over the semiconductor wafer 200 includes: forming a dielectric layer 206 over the semiconductor wafer 200; patterning the dielectric layer 206 to create a plurality of openings in the dielectric layer 206 for exposing conductive pads of the semiconductor wafer 200; depositing a conductive material over the semiconductor wafer 200 such that the dielectric layer 206 and the conductive pads exposed by the openings in the dielectric layer are covered by the conductive material, wherein the conductive material covers not only the dielectric layer 206 and the conductive pads, but also sidewall surfaces of the openings and completely fills the openings; and performing a grinding process (e.g.,a CMP process) to partially remove an excess portion of the conductive material until the top surface of the dielectric layer 206 is exposed to form arrays of conductive contacts 208 (e.g., metal vias and / or metal pads) in the dielectric layer 206. The redistribution layer 204 with the dielectric layer 206 and the arrays of conductive contacts 208 may serve as a bonding layer when a wafer-level bonding process is performed to bond the semiconductor wafer 200 to another wafer.

[0018] As in Fig. As shown in FIG. 2B, a first semiconductor wafer 200.1 and a second semiconductor wafer 200.2 are provided to be bonded to each other. In some embodiments, two different types of wafers 200.1 and 200.2 are provided. In other words, the integrated circuit components 100.1 to 100.n included in the first semiconductor wafer 200.1 and the integrated circuit components 100.1 to 100.n included in the second semiconductor wafer 200.2 may have different architectures and perform different functions. For example, the first semiconductor wafer 200.1 is a sensor wafer having a plurality of image sensor chips (e.g., CMOS image sensor chips), and the second semiconductor wafer 200.2 is an ASIC wafer (ASIC: Application Specific Integrated Circuit) having a plurality of ASIC units corresponding to the image sensor chips.The image sensor chips included in the sensor wafer may be back-side illuminated CMOS image sensors (BSI-CIS) capable of sensing light from the backside of the CMOS image sensors, and the redistribution layer 104.1 may be fabricated over active surfaces (i.e., surfaces facing the backside of the CMOS image sensors) of the CMOS image sensors. In some alternative embodiments, two similar or identical wafers 200.1 and 200.2 are provided. In other words, the integrated circuit components 100.1 to 100.n included in the first semiconductor wafer 200.1 and the integrated circuit components 100.1 to 100.n included in the second semiconductor wafer 200.2 may have the same or a similar architecture and perform the same or a similar function.

[0019] Before bonding the first semiconductor wafer 200.1 and the second semiconductor wafer 200.2, a first redistribution layer 204.1 and a second redistribution layer 204.2 are formed over the first semiconductor wafer 200.1 and the second semiconductor wafer 200.2, respectively. The process for forming the first redistribution layer 204.1 and the second redistribution layer 204.2 may be similar to the process for forming the redistribution layer 204 shown in Fig. 2A is shown.

[0020] In some embodiments, the process for forming the first redistribution layer 204.1 over the first semiconductor wafer 200.1 comprises: forming a first dielectric layer 206.1 over the first semiconductor wafer 200.1; patterning the first dielectric layer 206.1 to create a plurality of first openings in the first dielectric layer 206.1 for exposing first conductive pads of the first semiconductor wafer 200.1; depositing a first conductive material over the first semiconductor wafer 200.1 such that the first dielectric layer 206.1 and the first conductive pads exposed by the first openings in the first dielectric layer 206.1 are covered by the first conductive material, wherein the first conductive material does not only cover the first dielectric layer 206.1 and the first conductive pads, but also covers sidewall surfaces of the first openings and completely fills the first openings; and performing a first grinding process (e.g., a CMP process) to partially remove an excess portion of the first conductive material until the top surface of the first dielectric layer 206.1 is exposed to form a plurality of arrays of conductive contacts 208.1 (e.g., metal vias and / or metal pads) in the first dielectric layer 206.1. In some embodiments, the process for forming the second redistribution layer 204.2 over the second semiconductor wafer 200.2 includes: forming a second dielectric layer 206.2 over the second semiconductor wafer 200.2; Structuring the second dielectric layer 206.2 to form a plurality of second openings in the second dielectric layer 206.2 for exposing second conductive pads of the second semiconductor wafer 200.2; depositing a second conductive material over the second semiconductor wafer 200.2 such that the second dielectric layer 206.2 and the second conductive pads exposed by the second openings are covered by the second conductive material, wherein the second conductive material covers not only the second dielectric layer 206.2 and the second conductive pads, but also sidewall surfaces of the second openings and completely fills the second openings; and performing a second grinding process (e.g., a CMP process) to partially remove an excess portion of the second conductive material until the top surface of the second dielectric layer 206.2 is exposed to produce a plurality of matrices of conductive contacts 208.2 (e.g., metal vias and / or metal pads) in the second dielectric layer 206.2.

[0021] In some embodiments, the matrices of conductive contacts 208.1 slightly protrude from the top surface of the first dielectric layer 206.1, and the matrices of conductive contacts 208.2 slightly protrude from the top surface of the second dielectric layer 206.2, because during the CMP processes, the first and second dielectric layers 206.1 and 206.2 are polished at a relatively higher polishing rate while the conductive material is polished at a relatively lower polishing rate.

[0022] As in the Fig. 2B and Fig. 2C, after forming the first and second redistribution layers 204.1 and 204.2 over the first and second semiconductor wafers 200.1 and 200.2, the first semiconductor wafer 200.1 with the first redistribution layer 204.1 formed thereon is tilted onto the second redistribution layer 204.2 formed on the second semiconductor wafer 200.2 such that the plurality of arrays of conductive contacts 208.1 of the first redistribution layer 204.1 are substantially aligned with the plurality of arrays of conductive contacts 208.2 of the second redistribution layer 204.2. Then, the first semiconductor wafer 200.1 is bonded to the second semiconductor wafer 200.2 via the first and second redistribution layers 204.1 and 204.2 to fabricate a semiconductor device 210. In some embodiments, after performing the bonding process, the bonding interface is between the first redistribution layer 204.1 and the second redistribution layer 204.2 in the bonded structure (i.e., the semiconductor device) 210 is free of voids. This bonding process may include hybrid bonding, direct bonding, surface-activated bonding, plasma-activated bonding, anodic bonding, eutectic bonding, thermocompression bonding, reactive bonding, transient liquid-phase diffusion bonding, and / or any other known bonding method known to those skilled in the art without departing from the spirit and scope of the present invention. As will be explained in more detail later, the first redistribution layer 204.1, which is formed over the first semiconductor wafer 200.1, and the second redistribution layer 204.2, which is formed over the second semiconductor wafer 200.2, are configured and arranged to minimize discontinuities, such as air bubbles, between the first redistribution layer 204.1 and the second redistribution layer 204.2.

[0023] Since the arrays of conductive contacts 208.1 protrude slightly from the top surface of the first dielectric layer 206.1 and the arrays of conductive contacts 208.2 protrude slightly from the top surface of the second dielectric layer 206.2, an air gap may be created between the first and second redistribution layers 204.1 and 204.2 prior to bonding the first and second semiconductor wafers 200.1 and 200.2. After the plurality of arrays of conductive contacts 208.1 and 208.2 have been aligned on the first and second semiconductor wafers 200.1 and 200.2, a wafer-to-wafer hybrid bonding process may be performed such that the first and second semiconductor wafers 200.1 and 200.2 are physically and electrically connected to each other. During the hybrid bonding process, a bonding wave is used for the first and second semiconductor wafers 200.1 and 200.2 to displace air between the first and second redistribution layers 204.1 and 204.2.

[0024] It should be noted that during the hybrid bonding process, air may become trapped between the first and second redistribution layers 204.1 and 204.2 if the layout of the conductive contact arrays is not well configured and arranged. For example, if any two nearest adjacent conductive contact arrays that are parallel to each other are placed too close together, it is difficult to displace the air trapped between any two nearest adjacent conductive contact arrays, and this may result in voids being created between any two nearest adjacent conductive contact arrays. In other words, voids may be created at the bonding interface between the first and second redistribution layers 204.1 and 204.2, which may degrade device performance.In an exemplary embodiment, the arrays of conductive contacts are configured and arranged in the proper manner as shown in FIGS. Fig. 4A to 4I, in order to avoid the formation of voids at the bonding interface between the first and second redistribution layers 204.1 and 204.2.

[0025] In some embodiments, the aforementioned hybrid bonding process for the first and second semiconductor wafers 200.1 and 200.2 comprises simultaneously performing a metal-to-metal bond between the conductive contacts 208.1 and 208.2 and a dielectric-to-dielectric bond between the first and second dielectric layers 206.1 and 206.2. The metal-to-metal bond between the conductive contacts 208.1 and 208.2 comprises, for example, a via-to-via bond, a pad-to-pad bond, or a via-to-pad bond. Example redistribution layers of the example integrated circuit components

[0026] The Fig. 3A to 3B and 3E to 3J show exemplary redistribution layers of exemplary integrated circuit components, according to exemplary embodiments of the present invention. Fig. 3C and Fig. 3D show exemplary redistribution layers that are not part of the invention. A redistribution layer 300, which is shown in Fig. 3A, a redistribution layer 310, which in Fig. 3B, a redistribution layer 318 (not belonging to the invention) which is in Fig. 3C, a redistribution layer 320 (not belonging to the invention) which is in Fig. 3D, a redistribution layer 322, which in Fig. 3E, a redistribution layer 332, which in Fig. 3F, a redistribution layer 334, which in Fig. 3G, a redistribution layer 336, which in Fig. 3H, a redistribution layer 338, which in Fig. 3I, and a redistribution layer 340 shown in Fig. 3J, each represent a conductive layer of one or more conductive layers of a semiconductor stack of an integrated circuit, such as the integrated circuit component 100. The redistribution layer 300, the redistribution layer 310, the redistribution layer 318, the redistribution layer 320, the redistribution layer 322, the redistribution layer 332, the redistribution layer 334, the redistribution layer 336, the redistribution layer 338, and / or the redistribution layer 340 may be used to electrically connect the integrated circuit to other electrical, mechanical, and / or electromechanical components. In the exemplary embodiment shown in Fig. 3A, the redistribution layer 300 has a matrix of first conductive contacts 302. As shown in Fig. 3A, the matrix of first conductive contacts 302 extends along a first direction D1, such as an x-axis of a Cartesian coordinate system, along a first side of the integrated circuit component. Those skilled in the art will appreciate that the matrix of first conductive contacts 302 may alternatively extend along a second direction D2, such as a y-axis of the Cartesian coordinate system, along a second side of the redistribution layer 300 without departing from the spirit and scope of the present invention. In an exemplary embodiment, the matrix of first conductive contacts 302 includes conductive contacts 304.1.1 through 304.ik arranged in an array of i rows and k columns to form a matrix. In some embodiments, the array pitch of the conductive contacts 304.1.1 through 304.ik is about 3 μm to about 5 μm.The conductive contacts 304.1.1 to 304.ik may comprise one or more conductive materials, such as tungsten (W), aluminum (Al), copper (Cu), gold (Au), silver (Ag), or platinum (Pt). However, the conductive contacts 304.1.1 to 304.ik may alternatively or additionally comprise other materials, such as silicides, for example, nickel silicide (NiSi), sodium silicide (Na2Si), magnesium silicide (Mg2Si), platinum silicide (PtSi), titanium silicide (TiSi2), tungsten silicide (WSi2), or molybdenum disilicide (MoSi2), as would be appreciated by those skilled in the art, without departing from the spirit and scope of the present invention.

[0027] In the exemplary embodiment shown in Fig. 3A, the redistribution layer 300 may be bonded to other redistribution layers of other electrical, mechanical, or electromagnetic devices by hybrid bonding, direct bonding, surface-activated bonding, plasma-activated bonding, anodic bonding, eutectic bonding, thermocompression bonding, reactive bonding, transient liquid-phase diffusion bonding, and / or any other known bonding technique known to those skilled in the art without departing from the spirit and scope of the present invention. In this exemplary embodiment, the aforementioned bonding techniques utilize a bond wave to electrically and / or mechanically connect the redistribution layer 300 to other redistribution layers of other electrical, mechanical, and / or electromechanical devices.This configuration and arrangement of the matrix of conductive contacts 302 minimizes discontinuities, such as air bubbles, between these redistribution layers. For example, with this matrix of conductive contacts 302 in the redistribution layer 300, the bonding wave can displace air between the redistribution layer 300 and other redistribution layers of other electrical, mechanical, and / or electromechanical components during bonding of these redistribution layers.

[0028] In the exemplary embodiment shown in Fig. 3B, the redistribution layer 310 includes a matrix of first conductive contacts 312 and a matrix of second conductive contacts 314. As shown in Fig. 3B, the matrix of first conductive contacts 312 extends along the first direction D1, such as the x-axis of the Cartesian coordinate system, along a first side of the integrated circuit component, and the matrix of second conductive contacts 314 extends along the second direction D2, such as the y-axis of the Cartesian coordinate system, along a second side of the integrated circuit component. In an exemplary embodiment, the matrix of first conductive contacts 312 and the matrix of second conductive contacts 314 comprise conductive contacts arranged in a substantially similar manner as in the Fig. 3A. Those skilled in the art will appreciate that other configurations and arrangements for the matrix of first conductive contacts 312 and the matrix of second conductive contacts 314 are possible without departing from the spirit and scope of the present invention. For example, the matrix of first conductive contacts 312 and the matrix of second conductive contacts 314 may extend along the first direction D1 along a first side and a third side of the integrated circuit component, respectively, as shown in Fig. 3C (showing an embodiment not belonging to the invention). As a further example, the matrix of first conductive contacts 312 and the matrix of second conductive contacts 314 may extend along the second direction D2 along the second side and a fourth side of the integrated circuit component, respectively, as shown in Fig. 3D (which shows an embodiment not belonging to the invention).

[0029] In the exemplary embodiment shown in Fig. 3B, the redistribution layer 310 may be bonded to other redistribution layers of other electrical, mechanical, or electromagnetic devices in a substantially similar manner to the redistribution layer 300 described above with reference to Fig. 3B. In this exemplary embodiment, the aforementioned bonding methods utilize a bonding wave to electrically and / or mechanically connect the redistribution layer 310 to other redistribution layers of other electrical, mechanical, and / or electromechanical components. This configuration and arrangement of the matrix of first conductive contacts 312 and the matrix of second conductive contacts 314 minimizes discontinuities, such as air bubbles, between these redistribution layers. For example, with this configuration and arrangement of the matrix of first conductive contacts 312 and the matrix of second conductive contacts 314, the bonding wave may displace air between the redistribution layer 310 and other redistribution layers of other electrical, mechanical, and / or electromechanical components during the bonding of these redistribution layers.

[0030] Furthermore, in the exemplary embodiment shown in Fig. 3B, the redistribution layer 310 includes a gap or exhaust path 316 between the array of first conductive contacts 312 and the array of second conductive contacts 314 to allow air to be displaced during bonding of the redistribution layer 310 and the other redistribution layers of other electrical, mechanical, and / or electromechanical devices. If the exhaust path 316 is not present, that is, if the array of first conductive contacts 312 intersects or overlaps the array of second conductive contacts 314, in some cases, one or more discontinuities may be created near a region in the redistribution layer 310 where the array of first conductive contacts 312 intersects the array of second conductive contacts 314.This intersection traps air during bonding of the redistribution layer 310 and the other redistribution layers of other electrical, mechanical, and / or electromechanical components, thereby creating one or more discontinuities.

[0031] In the exemplary embodiment shown in Fig. 3E, the redistribution layer 322 includes a matrix of first conductive contacts 324, a matrix of second conductive contacts 326, a matrix of third conductive contacts 328, and a matrix of fourth conductive contacts 330. As shown in Fig. 3E, the matrix of first conductive contacts 324 and the matrix of third conductive contacts 328 extend along the first direction D1, such as the x-axis of the Cartesian coordinate system, along first and third sides of the integrated circuit component, respectively. The matrix of second conductive contacts 326 and the matrix of fourth conductive contacts 330 extend along the second direction D2, such as the y-axis of the Cartesian coordinate system, along second and fourth sides of the integrated circuit component, respectively. In an exemplary embodiment, lengths of the matrix of first conductive contacts 324 and the matrix of third conductive contacts 328 in the first direction D1 are less than half a length of the redistribution layer 322 in the first direction D1.Likewise, in this exemplary embodiment, lengths of the matrix of second conductive contacts 326 and the matrix of fourth conductive contacts 330 in the second direction D2 are less than half a length of the redistribution layer 322 in the second direction D2. In another exemplary embodiment, the matrix of first conductive contacts 324, the matrix of second conductive contacts 326, the matrix of third conductive contacts 328, and the matrix of fourth conductive contacts 330 comprise conductive contacts arranged in a substantially similar manner to that shown in FIG. Fig. 3A. Those skilled in the art will recognize that other configurations and arrangements for the matrix of first conductive contacts 324, the matrix of second conductive contacts 326, the matrix of third conductive contacts 328, and the matrix of fourth conductive contacts 330 are possible without departing from the spirit and scope of the present invention. For example, the matrix of first conductive contacts 324 and the matrix of third conductive contacts 328 may be mirrored along an axis of the second direction D2, for example, the y-axis of the Cartesian coordinate system, as shown in Fig. 3F. Furthermore, those skilled in the art will recognize that the redistribution layer 322 need not include all of the matrices from the group consisting of the matrix of first conductive contacts 324, the matrix of second conductive contacts 326, the matrix of third conductive contacts 328, and the matrix of fourth conductive contacts 330 without departing from the spirit and scope of the present invention. For example, the redistribution layer 334 includes the matrix of second conductive contacts 326 and the matrix of fourth conductive contacts 330, as shown in Fig. 3G. For example, the redistribution layer 336 includes the matrix of first conductive contacts 324 extending along the first direction D1 and the matrix of second conductive contacts 326 extending along the second direction D2, as shown in Fig. 3H. For example, the redistribution layer 338 includes the matrix of first conductive contacts 324 extending along the first direction D1 and the matrix of third conductive contacts 328 also extending along the first direction D1, as shown in Fig. 3I. For example, the redistribution layer 340 includes the matrix of first conductive contacts 324 extending along the first direction D1 and the matrix of fourth conductive contacts 330 extending along the second direction D2, as shown in Fig. 3J is shown.

[0032] As experts in the field will continue to recognize, the Fig. 3A shown redistribution layer 300, which in Fig. 3B shown redistribution layer 310, which in Fig. 3E shown redistribution layer 322, which in Fig. 3F shown redistribution layer 332, which in Fig. Redistribution layer 334 shown in Figure 3G, which in Fig. Redistribution layer 336 shown in Figure 3H, which in Fig. 3I shown redistribution layer 338 and / or the one shown in Fig. 3J may be rotated, for example, 90°, 180°, and / or 270° clockwise or counterclockwise to produce other exemplary redistribution layers without departing from the spirit and scope of the present invention. Example redistribution layers of the example semiconductor wafers

[0033] The Fig. 4A to 4I show exemplary semiconductor wafers with exemplary redistribution layers, according to exemplary embodiments of the present invention. Fig. 4A shown semiconductor wafer 400, a Fig. 4B shown semiconductor wafer 410, a Fig. 4C shown semiconductor wafer 420, a Fig. 4D shown semiconductor wafer 430, a Fig. 4E shown semiconductor wafer 440, a Fig. 4F shown semiconductor wafer 450, a Fig. 4G shown semiconductor wafer 460, a Fig. 4H and a semiconductor wafer 470 shown in Fig. 4I each have a plurality of integrated circuit components, such as the integrated circuit components 100.1 to 100.n described above with reference to Fig. 2A. The plurality of integrated circuit components 100.1 to 100.n are covered by a redistribution layer having a plurality of redistribution structures 300.1 to 300.r, wherein the plurality of redistribution structures 300.1 to 300.r have an identical layout. Each redistribution structure 300.1, 300.2 ... or 300.r may have the same layout as the Fig. 3A shown redistribution layer 300, which in Fig. 3B shows the redistribution layer 310, which in Fig. 3E shown redistribution layer 322, which in Fig. 3F shown redistribution layer 332, which in Fig. Redistribution layer 334 shown in Figure 3G, which in Fig. Redistribution layer 336 shown in Figure 3H, which in Fig. 3I shown redistribution layer 338 or the one in Fig. 3J shown redistribution layer 340.

[0034] At the Fig. 4A, the semiconductor wafer 400 includes integrated circuit components 402.1 to 402.r. As shown in Fig. 4A, the integrated circuit components 402.1 to 402.r are each covered by the redistribution structures 300.1 to 300.r of the redistribution layer, wherein each of the redistribution structures 300.1 to 300.r is identical to the one shown in Fig. 3A described redistribution layer 300. In the Fig. 4A, the matrix of first conductive contacts 302 is separated or spaced from the active area 100A by a distance a. The distance a is, for example, about 60 µm to about 70 µm, e.g., about 65 µm. Likewise, the matrix of first conductive contacts 302 is separated or spaced from peripheries or edges of the corresponding redistribution structures 310.1 to 310.r by a distance b. The distance b is, for example, about 60 µm to about 70 µm, e.g., about 65 µm. In an exemplary embodiment, the semiconductor wafer 400 comprises scribe trenches 404.1 to 404.y and scribe trenches 406.1 to 406.x intersecting with the scribe trenches 404.1 to 404.y. In this exemplary embodiment, the semiconductor wafer 400 may be diced along the scribe trenches 404.1 to 404.y and the scribe trenches 406.1 to 406.x to separate the semiconductor wafer 400 into a plurality of singulated integrated circuit components 402.1 to 402.r.to separate. In the exemplary embodiment shown in . Fig. 4A, at most one conductive contact of the matrix of first conductive contacts 302, corresponding to one of the redistribution structures 300.1 to 300.r, is adjacent to the scribe trenches 404.1 to 404.y at a position in the semiconductor wafer 400. As shown in Fig. For example, as shown in Figure 4A, the matrix of first conductive contacts 302 corresponding to the redistribution structure 300.2 disposed above the integrated circuit component 402.2 extends along the scribe trench 404.1 between the integrated circuit component 402.1 and the integrated circuit component 402.2. This configuration and arrangement of the redistribution structures 300.1 to 300.r facilitates the displacement of air during the bonding of the semiconductor wafer 400 and other redistribution layers of other electrical, mechanical, and / or electromechanical components during the bonding of these redistribution layers.

[0035] As in Fig. 4A, any two closest adjacent arrays of first conductive contacts 302 (e.g., a first array of first conductive contacts 302.1 and a second array of first conductive contacts 302.2) aligned with each other in the second direction D2 and each disposed above two adjacent first integrated circuit components (e.g., the integrated circuit components 402.1 and 402.2) are separated from each other by a first distance DS1, wherein the first distance DS1 is greater than a first dimension DM1 of the active area 100A in the second direction D2.

[0036] As in Fig. 4A, the first integrated circuit component 402.1 is closest to the second integrated circuit component 402.2 in the second direction D2, which is substantially perpendicular to the first direction D1. The first matrix of first conductive contacts 302.1 is arranged on the peripheral region 100B of the first integrated circuit component 402.1, while the second matrix of first conductive contacts 302.2 is arranged on the peripheral region 100B of the second integrated circuit component 402.2. The first and second matrixes of first conductive contacts 302.1 and 302.2 extend along the first direction D1 and are substantially aligned with each other in the second direction D2. Furthermore, the first and second matrixes of first conductive contacts 302.1 and 302.2 are separated from each other by a first distance DS1 in the second direction D2.

[0037] As in Fig. 4A, in some embodiments, the first and second arrays of first conductive contacts 302.1 and 302.2 are substantially aligned with each other in the second direction D2, and no other array of conductive contacts is disposed between the first and second arrays of first conductive contacts 302.1 and 302.2.

[0038] In some alternative embodiments, each of the redistribution structures 300.1 to 300.r further comprises a dummy structure DP (e.g., a dummy metal structure) embedded in the dielectric layer, wherein the dummy structure DP is electrically floating and arranged between any two nearest adjacent arrays of first conductive contacts 302. The dummy structure DP comprises, for example, at least one dummy metal pad or a plurality of dummy metal vias arranged in a matrix. The dummy structure DP is spaced from the arrays of first conductive contacts 302 to ensure that no air is trapped between the dummy structure DP and the arrays of first conductive contacts 302. For example, the dummy structure is embedded in the dielectric layer of the redistribution structures 310.1 to 310.r, and it is arranged over the active areas 100A and / or the peripheral areas 100B of the integrated circuit components 412.1 to 402.r. It should be noted that the metal content of the redistribution structures 300.1 to 300.r may affect the process window and the yields of the CMP process for forming the matrices of first conductive contacts 302 due to the charging effect. The thickness uniformity of the matrices of first conductive contacts 302 may be affected by the charging effect if the metal content of the redistribution structures 300.1 to 300.r is low. Thus, the dummy structure DP may improve the process window and the yields of the CMP process for forming the matrices of first conductive contacts 302. In the exemplary embodiment shown in FIG. Fig. 4B, the semiconductor wafer 410 has integrated circuit components 412.1 to 412.r. As shown in Fig. 4B, the integrated circuit components 412.1 to 412.r are each covered by the redistribution structures 310.1 to 310.r of the redistribution layer, wherein the redistribution structures 310.1 to 310.r are each identical to the redistribution layer 310 described above with reference to Fig. 3B. In the exemplary embodiment shown in Fig. As shown in Figure 4B, the matrix of first conductive contacts 312 and the matrix of second conductive contacts 314 are separated or spaced apart from the active area 100A by a distance a. The distance a is, for example, about 60 µm to about 70 µm, e.g., about 65 µm. Likewise, the matrix of first conductive contacts 312 and the matrix of second conductive contacts 314 are separated or spaced apart from peripheries or edges of their respective redistribution structures 310.1 to 310.r by a distance b. The distance b is, for example, about 60 µm to about 70 µm, e.g., about 65 µm. In an exemplary embodiment, the semiconductor wafer 410 comprises horizontal rows of scribe trenches 404.1 to 404.y and vertical columns of scribe trenches 406.1 to 406.x, which were described above with reference to Fig. 4A. In the exemplary embodiment shown in Fig. 4B, at most one conductive contact of the matrix of first conductive contacts 312 corresponding to one of the redistribution structures 310.1 to 310.r is adjacent to the horizontal rows of scribe trenches 404.1 to 404.y at a position in the semiconductor wafer 410, and at most one conductive contact of the matrix of second conductive contacts 314 corresponding to one of the redistribution structures 310.1 to 310.r is adjacent to the vertical columns of scribe trenches 406.1 to 406.x at a position in the semiconductor wafer 410. As shown in Fig. For example, as shown in Figure 4B, the matrix of first conductive contacts 312 corresponding to the redistribution structure 310.2 arranged above the integrated circuit component 412.2 runs along the horizontal row of the scribe trench 404.1 between the integrated circuit component 412.1 and the integrated circuit component 412.2. As another example shown in Fig. As shown in Figure 4B, the matrix of second conductive contacts 314 corresponding to the redistribution structure 310.1 disposed above the integrated circuit component 412.1 extends along the vertical column of scribe trenches 406.1 between the integrated circuit component 412.1 and the integrated circuit component 412.3. This configuration and arrangement of the redistribution structures 310.1 to 310.r facilitates the displacement of air during the bonding of the semiconductor wafer 410 and other redistribution layers of other electrical, mechanical, and / or electromechanical components during the bonding of these redistribution layers.

[0039] As in Fig. 4B, any two closest adjacent arrays of first conductive contacts 312 (e.g., a first array of first conductive contacts 312.1 and a second array of first conductive contacts 312.2) aligned with each other in the second direction D2 and each disposed above two adjacent integrated circuit components (e.g., the integrated circuit components 412.1 and 412.2) are separated from each other by a first distance DS1, wherein the first distance DS1 is greater than a first dimension DM1 of the active area 100A in the second direction D2. In addition, any two nearest adjacent matrices of second conductive contacts 314 (e.g., a first matrix of second conductive contacts 314.1 and a second matrix of second conductive contacts 314.2) that are aligned with each other in the first direction D1 and each disposed over two adjacent integrated circuit components (e.g.,the integrated circuit components 412.1 and 412.3) are separated from each other by a second distance DS2, wherein the second distance DS2 is greater than a second dimension DM2 of the active area 100A in the first direction D1.

[0040] As in Fig. 4B, the first integrated circuit component 412.1 is closest to the second integrated circuit component 412.2 in the second direction D2. The first matrix of first conductive contacts 312.1 is arranged on the peripheral region 100B of the first integrated circuit component 412.1, while the second matrix of first conductive contacts 312.2 is arranged on the peripheral region 100B of the second integrated circuit component 412.2. The first and second matrixes of first conductive contacts 312.1 and 312.2 extend along the first direction D1 and are substantially aligned with each other in the second direction D2. Furthermore, the first and second matrixes of first conductive contacts 312.1 and 312.2 are separated from each other by the first distance DS1 in the second direction D2.

[0041] In some embodiments, the first and second arrays of first conductive contacts 312.1 and 312.2, respectively, are substantially aligned with each other in the second direction D2, and no other array of conductive contacts is disposed between the first and second arrays of first conductive contacts 312.1 and 312.2.

[0042] As in Fig. 4B, the first integrated circuit component 412.1 is closest to the third integrated circuit component 412.3 in the first direction D1. The first matrix of second conductive contacts 314.1 is arranged on the peripheral region 100B of the first integrated circuit component 412.1, while the second matrix of second conductive contacts 314.2 is arranged on the peripheral region 100B of the third integrated circuit component 412.3. The first and second matrixes of second conductive contacts 314.1 and 314.2 extend along the second direction D2 and are substantially aligned with each other in the first direction D1. Furthermore, the first and second matrixes of second conductive contacts 314.1 and 314.2 are separated from each other by the second distance DS2 in the first direction D1.

[0043] In some embodiments, the first and second arrays of second conductive contacts 314.1 and 314.2, respectively, are substantially aligned with each other in the first direction D1, and no other array of conductive contacts is disposed between the first and second arrays of second conductive contacts 314.1 and 314.2.

[0044] In some alternative embodiments, each of the redistribution structures 310.1 to 310.r further comprises a dummy structure (e.g., a dummy metal structure formed in Fig. 4A) embedded in the dielectric layer, wherein the dummy structure is electrically floating and arranged between the matrices of conductive contacts 312 and / or 314. The dummy structure comprises, for example, at least one dummy metal pad or a plurality of dummy metal vias arranged in a matrix. The dummy structure is spaced from the matrices of conductive contacts 312 and / or 314 to ensure that no air is trapped between the dummy structure and the matrices of conductive contacts 312 and / or 314. For example, the dummy structure is embedded in the dielectric layer of the redistribution structures 300.1 to 300.r, and it is arranged over the active areas 100A and / or the peripheral areas 100B of the integrated circuit components 402.1 to 402.r. It should be noted that the metal content of the redistribution structures 310.1 to 310.r may impair the process window and the yields of the CMP process for producing the matrices of conductive contacts 312 and 314 due to the charging effect. The thickness uniformity of the matrices of conductive contacts 312 and 314 may be impaired by the charging effect if the metal content of the redistribution structures 310.1 to 310.r is low. Thus, the dummy structure may improve the process window and the yields of the CMP process for producing the matrices of first conductive contacts 312 and 314.

[0045] In the embodiment not belonging to the invention, which is shown in Fig. 4C, the semiconductor wafer 420 has integrated circuit components 422.1 to 422.r, which interlock with the integrated circuit components 424.1 to 424.s in a finger-like manner. As shown in Fig. 4C, the integrated circuit components 422.1 to 422.r are covered by the redistribution structures 318.1 to 318.r, respectively, wherein the redistribution structures 318.1 to 318.r are each identical to the redistribution layer 318 described above with reference to Fig. 3C. The integrated circuit components 424.1 to 424.s are each covered by the redistribution structures 320.1 to 320.s, wherein the redistribution structures 320.1 to 320.s are each identical to the redistribution layer 320 described above with reference to Fig. 3D has been described. As in Fig. 4C, the redistribution structures 318.1 to 318.r and the redistribution structures 320.1 to 320.s are configured and arranged to optimize the displacement of air during the bonding of the semiconductor wafer 420 and other redistribution layers of other electrical, mechanical, and / or electromechanical components. In the embodiment not belonging to the invention, which is shown in Fig. 4C, the matrix of first conductive contacts 312 of the redistribution structures 318.1 to 318.r is arranged along first sides, for example, top sides, of the redistribution structures 318.1 to 318.r, and the matrix of second conductive contacts 314 of the redistribution structures 318.1 to 318.r is arranged along third sides, for example, bottom sides, of the redistribution structures 318.1 to 318.r. Furthermore, in the embodiment not belonging to the invention, which is shown in Fig. 4C, the matrix of first conductive contacts 312 of the redistribution structures 320.1 to 320.s is arranged along second sides, for example, right sides, of the redistribution structures 320.1 to 320.s, and the matrix of second conductive contacts 314 of the redistribution structures 320.1 to 320.s is arranged along fourth sides, for example, left sides, of the redistribution structures 320.1 to 320.s.

[0046] In an exemplary embodiment, the semiconductor wafer 420 comprises the horizontal rows of scribe trenches 404.1 to 404.y and / or the vertical columns of scribe trenches 406.1 to 406.x, as described above with reference to Fig. 4A. In the embodiment not belonging to the invention, which is shown in Fig. 4C, at most one conductive contact of the matrix of first conductive contacts 312 and / or the matrix of second conductive contacts 314 corresponding to one of the redistribution structures 318.1 to 318.r is adjacent to the horizontal rows of scribe trenches 404.1 to 404.y at a position in the semiconductor wafer 420, and at most one conductive contact of the matrix of first conductive contacts 312 and / or the matrix of second conductive contacts 314 corresponding to one of the redistribution structures 320.1 to 320.s is adjacent to the vertical columns of scribe trenches 406.1 to 406.x at a position in the semiconductor wafer 420. As shown in Fig. 4C, the matrix of second conductive contacts 314, which corresponds to the redistribution structure 318.1 of the integrated circuit component 422.1, runs along the horizontal row of the scribe trench 404.1 between the integrated circuit component 422.1 and the integrated circuit component 424.1. As a further example not belonging to the invention, which is shown in Fig. 4C, the matrix of first conductive contacts 312, corresponding to the redistribution structure 320.1 on the integrated circuit component 424.2, runs along the vertical column of scribe trenches 406.1 between the integrated circuit component 422.1 and the integrated circuit component 424.2. This configuration and arrangement of the redistribution structures 320.1 to 320.r facilitate the displacement of air during the bonding of the semiconductor wafer 420 and other redistribution layers of other electrical, mechanical, and / or electromechanical components during the bonding of these redistribution layers. Furthermore, the aforementioned dummy structure (e.g., the one shown in Fig. 4A shown dummy metal structure) in which Fig. 4C shown embodiment can be used.

[0047] As in Fig. 4D, the semiconductor wafer 430 comprises redistribution structures 322.1 to 322.r, wherein the redistribution structures 322.1 to 322.r are each identical to the redistribution layer 322 described above with reference to Fig. 3E. In the exemplary embodiment shown in Fig. 4D, the matrix of first conductive contacts 324, the matrix of second conductive contacts 326, the matrix of third conductive contacts 328, and the matrix of fourth conductive contacts 330 are separated or spaced apart from the active area 100A by a distance a. The distance a is, for example, about 60 µm to about 70 µm, for example, about 65 µm. Likewise, the matrix of first conductive contacts 324, the matrix of second conductive contacts 326, the matrix of third conductive contacts 328, and the matrix of fourth conductive contacts 330 are separated or spaced apart from peripheries or edges of the corresponding redistribution structures 322.1 to 322.r by a distance b. The distance b is, for example, about 60 µm to about 70 µm, e.g. B. about 65 µm.

[0048] In an exemplary embodiment, the semiconductor wafer 430 includes horizontal rows of scribe trenches 404.1 to 404.y and vertical columns of scribe trenches 406.1 to 406.x, as described above with reference to Fig. 4A. In the exemplary embodiment shown in Fig. 4D, at most one conductive contact of the matrix of first conductive contacts 324 and the matrix of third conductive contacts 328 corresponding to one of the redistribution structures 322.1 to 322.r is adjacent to the horizontal rows of scribe trenches 404.1 to 404.y at a position in the semiconductor wafer 430, and at most one conductive contact of the matrix of second conductive contacts 326 and the matrix of fourth conductive contacts 330 corresponding to one of the redistribution structures 322.1 to 322.r is adjacent to the vertical columns of scribe trenches 406.1 to 406.x at a position in the semiconductor wafer 430. As shown in Fig. 4D, for example, the matrix of third conductive contacts 328 corresponding to the redistribution structure 322.1 of the integrated circuit component 432.1 runs along a first part of the horizontal row of the scribe trench 404.1 between the integrated circuit component 432.1 and the integrated circuit component 432.2, and the matrix of first conductive contacts 324 corresponding to the redistribution structure 322.2 of the integrated circuit component 432.2 runs along a second part of the horizontal row of the scribe trench 404.1 between the integrated circuit component 432.1 and the integrated circuit component 432.2. As another example shown in Fig. 4D, the matrix of second conductive contacts 326 corresponding to the redistribution structure 322.1 of the integrated circuit component 432.1 extends along a first part of the vertical column of the scribe trench 406.1 between the integrated circuit component 432.1 and the integrated circuit component 432.3, and the matrix of fourth conductive contacts 330 corresponding to the redistribution structure 322.3 of the integrated circuit component 432.3 extends along a second part of the vertical column of the scribe trench 406.1 between the integrated circuit component 432.1 and the integrated circuit component 432.3. This configuration and arrangement of the redistribution structures 322.1 to 322.r facilitates the displacement of air during the bonding of the semiconductor wafer 430 and other redistribution layers of other electrical, mechanical and / or electromechanical components during the bonding of these redistribution layers.

[0049] As in Fig. 4D, any two closest adjacent arrays of first conductive contacts 324 (e.g., a first array of first conductive contacts 324.1 and a second array of first conductive contacts 324.2) aligned with each other in the second direction D2 and each disposed above two adjacent integrated circuit components (e.g., the integrated circuit components 432.1 and 432.2) are separated from each other by a first distance DS1, wherein the first distance DS1 is greater than a first dimension DM1 of the active area 100A in the second direction D2. In addition, any two nearest adjacent matrices of second conductive contacts 326 (e.g., a first matrix of second conductive contacts 326.1 and a second matrix of second conductive contacts 326.2) that are aligned with each other in the first direction D1 and each disposed over two adjacent integrated circuit components (e.g.,the integrated circuit components 432.1 and 432.3) are arranged, are separated from each other by a second distance DS2, wherein the second distance DS2 is greater than a second dimension DM2 of the active area 100A in the first direction D1. Any two closest adjacent matrices of third conductive contacts 328 (e.g., a first matrix of third conductive contacts 328.1 and a second matrix of third conductive contacts 328.2) that are aligned with each other in the second direction D2 and are each arranged above two adjacent integrated circuit components (e.g., the integrated circuit components 432.1 and 432.2) are separated from each other by the first distance DS1, wherein the first distance DS1 is greater than the first dimension DM1 of the active area 100A in the second direction D2. In addition, any two closest adjacent matrices of fourth conductive contacts 330 (e.g.,a first matrix of fourth conductive contacts 330.1 and a second matrix of fourth conductive contacts 330.2) aligned with each other in the first direction D1 and each arranged above two adjacent integrated circuit components (e.g., the integrated circuit components 432.1 and 432.3), separated from each other by the second distance DS2, wherein the second distance DS2 is greater than the second dimension DM2 of the active area 100A in the first direction D1.

[0050] As in Fig. 4D, the first integrated circuit component 432.1 is closest to the second integrated circuit component 432.2 in the second direction D2. The first matrix of first conductive contacts 324.1 is arranged on the peripheral region 100B of the first integrated circuit component 432.1, while the second matrix of first conductive contacts 324.2 is arranged on the peripheral region 100B of the second integrated circuit component 432.2. The first and second matrixes of first conductive contacts 324.1 and 324.2 extend along the first direction D1 and are substantially aligned with each other in the second direction D2. Furthermore, the first and second matrixes of first conductive contacts 324.1 and 324.2 are separated from each other by the first distance DS1 in the second direction D2. Likewise, the first matrix of third conductive contacts 328.1 is arranged on the peripheral region 100B of the first integrated circuit component 432.1, while the second matrix of third conductive contacts 328.2 is arranged on the peripheral region 100B of the second integrated circuit component 432.2. The first and second matrixes of third conductive contacts 328.1 and 328.2 run along the first direction D1 and are substantially aligned with each other in the second direction D2. Furthermore, the first and second matrixes of third conductive contacts 328.1 and 328.2 are separated from each other by the first distance DS1 in the second direction D2. Furthermore, the first and second matrixes of first conductive contacts 324.1 and 324.2 are not aligned with the first and second matrixes of third conductive contacts 328.1 and 328.2 in the second direction D2.

[0051] As in Fig. 4D, the first integrated circuit component 432.1 is closest to the third integrated circuit component 432.3 in the first direction D1. The first matrix of second conductive contacts 326.1 is arranged on the peripheral region 100B of the first integrated circuit component 432.1, while the second matrix of second conductive contacts 326.2 is arranged on the peripheral region 100B of the third integrated circuit component 432.3. The first and second matrixes of second conductive contacts 326.1 and 326.2 extend along the second direction D2 and are substantially aligned with each other in the first direction D1. Furthermore, the first and second matrixes of second conductive contacts 326.1 and 326.2 are separated from each other by the second distance DS2 in the first direction D1. Likewise, the first matrix of fourth conductive contacts 330.1 is arranged on the peripheral region 100B of the first integrated circuit component 432.1, while the second matrix of fourth conductive contacts 330.2 is arranged on the peripheral region 100B of the third integrated circuit component 432.3. The first and second matrixes of fourth conductive contacts 330.1 and 330.2 run along the second direction D2 and are substantially aligned with each other in the first direction D1. Furthermore, the first and second matrixes of fourth conductive contacts 330.1 and 330.2 are separated from each other by the second distance DS2 in the first direction D1. Furthermore, the first and second matrixes of second conductive contacts 326.1 and 326.2 are not aligned with the first and second matrixes of fourth conductive contacts 330.1 and 330.2 in the first direction D1.

[0052] In some embodiments, the first matrix of first conductive contacts 324.1 and the second matrix of first conductive contacts 324.2 are substantially aligned with each other in the second direction D2, and no other matrix of conductive contacts is arranged between the first and second matrix of first conductive contacts 324.1 and 324.2. In some embodiments, the first matrix of second conductive contacts 326.1 and the second matrix of second conductive contacts 326.2 are substantially aligned with each other in the first direction D1, and no other matrix of conductive contacts is arranged between the first and second matrix of second conductive contacts 326.1 and 326.2. In some embodiments, the first matrix of third conductive contacts 328.1 and the second matrix of third conductive contacts 328.2 are substantially aligned with each other in the second direction D2, and no other matrix of conductive contacts is arranged between the first and second matrix of third conductive contacts 328.1 and 328.2. Likewise, the first matrix of fourth conductive contacts 330.1 and the second matrix of fourth conductive contacts 330.2 are substantially aligned with each other in the first direction D1, and no other matrix of conductive contacts is arranged between the first and second matrix of fourth conductive contacts 330.1 and 330.2.

[0053] In some alternative embodiments, each of the redistribution structures 322.1 to 322.r further comprises a dummy structure (e.g., the dummy metal structure shown in Fig. 4A) embedded in the dielectric layer, wherein the dummy structure is electrically floating and disposed between the matrices of first conductive contacts 324, 326, 328, and / or 330. The dummy structure is spaced apart from the matrices of first conductive contacts 324, 326, 328, and / or 330 to ensure that no air is trapped between the dummy structure and the matrices of first conductive contacts 324, 326, 328, and / or 330. For example, the dummy structure is embedded in the dielectric layer of the redistribution structures 322.1 to 322.r, and is disposed over the active areas 100A and / or the peripheral areas 100B of the integrated circuit components 432.1 to 432.r. It should be noted that the metal content of the redistribution structures 322.1 to 322.r may impair the process window and the yields of the CMP process for producing the matrices of first conductive contacts 324, 326, 328, and / or 330 due to the charging effect when the metal content of the redistribution structures 322.1 to 322.r is low. Thus, the dummy structure may improve the process window and the yields of the CMP process for producing the matrices of first conductive contacts 324, 326, 328, and 330.

[0054] As in Fig. 4E, the semiconductor wafer 440 comprises redistribution structures 332.1 to 332.r, wherein the redistribution structures 332.1 to 332.r are each identical to the redistribution layer 332 described above with reference to Fig. 3F. In the exemplary embodiment shown in Fig. 4E, the matrix of first conductive contacts 324, the matrix of second conductive contacts 326, the matrix of third conductive contacts 328, and the matrix of fourth conductive contacts 330 are separated or spaced from the active area 100A by a distance a. The distance a is, for example, about 60 µm to about 70 µm, for example, about 65 µm. Likewise, the matrix of first conductive contacts 324, the matrix of second conductive contacts 326, the matrix of third conductive contacts 328, and the matrix of fourth conductive contacts 330 are separated or spaced from peripheries or edges of the corresponding redistribution structures 332.1 to 332.r by a distance b. The distance b is, for example, about 60 µm to about 70 µm, e.g. B. about 65 µm.The arrangement of the matrix of first conductive contacts 324, the matrix of second conductive contacts 326, the matrix of third conductive contacts 328, and the matrix of fourth conductive contacts 330 in the semiconductor wafer 440 is similar to the arrangement in the semiconductor wafer 430 except for the positions of the matrix of first conductive contacts 324 and the matrix of third conductive contacts 328.

[0055] In an exemplary embodiment, the semiconductor wafer 440 comprises horizontal rows of scribe trenches 404.1 to 404.y and / or vertical columns of scribe trenches 406.1 to 406.x, as described above with reference to Fig. 4A. In the exemplary embodiment shown in Fig. 4E, at most one conductive contact of the matrix of first conductive contacts 324 and the matrix of third conductive contacts 328 corresponding to one of the redistribution structures 332.1 to 332.r is adjacent to the horizontal rows of scribe trenches 404.1 to 404.y at a position in the semiconductor wafer 440, and at most one conductive contact of the matrix of second conductive contacts 326 and the matrix of fourth conductive contacts 330 corresponding to one of the redistribution structures 332.1 to 332.r is adjacent to the vertical columns of scribe trenches 406.1 to 406.x at a position in the semiconductor wafer 440. As shown in Fig. 4E, for example, the matrix of third conductive contacts 328 corresponding to the redistribution structure 332.1 of the integrated circuit component 442.1 runs along a first part of the horizontal row of the scribe trench 404.1 between the integrated circuit component 442.1 and the integrated circuit component 442.2, and the matrix of first conductive contacts 324 corresponding to the redistribution structure 332.2 of the integrated circuit component 442.2 runs along a second part of the horizontal row of the scribe trench 404.1 between the integrated circuit component 442.1 and the integrated circuit component 442.2. As another example shown in Fig. As shown in Figure 4E, the matrix of second conductive contacts 326 corresponding to the redistribution structure 332.1 of the integrated circuit component 442.1 extends along a first part of the vertical column of the scribe trench 406.1 between the integrated circuit component 442.1 and the integrated circuit component 442.3, and the matrix of fourth conductive contacts 330 corresponding to the redistribution structure 332.3 of the integrated circuit component 442.3 extends along a second part of the vertical column of the scribe trench 406.1 between the integrated circuit component 442.1 and the integrated circuit component 442.3. This configuration and arrangement of the redistribution structures 332.1 to 332.r facilitates the displacement of air during bonding of the semiconductor wafer 440 and other redistribution layers of other electrical, mechanical and / or electromechanical components during bonding of these redistribution layers.

[0056] As in Fig. 4F, the semiconductor wafer 450 comprises redistribution structures 334.1 to 334.r, wherein the redistribution structures 334.1 to 334.r are each identical to the redistribution layer 334 described above with reference to Fig. 3G. In the exemplary embodiment shown in Fig. As shown in FIG. 4F, the matrix of second conductive contacts 326 and the matrix of fourth conductive contacts 330 are separated or spaced apart from the active area 100A in the semiconductor stack by a distance a. The distance a is, for example, about 60 µm to about 70 µm, e.g., about 65 µm. Likewise, the matrix of second conductive contacts 326 and the matrix of fourth conductive contacts 330 are separated or spaced apart from peripheries or edges of their respective redistribution structures 334.1 to 334.r by a distance b. The distance b is, for example, about 60 µm to about 70 µm, e.g., about 65 µm.The arrangement of the matrix of second conductive contacts 326 and the matrix of fourth conductive contacts 330 in the semiconductor wafer 450 is the same as in the semiconductor wafer 430, and therefore, the detailed descriptions of the matrix of second conductive contacts 326 and the matrix of fourth conductive contacts 330 in the semiconductor wafer 450 are omitted.

[0057] In an exemplary embodiment, the semiconductor wafer 450 comprises the horizontal rows of scribe trenches 404.1 to 404.y and / or the vertical columns of scribe trenches 406.1 to 406.x, as described above with reference to Fig. 4A. In the exemplary embodiment shown in Fig. 4F, at most one conductive contact of the matrix of second conductive contacts 326 and the matrix of fourth conductive contacts 330 corresponding to one of the redistribution structures 334.1 to 334.r is adjacent to the vertical columns of scribe trenches 406.1 to 406.x at a position in the semiconductor wafer 450. As shown in Fig. As shown in Figure 4F, the matrix of second conductive contacts 326, corresponding to the redistribution structure 334.1 of the integrated circuit component 452.1, extends along a first part of the vertical column of the scribe trench 406.1 between the integrated circuit component 452.1 and the integrated circuit component 452.2, and the matrix of fourth conductive contacts 330, corresponding to the redistribution structure 334.3 of the integrated circuit component 452.2, extends along a second part of the vertical column of the scribe trench 406.1 between the integrated circuit component 452.1 and the integrated circuit component 452.2. This configuration and arrangement of the redistribution structures 334.1 to 334.r facilitates the displacement of air during bonding of the semiconductor wafer 450 and other redistribution layers of other electrical, mechanical and / or electromechanical components during bonding of these redistribution layers.

[0058] As in Fig. 4G, the semiconductor wafer 460 has redistribution structures 336.1 to 336.r. In the exemplary embodiment shown in Fig. As shown in FIG. 4G, the matrix of first conductive contacts 324 and the matrix of second conductive contacts 326 are separated or spaced apart from the active area 100A in the semiconductor stack by a distance a. The distance a is, for example, about 60 µm to about 70 µm, for example, about 65 µm. Likewise, the matrix of first conductive contacts 324 and the matrix of second conductive contacts 326 are separated or spaced apart from peripheries or edges of the respective redistribution structures 336.1 to 336.r by a distance b. The distance b is, for example, about 60 µm to about 70 µm, e.g., about 65 µm.The arrangement of the matrix of first conductive contacts 324 and the matrix of second conductive contacts 326 in the semiconductor wafer 460 is the same as in the semiconductor wafer 430, and therefore, the detailed descriptions of the matrix of first conductive contacts 324 and the matrix of second conductive contacts 326 in the semiconductor wafer 460 are omitted.

[0059] As in Fig. 4H, the semiconductor wafer 470 has redistribution structures 338.1 to 338.r. In the exemplary embodiment shown in Fig. As shown in Figure 4H, the matrix of first conductive contacts 324 and the matrix of third conductive contacts 328 are separated or spaced apart from the active area 100A in the semiconductor stack by a distance a. The distance a is, for example, about 60 µm to about 70 µm, e.g., about 65 µm. Likewise, the matrix of first conductive contacts 324 and the matrix of third conductive contacts 328 are separated or spaced apart from peripheries or edges of their respective redistribution structures 338.1 to 338.r by a distance b. The distance b is, for example, about 60 µm to about 70 µm, e.g., about 65 µm.The arrangement of the matrix of first conductive contacts 324 and the matrix of third conductive contacts 328 in the semiconductor wafer 470 is the same as in the semiconductor wafer 430, and therefore, the detailed descriptions of the matrix of first conductive contacts 324 and the matrix of third conductive contacts 328 in the semiconductor wafer 470 are omitted.

[0060] As in Fig. 4I, the semiconductor wafer 480 comprises redistribution structures 340.1 to 340.r. In the exemplary embodiment shown in Fig. As shown in FIG. 4I, the matrix of first conductive contacts 324 and the matrix of fourth conductive contacts 330 are separated or spaced apart from the active area 100A in the semiconductor stack by a distance a. The distance a is, for example, about 60 µm to about 70 µm, e.g., about 65 µm. Likewise, the matrix of first conductive contacts 324 and the matrix of fourth conductive contacts 330 are separated or spaced apart from peripheries or edges of their respective redistribution structures 340.1 to 340.r by a distance b. The distance b is, for example, about 60 µm to about 70 µm, e.g., about 65 µm.The arrangement of the matrix of first conductive contacts 324 and the matrix of fourth conductive contacts 330 in the semiconductor wafer 480 is the same as in the semiconductor wafer 430, and therefore the detailed descriptions of the matrix of first conductive contacts 324 and the matrix of fourth conductive contacts 330 in the semiconductor wafer 480 are omitted.

[0061] In addition, the aforementioned dummy structure (e.g. the one in Fig. 4A) may be used in the embodiments described in the Fig. 4E to 4J are shown. Example production of the example semiconductor wafers

[0062] Fig. 5 shows a flowchart of exemplary steps for manufacturing the exemplary semiconductor wafers with the exemplary integrated circuit components, according to an exemplary embodiment of the present invention. The invention is not limited to this description of steps. Those skilled in the art will appreciate that other process flows are within the spirit and scope of the present invention. An exemplary process flow 500 for manufacturing a semiconductor wafer, such as semiconductor wafer 200, is described below.

[0063] In step 502, in the exemplary process flow 500, a first semiconductor wafer is manufactured. In the exemplary process flow 500, a plurality of integrated circuit components, such as the integrated circuit components 100.1 to 100.n, are manufactured on a semiconductor substrate, such as the semiconductor substrate 202, using a first predetermined sequence of photographic and / or chemical processing steps to produce the first semiconductor wafer. The first predetermined sequence of photographic and / or chemical processing steps may include deposition, removal, patterning, and modification. Deposition is a process used to grow, deposit, or otherwise transfer a material onto the semiconductor substrate and may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), and / or molecular beam epitaxy (MBE).Ablation is a process used to remove material from the semiconductor substrate and may include, for example, wet etching, dry etching, and / or chemical mechanical planarization (CMP). Patterning, often referred to as lithography, is a process for shaping or altering the semiconductor substrate material to create various geometric shapes for the analog and / or digital circuitry for the electronic device. Electrical modification is a process for changing the physical, electrical, and / or chemical properties of the semiconductor substrate material, usually through ion implantation.

[0064] In step 504, in the exemplary process flow 500, a second semiconductor wafer is manufactured. In the exemplary process flow 500, a plurality of integrated circuit components, such as the integrated circuit components 100.1 to 100.n, are manufactured on a semiconductor substrate, such as the semiconductor substrate 202, using a second predetermined sequence of photographic and / or chemical processing steps to produce the second semiconductor wafer. The second predetermined sequence of photographic and / or chemical processing steps may include the deposition, removal, patterning, and modification described above in step 502.

[0065] In step 506, in the exemplary process flow 500, the first semiconductor wafer from step 502 and the second semiconductor wafer from step 504 are cleaned. In the exemplary process flow 500, foreign matter is removed from a first redistribution layer of the first semiconductor wafer from step 502 and from a second redistribution layer of the second semiconductor wafer from step 504. In the exemplary process flow 500, dry cleaning, such as plasma treatments, ultraviolet cleaning, and / or ozone cleaning, and / or a wet chemical cleaning process may be used to remove the foreign matter.

[0066] In step 508, in the exemplary process flow 500, the first semiconductor wafer from step 502 and the second semiconductor wafer from step 504 are aligned. In the exemplary process flow 500, the first redistribution layer of the first semiconductor wafer from step 502 and the second redistribution layer of the second semiconductor wafer from step 504 are aligned for bonding. In the exemplary process flow 500, the first redistribution layer of the first semiconductor wafer from step 502 is a mirror image, or substantially a mirror image, of the second redistribution layer of the second semiconductor wafer from step 504 to enable bonding.

[0067] In step 510, the exemplary process flow 500 bonds the first semiconductor wafer from step 502 and the second semiconductor wafer from step 504. The exemplary process flow 500 uses the following methods to bond the first semiconductor wafer from step 502 and the second semiconductor wafer from step 504: hybrid bonding, direct bonding, surface-activated bonding, plasma-activated bonding, anodic bonding, eutectic bonding, thermocompression bonding, reactive bonding, transient liquid-phase diffusion bonding, and / or any other known bonding method known to those skilled in the art without departing from the spirit and scope of the present invention.

[0068] In step 512, after performing the bonding process (ie, step 510) in the exemplary process flow 500, a dicing process is performed on the bonded first and second semiconductor wafers (ie, the bonded structure 210 shown in Fig. 2C) to produce single-chip semiconductor devices. Concluding remark

[0069] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims.

Claims

[1] A method of manufacturing a semiconductor device comprising the following steps: Providing a first semiconductor structure with first integrated circuit components (100.1, 402.1, 412.1, 432.1), wherein the first integrated circuit components (100.1, 402.1, 412.1, 432.1) each have an active region (100A) and a peripheral region (100B) surrounding the active region (100A); Producing a first redistribution layer (104.1, 204.1) over the first semiconductor structure, wherein the first redistribution layer (104.1, 204.1) comprises a dielectric layer (206, 206.1) and matrices of first conductive contacts (302, 302.1, 302.2, 312, 312.1, 312.2, 324, 324.1, 324.2) embedded in the dielectric layer (206, 206.1), wherein the matrices of first conductive contacts (302, 302.1, 302.2, 312, 312.1, 312.2, 324, 324.1, 324.2) are each arranged on a first region of the peripheral region (100B) and extend along a first direction (D1), wherein any two nearest adjacent matrices of first conductive contacts (302, 302.1, 302.2, 312, 312.1, 312.2, 324, 324.1, 324.2) which are aligned with each other in a second direction (D2) and each on two adjacent first integrated circuit components (100.1, 402.1, 412.1, 432.1) are arranged spaced apart from one another by a first distance (DS1), the first distance (DS1) being greater than a first dimension (DM1) of the active region (100A) in the second direction (D2), the second direction (D2) being substantially perpendicular to the first direction (D1), no other matrix of conductive contacts being arranged between any two nearest adjacent matrices of first conductive contacts (302, 302.1, 302.2, 312, 312.1, 312.2, 324, 324.1, 324.2);. Providing a second semiconductor structure; forming a second redistribution layer (104.2, 204.2) over the second semiconductor structure; and Performing a bonding process for bonding the first and second redistribution layers (104.2, 204.2) to produce a bonded structure (210). [2] The method of claim 1, wherein the first redistribution layer (104.1, 204.1) further comprises matrices of second conductive contacts (314, 314.1, 314.2, 326, 326.1, 326.2) embedded in the dielectric layer (206, 206.1), the matrices of second conductive contacts (314, 314.1, 314.2, 326, 326.1, 326.2) each being arranged on a second region of the peripheral region (100B) and extending along the second direction (D2), any two nearest adjacent matrices of second conductive contacts (314, 314.1, 314.2, 326, 326.1, 326.2) that are arranged relative to each other in the first direction (D1) and are each located on different first integrated circuit components (100.1, 402.1, 412.1, 432.1) are arranged at a second distance (DS2) from each other, wherein the second distance (DS2) is greater than a second dimension (DM2) of the active area (100A) in the first direction (D1), wherein no other matrix of conductive contacts is arranged between any two nearest adjacent matrices of second conductive contacts (314, 314.1, 314.2, 326, 326.1, 326.2). [3] The method of claim 1 or 2, wherein the first redistribution layer (104.1, 204.1) further comprises matrices of third conductive contacts (328, 328.1, 328.2) embedded in the dielectric layer (206, 206.1), the matrices of third conductive contacts (328, 328.1, 328.2) each being arranged on a third region of the peripheral region (100B) and extending along the first direction (D1), any two nearest adjacent matrices of third conductive contacts (328, 328.1, 328.2) aligned with each other in the second direction (D2) and each being arranged on different first integrated circuit components (100.1, 402.1, 412.1, 432.1) are spaced apart from one another by a third distance, the third distance being greater than the first dimension (DM1), wherein no other matrix of conductive contacts is arranged between any two nearest adjacent matrices of third conductive contacts (328, 328.1, 328.2). [4] The method of any one of the preceding claims, wherein the first redistribution layer (104.1, 204.1) further comprises matrices of fourth conductive contacts (330, 330.1, 330.2) embedded in the dielectric layer (206, 206.1), the matrices of fourth conductive contacts (330, 330.1, 330.2) each being arranged on a fourth region of the peripheral region (100B) and extending along the second direction (D2), any two nearest adjacent matrices of fourth conductive contacts (330, 330.1, 330.2) aligned with each other in the first direction (D1) and each being arranged on different first integrated circuit components (100.1, 402.1, 412.1, 432.1) are spaced apart from each other by a fourth distance, the fourth distance being greater than the second dimension (DM2) of the active region (100A) in the first direction (D1), wherein no other matrix of conductive contacts is arranged between any two nearest adjacent matrices of fourth conductive contacts (330, 330.1, 330.2). [5] A method according to any one of the preceding claims, further comprising: after performing the bonding process, performing a dicing process on the bonded structure (210) to produce dicing semiconductor devices. [6] A method according to any one of the preceding claims, wherein during the bonding process a bonding wave is used for the first and second semiconductor structures to displace air between the first and second redistribution layers (104.2, 204.2). [7] Method according to one of the preceding claims, wherein after performing the bonding process, a bonding interface between the first redistribution layer (104.1, 204.1) and the second redistribution layer (104.2, 204.2) in the bonded structure (210) is free of voids. [8] A method of manufacturing a semiconductor device comprising the following steps: Providing a first semiconductor structure having a first integrated circuit component (100.1, 402.1, 412.1, 432.1) and a second integrated circuit component (100.2, 402.2, 412.2, 432.2), wherein the first and second integrated circuit components (100.2, 402.2, 412.2, 432.2) each have an active region (100A) and a peripheral region (100B) surrounding the active region (100A); Producing a first redistribution layer (104.1, 204.1) over the first semiconductor structure, wherein the first redistribution layer (104.1, 204.1) comprises a dielectric layer (206, 206.1), a first matrix of first conductive contacts (302.1, 312.1, 324.1) embedded in the dielectric layer (206, 206.1), and a second matrix of first conductive contacts (302.2, 312.2, 324.2) embedded in the dielectric layer (206, 206.1), wherein the first matrix of first conductive contacts (302.1, 312.1, 324.1) is formed on the peripheral region (100B) of the first integrated circuit component (100.1, 402.1, 412.1, 432.1), the second matrix of first conductive contacts (302.2, 312.2, 324.2) is arranged on the peripheral region (100B) of the second integrated circuit component (100.2, 402.2, 412.2, 432.2), the first and second matrix of first conductive contacts (302.1, 302.2, 312.1, 312.2, 324.1, 324.2) run along a first direction (D1), the first integrated circuit component (100.1, 402.1, 412.1, 432.1) is closest to the second integrated circuit component (100.2, 402.2, 412.2, 432.2) in a second direction (D2) which is substantially perpendicular to the first direction (D1), wherein the first and second arrays of first conductive contacts (302.1, 302.2, 312.1, 312.2, 324.1, 324.2) aligned with each other in the second direction (D2) are spaced apart from each other by a first distance (DS1) in the second direction (D2), wherein the first distance (DS1) is greater than a first dimension (DM1) of the active area (100A) in the second direction (D2), wherein no other array of conductive contacts is arranged between the first matrix of first conductive contacts (302.1, 312.1, 324.1) and the second matrix of first conductive contacts (302.2, 312.2, 324.2);. Providing a second semiconductor structure; forming a second redistribution layer (104.2, 204.2) over the second semiconductor structure; and Performing a bonding process for bonding the first and second redistribution layers (104.2, 204.2) to produce a bonded structure (210). [9] The method of claim 8, wherein the first redistribution layer (104.1, 204.1) further comprises: a first matrix of second conductive contacts (314.1, 326.1) embedded in the dielectric layer (206, 206.1); and a second matrix of second conductive contacts (314.2, 326.2) embedded in the dielectric layer (206, 206.1), wherein the first matrix of second conductive contacts (314.1, 326.1) is arranged on the peripheral region (100B) of the first integrated circuit component (100.1, 402.1, 412.1, 432.1), the second matrix of second conductive contacts (314.1, 326.2) is arranged on the peripheral region (100B) of the second integrated circuit component (100.2, 402.2, 412.2, 432.2), the first and second matrix of second conductive contacts (314.1, 314.2, 326.1, 326.2) run along the second direction (D2) and the first and second matrix of second conductive contacts (314.1, 314.2, 326.1, 326.2) aligned with each other in the first direction (D1), are spaced apart from each other by a second distance (DS2), wherein the second distance (DS2) is greater than a second dimension (DM2) of the active area (100A) in the first direction (D1), wherein no other matrix of conductive contacts is arranged between the first matrix of second conductive contacts (314.1, 326.1) and the second matrix of second conductive contacts (314.2, 326.2). [10] The method of claim 8, wherein the first redistribution layer (104.1, 204.1) further comprises: a first matrix of third conductive contacts (328.1) embedded in the dielectric layer (206, 206.1); and a second matrix of third conductive contacts (328.2) embedded in the dielectric layer (206, 206.1), wherein the first matrix of third conductive contacts (328.1) is arranged on the peripheral region (100B) of the first integrated circuit component (100.1, 402.1, 412.1, 432.1), the second matrix of third conductive contacts (328.2) is arranged on the peripheral region (100B) of the second integrated circuit component (100.2, 402.2, 412.2, 432.2), the first and the second matrix of third conductive contacts (328.1, 328.2) run along the first direction (D1), and the first and the second matrix of third conductive contacts (328.1, 328.2) aligned with each other in the second direction (D2), are spaced apart from each other by a third distance, the third distance being greater than the first dimension (DM1), wherein no other matrix of conductive contacts is arranged between the first matrix of third conductive contacts (328.1) and the second matrix of third conductive contacts (328.2). [11] The method of claim 8, wherein the first redistribution layer (104.1, 204.1) further comprises: a first matrix of fourth conductive contacts (330.1) embedded in the dielectric layer (206, 206.1); and a second matrix of fourth conductive contacts (330.2) embedded in the dielectric layer (206, 206.1), wherein the first matrix of fourth conductive contacts (330.1) is arranged on the peripheral region (100B) of the first integrated circuit component (100.1, 402.1, 412.1, 432.1), the second matrix of fourth conductive contacts (330.2) is arranged on the peripheral region (100B) of the second integrated circuit component (100.2, 402.2, 412.2, 432.2), the first and the second matrix of fourth conductive contacts (330, 330.1, 330.2) run along the second direction (D2), and the first and the second matrix of fourth conductive contacts (330.1, 330.2) aligned with each other in the first direction (D1), are spaced apart from each other by a fourth distance, the fourth distance being greater than a second dimension (DM2) of the active area (100A) in the first direction (D1), wherein no other matrix of conductive contacts is arranged between the first matrix of fourth conductive contacts (330.1) and the second matrix of fourth conductive contacts (330.2). [12] A method according to any one of claims 8 to 11, further comprising: after performing the bonding process, performing a dicing process on the bonded structure (210) to produce dicing semiconductor devices. [13] The method of any one of claims 8 to 12, wherein during the bonding process a bonding wave is used for the first and second semiconductor structures to displace air between the first and second redistribution layers (104.2, 204.2). [14] Method according to one of claims 8 to 13, wherein after performing the bonding process, a bonding interface between the first redistribution layer (104.1, 204.1) and the second redistribution layer (104.2, 204.2) in the bonded structure (210) is free of voids. [15] Semiconductor device comprising: a first semiconductor structure having first integrated circuit components (100.1, 402.1, 412.1, 432.1), wherein the first integrated circuit components (100.1, 402.1, 412.1, 432.1) each have an active region (100A) and a peripheral region (100B) surrounding the active region (100A); a first redistribution layer (104.1, 204.1) arranged above the first semiconductor structure, wherein the first redistribution layer (104.1, 204.1) comprises a dielectric layer (206, 206.1) and matrices of first conductive contacts (302, 302.1, 302.2, 312, 312.1, 312.2, 324, 324.1, 324.2) embedded in the dielectric layer (206, 206.1), wherein the matrices of first conductive contacts (302, 302.1, 302.2, 312, 312.1, 312.2, 324, 324.1, 324.2) are each arranged on a first region of the peripheral region (100B) are arranged and run along a first direction (D1), wherein any two nearest adjacent matrices of first conductive contacts (302, 302.1, 302.2, 312, 312.1, 312.2, 324, 324.1, 324.2), which are aligned with each other in a second direction (D2) and each on two adjacent first integrated circuit components (100.1, 402.1, 412.1, 432.1) are arranged at a distance from each other, the distance being greater than a first dimension (DM1) of the active area (100A) in the second direction (D2), the second direction (D2) being substantially perpendicular to the first direction (D1), no other matrix of conductive contacts being arranged between any two nearest adjacent matrices of first conductive contacts (302, 302.1, 302.2, 312, 312.1, 312.2, 324, 324.1, 324.2);. a second semiconductor structure; and a second redistribution layer arranged over the second semiconductor structure, wherein a structure of the matrices of first conductive contacts (302, 302.1, 302.2, 312, 312.1, 312.2, 324, 324.1, 324.2) is largely similar to a structure of the matrices of second conductive contacts (314, 314.1, 314.2, 326, 326.1, 326.2) in the second redistribution layer (104.2, 204.2), and the first and second semiconductor structures are connected by the first and second redistribution layers (104.2, 204.2). [16] The semiconductor device of claim 15, wherein the first semiconductor structure comprises a first semiconductor substrate (101.1, 202) and a first interconnect structure (102.1) disposed on the first semiconductor substrate (101.1), and the arrays of first conductive contacts (302, 302.1, 302.2, 312, 312.1, 312.2, 324, 324.1, 324.2) are electrically connected to the first interconnect structure (102.1). [17] The semiconductor device according to claim 15 or 16, wherein a bonding interface between the first redistribution layer (104.1, 204.1) and the second redistribution layer (104.2, 204.2) is free of voids. [18] A semiconductor device according to any one of claims 15 to 17, wherein the first integrated circuit components (100.1, 402.1, 412.1, 432.1) are arranged in a matrix on a first semiconductor wafer (200.1), the second semiconductor structure comprises second integrated circuit components (100.2, 402.2, 412.2, 432.2) arranged in a matrix on a second semiconductor wafer (200.2), and the first integrated circuit components (100.1, 402.1, 412.1, 432.1) are each bonded to one of the second integrated circuit components (100.2, 402.2, 412.2, 432.2). [19] A semiconductor device according to any one of claims 15 to 18, wherein the arrays of first conductive contacts (302, 302.1, 302.2, 312, 312.1, 312.2, 324, 324.1, 324.2) are each configured and arranged in a plurality of rows and a plurality of columns. [20] The semiconductor device of claim 19, wherein an array pitch of each of the arrays of first conductive contacts (302, 302.1, 302.2, 312, 312.1, 312.2, 324, 324.1, 324.2) is about 3 µm to about 5 µm.

Images