TRANSISTOR ELEMENT WITH A BURIED INSULATING LAYER WITH ADDED FUNCTION

Abstract

Transistor element (100A), with a channel region (131) formed in a semiconductor layer (130, 130N, 130P) and arranged laterally between a drain region (133) and a source region (132); a control gate electrode structure (120) formed on the channel region (131); a buried insulating layer stack (110) formed below the semiconductor layer (131) comprising at least two different dielectric material layers (111, 113) and a charge-trapping layer (112); and a semiconductor body region (102N, 102P) formed below the buried insulating layer stack (110) and connected to receive a control voltage, wherein the semiconductor body region (102N, 102P) comprises a doped region (102N) for setting a type of charge carrier to be trapped in the charge-trapping layer (112) and the semiconductor body region (102N, 102P) has a further doped region (102P) for setting a type of charge carrier to be trapped in the charge-capture layer (112), wherein the further doped region (102P) is of inverse conductivity type compared to the doped region (102N).

Description

BACKGROUND 1. AREA OF REVELATION

[0001] The present disclosure relates generally to semiconductor devices with transistor elements that are manufactured on the basis of an SOI (semiconductor-on-insulator) architecture, i.e., which have a buried insulating layer. 2. DESCRIPTION OF THE STATE OF THE ART

[0002] Significant progress has been made in the field of semiconductor devices, particularly with regard to small-signal processing and power applications. In particular, the continuous scaling of critical semiconductor device dimensions has contributed to remarkable improvements in the overall complexity of analog and digital circuits, such as microcontrollers, CPUs, GPUs, and the like. Complex microprocessors can contain up to several hundred million or even over a billion individual transistor elements forming one or more complex circuits. In addition to the continuous reduction of the critical dimensions of transistor elements that form the backbone of complex circuits, various other aspects have been considered to promote improved performance.For example, when attempts are made to further improve certain aspects of circuit behavior, such as signal processing speed, power consumption, information density, processability, and the like, various approaches have been pursued to address these diverse aspects. For instance, when critical dimensions of field-effect transistors, such as the gate length, are continuously reduced—currently on the order of 30 nm or less in demanding small-signal applications—certain measures must be implemented to combat the various negative effects associated with the reduced gate length.In this respect, reduced channel controllability for short channel lengths, fluctuations in dopant concentration in channel regions, and the like can represent some of the adverse effects that must be addressed to fully exploit the advantages associated with a reduced gate length. Similarly, with regard to reduced overall power consumption, static and dynamic leakage currents can increasingly lead to undesirable transistor behavior.

[0003] Regarding some of the side effects of reducing critical transistor dimensions, certain approaches have been pursued, leading to more advanced and complex integrated circuits. However, each of these diverse approaches can still introduce certain disadvantages, while offering better results in other aspects related to the aforementioned side effects. For example, three-dimensional transistor architectures have been developed to provide improved channel controllability and increased forward current without unnecessarily affecting or further reducing the overall transistor dimensions. On the other hand, such solutions can significantly contribute to overall process complexity, making these approaches less desirable for applications requiring low cost at high circuit complexity.

[0004] In other approaches, the well-established planar transistor configuration can be used in highly complex circuit designs with gate lengths in the aforementioned range. A so-called "SOI" (silicon-on-insulator) configuration is often employed in an attempt to improve overall performance and extend the applicability of the planar architecture to even further reduced transistor dimensions. In general, an SOI architecture can be advantageous in terms of reducing the overall parasitic capacitance of the transistor's semiconductor body. This is because the semiconductor area containing the drain, source, and channel regions is bounded vertically (i.e., along the depth direction) by a buried insulating material, thus generally reducing the transistor size along the vertical direction compared to a full-substrate configuration.Furthermore, in current developments, the thickness of the base semiconductor material of an SOI transistor is significantly smaller, for example, down to 15 nm and considerably less, to achieve an essentially depleted transistor configuration, which in particular contributes to improved channel controllability. Additionally, the dopant concentration in the channel region can be significantly reduced, or the channel region can be implemented as an essentially undoped material, resulting in significantly lower power fluctuations. These fluctuations are typically attributed to the unavoidable dopant concentration variations in devices requiring substantial channel doping.

[0005] Furthermore, with regard to channel controllability, which can be significantly improved by using a three-dimensional transistor architecture, it was recognized that even in a planar transistor configuration, the controllability of the channel region can be improved by providing a configuration that allows the application of a "bias" applied to a transistor region capacitively coupled to the channel regions of the transistor under consideration. It turns out that transistor elements fabricated based on the concept of a SOL architecture are particularly suitable for applying a backside bias, since the channel region is electrically isolated from the underlying solid substrate material, which can then be efficiently used as an electrode material for applying the backside bias.Since the fully depleted SOI transistor architecture inherently exhibits improved channel controllability, the concept of applying a backside bias further enhances the overall performance of these transistor types. Because fully depleted SOI transistors demonstrate improved performance in terms of channel controllability, comparable to complex three-dimensional transistor architectures, and because these fully depleted transistors can be advantageous in reducing overall manufacturing process complexity, significant efforts have been made to exploit the backside bias concept to improve overall transistor performance. To this end, voltage generators and control circuits have been incorporated throughout the circuit design to provide the necessary voltages on the "backside" of the channel regions according to the transistor elements.This means that in order to achieve an additional control function for the channel area similar to a dual-gate concept, a special bias, typically several different biases, must be provided by suitably designed voltage generators and supplied to special transistor elements, which typically requires a certain control scheme, especially if a dynamic backside bias mechanism is to be used.

[0006] This means that although a voltage of a specific magnitude is typically constantly applied to specific transistor elements, which are controlled based on a backside bias, it may be necessary, with regard to overall power consumption and thus the reduction of leakage currents, to dynamically apply the backside bias during those operating times when the backside bias control mechanism is actually required, while switching off the backside bias during other inactive times of the corresponding transistor. Although this control strategy offers improved controllability of the corresponding transistor elements while still keeping the overall power consumption, for example in the form of leakage currents, to a low level, it becomes apparent that significant design effort is required and that the overall dynamic behavior of such a transistor element is affected.This means that when activating a transistor requiring a backside bias, a certain settling time is necessary before the actual signal is applied to the gate electrode, in order to switch the transistor as required by the input signal. Furthermore, if different backside bias values ​​are required for the circuit design under consideration, even with statically applied different backside voltages, a corresponding circuit structure must be implemented with respect to a suitable reference voltage. This contributes to the overall higher circuit complexity and lower circuit density for a given functional behavior of the circuit under consideration.

[0007] Furthermore, the effect of the backside bias can be significantly influenced by the overall transistor design, such as the degree of depletion in the channel region, the thickness of the buried insulating layer, the gate length, and the like. These aspects must also be considered when appropriately designing a backside bias mechanism in complex SOI transistors.

[0008] Further reduction of the critical transistor dimensions typically also reduces the thickness of the buried insulating layer, which can lead to corresponding problems with regard to leakage currents and the like, potentially diminishing some of the advantages typically associated with the implementation of a backside biasing mechanism.

[0009] Document US 2004 / 0007734A1 describes a memory cell of a non-volatile semiconductor memory, which also describes embodiments in which a charge-trapping layer is provided in a buried stack of layers. Furthermore, a doped region located beneath the buried stack of layers is shown.

[0010] Document US 2008 / 0 237 695 A1 discloses a semiconductor memory in which a layer stack, located beneath a channel region, is arranged within a corresponding transistor element and includes a charge-trapping layer. Furthermore, a back-side gate is provided to perform the write and erase operations, whereas for normal transistor operation, the gate dielectric and the corresponding operating conditions can be selected relatively independently of the front-side gate.

[0011] Document US 2017 / 0004873A1 also describes transistor elements in which a buried layer stack is provided, in which charge carriers can be trapped to adjust the operating conditions, such as the threshold voltage, of the transistor elements. This document also describes the concept of a buried charge-trapping layer, which allows a gate electrode to be implemented relatively independently of the charge-trapping mechanism.

[0012] In view of the situation described above, the present disclosure therefore relates to semiconductor devices and in particular transistor devices in which the performance of elaborate SOI-based transistor architectures can be improved by additionally controlling the channel conductivity from the “back side” of the transistor device, while avoiding or at least reducing the effects of one or more of the problems identified above. OVERVIEW OF THE REVELATION

[0013] In general, the present disclosure is based on the concept that the behavior and / or function of SOL-based transistor elements can be extended by establishing a channel conductance control mechanism based on one or more buried insulating materials, which are processed to improve the overall controllability of the channel region and / or generally extend the function of a particular transistor element. To this end, in some aspects of the present disclosure, the buried insulating layer is replaced by a stack of two or more material layers with different properties in order to achieve the desired overall functional behavior.For example, in some illustrative embodiments, a charge-trapping mechanism is incorporated in the buried insulating layer or layer stack, which can then be used to appropriately adjust the backside bias behavior of the buried insulating layer stack based on charges captured or released by the charge-trapping mechanism. In this way, a non-volatile yet programmable mechanism can be provided to influence the channel conductance, thereby achieving various operating concepts for a transistor element incorporating the charge-trapping mechanism based on the buried insulating layer stack.For example, in some illustrative embodiments, the charge-trapping mechanism can be considered a non-volatile memory cell of the transistor and, if suitable, can be used as a storage transistor for storing information. This allows the process of programming the memory cell and the process of reading the stored information bit to be accomplished based on different mechanisms, thus contributing to improved overall performance. This avoids certain types of damage that are conventionally caused in non-volatile storage transistors that rely on a charge-trapping mechanism located in the gate electrode structure.If, on the other hand, the transistor, which has a charge-trapping mechanism based on the modified buried insulating layer or layer stack, is considered as a transistor element that operates on the basis of a backside bias mechanism, then the corresponding backside "bias" can be easily implemented with a desired "size" by arranging a specific amount of charge in the buried insulating layer, so that an "instantaneous" backside bias is obtained upon activation of the corresponding standard gate electrode structure.Consequently, by using one or more programming voltages, a desired range of "backside biases" can be set in a circuit, which can be accomplished in a final phase of the entire manufacturing process, or even dynamically during an operating phase of the circuit under consideration.

[0014] In other aspects of the present disclosure that contribute to the understanding of the invention, the design of the buried insulating materials can be achieved by applying techniques for implementing a dielectric material with a high dielectric constant, thereby providing a desired physical thickness while simultaneously reducing the corresponding oxide equivalent thickness of the resulting buried insulating material. In this way, the capacitive coupling to the channel area can be increased while simultaneously reducing static and dynamic leakage currents through the buried insulating stack.Furthermore, if the transistor elements are further reduced in size, requiring a corresponding scaling of the equivalent oxide thickness, the incorporation of additional charge carriers into a physically thick buried insulating material based on a dielectric material with a large dielectric constant may have a significantly reduced effect on the overall transistor behavior compared to a correspondingly scaled physical thickness of a standard silicon dioxide-based buried insulating layer.

[0015] In other aspects of the present disclosure, which serve general understanding, the design of the buried insulating layer or layer stack may involve the incorporation of a ferroelectric material used to appropriately influence the channel conductivity in a desired manner. That is to say, in this case too, this mechanism can be considered a non-volatile memory cell or memory region of the transistor under consideration, whereby the process of programming and the process of reading the stored information can be spatially separated from one another, as was also previously explained in connection with the charge-trapping mechanism.This means that the voltage required to generate a specific polarization state can be applied without requiring a high voltage difference between the actual gate electrode structure and the respective drain and source regions, thus essentially avoiding corresponding negative effects on the actual gate electrode structure. In other aspects, as previously explained, the ferroelectric material in the buried insulating layer or in the layer stack can be suitably designed, for example, with respect to crystal configuration, thickness, and the like, so that different magnitudes of electric fields are generated in the channel region, thereby also obtaining different "backside biases" in a non-volatile manner, while maintaining the basic transistor structure.

[0016] According to the invention, the aforementioned problem is solved by a transistor element having the features of claim 1.

[0017] Further advantageous embodiments are defined in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The revelation can be understood by referring to the following description in conjunction with the accompanying drawings, in which the same reference symbols denote the same elements and in which: Fig. Figure 1A schematically shows a cross-sectional view of a semiconductor device containing one or more transistor elements manufactured on the basis of an SOL architecture, with a buried insulating layer having specially designed properties to improve or extend the function of the transistor elements, wherein in the embodiment shown in this figure a charge-trapping material is incorporated in the buried insulating layer; Fig. Figure 1B shows a cross-sectional view of a transistor element according to the invention, which contains a buried insulating layer with a charge-trapping layer incorporated therein, wherein charge carriers in the charge-trapping material are arranged differently in the locality within a single transistor element; Fig. Figure 2 schematically shows a cross-sectional view of a transistor element with a suitably designed buried insulating layer, which in the illustrated embodiment contains a dielectric material with a high dielectric constant; Fig. Figure 3A schematically shows a cross-sectional view of a transistor element formed on the basis of a buried insulating layer containing a ferroelectric material in a state in which a control voltage can be applied to set a specific polarization state; and Fig. 3B schematically the transistor element from Fig. Figure 3A shows during a “normal” operation in which the standard control gate electrode structure receives a signal based on the standard operating voltage of the transistor element. The Fig. 2, Fig. 3A and Fig. Figure 3B shows examples that contribute to the understanding of the present invention but are not the subject of the invention. DETAILED DESCRIPTION

[0019] The present disclosure will now be described with reference to the accompanying drawings. Various structures, systems, and components are shown schematically in the drawings for illustrative purposes only and are not intended to obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain the present disclosure by providing illustrative examples.

[0020] As briefly explained above, the present disclosure is generally based on the concept that the performance and / or function of SOI-based transistor elements can be enhanced by appropriately designing the buried insulating layer, which is conventionally provided based on a single silicon dioxide layer. As previously explained, the SOI architecture can generally offer significant advantages, such as reduced parasitic capacitance and the like, with the ability to enable efficient additional control of the channel conductance by a backside biasing mechanism offering further opportunities for improving the overall transistor performance.According to the principles disclosed herein, a buried insulating layer is provided, in the form of a buried insulating layer stack, in which at least two different materials are provided such that improved behavior and / or extended functionality is obtained. The incorporation of a charge-trapping mechanism into the buried insulating layer or into the layer stack offers the possibility of incorporating a non-volatile memory region into a single transistor element without altering the overall transistor dimensions.The memory area of ​​the transistor element under consideration can then, in some illustrative embodiments, be used as a memory cell for storing one or more bits of information. The charge-trapping mechanism in the buried insulating layer allows for the decoupling of write and read operations, since the read operation can be performed based on the standard gate electrode structure, while the write operations—i.e., the programming and erasing processes—are performed based on the charge-trapping mechanism of the buried insulating layer. In this way, typical negative aspects associated with incorporating charge-trapping materials into the standard gate electrode structures, as is more commonly used in conventional strategies, can be largely avoided, since the high voltages typically required for programming, i.e.,The processes required to imprint charges into and remove charges from the charge-trapping material do not affect the gate electrode structure, thus contributing to a reduced complexity of the gate electrode structure and additionally increasing the overall reliability.

[0021] In other illustrative embodiments, the transistor element can be viewed as a standard logic element or, if required, as an analog field-effect transistor, wherein the channel conductance, in addition to the standard control mechanism provided by the gate electrode structure, is set by charge trapped in the charge-trapping material, thereby obtaining a corresponding electric field in or at least near the channel region, which may correspond to the electric field produced by a backside bias such as that used in conventional complex SOI transistor elements.In contrast to these conventionally applied backside biases, as briefly explained earlier, the electric field generated by the trapped charge carriers can be considered an "instantaneous" backside bias, since it is present in the channel region independently of the state of the actual control gate electrode structure. Therefore, when a signal is applied to the gate electrode structure, the "backside bias" becomes effective immediately according to the principles explained herein, thus eliminating the need for corresponding settling times and control strategies for the appropriate timing of the generation of the backside bias and the application of a signal to the gate electrode structure.

[0022] Furthermore, since the corresponding trapped charge carriers typically have a residence time of at least 10 years or even considerably longer, the corresponding "backside biases" obtained by the trapped charge carriers can be considered non-volatile and permanent backside biases, thus eliminating the need for corresponding voltage generators when dynamic backside bias control is not required. For example, in such cases, appropriate control voltages, i.e., programming voltages, can be applied during a final phase of the manufacturing process, such as during electrical testing, test operation, and the like, to establish appropriate backside bias mechanisms for the corresponding transistor elements.It should be noted that such programming operations can also be carried out during the use of the semiconductor device under consideration, provided that a corresponding contact regime is accessible from the outside, for example on the basis of a peripheral circuit, if dynamic operation of the backside bias mechanism is required.

[0023] In other illustrative embodiments, one or more voltage generators, such as charge pumps, and the like, can be provided in conjunction with a corresponding control circuit in the semiconductor device under consideration, thereby enabling the implementation of a dynamic backside bias mechanism, since suitable programming or control voltages for the imprinting and / or removal of charge carriers into / from the charge-trapping material can be achieved on the basis of chip-internal mechanisms.Although the advantage of avoiding significant additional effort compared to conventional voltage generators and their corresponding control schemes when applying actual voltages across the buried insulating layer of conventional transistor elements may be less pronounced, a substantial improvement in dynamic behavior can still be achieved. This is because settling times can be avoided due to the non-volatile nature of the mechanism, which relies on the charge-trapping material contained within the buried insulating layer. Consequently, at least the design effort and software overhead required for suitable timing control of conventional backside-biased SOI transistors can be significantly reduced.

[0024] In other examples that contribute to the understanding of the invention, the transistor behavior can be significantly improved by incorporating a dielectric material with a large dielectric constant into the buried insulating layer, so that a suitable bandgap setting of the buried insulating layer can lead to better control of the channel region, which also provides the possibility of further reducing the transistor dimensions and, in particular, the oxide equivalent thickness of the buried insulating material.This means that by implementing a dielectric material with a high dielectric constant, defined as a dielectric material with a permittivity of 20 or even higher, a significantly increased capacitive coupling to the channel region can be achieved compared to the standard silicon dioxide-based dielectric material used in conventional SOI-based transistor devices. In this way, a true dual-gate control scheme can be established, particularly in fully depleted SOI transistor devices where the semiconductor layer thickness of the channel region is approximately 15 nm or significantly less. Furthermore, the physical thickness of the buried insulating material can be maintained or adjusted to a desired value, resulting in superior leakage current performance in extremely small-scale transistor devices.Based on a given transistor architecture, the design of the buried insulating layer can thus be efficiently integrated into the overall process flow with full compatibility with existing process strategies for the fabrication of the transistor components. In particular, the design of the buried insulating layer can be achieved using processes and materials typically employed in the fabrication of sophisticated metal-gate electrode structures with high dielectric constants. Therefore, superior overall performance can be obtained without requiring design changes and, in particular, without needing additional area on an integrated circuit chip.

[0025] In further illustrative examples disclosed herein, which serve to clarify the invention but are not the subject of the invention itself, the design of the buried insulating layer may include the incorporation of a ferroelectric material such that it is possible to generate a polarization state in this material suitable for influencing the channel conductivity, as previously explained. In some illustrative embodiments, the design may include the incorporation of the ferroelectric material with different thicknesses and / or material properties in order to provide different electric fields, thereby obtaining different magnitudes of non-volatile "backside biases" to meet the different requirements of different transistor elements.In other illustrative embodiments, a non-volatile memory cell based on the ferroelectric material can be fabricated, in which case decoupling of the write and read operations is achievable. Again, as previously explained, a significant reduction in the load during operation of the standard gate electrode structure can be achieved, since high voltages for programming or erasing the memory cell at the gate electrode structure can be avoided. In some illustrative embodiments, the ferroelectric material can be incorporated in the form of a layer stack, with at least one conventional dielectric material, such as silicon dioxide, provided as a final layer to offer a high degree of compatibility with conventional silicon dioxide-based buried insulating layers.

[0026] Fig. Figure 1A schematically shows a cross-sectional view of a semiconductor device 100, which may have one or more transistor elements fabricated on the basis of a suitably designed buried insulating layer or a layer stack. In the context of the Fig. In the embodiments shown in Figure 1A, for the sake of simplicity, two transistor elements 100N and 100P are depicted, which can represent suitable transistor elements required for the semiconductor device 100. For example, the transistor element 100N can represent an N-type transistor element, while the transistor element 100P represents a P-type transistor element in some illustrative embodiments, while in other cases the transistor elements 100N and 100P can represent transistors of the same conductivity type, but which may differ in certain properties, such as the transistor dimensions, the operating voltage and thus the thickness of the dielectric, and the like.Furthermore, it should be noted that the transistor elements 100N, 100P are shown as adjacent transistor elements separated by an insulation structure 103, such as a flat trench insulation, while in other cases the transistor elements 100N, 100P are provided in different component areas of the semiconductor device 100.

[0027] The transistor elements 100N, 100P are shown in a moderately advanced stage of fabrication, in which a control gate electrode structure 120 is formed over a corresponding semiconductor layer. For the sake of simplicity, corresponding semiconductor layers for the transistor elements 100N, 100P are specified as semiconductor layers 130N, 130P, whereby, depending on the overall requirements, these semiconductor layers may differ in material composition and / or dopant concentration and / or thickness, etc. For example, the semiconductor layers 130N, 130P may, in certain areas, contain semiconductor alloys such as silicon / germanium, silicon / carbon, and the like, depending on the requirements with regard to the performance and / or function of the transistor elements 100N, 100P.The semiconductor layers 130N, 130P can have a source and drain region 132, 133, which typically represent areas with increased dopant concentration and thus conductivity compared to a channel region 131, which is typically located below the gate electrode structure 120 and is therefore laterally enclosed by the source and drain regions 132, 133. It should be noted that in some illustrative embodiments, such as in . Fig. As shown in Figure 1A, the source and drain regions 132, 133 can be provided in the form of so-called “raised” source and drain regions, in which a heavily doped semiconductor material is formed such that it extends along a vertical direction, i.e. in Fig. 1A extends along the vertical direction, providing contact areas at the upper end, while also connecting to the channel region 131 at the lower ends of the drain and source regions 133, 132. Typically, the additional areas of the raised source and drain regions 132, 133 can represent in-situ doped semiconductor materials formed on or within the semiconductor layers 130N, 130P. It should be noted that the raised source and drain regions 132, 133 of transistor element 100P can be of the opposite conductivity type with respect to transistor element 100N if these transistors represent complementary transistor elements.

[0028] Regardless of the specific structure of the source and drain regions 132, 133, the thickness of the semiconductor layers 130N, 130P can be defined such that it corresponds to a thickness, i.e., an extent along the height direction 130T at or within the area of ​​the gate electrode structure 120. As previously explained, in sophisticated applications, the thickness 130T of the semiconductor layers 130N, 130P can be selected to be in the range of 15 nm and significantly less, approximately 10 nm and below. In this case, the transistor elements 100N, 100P can be considered as completely depleted transistor elements, where the dopant concentration in the respective channel regions 131 may be relatively low or may represent an essentially undoped semiconductor region.

[0029] Furthermore, a “length” of the channel regions 131 can be essentially determined by a “length” of the gate electrode structure 120, wherein a corresponding electrically effective length, i.e. a length extending along the horizontal direction in Fig. 1A extends, essentially defined by a corresponding dimension of an electrode material 121 and a gate dielectric layer 122 of the gate electrode structure 120. It should be noted that in sophisticated applications, a corresponding gate length of 30 nm or significantly less may be required, while in other cases a larger gate length is used if this is compatible with the overall circuit design under consideration. Depending on the level of sophistication of the transistor elements 100N and / or 100P, the gate dielectric material 122 may be a dielectric material with a high dielectric constant, possibly in conjunction with a standard dielectric material with reduced thickness, such as silicon dioxide, silicon oxynitride, silicon nitride, and the like.Dielectric materials with a large dielectric constant, such as hafnium-based dielectric materials, are well known in the semiconductor industry and can be used to produce a dielectric material with a permittivity of 20 and significantly higher, depending on the overall requirements.

[0030] Furthermore, a suitable substance, such as a metal compound, can be incorporated into the dielectric layer 122 to adjust the overall bandgap properties, as is well known in the prior art. Similarly, the electrode material 121 can be produced based on well-established semiconductor materials, such as polysilicon, amorphous germanium, silicon / germanium, and the like, with suitable dopants, while in other cases, metal-containing materials with increased conductivity can be used additionally or alternatively. It should also be noted that the electrode material 121, as well as the source and drain regions 132, 133, can incorporate a metal-containing semiconductor compound, such as nickel silicide, to generally reduce the contact resistance of these regions.In other cases, such contact areas with increased conductivity can be produced in a later manufacturing phase.

[0031] The transistor elements 100N, 100P can further comprise a buried insulating layer 110, which, according to the invention, is provided in the form of a layer stack designated by the same reference numeral 110 for the sake of simplicity. As previously explained, the buried insulating layer stack 110 can be designed to exhibit enhanced functionality and / or improved performance by incorporating one or more materials with different properties compared to conventional dielectric materials used in conventional SOI-based transistor elements, such as silicon dioxide and silicon nitride. In the Fig. In the embodiment shown in Figure 1A, the buried insulating layer stack 110 can include a charge-trapping layer 112, which is understood to be a material capable of trapping charge carriers, such as electrons and / or holes, with sufficient efficiency and retaining these trapped charges for an extended period of time, approximately 10 years or even longer, as is known, for example, for non-volatile storage transistors that incorporate a charge-trapping material in the corresponding gate electrode structures. Silicon nitride, hafnium-enriched silicon oxynitride, and the like are known as charge-trapping materials that can also be used efficiently in the charge-trapping layer 112. The charge-trapping layer 112 can be provided in the form of a layer with a thickness of approximately 1 nm to several tens of nm, depending on the overall device structure.

[0032] In some illustrative embodiments, the buried insulating layer stack 110 may further comprise a dielectric layer 111, which provides separation of the charge-trapping layer 112 from an underlying semiconductor region 120N, 120P, also referred to as a "semiconductor body region" or solid substrate region, which can be used as an electrode material for applying a suitable control voltage to imprint / remove charge carriers into / from the charge-trapping layer 112, as explained in more detail below. For example, the dielectric layer 111 may be considered a dielectric tunneling layer, such as an oxide layer, which allows the passage, i.e., the tunneling, of charge carriers.For this purpose, a suitable thickness and density of the oxide material in layer 111 is selected, as is known, for example, for corresponding ONO layer stacks of conventional storage transistors, which incorporate a charge-trapping mechanism based on an oxide-nitride-oxide layer stack. Similarly, a further dielectric layer 113, described as a blocking layer, can be provided such that the charge-trapping layer 112 is separated from the semiconductor layers 130N and 130P. The dielectric blocking layer 113 can be based on a suitable material, such as silicon dioxide, and can have a suitable density and thickness to essentially suppress the passage of charge carriers to and from the corresponding semiconductor layers 130N and 130P.For example, the thickness of the dielectric tunneling layer 112 can be in the range of 1 to several nm, while the thickness of the dielectric blocking layer 113 can be in the range of a few nm to several tens of nm, depending on the overall requirements.

[0033] It should be noted that the buried insulating layer or layer stack 110 separates the semiconductor layer, and in particular the channel region 131, from the underlying semiconductor body region, i.e., body region 102N for transistor 100N and from semiconductor body region 102P for transistor element 100P. The semiconductor body regions 102N and 102P represent doped regions which, depending on the type of charge carriers to be trapped in the respective charge-trapping layers 112, have either p-type or n-type doping and typically form a PN junction with each other to achieve electrical isolation of the regions 102N and 102P. The regions 102N and 102P can therefore represent upper regions of a substrate material 101, such as a silicon material, a germanium material, and the like, which are appropriately doped.For example, in some illustrative embodiments, the semiconductor body region 102N is provided in the form of a p-type semiconductor material if, for instance, the transistor element 100N represents an N-type transistor. Similarly, the semiconductor body region 102P can be an N-type semiconductor material if, for example, the transistor element 100P represents a P-type transistor. However, it should be noted that a different structure can be selected depending on the required type of charge carriers to be trapped in the respective charge-trapping layers 112.

[0034] Furthermore, in the Fig. In the embodiment shown in Figure 1A, the semiconductor body region 102P is connected to a heavily doped semiconductor region 134P, which represents a heavily doped semiconductor material with a similar or identical structure to the raised drain and source regions 133, 132, possibly in conjunction with an additional metal-containing semiconductor compound, such as nickel silicide and the like (not shown), to reduce the contact resistance for connection to the semiconductor body region 102P. Similarly, the semiconductor body region 102N can be connected to a heavily doped semiconductor region 134N to reduce the overall contact resistance to the semiconductor body region 102N. Again, the region 134N can have a structure similar to the raised drain and source regions 133, 132 and can possess the same type of conductivity as the semiconductor body region 102N.Furthermore, a highly conductive metal-containing semiconductor compound may be incorporated in region 134N or may be fabricated in a later stage. Additionally, the corresponding areas of the semiconductor body regions 102N and 102P are typically separated by an insulating structure 103A, which extends deeper into the substrate 101 compared to the insulating structures 103, thus providing improved performance since at least a substantial portion of regions 102N and 102P is electrically isolated by the structure 103A instead of by a PN junction.

[0035] The in Fig. The semiconductor device 100 shown in Figure 1A can be fabricated using the following processes. The substrate 101 is provided in several illustrative embodiments as an SOI substrate in which, at least in certain component regions, the buried insulating layer stack 100 is formed. This stack is formed on a special support material by deposition and / or oxidation techniques, for example, by fabricating the dielectric tunnel layer 111, to which the charge-trapping layer 112 and the dielectric blocking layer 113 are attached. Well-established process techniques, such as those known for the fabrication of flash memory devices in the form of storage transistors, can be used for this purpose.In other cases, corresponding component areas can be masked, for example, by retaining a conventional buried insulating material, such as silicon dioxide, while unmasked areas are processed in such a way that at least the thickness of the corresponding silicon dioxide-based material is reduced, and that the charge-trapping layer 112 and the dielectric blocking layer 113 are formed, with a subsequent leveling process creating a flat surface topography if required, which is then used for bonding a special donor substrate to form an initial version of the semiconductor layers 130N, 130P.

[0036] Subsequently, processing can continue based on well-established process strategies, for example, by fabricating the isolation structures 103, 103A using well-established process techniques such as masking, etching, deposition, and oxidation processes, thereby obtaining the structures 103, 103A with the desired material composition and geometry. Before and / or after the fabrication of the isolation structures 103, 103A, the semiconductor body regions 102N, 102P can be fabricated, for example, by ion implantation techniques in conjunction with appropriate masking strategies. Such processes can be carried out in connection with providing well regions for other transistors, and the corresponding connection for applying suitable control voltages to the regions 102N, 102P is also established.It should be noted that in some cases, corresponding semiconductor body regions are electrically connected to a single or only a few contact regions when essentially the same control voltage is to be applied to a corresponding number of transistor elements. In the [reference]... Fig. In the embodiments shown in 1A, the semiconductor body regions 102N, 102P can be individually supplied with a suitable control voltage.

[0037] Next, the gate electrode structures 120 are fabricated using well-established process techniques, requiring complex lithography and structuring sequences in conjunction with appropriate material deposition techniques to produce the dielectric layers 122 and one or more of the gate electrode materials 121. If necessary, corresponding sidewall spacer structures 123 can be formed after structuring the gate electrode material 121 and the gate dielectric layer 122.As previously explained, the process flow for manufacturing a gate electrode structure 120 can also include the incorporation of a dielectric material with a large dielectric constant in the dielectric layer 122 in conjunction with suitable substances for adjusting the threshold voltage if required, and suitable metal-containing layers can be incorporated into the material 121, possibly in conjunction with metal-containing electrode materials.

[0038] Next, the raised drain and source regions 133, 132 are fabricated using appropriate masked epitaxial growth techniques, with a suitably high dopant concentration being provided in situ. In other cases, other techniques, such as ion implantation, are employed to form the drain and source regions 133, 132 in accordance with the overall device requirements. It should be noted that further implantation processes can be performed to obtain a desired dopant profile in other regions of the semiconductor layers 130N, 130P, if necessary.Throughout the entire process, additional bake-out processes are applied, as is necessary for implementing suitable material properties, such as the activation of dopants, the adjustment of material properties of dielectric materials with a large dielectric constant, and the like.

[0039] Further processing then continues by fabricating appropriate semiconductor connections as needed, followed by the provision of a dielectric material (not shown) which is given corresponding contact openings that establish a connection to the source and drain regions 132, 133, to the gate electrode structures 120 and to the contact regions 134P, 134N. Subsequently, a suitable metallization structure (not shown) is fabricated based on well-established process strategies.

[0040] When operating the semiconductor device 100, as it is in Fig. As shown in Figure 1A, the transistors 100N, 100P are considered as non-volatile storage transistors, with the buried insulating layer stack 110 in conjunction with the semiconductor body regions 102N, 102P and the corresponding semiconductor layers 130N, 130P being considered as a memory cell.

[0041] On the other hand, the gate electrode structure 120, the drain and source regions 133, 132, and the semiconductor layers 130N, 103P can be considered the actual transistor region that responds to a logic signal applied to the gate electrode structure 120. For example, by connecting the drain and source and the gate electrode 133, 132, 120 with a suitable reference voltage and by applying a corresponding control voltage of sufficient magnitude to the contact region 134P, charge carriers can preferably be impressed into or removed from the charge-trapping layer 112 due to the asymmetric structure in the vertical direction of the layer stack 110. If, for example, region 102N is provided as a p-type semiconductor region, a corresponding control voltage can lead to the imprinting of holes into the charge-trapping layer 112, while a reverse-polarized control voltage leads to the removal of previously trapped charge carriers.In some illustrative embodiments, the corresponding control voltage is applied such that sufficient charge is obtained in the charge-trapping layer 112, resulting in two distinctly different threshold voltages for the respective transistor elements 100N and 100P, thus creating an efficient non-volatile memory cell. As previously explained, in this case, the read operation can be achieved by providing a logic signal at the gate electrode 120 based on the standard operating voltage, while, on the other hand, the programming operation, i.e., the write operation, is accomplished based on the buried insulating layer stack 110 without significantly affecting the gate electrode structure.

[0042] In other cases, the duration and / or magnitude of the control voltage can be controlled such that a certain amount of charge carriers is present in the charge-trapping layer 112 to establish a desired "backside bias," i.e., a corresponding non-volatile electric field in the semiconductor layers 130N, 130P, thereby enabling the setting of different operating conditions. Thus, in this case as well, the respective transistor elements 100N, 100P can be operated based on suitable backside fields that are instantaneously available and permanently established, thereby achieving the advantages of improved channel controllability without requiring the complex timing control typically needed in conventional strategies where the backside bias must be provided in a time-controlled manner relative to the application of a logic signal to the gate electrode structure 120.Consequently, the development of algorithms for the appropriate time-controlled coordination of the application of the backside bias and the gate voltage can be avoided or at least significantly simplified.

[0043] It should be noted that the production of the respective charge-trapping layers 112 can be accomplished, for example, in a permanent or "static" manner by applying suitable control voltages to the respective semiconductor body regions 102N, 102P during a final phase, such as during an electrical test, a run-in phase, and the like, thereby permanently establishing corresponding transistor-internal "backside bias voltages." In this case, the respective control voltages for maintaining the required charge in the charge-trapping layer 112 can be supplied by an external device, requiring only a suitable connection scheme for contacting the respective contact regions 134P, 134N.If dynamic programmability is desired in other cases, appropriate voltage sources for the one or more control voltages in the transistor component 100 can be provided such that the corresponding transistor-internal “permanent” backside bias voltages are reconfigured during the operation of the component 100.

[0044] Fig. Figure 1B shows a cross-sectional view of a transistor element according to the invention, which contains a buried insulating layer with a charge-trapping layer incorporated therein, wherein charge carriers in the charge-trapping material are arranged differently in the locality within a single transistor element;

[0045] Fig. Figure 2 schematically shows a cross-sectional view of a semiconductor device 200 according to comparative examples that contribute to the understanding of the invention but are not part of the invention, in which a transistor element is fabricated based on a SOl architecture having a specially designed buried insulating layer or layer stack. As shown, the transistor element 200A has a semiconductor layer 230 with a channel region 231 laterally bounded by source and drain regions 232, 233, which can be provided in the form of raised source and drain regions, as previously explained, or which can have another suitable structure depending on the overall structure of the transistor element 200A.

[0046] In some examples, the semiconductor layer 230 can have a thickness of approximately 15 nm or significantly less, and can exhibit a corresponding dopant concentration, particularly in the channel region 231, such that a fully depleted field-effect transistor is created, as previously explained. However, it should be noted that other transistor configurations, such as a partially depleted architecture, etc., are also applicable if the basic design of the semiconductor device 200 requires such transistor elements. Furthermore, the transistor element 200A can have a buried insulating layer stack 210, which may comprise a dielectric material with a high dielectric constant formed in the form of one or more layers, such as the dielectric layer with a high dielectric constant 212. In the Fig. In the illustrated example variant 2, the buried insulating layer or layer stack 210 features the high-dielectric-constant dielectric material in the form of a single layer, such as layer 212, whereas in other cases (not shown) two or more high-dielectric-constant dielectric layers are provided. It should be noted that many high-dielectric-constant dielectric materials are well established in the field of semiconductor fabrication, and any of these materials can be used, with such materials typically being selected with regard to their compatibility with the overall process flow for the fabrication of the semiconductor device 200.For example, dielectric materials based on hafnium oxide are frequently used in connection with the production of complex metal gate electrode structures with large dielectric constants, and corresponding materials and associated process strategies for their production can also be efficiently used for the formation of one or more dielectric layers with large dielectric constants 212.

[0047] Furthermore, the buried insulating layer stack 210 can comprise two or more dielectric layers that do not possess a large dielectric constant, i.e., dielectric layers with a permittivity of approximately 10 and less, such as silicon nitride, silicon dioxide, silicon oxynitride, and the like. In the embodiments shown, the dielectric layer 213 without a large dielectric constant can be fabricated such that it separates the one or more dielectric layers with a large dielectric constant 212 from the semiconductor layer 230.Furthermore, another dielectric layer without a large dielectric constant 211 can be provided such that it separates the dielectric layer with a large dielectric constant 212 from an underlying semiconductor body region 202A, which can represent any suitably doped semiconductor region required to apply a control voltage and thus generate an electric field in the buried insulating layer stack 210 in order to suitably influence the conductivity in the channel region 231.

[0048] Furthermore, another semiconductor body region 202B is provided such that it lies below a lower transistor element (not shown), wherein the corresponding semiconductor body regions 202A, 202B are appropriately connected to contact regions 234A, 234B, which may have a similar structure to the drain and source regions 233, 232.

[0049] In principle, the transistor element 200A of the semiconductor device 200 can be fabricated based on well-established process strategies in accordance with a desired structure, since, as already explained, the appropriately designed buried insulating layer stack 210, similar to the layer stack 110 previously explained with reference to the semiconductor device 100, can provide the possibility of well-established transistor configurations based on well-established manufacturing strategies due to the high degree of compatibility with existing process flows, although the overall performance and / or function of the corresponding transistor elements are nevertheless significantly enhanced. Consequently, the transistor element 200A can be fabricated in accordance with similar process techniques as those already described, i.e.The body regions 202A, 202B and insulation structures 203, 203A can be produced in accordance with well-established process techniques and using a suitable substrate material 201. Subsequently, the gate electrode structure 220 with a suitable assembly (an electrode material 221 and a gate dielectric layer 222) is produced, followed by the formation of the drain and source regions 233, 232 and the contact regions 234A, 234B.

[0050] It should be noted that the buried insulating layer stack 210 can be fabricated across the entire substrate 201, while in other cases a corresponding buried insulating layer stack is formed only locally when a "full substrate architecture" is required in some other component regions, such as for connection to the respective body regions 202A, 202B. That is to say, a full substrate configuration is to be understood as an area in which the buried insulating layer stack 210 is removed and a semiconductor material extends from the surface of the substrate 201.For example, the layer stack 210 can be efficiently produced on the substrate 201 as a top layer stack by forming, for example, layer 211 by deposition and / or oxidation, followed by the deposition of one or more dielectric materials with a large dielectric constant and their appropriate treatment if required, while finally layer 213 is provided, for example, by deposition, thereby creating a dielectric surface suitable for carrying out a disk bonding process based on well-established process recipes, thus obtaining an initial version of the semiconductor layer 230.

[0051] When the layer stack 210 is manufactured, a desired physical thickness can be set to achieve improved leakage current suppression. This can be achieved by applying an increased target thickness for one or more dielectric layers with a large dielectric constant, as shown by 212T, while the thickness 213T of the conventional dielectric layer 213 and the thickness 211T of the conventional dielectric layer 211 and other additional dielectric layers without a large dielectric constant are chosen to be relatively small, so that this is compatible with the overall manufacturing requirements without unnecessarily increasing the resulting oxide equivalent thickness.

[0052] In some illustrative embodiments, the combined thickness of one or more dielectric materials with a large dielectric constant, here specified as thickness 212T, can be greater than the individual thickness of any dielectric material without a large dielectric constant. Furthermore, in one exemplary embodiment, the combined thickness of the dielectric materials with a large dielectric constant, here specified as 212T, is greater than the combined thickness of all dielectric materials without a large dielectric constant, represented here as the sum of the thickness values ​​213T and 211T. In this way, it can be ensured that the substantial contribution to the physical thickness comes from the dielectric material with a large dielectric constant, which, on the other hand, makes a moderately small contribution to the overall oxide equivalent density.For example, if the physical thickness of the buried insulating layer stack 210 is specified as 25 nm, a thickness of 2 nm for each of the layers 213 and 211 may be required with respect to process and device characteristics, and the remaining 21 nm can be contributed by one or more dielectric layers with a high dielectric constant, such as layer 212 with a thickness of 212T. Using hafnium oxide-based material with a relative permittivity of 25, an equivalent oxide thickness of 7.3 nm can be achieved, thereby providing efficient capacitive coupling between the channel region 231 and the semiconductor body region 202A, while the physical thickness of 25 nm provides sufficient physical separation of these regions.

[0053] Further component size reduction allows for the maintenance of a relatively large physical thickness, while still enabling a suitable reduction of the oxide equivalent thickness to meet the requirements for improved channel controllability, thereby establishing a true dual-gate control regime. It should be noted that by using dielectric materials with a high dielectric constant and even higher relative permittivity, the oxide equivalent thickness can be further reduced while still maintaining a given physical thickness.

[0054] Fig. Figure 3A schematically shows a cross-sectional view of a semiconductor device 300 according to further exemplary variants that are not part of the invention. The semiconductor device 300 comprises a transistor element 300A with a gate electrode structure 230 formed on and above a channel region 331, which represents a region of a semiconductor layer 330 having or being connected to corresponding source and drain regions 332, 333, thereby laterally delimiting the channel region 331. Furthermore, insulating structures 303 are provided to delimit the semiconductor layer 330 in the lateral direction. Additionally, a buried insulating layer stack 310 is provided and comprises a ferroelectric material 312 in conjunction with one or more buffer layers, such as a layer 313 and a layer 311, which separate the ferroelectric layer 312 from the semiconductor layer 330 on the one hand and a semiconductor body region 302A on the other.The buffer layers 313, 311 can be made of any dielectric material, such as silicon dioxide, silicon nitride, dielectric materials with a high dielectric constant, or a combination thereof. It should be noted, however, that one or both buffer layers 313, 311 may be optional. Furthermore, the semiconductor body region 302A can be connected to a contact region 334A, which may have a similar structure to the drain and source regions 333, 332.

[0055] In principle, the transistor element 300A can have a structure similar to the transistor elements previously described with reference to the semiconductor devices 100 and 200, with this applying to any component except the buried insulating layer 310. That is, the gate electrode structure 320, the semiconductor layer 330, and thus the source and drain regions 332, 333, and the channel region 331 can be provided in accordance with the device requirements and can have a structure as already explained. Similarly, the semiconductor body region 302A can be provided as a doped semiconductor region such that it has a connection to the connection region 334A to form a capacitive structure in combination with the semiconductor layer 330 and the buried insulating layer stack 310, the dielectric of the capacitive structure being formed mainly by the ferroelectric material 312.

[0056] It should be noted that several dielectric materials with high dielectric constants also exhibit ferroelectric properties, such as dielectric materials based on hafnium, oxygen, and silicon, and the like. Other candidates for ferroelectric materials include, for example, LiNbO3 and Bi4Ti3O. 12 (BIT), Bi4-xLa x Ti3O 12 (BLT), Bi3TiNbO9 (BTN), SrBi2Ta2O9 (SBT), Ba x Sr 1-xTiO3 (BST), SrTiO3 (STO), and many other compositions. Consequently, layer 312 can possess properties and be fabricated using materials and techniques that are efficiently employed for the formation of gate electrode structures incorporating a ferroelectric material to provide a non-volatile yet programmable change in channel conductivity. It is well known that upon generation of an external electric field in a ferroelectric material, a corresponding polarization state can be induced, which is then retained after the removal of the external electric field and can even continue to prevail upon generation of another external field, provided that this external field does not exceed a certain threshold.Consequently, ferroelectric transistors are typically operated based on a "normal" supply voltage that does not significantly affect a pre-established polarization state of a ferroelectric material located near a channel region, thus generating a specific threshold voltage for the transistor. Conversely, if a voltage exceeding a threshold is applied to the ferroelectric material, and this voltage has a reversed polarity with respect to the pre-established polarization state, then the polarization in the ferroelectric material can be reversed, resulting in a significantly different influence on the channel region and, consequently, a significantly different threshold voltage. In this way, for example, a non-volatile storage transistor in a gate electrode structure can be configured.

[0057] By applying these principles to the buried insulating layer or layer stack 310, a corresponding modulation of the conductivity of the channel 331 can be achieved without requiring the incorporation of complex ferroelectric materials into the gate electrode structure 320. In this way, the overall complexity of the gate electrode structure 320 is significantly reduced compared to a conventional ferroelectric transistor element, and negative effects during the operation of a conventional ferroelectric transistor element can be avoided or at least significantly reduced, since the high voltages required to generate a desired polarization state in the ferroelectric material arranged in the gate electrode structure are no longer necessary due to the positioning of the ferroelectric material in the buried insulating stack 310.

[0058] It should be noted that the buried insulating layer stack 310 with the ferroelectric material 312 can be provided over the entire semiconductor device 300, i.e. over an entire substrate material 301, or in other illustrative example variants, the stack is provided only locally in the substrate 301 in special component areas that require non-volatile storage transistors and / or transistor elements with improved backside bias behavior, as provided by the ferromagnetic material 312.Furthermore, the buried insulating layer stack 310 can be produced locally or globally on the basis of a suitable support substrate having the substrate material 301, as previously explained, by, for example, forming and treating the ferroelectric material 312 on a surface of the substrate material 301, to which the buffer layer 313 may be added to create similar surface properties to those obtained for a standard SOI support substrate.

[0059] It should be noted that when fabricating the buried insulating layer stack 310, for example by forming depressions and filling the depressions with the ferroelectric material 312, appropriate leveling techniques can be applied to obtain an essentially flat surface typography before bonding the support substrate to a donor substrate containing an initial version of the semiconductor layer 330. During this process, the optional layer 313 can be created and leveled so that the desired surface properties are achieved. Further processing then proceeds as previously explained with reference to the semiconductor devices 100 and 200.

[0060] During operation of the transistor element 300A, a suitable programming voltage, specified as VP, is applied to the contact area 334A and thus to the semiconductor body area 302A, the drain and source areas 333, 332 and the gate electrode 320, as shown schematically in Fig. 3A is shown. Consequently, if a suitably high programming voltage, for example approximately 5V, is selected, then a polarization state 312A can be generated in the material 312, thereby creating a permanent, yet programmable electric field in the channel region 331 and thus generating, for example, a corresponding threshold voltage. When the reverse programming voltage VP is applied, an opposite polarization state 321B is generated, resulting in a significantly different threshold voltage and thus a different conductivity.

[0061] Fig. Figure 3B schematically shows the semiconductor device 300 during a “normal” operating phase, in which the operating voltage VP (see Fig. 3A) is switched off and the semiconductor body region 302A is connected to a suitable reference voltage (0V), such as ground potential, as is also supplied to the source region 332. On the other hand, a logic signal is supplied to the gate electrode structure 320 based on the normal operating voltage VDD, which can be approximately 1V when considering, for example, modern depleted SOI transistors manufactured based on a gate length of 30nm or less. Consequently, a threshold voltage of the transistor element 300A, in addition to the overall transistor structure, is significantly determined by the polarization state in the material 312, thus providing an efficient mechanism for, for example, storing information in the transistor 300A and / or operating the transistor 300A based on a permanently established electric field that serves as a "backside bias".

[0062] If a different state of the ferroelectric material 312 is required, for example to generate the polarization state 312B, a corresponding programming voltage is applied, as previously described with reference to Fig.3A is described. It should be noted that, particularly when using the buried insulating layer stack 310 as a backside biasing mechanism, the appropriate setting of a suitable polarization state can be achieved during a specific manufacturing phase, such as electrical testing or run-in operation, based on an external device that provides the required programming voltage, as previously explained. In this case, corresponding internal voltage sources may no longer be necessary. On the other hand, if a more dynamic behavior is desired, corresponding programming voltages can be set based on voltage sources, such as charge pumps and the like. As already explained,In this case, too, a correspondingly complex timing control is not required, since the corresponding "backside bias" provided by the polarization states 312A, 312B can be considered an instantaneous or immediately effective voltage when a logic signal is applied to the gate electrode structure 320.

[0063] When the transistor element 300A is used as a non-volatile memory cell, it should be noted that the corresponding voltage drop during programming of the ferroelectric material 312 in the gate electrode structure 320 is less pronounced compared to conventional ferroelectric non-volatile memory cells, which require a correspondingly thick gate dielectric material to withstand the high programming voltage. Thus, in this case as well, the design of the gate electrode structure 320 is less demanding compared to conventional ferroelectric transistor elements.

[0064] Furthermore, by appropriately adjusting the thickness of the ferroelectric material 312 and / or by incorporating one or more buffer layers into the layer stack 310, the corresponding influence on the channel region 331 can be adjusted to meet the design requirements. For example, different "backside biases" can be obtained by providing different thicknesses for different transistor elements in otherwise identical configurations. This can be easily achieved by appropriate masked etching steps during the fabrication of the insulating layer stack 310. In other cases, one or more buffer regions 314, which may contain, for example, a conventional dielectric material such as silicon dioxide, etc., can be incorporated., are provided in layer 312, which then has essentially the same thickness over a corresponding area in which the buried insulating layer stack 310 is to be installed. By varying the size and / or number of buffer areas 314, the resulting influence on the channel area 331 can also be modulated, thereby obtaining different "backside bias" conditions. The buffer areas 314 can be efficiently produced before or after the fabrication of the ferroelectric layer 312, for example, by etching, deposition, and leveling techniques.

[0065] It should be noted that two or more of the previously described concepts for the specific design of the buried insulating material in modern SOI transistors can be combined, as is appropriate for a particular application. For example, a dielectric material with a high dielectric constant can be configured to reduce the oxide equivalent thickness of the buried insulating layer while maintaining its function as a charge-trapping layer. Similarly, the ferromagnetic material can be used in combination with a dielectric layer with a high dielectric constant, provided that a reduced oxide equivalent thickness and increased controllability of the channel conductance are achieved. Furthermore, a charge-trapping layer can be combined with a ferroelectric material.

[0066] Therefore, the present disclosure provides semiconductor devices in which transistor elements are fabricated based on an SOL architecture with a layer stack that offers extended functionality and / or improved behavior by incorporating a charge-trapping layer. In this way, non-volatile, yet programmable memory mechanisms and / or backside bias mechanisms can be provided.

Claims

Transistor element (100A) comprising a channel region (131) formed in a semiconductor layer (130, 130N, 130P) and arranged laterally between a drain region (133) and a source region (132); a control gate electrode structure (120) formed on the channel region (131); a buried insulating layer stack (110) formed below the semiconductor layer (131) comprising at least two different dielectric material layers (111, 113) and a charge-trapping layer (112);and a semiconductor body region (102N, 102P) formed below the buried insulating layer stack (110) and connected to receive a control voltage, wherein the semiconductor body region (102N, 102P) comprises a doped region (102N) for setting a type of charge carriers to be trapped in the charge-trapping layer (112) and the semiconductor body region (102N, 102P) has another doped region (102P) for setting a type of charge carriers to be trapped in the charge-trapping layer (112), and wherein the further doped region (102P) is of inverse conductivity type compared to the doped region (102N). Transistor element according to claim 1, wherein the charge-trapping layer (112) comprises nitrogen and / or hafnium. Transistor element according to claim 1, wherein the buried insulating layer stack (110) further comprises a dielectric blocking layer (113) configured to separate the charge-trapping layer (112) from the semiconductor layer (130). Transistor element according to claim 1, wherein the buried insulating layer stack (110) further comprises a charge tunneling layer (111) which is designed to allow tunneling of charge carriers through it and separates the charge trapping layer (112) from the semiconductor body region (102P, 102N). Transistor element according to claim 1, wherein the buried insulating layer stack (110) comprises at least one dielectric layer with a large dielectric constant (113) containing a dielectric material with a large dielectric constant. Transistor element according to claim 5, wherein the buried insulating layer stack (110) further comprises two or more dielectric layers (112, 113) without a large dielectric constant, which contain a dielectric material with a dielectric constant of 10 or less. Transistor element according to claim 5, wherein the thickness of the at least one dielectric layer with a large dielectric constant (113) is greater than the thickness of any dielectric layer without a large dielectric constant of the buried insulating layer stack (110). Transistor element according to claim 7, wherein a combined thickness of the at least one dielectric layer with a large dielectric constant (113) is greater than a combined thickness of all dielectric layers without a large dielectric constant of the buried insulating layer stack.

Images