Self-holding comparator circuit and its use in a vehicle

Abstract

Self-latching comparator circuit (1) with at least one input (E1, E2), comprising a comparator (2) with a non-inverting comparator input (2.1) and with an inverting comparator input (2.2) and a comparator output (2.3), and comprising a transistor circuit (7) with at least one transistor (9) arranged between the supply voltage (U), ground (M), and the comparator output (2.3), wherein the transistor circuit (7) is connected to at least one comparator input (2.1, 2.2) such that when the comparator output (2.3) is activated, the level of the non-inverting comparator input (2.1) is raised independently of the at least one input (E1, E2), wherein the transistor circuit (7) comprises a transistor (9) and an inverter stage (8) which inverts the comparator output (2.3) and which is connected to the transistor (9) such that the transistor (9) conducts when the comparator output (2.3) is activated and wherein the transistor (9) in the conducting state connects the at least one input (E1, E2) to the supply voltage (U) and in the off state disconnects it from the supply voltage (U), and wherein the transistor is designed as a PNP bipolar transistor (9) in emitter circuit to the supply voltage (U) and the inverter stage (8) is designed as an NPN bipolar transistor (8.1) in emitter circuit to ground (M).

Description

[0001] The invention relates to a comparator circuit in which, upon a single exceedance of a reference voltage set at a comparator input, the comparator output is permanently activated and thus permanently set to the level of the maximum positive output voltage. Such a comparator circuit is hereinafter referred to as a self-latching comparator circuit.

[0002] Self-holding comparator circuits are known from the prior art, but their reliable operation over a wide temperature range requires the use of specialized components, such as a controller, a quartz resonator, a charge pump, and / or a bootstrap circuit. Furthermore, solutions known from the prior art require circuits for powering and monitoring such specialized components.

[0003] A device for suppressing background noise is known from US Patent 2003 / 0076182A1. A coincidence circuit of the device receives an input signal and an output signal to determine whether the level of the input signal matches the level of the output signal. An oscillation circuit of the device performs an oscillation only if the level of the input signal does not match the level of the output signal. A counter of the device counts an output signal of the oscillation circuit and is reset when the level of the input signal matches the level of the output signal. An output signal generation circuit of the device inverts the level of the output signal when a counter value reaches a predetermined value.

[0004] The invention is based on the objective of providing a self-latching comparator circuit that is simpler than the prior art and does not require special components. The invention is further based on the objective of providing a use for such a self-latching comparator circuit.

[0005] With regard to the self-holding comparator circuit, the problem is solved according to the invention by the features of claim 1. With regard to the use of a self-holding comparator circuit, the problem is solved according to the invention by the features of claim 7.

[0006] A self-holding comparator circuit has at least one input, wherein the signal level at the at least one input is compared against a reference level.

[0007] The self-latching comparator circuit comprises a comparator with a non-inverting input and an inverting input, as well as a comparator output. The comparator output is activated when the signal level at the non-inverting input is greater than or equal to the signal level at the inverting input.

[0008] The self-holding comparator circuit further comprises a transistor circuit with at least one transistor. The transistor circuit is arranged between the supply voltage, ground, and the comparator output and is connected to at least one comparator input such that when the comparator output is activated, the level of the non-inverting comparator input is raised.

[0009] Thus, the comparator output remains permanently activated even if the level at the non-inverting comparator input was only temporarily higher than the level at the inverting comparator input. The self-latching comparator circuit is therefore advantageously suited to permanently storing transient level changes at one or more inputs.

[0010] According to the invention, the transistor circuit comprises a transistor and an inverter stage which inverts the comparator output. The inverter stage is connected to the transistor such that the transistor conducts when the comparator output is activated. The transistor is designed and arranged such that, in the conducting state, it connects the at least one input to the supply voltage and, in the off state, it disconnects the at least one input from the supply voltage.

[0011] Advantageously, such an embodiment of a self-holding comparator circuit can be implemented using components that are inexpensive and available for a wide range of environmental parameters, for example, for a wide range of operating temperatures.

[0012] In one embodiment of a self-holding comparator circuit, the inverting comparator input is connected to a reference voltage divider between the supply voltage and ground, and the non-inverting comparator input is connected to the at least one input, wherein the transistor circuit connects the at least one input to the supply voltage when the comparator output is activated.

[0013] Using this embodiment, a reference level can be set in a particularly simple way by means of the reference voltage divider, whereby a transient exceedance of the set reference level at one or more inputs is permanently signaled by an activated comparator output.

[0014] According to the invention, the transistor is designed as a PNP bipolar transistor in emitter circuit to the supply voltage and the inverter stage as an NPN bipolar transistor in emitter circuit to ground.

[0015] A PNP transistor is a bipolar transistor in which a central, negatively conductive layer, connected to a base, is bordered by two positively conductive layers, one of which is connected to an emitter and the other to a collector. An NPN transistor is a bipolar transistor in which a central, positively conductive layer, connected to a base, is bordered by two negatively conductive layers, one of which is connected to an emitter and the other to a collector.

[0016] One advantage of this embodiment is that bipolar transistors are particularly inexpensive and available for a particularly wide range of environmental conditions.

[0017] In one embodiment of a self-latching comparator circuit, a plurality of inputs are connected via forward-biased diodes and routed to a single comparator input. Advantageously, this allows for an OR configuration of the multiple inputs; in other words, exceeding the reference level at one input does not affect the other inputs and permanently activates the comparator output.

[0018] In one embodiment of a self-latching comparator circuit, the at least one input is connected to a comparator input via a resistive-capacitor low-pass filter. Advantageously, such a resistive-capacitor or RC low-pass filter allows for the suppression of noise acting on the at least one input.

[0019] According to the invention, a self-holding comparator circuit is used to monitor at least one voltage at an electronic assembly in a vehicle. Advantageously, this makes it possible to monitor signals, voltages, or levels cost-effectively and reliably under the environmental conditions required for use in the automotive sector.

[0020] For example, it is possible to implement short-circuit protection on a high-side controller at a valve output stage using a step-down controller with frequency as the control variable over a wide temperature range using cost-effective components.

[0021] Details and embodiments of the invention are explained in more detail below with reference to a drawing. This drawing shows Fig. 1. Schematic diagram of a circuit for a self-holding comparator circuit.

[0022] Comparator circuit 1 has a first input E1, a second input E2, and an output A. Output A is connected to comparator output 2.3 of comparator 2. Comparator 2 also has a non-inverting comparator input 2.1 and an inverting comparator input 2.2. Comparator 2 is supplied by a supply voltage U and a ground M.

[0023] Inputs E1 and E2 are connected via forward-biased diodes 4 and 5 to a resistive-capacitor low-pass filter 3, hereinafter referred to as RC low-pass filter 3. The diodes 4 and 5 ensure that the highest voltage level of all inputs E1 and E2 is always present at the input of the RC low-pass filter 3. Thus, the diodes 4 and 5 function as an OR gate for all inputs E1 and E2, and the number of inputs can be increased as desired, provided that each additional input is also connected via a forward-biased diode to the RC low-pass filter 3.

[0024] The RC low-pass filter 3 comprises a first resistor R1, which is connected in series with an RC circuit formed in parallel by a second resistor R2 and a capacitor C2. The non-inverting comparator input 2.1 is connected to the junction between the RC circuit and the first resistor R1. The RC circuit is also connected to ground M.

[0025] The inverting comparator input 2.2 is fixed to a voltage level between the supply voltage U and ground M via a reference voltage divider 6 formed from a third resistor R3 and a fourth resistor R4, arranged between the supply voltage U and ground M.

[0026] The comparator output 2.3 is connected to ground M via a fifth resistor R5, which acts as a pull-down resistor, so that the level of the comparator output 2.3 is pulled to ground M in the inactive state.

[0027] The comparator output 2.3 is further connected via a transistor circuit 7 to the input of the RC low-pass filter 3, and thus also to the connection point of the diodes 4, 5.

[0028] The transistor circuit 7 includes an inverter stage 8. The inverter stage 8 is formed by an NPN bipolar transistor 8.1 connected in common-emitter configuration to ground M, whose base is connected to the comparator output 2.3 via a sixth resistor R6, which acts as a series resistor. Thus, the inverted level of the comparator output 2.3 is present at the collector of the NPN bipolar transistor 8.1.

[0029] The collector of the NPN bipolar transistor 8.1 is connected via a seventh resistor R7, which acts as a series resistor, to the base of a PNP bipolar transistor 9 connected in emitter circuit against the supply voltage U.

[0030] Furthermore, the base of this PNP bipolar transistor 9 is connected to the supply voltage U via an eighth resistor R8, which acts as a pull-up resistor. This ensures that when the NPN bipolar transistor 8.1 is switched off, i.e., when the comparator output 2.3 is inactive, the base of the PNP bipolar transistor 9 is pulled to the supply voltage U, thus switching off the PNP bipolar transistor 9.

[0031] If the voltage at at least one of the inputs E1, E2 exceeds a threshold value for a minimum time determined by the time constant of the RC circuit in the RC low-pass filter 3, the comparator output 2.3 is activated and supplied with the level of the supply voltage U. The threshold value is determined by the reference voltage divider 6 at the inverting comparator input 2.2 on the one hand, and by the voltage divider formed by the first and second resistors R1, R2 in the RC low-pass filter 3 on the other. Methods for dimensioning the first to fourth resistors R1 to R4 and the capacitor C2 are known from the prior art, with which a predetermined cutoff frequency for smoothing a noisy input signal at an input E1, E2 and a specific voltage level of a smoothed input signal can be set, above which the comparator output 2.3 is activated.

[0032] With comparator output 2.3 activated, the NPN bipolar transistor 8.1 of inverter stage 8 switches on. The voltage across the ground of the PNP bipolar transistor 9, operating in common-emitter configuration, is reduced via the voltage divider formed by the eighth and seventh resistors R8 and R7, so that its collector is connected to the supply voltage U.

[0033] This means that, regardless of the level at inputs E1 and E2, the input of the RC low-pass filter 3 is at the level of the supply voltage U. Consequently, the comparator output 2.3 remains activated even when the levels of all inputs E1 and E2 fall below the reference value of the comparator 2 set by the reference voltage divider 6. Thus, the comparator circuit 1 is self-holding as long as it is supplied with the supply voltage U.

[0034] Advantageously, the reference voltage divider 6 is dimensioned such that the voltage drop across the third resistor R3 is greater than the voltage drop across the first resistor R1 of the RC low-pass filter 3 plus the voltage drop along the emitter-collector path of the switched-on PNP bipolar transistor 9.

[0035] An advantage of the comparator circuit 1 according to the invention is that the self-holding effect is achieved by means of a simple transistor circuit 7, which requires only transistors 8.1, 9 in a standardized design as active components. Such transistors are very cost-effective and are also available in packages that can be operated stably and reliably over a wide range of environmental conditions, for example, over a wide temperature range. Reference symbol list 1 Comparator circuit 2 Comparator 2.1 Non-inverting comparator input 2.2 Inverting comparator input 2.3 Comparator output 3 Resistance-Capacitance Low-Pass Filter, RC Low-Pass Filter 4, 5 diode 6 reference voltage dividers 7 Transistor circuit 8 inverter stages 8.1 NPN Bipolar Transistor 9 PNP Bipolar Transistor A Exit C2 capacity E1, E2 first, second entrance M mass R1 to R8 first to eighth resistor U Supply voltage

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