METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT AND SEMICONDUCTOR COMPONENT

Abstract

A method of manufacturing a semiconductor device comprising the following steps: Forming a semiconductor layer (30) on a dielectric layer (20) disposed over a substrate (10); Producing a seed layer (40) on the semiconductor layer (30); Structuring the seed layer (40) into a structured seed layer (45); and Performing a crystallization process on the semiconductor layer (30) using the patterned seed layer (45) as a crystallization nucleus to form a crystallized semiconductor layer (30); forming sidewall spacers (50) on opposite side surfaces of the patterned seed layer (45); Removing the patterned seed layer (45) to form a gate gap (47); and Forming a gate dielectric layer (70) and a gate electrode layer (75) in the gate gap (47).

Description

Background of the invention

[0001] Conventional complementary metal oxide semiconductor (CMOS) technology is often implemented to fabricate a large number of semiconductor devices, such as metal oxide semiconductor field-effect transistors (MOSFETs) and bipolar transistors (BJTs), on approximately the same level on a single integrated circuit (IC) chip. In modern IC chips, transistors are arranged on multiple levels.

[0002] US Pat. No. 6,997,985 B1 describes a method for manufacturing a semiconductor device, the method comprising a crystallization process using a metal layer as a crystallization nucleus. In US Pat. No. 2006 / 0 073 648 A1, a thin-film transistor is arranged over a crystallized semiconductor layer. US Pat. No. 2015 / 0 214 256 A1 describes a plurality of transistors arranged one above the other, each having a single-crystal semiconductor layer. Short description of the drawings

[0003] The present invention can best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale and are for purposes of illustration only. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. Fig. 1 shows one of several manufacturing stages for a FET semiconductor device according to an embodiment of the present invention. Fig. 2 shows one of several manufacturing stages for a FET semiconductor device according to an embodiment of the present invention. Fig. 3 shows one of several manufacturing stages for a FET semiconductor device according to an embodiment of the present invention. Fig. 4 shows one of several manufacturing stages for a FET semiconductor device according to an embodiment of the present invention. Fig. 5 shows one of several manufacturing stages for a FET semiconductor device according to an embodiment of the present invention. Fig. 6 shows one of several manufacturing stages for a FET semiconductor device according to an embodiment of the present invention. Fig. 7 shows one of several manufacturing stages for a FET semiconductor device according to an embodiment of the present invention. Fig. 8 shows one of several manufacturing stages for a FET semiconductor device according to an embodiment of the present invention. Fig. 9 shows one of several manufacturing stages for a FET semiconductor device according to an embodiment of the present invention. Fig. 10 shows one of several manufacturing stages for a FET semiconductor device according to an embodiment of the present invention. Fig. 11 shows one of several manufacturing stages for a FET semiconductor device according to an embodiment of the present invention. Fig. 12 shows one of several manufacturing stages for a FET semiconductor device according to an embodiment of the present invention. The Fig. 13A and Fig. 13B show one of several manufacturing stages for a FET semiconductor device according to an embodiment of the present invention. Fig. 14 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 15 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 16 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 17 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 18 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 19 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 20 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 21 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 22 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 23 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 24 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 25 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 26 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 27 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 28 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 29 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 30 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 31 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 32 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 33 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 34 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 35 shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 36A shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 36B shows one of several manufacturing stages for a FET semiconductor device according to another embodiment of the present invention. Fig. 37 shows a sectional view of a FET semiconductor device according to an embodiment of the present invention. Detailed description

[0004] It will be appreciated that the following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below. For example, the dimensions of elements are not limited to the specified range or values, but may depend on process conditions and / or desired properties of the device. Furthermore, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact.For the sake of simplicity and clarity, various elements can be drawn at different scales.

[0005] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly. Furthermore, the term "made of" can mean either "comprises" or "consists of."In the present invention, the phrase "an element selected from the group A, B and C" means "A, B and / or C" (A, B, C, A and B, A and C, B and C, or A, B and C) and does not mean an element of A, an element of B and an element of C unless otherwise specified.

[0006] In a back-end-of-line (BEOL) transistor manufacturing process, there is a key process for growing a high-quality crystalline semiconductor layer for a transistor channel over a non-crystalline layer, such as a silicon oxide layer. The methods for growing a crystalline semiconductor layer on a silicon oxide layer are: (a) growing a semiconductor layer in an amorphous state followed by high-temperature annealing; and (b) growing a semiconductor layer using a seed crystal from a crystalline Si substrate. Both methods are unsuitable for a BEOL process because, in method (a), the heat budget is limited, for example, below 450 °C, and in method (b), the crystalline seed layer must pass through multiple metal and interlayer dielectric layers.

[0007] The present invention provides a method for fabricating a high-quality crystalline semiconductor layer and an amorphous (non-crystalline) dielectric layer. Furthermore, the present invention provides a self-aligned method for fabricating transistors in regions where polycrystalline or amorphous semiconductor layers are converted into a crystalline layer with a higher degree of crystallinity.

[0008] In the following embodiments, materials, configurations, dimensions, and / or processes of one embodiment may be used in another embodiment unless otherwise stated, and their detailed explanation may be omitted.

[0009] The Fig. 1 to 13A show various manufacturing stages for a FET semiconductor device according to an embodiment of the present invention. It is clear that further steps before, during, and after the Fig. 1 to 13A, and some of the steps described below may be replaced or omitted in further embodiments of the method. The order of the steps / processes is interchangeable. Furthermore, in the present invention, a source and a drain are used interchangeably, and a source / drain refers to a source and / or a drain.

[0010] As in Fig. 1, a substrate 10 is provided. In some embodiments, the substrate 10 includes a single-crystal semiconductor layer at least on its surface portion. The substrate 10 may include a single-crystal semiconductor material such as Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In certain embodiments, the substrate 10 is made of crystalline Si, SiGe, or Ge. The substrate 10, in some embodiments, may include one or more buffer layers (not shown) in its surface region. The buffer layers serve to gradually change the lattice constant from that of the substrate to that of the source / drain regions. The buffer layers can consist of epitaxially grown single-crystalline semiconductor materials such as Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP and InP.In a specific embodiment, the substrate 10 comprises silicon germanium (SiGe) buffer layers epitaxially grown on the silicon substrate 10. The germanium concentration of the SiGe buffer layers can increase from 30 atomic percent germanium for the bottom polymer layer to 70 atomic percent germanium for the top polymer layer.

[0011] As continued in Fig. 1, one or more dielectric layers 20 are formed over the substrate 10. In some embodiments, one or more electronic devices, such as transistors, memory, e.g., dynamic random access memory (DRAM), static RAM, magnetic RAM, and / or phase change RAM, are formed on the substrate 10, and the one or more dielectric layers 20 cover the electronic devices. In addition, one or more metal wiring structures are embedded in the dielectric layers 20. The dielectric material for the dielectric layers 20 comprises silicon oxide, silicon nitride, silicon oxynitride (SiON), SiCN, fluorosilicate glass (FSG), or a low-k dielectric material, and is deposited by low-pressure chemical vapor deposition (LPCVD), plasma CVD, or flowable CVD, or by another suitable layer formation technique.After forming the dielectric layers 20, an annealing process may be performed. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP) and / or an etch-back process, is performed to flatten the surface of the dielectric layer 20.

[0012] Let us stay with Fig. 1. A semiconductor layer 30 is formed as a channel semiconductor material over the dielectric layer 20. The semiconductor material for the semiconductor layer 30 includes, in some embodiments, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In certain embodiments, the semiconductor layer 30 is made of Si, SiGe, or Ge.

[0013] In some embodiments, the semiconductor layer 30 is formed by CVD, atomic layer deposition (ALD), or another suitable layer formation method. In some embodiments, the layer formation occurs at a temperature of less than about 450°C. In some embodiments, the layer formation occurs at a temperature equal to or greater than about 25°C. In some embodiments, Si 2 H 6 -Gas is used as a gas source for Si, and Ge 2 H 6 -Gas is used as a gas source for Ge. In certain embodiments, instead of or in addition to Ge 2 H 6 and / or Si 2 H 6 GeH 4 and / or SiH 4used. In some embodiments, the semiconductor layer 30 is amorphous or polycrystalline. In some embodiments, the semiconductor layer 30 is doped with dopants, such as P, As, Sb, and / or B, as appropriate. The dopants are doped in situ during layer formation or doped by ion implantation or plasma doping after formation of the semiconductor layer 30. A thickness of the semiconductor layer 30 is about 5 nm to about 500 nm in some embodiments and about 10 nm to about 50 nm in other embodiments.

[0014] As in Fig. 2, a seed layer 40 is then formed over the semiconductor layer 30. In some embodiments, no seed layer is formed beneath the semiconductor layer 30. In some embodiments, the seed layer 40 is comprised of a metal oxide having the property of being crystalline upon deposition or upon cryogenic annealing at about 300°C to about 450°C. In certain embodiments, the seed layer 40 is comprised of magnesium oxide (MgO). In some embodiments, the MgO seed layer 40 is single-crystalline. In other embodiments, the MgO seed layer 40 is polycrystalline or has multiple single-crystalline domains. The seed layer 40 may be formed by CVD, ALD, physical vapor deposition (PVD) such as sputtering, or by another suitable layer formation technique. A thickness of the seed layer 40 is about 1 nm to about 100 nm in some embodiments and about 2 nm to about 20 nm in other embodiments.In certain embodiments, the thickness of the seed layer 40 is about 1 nm to about 10 nm. In other embodiments, HfO. 2, La 2 Hf 2 O 7 , Y 2 O 3 , SrTiO 3 or HfZrO 2 used as the seed layer 40.

[0015] As in Fig. 3, the seed layer 40 is then patterned into a patterned seed layer 45 using one or more lithographic and etching processes. The lithographic process includes UV lithography, DUV (deep ultraviolet) lithography, EUV (extreme ultraviolet) lithography, electron beam (e-beam) lithography, and the etching process includes plasma dry etching. The patterned seed layer 45 corresponds to a gate electrode of a later-fabricated FET. Thus, a width W1 of the patterned seed layer 45 corresponds to a gate length of the FET, and the patterned seed layer 45 has a shape corresponding to the gate electrode of the FET. In some embodiments, the patterned seed layer 45 has a line shape. The width W1 is about 5 nm to about 500 nm in some embodiments and about 20 nm to about 200 nm in other embodiments.

[0016] As in the Fig. 4 to 7, a crystallization process is then performed to crystallize the semiconductor layer 30. The crystallization process includes thermal annealing. In some embodiments, the thermal annealing includes a laser annealing process using a nanosecond laser transmitted through the seed layer. In other embodiments, the thermal annealing includes a cryogenic anneal at about 350°C to about 450°C.

[0017] As in the Fig. 5 and Fig. As shown in Figure 6, the semiconductor layer 30 begins to crystallize from the underside of the patterned seed layer (corresponding to a channel region of the later-fabricated FET) as a crystal template. By continuing the thermal annealing process, crystallized portions 35 of the semiconductor layer 30 expand laterally into source / drain regions, as shown in Fig. 7. In some embodiments, the entire semiconductor layer 30 becomes crystalline.

[0018] As in Fig. 8, sidewall spacers 50 are then formed on opposite side surfaces of the patterned seed layer 45. A protective layer of an insulating material for the sidewall spacers 50 is conformally formed by CVD or other suitable methods. The protective layer is conformally deposited such that it is formed to have substantially equal thicknesses on vertical surfaces, such as the sidewalls, on horizontal surfaces, and on a top surface of the patterned seed layer 45. In some embodiments, the protective layer is deposited to a thickness of about 2 nm to about 30 nm. In one embodiment, the insulating material of the protective layer is different from the materials of the patterned seed layer 45 and is a silicon nitride-based material, such as silicon nitride, SiON, SiOCN, or SiCN, or combinations thereof.In some embodiments, the protective layer (sidewall spacers 50) is made of silicon nitride. The sidewall spacers 50 are formed by anisotropic etching on opposite side surfaces of the patterned seed layer 45, as shown in FIG. Fig. 8. The patterned seed layer 45 functions as a dummy gate electrode in a gate replacement process.

[0019] As in Fig. 9, a source region and a drain region are then formed. In some embodiments, the source / drain regions 60 comprise one or more epitaxial semiconductor layers. The source / drain epitaxial layer 60 comprises one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET, or Si, SiGe, and Ge for a p-channel FET. For the p-channel FET, boron (B) may also be used in the source / drain region. The source / drain epitaxial layer 60 is formed using an epitaxial growth method such as CVD, ALD, or molecular beam epitaxy (MBE). In some embodiments, the source / drain regions of the crystallized semiconductor layer 35 are recessed by etching, and then the source / drain epitaxial layer 60 is formed over the recessed source / drain regions of the crystallized semiconductor layer 35.In other embodiments, one or more ion implantation processes are performed to introduce dopants into the source / drain regions of the crystallized semiconductor layer 35.

[0020] Then, a first interlayer dielectric (ILD) layer 65 is formed over the source / drain epitaxial layer 60 and the patterned seed layer 45. The materials for the first ILD layer 65 are compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials, such as polymers, can be used for the first ILD layer 65. After the first ILD layer 65 has been formed, a planarization process, such as CMP, is performed so that the upper part of the patterned seed layer 45 is exposed, as shown in Fig. 10. In some embodiments, the patterned seed layer 45 functions as a CMP stop layer. In some embodiments, a contact etch stop layer, such as a silicon nitride layer or a silicon oxynitride layer, is formed prior to the formation of the first ILD layer 65.

[0021] Then, the patterned seed layer 45 is removed, leaving a gate gap 47, as shown in Fig. 11. The patterned seed layer 45 is removed by plasma dry etching and / or wet etching.

[0022] After the patterned seed layer 45 has been removed, a gate dielectric layer 70 and a gate electrode 75 are formed in the gate gap 47, as shown in Fig. 12. In some embodiments, the gate dielectric layer 70 comprises one or more layers of a dielectric material, such as silicon oxide, silicon nitride, a high-k dielectric material, another suitable dielectric material, and / or combinations thereof. Examples of the high-k dielectric material include HfO 2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium oxide-alumina alloy (HfO 2 -Al 2 O 3), other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the gate dielectric layer 70 includes an interface layer formed between the channel layer 35 and the dielectric material by chemical oxidation. The gate dielectric layer 70 may be formed by CVD, ALD, or another suitable method. In one embodiment, the gate dielectric layer 70 is formed using a highly conformal deposition method such as ALD to ensure the formation of a gate dielectric layer with a consistent thickness near each channel layer. The thickness of the gate dielectric layer 70, in one embodiment, is about 1 nm to about 10 nm.

[0023] A gate electrode layer 75 is then formed on the gate dielectric layer 70. The gate electrode layer 75 comprises one or more layers of a conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 75 may be formed by CVD, ALD, electroplating, or another suitable method. The metals for the gate dielectric layer 70 and the gate electrode layer 75 are also deposited over the top of the first ILD layer 65. The material for the gate electrode layer that has been deposited over the ILD layer 65 is then planarized, for example, using a CMP, until the top surface of the ILD layer 65 is exposed.In some embodiments, after planarization, the metal gate electrode layer 75 is recessed, and an insulating capping layer (not shown) is formed over the recessed gate electrode layer. The insulating capping layer comprises one or more layers of a silicon nitride-based material, such as silicon nitride. The insulating capping layer may be formed by depositing an insulating material followed by planarization.

[0024] In certain embodiments of the present invention, one or more work function adjustment layers (not shown) are sandwiched between the gate dielectric layer 70 and the gate electrode layer 75. The work function adjustment layers are made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. For the n-channel FET, one or more of the compounds / elements TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function adjustment layer, and for the p-channel FET, one or more of the compounds / elements TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used for the work function adjustment layer. The work function adjustment layer can be fabricated by ALD, PVD, CVD, electron beam evaporation or any other suitable method.In addition, the work function adjustment layer can be fabricated separately for the n-channel FET and the p-channel FET, for which different metal layers can be used.

[0025] As in Fig. 13A, a second ILD layer 80 is also formed over the first ILD layer 65, and conductive contacts 85 passing through the second ILD layer 80 or the second and first ILD layers are formed to contact the gate electrode 75 and the source / drain epitaxial layers 60. Contact openings are formed in the first and / or second ILD layers. One or more layers of conductive materials are formed in and over the contact openings, and then planarization, such as CMP, is performed to form the conductive contacts 85, as shown in Fig. 13A. In some embodiments, the conductive contacts 85 include a cap layer and a body layer. The cap layer is a barrier layer and / or an adhesive layer. In some embodiments, a Ti layer is formed on the source / drain epitaxial layer 60, and a TiN or TaN layer is formed on the Ti layer as the cap layer. The body layer comprises one or more layers of Co, Ni, W, Ti, Ta, Cu, or Al, or another suitable material.

[0026] It is clear that the FET undergoes further CMOS processes to produce various structural elements such as contacts / vias, metallic interconnect layers, dielectric layers, passivation layers, etc.

[0027] As in Fig. 13A, in other embodiments, the crystallization process is terminated when the crystallized portions 35 have been formed in the required regions, such as the channel regions and the source / drain regions. Therefore, there is a portion of the uncrystallized semiconductor layer 30 that is amorphous or polycrystalline.

[0028] The Fig. Figures 14 to 23 show various stages of fabricating a FET semiconductor device according to an embodiment of the present invention. It is clear that further steps may be performed before, during, and after the steps shown in Figures Fig. 14 to 23 may be provided, and some of the steps described below may be replaced or omitted in further embodiments of the method. The order of the steps / processes is interchangeable.

[0029] Similar to the Fig. 1 and Fig. 2, a seed layer 40 is formed over the semiconductor layer 30. As in Fig. As shown in Figure 14, the seed layer 40 is then patterned into a plurality of patterned seed layers 45 using one or more lithographic and etching processes. The lithographic process includes UV lithography, DUV lithography, EUV lithography, electron beam lithography, and the etching process includes plasma dry etching. The patterned seed layers 45 correspond to gate electrodes of later-fabricated FETs. In some embodiments, the patterned seed layers 45 have a line shape. The width W1 of the patterned seed layers 45 is about 5 nm to about 500 nm in some embodiments and about 20 nm to about 200 nm in other embodiments.

[0030] As in the Fig. 15 to 18, a crystallization process is then performed to crystallize the semiconductor layer 30. The crystallization process includes a thermal anneal. In some embodiments, the thermal anneal includes a laser annealing process using a nanosecond laser transmitted through the seed layer. In other embodiments, the thermal anneal includes a cryogenic anneal at about 350°C to about 450°C.

[0031] As in the Fig. 16 and Fig. As shown in Figure 17, the semiconductor layer 30 begins to crystallize from the undersides of the patterned seed layers 45 (corresponding to channel regions of the later-fabricated FETs) as a crystal template. By continuing the thermal annealing process, crystallized portions 35 of the semiconductor layer 30 expand laterally into source / drain regions, as shown in Fig. 17 is shown.

[0032] As in Fig. 18, the front parts of the crystallized semiconductor layers 35 each meet with the adjacent front part of the crystallized semiconductor layers 35, so that a grain boundary 37 is formed.

[0033] As in Fig. 19, sidewall spacers 50 are then formed on opposite side surfaces of the patterned seed layers 45. A protective layer of an insulating material for the sidewall spacers 50 is conformally formed by CVD or other suitable methods. The protective layer is conformally deposited so that it is formed to have substantially equal thicknesses on vertical surfaces, such as the sidewalls, and on horizontal surfaces and top surfaces of the patterned seed layers 45. In some embodiments, the protective layer is deposited to a thickness of about 2 nm to about 30 nm. In one embodiment, the insulating material of the protective layer is different from the materials of the patterned seed layers 45 and is a silicon nitride-based material, such as silicon nitride, SiON, SiOCN, or SiCN, or combinations thereof.In some embodiments, the protective layer (sidewall spacers 50) is made of silicon nitride. The sidewall spacers 50 are formed by anisotropic etching on opposite side surfaces of the patterned seed layers 45, as shown in FIG. Fig. 19. The patterned seed layers 45 function as a dummy gate electrode in a gate replacement process.

[0034] As in Fig. 20, source and drain regions are then formed. In some embodiments, the source / drain regions 60 comprise one or more epitaxial semiconductor layers. The source / drain epitaxial layers 60 include one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET, or Si, SiGe, and Ge for a p-channel FET. For the p-channel FET, boron (B) may also be used in the source / drain region. The source / drain epitaxial layer 60 is formed using an epitaxial growth method such as CVD, ALD, or MBE. In some embodiments, the source / drain regions of the crystallized semiconductor layer 35 are recessed by etching, and then the source / drain epitaxial layers 60 are formed over the recessed source / drain regions of the crystallized semiconductor layer 35.In other embodiments, one or more ion implantation processes are performed to introduce dopants into the source / drain regions of the crystallized semiconductor layer 35. In some embodiments, the source / drain epitaxial layers 60 completely fill gaps between adjacent dummy gate electrodes (patterned seed layers 45), and in other embodiments, the source / drain epitaxial layers 60 only partially fill gaps between adjacent dummy gate electrodes.

[0035] Then, a first interlayer dielectric (ILD) layer 65 is formed over the source / drain epitaxial layers 60 and the patterned seed layers 45. The materials for the first ILD layer 65 are compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials, such as polymers, can be used for the first ILD layer 65. After the first ILD layer 65 has been formed, a planarization process, such as CMP, is performed so that the upper portions of the patterned seed layers 45 are exposed, as shown in Fig. 21. In some embodiments, the patterned seed layers 45 function as a CMP stop layer. In some embodiments, a contact etch stop layer, such as a silicon nitride layer or a silicon oxynitride layer, is formed prior to the formation of the first ILD layer 65.

[0036] Then the patterned seed layers 45 are removed, creating gate gaps 47, as shown in Fig. 22. The structured seed layers 45 are removed by plasma dry etching and / or wet etching.

[0037] After the patterned seed layers 45 have been removed, a gate dielectric layer 70 and a gate electrode 75 are formed in each of the gate gaps 47, as shown in Fig. 23. In some embodiments, the gate dielectric layer 70 comprises one or more layers of a dielectric material, such as silicon oxide, silicon nitride, a high-k dielectric material, another suitable dielectric material, and / or combinations thereof. Examples of high-k dielectric materials are HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium oxide-aluminum oxide alloy (HfO 2 -Al 2 O 3), other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the gate dielectric layer 70 includes an interface layer formed between the channel layer 35 and the dielectric material by chemical oxidation. The gate dielectric layer 70 may be formed by CVD, ALD, or another suitable method. In one embodiment, the gate dielectric layer 70 is formed using a highly conformal deposition method such as ALD to ensure the formation of a gate dielectric layer with a consistent thickness near each channel layer. The thickness of the gate dielectric layer 70, in one embodiment, is about 1 nm to about 10 nm.

[0038] A gate electrode layer 75 is then formed on the gate dielectric layer 70. The gate electrode layer 75 comprises one or more layers of a conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 75 may be formed by CVD, ALD, electroplating, or another suitable method. The metals for the gate dielectric layer 70 and the gate electrode layer 75 are also deposited over the top of the first ILD layer 65. The material for the gate electrode layer that has been deposited over the ILD layer 65 is then planarized, for example, using a CMP, until the top surface of the ILD layer 65 is exposed.In some embodiments, after planarization, the metal gate electrode layer 75 is recessed, and an insulating capping layer (not shown) is formed over the recessed gate electrode layer. The insulating capping layer comprises one or more layers of a silicon nitride-based material, such as silicon nitride. The insulating capping layer may be formed by depositing an insulating material followed by planarization.

[0039] In certain embodiments of the present invention, one or more work function adjustment layers (not shown) are sandwiched between the gate dielectric layer 70 and the gate electrode layer 75. The work function adjustment layers are made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. For the n-channel FET, one or more of the compounds / elements TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function adjustment layer, and for the p-channel FET, one or more of the compounds / elements TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used for the work function adjustment layer. The work function adjustment layer can be fabricated by ALD, PVD, CVD, electron beam evaporation or any other suitable method.In addition, the work function adjustment layer can be fabricated separately for the n-channel FET and the p-channel FET, for which different metal layers can be used.

[0040] Similar to Fig. 13A, a second ILD layer is also formed over the first ILD layer, and conductive contacts passing through the second ILD layer or the second and first ILD layers are formed to contact the gate electrode and the source / drain epitaxial layers.

[0041] In other embodiments, the crystallization process is terminated before the front portions of the crystallized semiconductor layers 35 each meet the adjacent front portion of the crystallized semiconductor layers 35. In this case, a portion of the uncrystallized semiconductor layer 30 remains between adjacent FETs.

[0042] It is clear that the FET undergoes further CMOS processes to produce various structural elements such as contacts / vias, metallic interconnect layers, dielectric layers, passivation layers, etc.

[0043] The Fig. 24 to 36A show various stages of fabricating a FET semiconductor device according to an embodiment of the present invention. It is clear that further steps may be performed before, during, and after the steps shown in Fig. 24 to 36A may be provided, and some of the steps described below may be replaced or omitted in further embodiments of the method. The order of the steps / processes is interchangeable.

[0044] Similar to Fig. 1 is in Fig. 25, a semiconductor layer 30 is formed over a dielectric layer 20, which is arranged over a substrate 10. Then, similar to Fig. 2 a seed layer 40 is formed over the semiconductor layer 30, as in Fig. 25. In some embodiments, the seed layer 40 is made of a metal oxide having the property of being crystalline upon deposition or upon cryogenic annealing of about 350°C to about 450°C. In certain embodiments, the seed layer 40 is made of magnesium oxide (MgO). In some embodiments, the MgO seed layer 40 is single-crystalline. In other embodiments, the MgO seed layer 40 is polycrystalline or has multiple single-crystalline domains. The seed layer 40 may be formed by CVD, ALD, physical vapor deposition (PVD) such as sputtering, or by another suitable layer formation technique. A thickness of the seed layer 40 is about 1 nm to about 100 nm in some embodiments and about 2 nm to about 20 nm in other embodiments. In certain embodiments, the thickness of the seed layer 40 is about 1 nm to about 10 nm.

[0045] As in Fig. 26, a dummy gate layer 90 is then formed over the seed layer 40'. In some embodiments, the dummy gate layer 90 is made of polysilicon or amorphous silicon. Other semiconductor materials or dielectric materials that can be selectively removed with respect to an ILD layer and sidewall spacers may also be used. A thickness of the dummy gate layer 90 is about 50 nm to about 500 nm in some embodiments and about 100 nm to about 200 nm in other embodiments. The dummy gate layer 90 may be formed by CVD, ALD, physical vapor deposition such as sputtering, or by another suitable layer formation technique.

[0046] As in Fig. As shown in Figure 27, the dummy gate layer 90 and the seed layer 40' are then patterned into a plurality of patterned dummy gate layers 95 and a plurality of patterned seed layers 45' using one or more lithographic and etching processes. The lithographic process includes UV lithography, DUV lithography, EUV lithography, electron beam lithography, and the etching process includes plasma dry etching. The patterned dummy gate layers 95 and the patterned seed layers 45' correspond to gate electrodes of later-fabricated FETs. In some embodiments, the patterned dummy gate layers 95 and the patterned seed layers 45' have a line shape. The width of the patterned dummy gate layers 95 and the patterned seed layers 45' is about 5 nm to about 500 nm in some embodiments and about 20 nm to about 200 nm in other embodiments.

[0047] As in the Fig. 28 to 31, a crystallization process is then performed to crystallize the semiconductor layer 30. The crystallization process includes thermal annealing. In some embodiments, the thermal annealing includes a laser annealing process using a nanosecond laser transmitted through the seed layer. In other embodiments, the thermal annealing includes a cryogenic anneal at about 350°C to about 450°C.

[0048] As in the Fig. 29 and Fig. 30, the semiconductor layer 30 begins to crystallize from the undersides of the patterned seed layers 45' (corresponding to channel regions of the later-fabricated FETs) as a crystal template. By continuing the thermal annealing process, crystallized portions 35 of the semiconductor layer 30 expand laterally into source / drain regions, as shown in Fig. 30 is shown.

[0049] As in Fig. 31, front parts of the crystallized semiconductor layers 35 each meet with the adjacent front part of the crystallized semiconductor layers 35, so that a grain boundary 37 is formed.

[0050] As in Fig. 32, sidewall spacers 50 are then formed on opposite side surfaces of the patterned dummy gate layers 95 and the patterned seed layers 45'. A protective layer of an insulating material for the sidewall spacers 50 is conformally deposited by CVD or other suitable methods. The protective layer is conformally deposited so that it is formed to have substantially equal thicknesses on vertical surfaces, such as the sidewalls, on horizontal surfaces and top surfaces of the patterned dummy gate layers 95 and the patterned seed layers 45'. In some embodiments, the protective layer is deposited to a thickness of about 2 nm to about 30 nm.In one embodiment, the insulating material of the protection layer is different from the materials of the patterned dummy gate layers 95 and the patterned seed layers 45' and is a silicon nitride-based material, such as silicon nitride, SiON, SiOCN, or SiCN, or combinations thereof. In some embodiments, the protection layer (sidewall spacers 50) is made of silicon nitride. The sidewall spacers 50 are formed by anisotropic etching on opposite side surfaces of the patterned dummy gate layers 95 and the patterned seed layers 45', as shown in FIG. Fig. 32. The patterned dummy gate layers 95 and the patterned seed layers 45' function as a dummy gate electrode in a gate replacement process.

[0051] As in Fig. 33, source and drain regions are then formed. In some embodiments, the source / drain regions 60 comprise one or more epitaxial semiconductor layers. The source / drain epitaxial layers 60 include one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET, or Si, SiGe, and Ge for a p-channel FET. For the p-channel FET, boron (B) may also be used in the source / drain region. The source / drain epitaxial layer 60 is formed using an epitaxial growth method such as CVD, ALD, or MBE. In some embodiments, the source / drain regions of the crystallized semiconductor layer 35 are recessed by etching, and then the source / drain epitaxial layers 60 are formed over the recessed source / drain regions of the crystallized semiconductor layer 35.In other embodiments, one or more ion implantation processes are performed to introduce dopants into the source / drain regions of the crystallized semiconductor layer 35. In some embodiments, the source / drain epitaxial layers 60 completely fill gaps between adjacent dummy gate electrodes (patterned dummy gate layers 95 and patterned seed layers 45'), and in other embodiments, the source / drain epitaxial layers 60 only partially fill gaps between adjacent dummy gate electrodes.

[0052] Then, a first interlayer dielectric (ILD) layer 65 is formed over the source / drain epitaxial layers 60 and the patterned seed layers 45'. The materials for the first ILD layer 65 are compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials, such as polymers, can be used for the first ILD layer 65. After the first ILD layer 65 has been formed, a planarization process, such as CMP, is performed so that the upper portions of the patterned dummy gate layers 95 and the patterned seed layers 45' are exposed, as shown in Fig. 34. In some embodiments, the patterned dummy gate layers 95 function as a CMP stop layer. In some embodiments, a contact etch stop layer, such as a silicon nitride layer or a silicon oxynitride layer, is formed prior to the formation of the first ILD layer 65.

[0053] Then, the patterned dummy gate layers 95 and the patterned seed layers 45' are removed, so that gate gaps 47 are formed, as shown in Fig. 35. The patterned dummy gate layers 95 and the patterned seed layers 45' may be removed by plasma dry etching and / or wet etching. If the patterned dummy gate layers 95 are made of polysilicon or amorphous silicon, a wet etchant, such as a TMAH solution (TMAH: tetramethylammonium hydroxide), may be used to selectively remove the dummy gate structures. Subsequently, the patterned seed layers 45' are removed by plasma dry etching and / or wet etching.

[0054] After the patterned dummy gate layers 95 and the patterned seed layers 45' have been removed, a gate dielectric layer 70 and a gate electrode 75 are formed in each of the gate gaps 47, as shown in Fig. 36A. In some embodiments, the gate dielectric layer 70 comprises one or more layers of a dielectric material, such as silicon oxide, silicon nitride, a high-k dielectric material, another suitable dielectric material, and / or combinations thereof. Examples of high-k dielectric materials are HfO 2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium oxide-alumina alloy (HfO 2 -Al 2 O 3), other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the gate dielectric layer 70 includes an interface layer formed between the channel layer 35 and the dielectric material by chemical oxidation. The gate dielectric layer 70 may be formed by CVD, ALD, or another suitable method. In one embodiment, the gate dielectric layer 70 is formed using a highly conformal deposition method such as ALD to ensure the formation of a gate dielectric layer with a consistent thickness near each channel layer. The thickness of the gate dielectric layer 70, in one embodiment, is about 1 nm to about 10 nm.

[0055] A gate electrode layer 75 is then formed on the gate dielectric layer 70. The gate electrode layer 75 comprises one or more layers of a conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 75 may be formed by CVD, ALD, electroplating, or another suitable method. The metals for the gate dielectric layer 70 and the gate electrode layer 75 are also deposited over the top of the first ILD layer 65. The material for the gate electrode layer that has been deposited over the ILD layer 65 is then planarized, for example, using a CMP, until the top surface of the ILD layer 65 is exposed.In some embodiments, after planarization, the metal gate electrode layer 75 is recessed, and an insulating capping layer (not shown) is formed over the recessed gate electrode layer. The insulating capping layer comprises one or more layers of a silicon nitride-based material, such as silicon nitride. The insulating capping layer may be formed by depositing an insulating material followed by planarization.

[0056] In certain embodiments of the present invention, one or more work function adjustment layers (not shown) are sandwiched between the gate dielectric layer 70 and the gate electrode layer 75. The work function adjustment layers are made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. For the n-channel FET, one or more of the compounds / elements TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function adjustment layer, and for the p-channel FET, one or more of the compounds / elements TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used for the work function adjustment layer. The work function adjustment layer can be fabricated by ALD, PVD, CVD, electron beam evaporation or any other suitable method.In addition, the work function adjustment layer can be fabricated separately for the n-channel FET and the p-channel FET, for which different metal layers can be used.

[0057] Similar to Fig. 13A, a second ILD layer is also formed over the first ILD layer, and conductive contacts passing through the second ILD layer or the second and first ILD layers are formed to contact the gate electrode and the source / drain epitaxial layers. As shown in Fig. 13A, in some embodiments, the fabricated FET is a thin film transistor (TFT).

[0058] In other embodiments, the crystallization process is terminated before front portions of the crystallized semiconductor layers 35 each meet the adjacent front portion of the crystallized semiconductor layers 35. In this case, a portion of the non-crystallized semiconductor layer 30 remains between adjacent FETs, as shown in Fig. 36B is shown.

[0059] It is clear that the FET undergoes further CMOS processes to produce various structural elements such as contacts / vias, metallic interconnect layers, dielectric layers, passivation layers, etc.

[0060] Fig. 37 shows a sectional view of a semiconductor device according to an embodiment of the present invention. As in Fig. As shown in Figure 37, a bottom layer device 100 is fabricated over a substrate. The bottom layer device 100 includes one or more fin field-effect transistors (FinFETs), gate-all-around FETs (GAA-FETs), planar FETs, vertical FETs, or other electronic components. Fig. 37 also shows an upper-layer device 200 disposed over the lower-layer device 100. In some embodiments, one or more ILD layers, metal interconnect layers, and / or vias are disposed between the lower-layer device 100 and the upper-layer device 200. In some embodiments, the upper-layer device 200 includes one or more FETs fabricated with the above embodiments of the present invention.

[0061] The various embodiments or examples described herein offer several advantages over the prior art. For example, in the present invention, a crystallization process is performed on a non-crystalline semiconductor layer using a patterned seed layer formed on the non-crystalline semiconductor layer (an upper seed layer). Since the crystallization of the non-crystalline semiconductor layer starts from the bottom of the patterned seed layer and the patterned seed layer is used as a dummy gate, the first-crystallized portion (closer to the seed layer) with higher crystallinity can be used as a channel region of an FET. In other words, the portions with the best crystallinity can be self-aligned to be used as channel regions.Furthermore, by using the seed layer as a dummy gate for a gate replacement process, an increase in the number of process steps for manufacturing the semiconductor device can be suppressed. The steps of the present invention are compatible with BEOL processes of semiconductor manufacturing.

[0062] It is understood that not all advantages have necessarily been discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer other advantages.

[0063] According to one aspect of the present invention, in a method for manufacturing a semiconductor device, a semiconductor layer is formed on a dielectric layer disposed over a substrate. A seed layer is formed on the semiconductor layer. The seed layer is patterned into a patterned seed layer. A crystallization process is performed on the semiconductor layer using the patterned seed layer as a crystallization nucleus, thereby forming a crystallized semiconductor layer. In one or more of the above and below embodiments, the seed layer is made of MgO. In one or more of the above and below embodiments, the semiconductor layer is amorphous or polycrystalline. In one or more of the above and below embodiments, the semiconductor layer is made of Si, SiGe, or Ge.In one or more of the above and following embodiments, a thickness of the seed layer is 1 nm to 10 nm. In one or more of the above and following embodiments, the thickness of the seed layer is 10 nm to 50 nm. In one or more of the above and following embodiments, the crystallization process comprises thermal annealing at a temperature of 350°C to 450°C or laser annealing. In one or more of the above and following embodiments, sidewall spacers are formed on opposite side surfaces of the patterned seed layer. A source / drain structure is formed. An interlayer dielectric (ILD) layer is formed over the sidewall spacers, the patterned seed layer, and the source / drain structure. After the ILD layer is formed, the patterned seed layer is removed to form a gate gap.A gate dielectric layer and a gate electrode layer are formed in the gate gap.

[0064] According to another aspect of the present invention, in a method for manufacturing a semiconductor device, a semiconductor layer is formed on a dielectric layer disposed over a substrate. A seed layer is formed on the semiconductor layer. The seed layer is patterned into patterned seed layers. A crystallization process is performed on the semiconductor layer using the patterned seed layers as a crystallization nucleus, thereby forming crystallized semiconductor layers. In one or more of the above and following embodiments, the seed layer is made of MgO. In one or more of the above and following embodiments, the semiconductor layer is amorphous or polycrystalline and is made of Si, SiGe, or Ge.In one or more of the above and following embodiments, the crystallization process comprises thermal annealing at a temperature of 350°C to 450°C or laser annealing. In one or more of the above and following embodiments, sidewall spacers are formed on opposite side surfaces of the patterned seed layers. A source / drain structure is formed. An interlayer dielectric (ILD) layer is formed over the sidewall spacers, the patterned seed layers, and the source / drain structure. After the ILD layer is formed, the patterned seed layers are removed to form gate gaps. A gate dielectric layer and a gate electrode layer are formed in each of the gate gaps.In one or more of the above and following embodiments, the crystallization process is performed such that a front portion of a crystallized semiconductor layer under one of the seed layers meets a front portion of a crystallized semiconductor layer under another of the seed layers that is adjacent to the one of the seed layers, thereby forming a grain boundary. In one or more of the above and following embodiments, the crystallization process is terminated before a front portion of a crystallized semiconductor layer under one of the seed layers meets a front portion of a crystallized semiconductor layer under another of the seed layers that is adjacent to the one of the seed layers.

[0065] According to another aspect of the present invention, in a method for manufacturing a semiconductor device, a semiconductor layer is formed on a dielectric layer disposed over a substrate. A seed layer is formed on the semiconductor layer. A dummy gate layer is formed on the seed layer. The dummy gate layer and the seed layer are patterned into a patterned dummy gate layer and a patterned seed layer. A crystallization process is performed on the semiconductor layer using the patterned seed layer as a crystallization nucleus, thereby forming a crystallized semiconductor layer. In one or more of the above and following embodiments, the dummy gate layer is amorphous or polycrystalline and is made of Si, SiGe, or Ge.In one or more of the above and following embodiments, a thickness of the dummy gate layer is 50 nm to 200 nm. In one or more of the above and following embodiments, the seed layer is made of MgO. In one or more of the above and following embodiments, sidewall spacers are formed on opposite side surfaces of the patterned dummy gate layer and the patterned seed layer. A source / drain structure is formed. An interlayer dielectric (ILD) layer is formed over the sidewall spacers, the patterned dummy gate layer, and the source / drain structure. After the ILD layer is formed, the patterned dummy gate layer and the patterned seed layer are removed to form a gate gap. A gate dielectric layer and a gate electrode layer are formed in the gate gap.

[0066] According to another aspect of the present invention, a semiconductor device comprises: a channel as a portion of a semiconductor layer disposed on a dielectric layer; a gate dielectric layer disposed over the channel; a gate electrode layer disposed over the gate dielectric layer; sidewall spacers disposed on opposite side surfaces of the gate electrode layer; and a source and a drain. The semiconductor layer comprises a crystalline portion as the channel and a non-crystalline portion. In one or more of the above and following embodiments, the semiconductor device further comprises one or more transistors covered by the dielectric layer. In one or more of the above and following embodiments, the one or more transistors comprise fin field-effect transistors.In one or more of the above and following embodiments, the semiconductor layer consists of Si, SiGe, or Ge. In one or more of the above and following embodiments, a thickness of the semiconductor layer is 10 nm to 50 nm.

[0067] According to another aspect of the present invention, a semiconductor device comprises: an electronic device disposed on a substrate; one or more dielectric layers disposed over the electronic device; and thin-film transistors disposed on a topmost layer of the one or more dielectric layers. The thin-film transistors each comprise: a channel fabricated as a part of a semiconductor layer disposed on the topmost layer; a gate dielectric layer disposed over the channel; a gate electrode layer disposed over the gate dielectric layer; sidewall spacers disposed on opposite side surfaces of the gate electrode layer; and a source and a drain.The semiconductor layer is single-crystalline, and a grain boundary is present between the semiconductor layer of one of the thin-film transistors and the semiconductor layer of another of the thin-film transistors adjacent to the one of the thin-film transistors. In one or more of the above and following embodiments, the electronic device is a transistor. In one or more of the above and following embodiments, the transistor is a fin field-effect transistor or a gate-all-around transistor. In one or more of the above and following embodiments, the semiconductor layer is made of Si, SiGe, or Ge. In one or more of the above and following embodiments, the topmost layer is made of silicon oxide. In one or more of the above and following embodiments, a thickness of the semiconductor layer is 10 nm to 50 nm.In one or more of the above and following embodiments, the source and drain comprise an epitaxial semiconductor layer. In one or more of the above and following embodiments, the epitaxial semiconductor layer is in contact with one of the sidewall spacers of one of the thin-film transistors and with one of the sidewall spacers of the other of the thin-film transistors.

[0068] According to another aspect of the present invention, a semiconductor device comprises: an electronic device disposed on a substrate; one or more dielectric layers disposed over the electronic device; and thin-film transistors disposed on a topmost layer of the one or more dielectric layers. The thin-film transistors each comprise: a channel fabricated as a part of a semiconductor layer disposed on the topmost layer; a gate dielectric layer disposed over the channel; a gate electrode layer disposed over the gate dielectric layer; sidewall spacers disposed on opposite side surfaces of the gate electrode layer; and a source and a drain.The channel is single-crystalline, and between the semiconductor layer of one of the thin-film transistors and the semiconductor layer of another of the thin-film transistors adjacent to the one of the thin-film transistors, there is a non-crystalline semiconductor layer made of the same material as the semiconductor layer. In one or more of the above and following embodiments, the electronic device is a transistor. In one or more of the above and following embodiments, the transistor is a fin field-effect transistor or a gate-all-around transistor. In one or more of the above and following embodiments, the semiconductor layer is made of Si, SiGe, or Ge. In one or more of the above and following embodiments, a thickness of the semiconductor layer is 10 nm to 50 nm.In one or more of the above and following embodiments, the source and drain comprise an epitaxial semiconductor layer. In one or more of the above and following embodiments, the epitaxial semiconductor layer is in contact with one of the sidewall spacers of one of the thin-film transistors and with one of the sidewall spacers of the other of the thin-film transistors.

Claims

[1] A method of manufacturing a semiconductor device comprising the following steps: Producing a semiconductor layer (30) on a dielectric layer (20) arranged over a substrate (10); Producing a seed layer (40) on the semiconductor layer (30); Structuring the seed layer (40) into a structured seed layer (45); and Performing a crystallization process on the semiconductor layer (30) using the structured seed layer (45) as a crystallization nucleus, so that a crystallized semiconductor layer (30) is formed; Producing sidewall spacers (50) on opposite side surfaces of the structured seed layer (45); Removing the structured seed layer (45) to form a gate gap (47); and Forming a gate dielectric layer (70) and a gate electrode layer (75) in the gate gap (47). [2] The method of claim 1, wherein the seed layer (40) is made of MgO. [3] The method according to claim 1 or 2, wherein the semiconductor layer (30) is amorphous or polycrystalline. [4] Method according to one of the preceding claims, wherein the semiconductor layer (30) consists of Si, SiGe or Ge. [5] Method according to one of the preceding claims, wherein a thickness of the seed layer (40) is 1 nm to 10 nm. [6] Method according to one of the preceding claims, wherein a thickness of the semiconductor layer (30) is 10 nm to 50 nm. [7] A method according to any one of the preceding claims, wherein the crystallization process comprises thermal annealing at a temperature of 350°C to 450°C or laser annealing. [8] A method according to any one of the preceding claims, further comprising: Before removing the structured seed layer (45), producing a source / drain structure (60); and forming an interlayer dielectric layer (65) over the sidewall spacers (50), the patterned seed layer (45) and the source / drain structure (60); and Performing a planarization process in which the interlayer dielectric layer (65) above the patterned seed layer (45) is removed. [9] A method of manufacturing a semiconductor device comprising the following steps: Producing an amorphous or polycrystalline semiconductor layer (30) on a dielectric layer (20) disposed over a substrate (10); Producing a seed layer (40) on the semiconductor layer (30); Structuring the seed layer (40) into a plurality of structured seed layers (45); and Performing a crystallization process on the semiconductor layer (30) using the structured seed layers (45) as a crystallization nucleus, so that a plurality of single-crystalline semiconductor layers (30) are formed above the dielectric layer (20); Producing sidewall spacers (50) on opposite side surfaces of the structured seed layers (45); Removing the structured seed layers (45) to form gate gaps (47); and Forming a gate dielectric layer (70) and a gate electrode layer (75) in each of the gate gaps (47). [10] The method of claim 9, wherein the seed layer (45) is made of MgO. [11] A method according to claim 9 or 10, wherein the semiconductor layer (30) is amorphous or polycrystalline and consists of Si, SiGe or Ge. [12] A method according to any one of claims 9 to 11, wherein the crystallization process comprises thermal annealing at a temperature of 350°C to 450°C or laser annealing. [13] A method according to any one of claims 9 to 12, further comprising: Before removing the structured seed layers (45), producing a source / drain structure (60); forming an interlayer dielectric layer (65) over the sidewall spacers (50), the patterned seed layers (45) and the source / drain structure (60); and Performing a planarization process in which the interlayer dielectric layer (65) above the patterned seed layers (45) is removed. [14] The method according to any one of claims 9 to 13, wherein the crystallization process is carried out such that a front part of a crystallized semiconductor layer (30) under one of the seed layers (40) meets a front part of a crystallized semiconductor layer (30) under another of the seed layers (40) which is adjacent to the one of the seed layers (40), so that a grain boundary (37) is formed. [15] The method of any one of claims 9 to 14, wherein the crystallization process is terminated before a front portion of a crystallized semiconductor layer (30) under one of the seed layers (40) meets a front portion of a crystallized semiconductor layer (30) under another of the seed layers (40) that is adjacent to the one of the seed layers (40). [16] Semiconductor device comprising: an electronic device (100) arranged on a substrate (10); one or more dielectric layers (20) disposed over the electronic device (100); and Thin-film transistors (200) arranged on a top layer of the one or more dielectric layers (20), the thin-film transistors (200) each comprising: a channel (35) formed as part of a semiconductor layer (30) disposed on the topmost layer, a dielectric gate layer (70) disposed over the channel (35), a gate electrode layer (75) disposed over the gate dielectric layer (70), Sidewall spacers (50) arranged on opposite side surfaces of the gate electrode layer (75), and a source and a drain (60), wherein the channel (35) is single-crystalline and a grain boundary (37) is located between the semiconductor layer (30) of one of the thin-film transistors (200) and the semiconductor layer (30) of another of the thin-film transistors (200) which is adjacent to the one of the thin-film transistors (200). [17] The semiconductor device of claim 16, wherein the electronic device (100) is a transistor. [18] A semiconductor device according to claim 17, wherein the transistor is a fin field effect transistor or a gate all-around transistor. [19] A semiconductor device according to any one of claims 16 to 18, wherein the semiconductor layer (30) is made of Si, SiGe or Ge. [20] A semiconductor device according to any one of claims 16 to 19, wherein the uppermost layer is made of silicon oxide.

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