Semiconductor structure and manufacturing method of semiconductor structure

Abstract

The invention discloses a manufacturing method of a semiconductor structure and the semiconductor structure. The manufacturing method comprises the following steps: providing a substrate; forming a laminated structure formed by alternately stacking a plurality of semiconductor material layers and a plurality of insulating material layers on the substrate; channel region laminations and an initial gate column are formed in the lamination structure, the initial gate column at least comprises an initial gate conductive layer and an initial gate dielectric layer, the initial gate column is provided with two opposite first side walls which are in contact with the two adjacent channel region laminations respectively, and a second side wall is not in contact with the channel region laminations; at least removing the gate dielectric layer and the gate conductive layer on the second side wall to form a target gate column, the target gate column having two opposite third side walls in contact with the two adjacent channel region lamination layers, the gate conductive layer on the third side walls having a first length and the gate dielectric layer having a second length, the first length being smaller than the second length, the semiconductor structure with relatively high performance can be obtained through the manufacturing method.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and a method for fabricating the semiconductor structure. Background Technology

[0002] The development of dynamic memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. As the size of semiconductor device structures shrinks, the technological barriers encountered by existing structures are becoming increasingly apparent. Therefore, developing more novel structures based on existing structures is a powerful means to break through existing technological barriers.

[0003] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM that includes multilayer horizontal cell (MHC), typically comprising multiple transistors stacked on a substrate, has met the above requirements.

[0004] However, the process of fabricating multi-layer horizontal memory cells in a confined space, especially the fabrication of horizontal memory transistors, is quite challenging, and the performance of the fabricated horizontal memory transistors needs to be improved. Summary of the Invention

[0005] According to a first aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, comprising: providing a substrate; forming a stacked structure on the substrate consisting of alternating layers of semiconductor materials and layers of insulating materials; forming a channel region stack and an initial gate pillar extending along a first direction perpendicular to the surface of the substrate in the stacked structure, the initial gate pillar comprising at least an initial gate conductive layer and an initial gate dielectric layer, the initial gate pillar having two opposing first sidewalls respectively contacting two adjacent channel region stacks and a second sidewall not contacting any of the channel region stacks; removing at least the initial gate dielectric layer and the initial gate conductive layer located on the second sidewall of the initial gate pillar to form a target gate pillar, the target gate pillar comprising two opposing third sidewalls respectively contacting two adjacent channel region stacks, and a gate conductive layer having a first length and a gate dielectric layer having a second length located on the third sidewall, the gate dielectric layer being located between the gate conductive layer and the channel region stack, the first length being less than the second length, the length directions of the first length and the second length being both a second direction, the second direction being parallel to the surface of the substrate and the surface of the third sidewall.

[0006] In some embodiments, forming a channel region stack extending along a first direction perpendicular to the substrate surface in the stacked structure includes: forming a plurality of first through holes in the stacked structure, the first through holes extending along the first direction and penetrating the stacked structure, the plurality of first through holes being spaced apart along a third direction parallel to the substrate surface, the stacked structure between adjacent first through holes serving as the channel region stack, the third direction being perpendicular to the second direction.

[0007] In some embodiments, forming an initial gate pillar extending along a first direction perpendicular to the substrate surface in the stacked structure includes: filling a first through-hole with sacrificial material to form a first sacrificial pillar; forming a first mask with a first opening on the stacked structure; etching along the first opening to form a second through-hole in the first sacrificial pillar, the second through-hole penetrating the stacked structure and, at least in the third direction, having a size substantially the same as the size of the first through-hole; sequentially forming an initial gate dielectric layer, an initial gate conductive layer, and a first insulating layer in the second through-hole to constitute the initial gate pillar; in the third direction, the initial gate pillar has two opposing first sidewalls that respectively contact two adjacent channel region stacks; and in the second direction, the initial gate conductive layer on the first sidewall of the initial gate pillar has a third length, the third length being greater than the first length and the third length being greater than or equal to the second length.

[0008] In some embodiments, after forming the second through-hole and before forming the initial gate pillar in the second through-hole, the fabrication method further includes: ion implantation of the channel region stack through the second through-hole to form an inversion-doped channel region.

[0009] In some embodiments, removing at least the initial gate dielectric layer and the initial gate conductive layer located on the second sidewall of the initial gate pillar to form a target gate pillar includes: forming a second mask having a second opening on the stacked structure; etching along the second opening to form a third through-hole in the first sacrificial pillar, the third through-hole penetrating the stacked structure and exposing the second sidewall of the initial gate pillar; and using the third through-hole to remove at least the initial gate dielectric layer and the initial gate conductive layer located on the second sidewall to form the target gate pillar, wherein, along the third direction, the target gate pillar has two opposing third sidewalls that respectively contact two adjacent channel region stacks.

[0010] In some embodiments, after forming the third through-hole and before using the third through-hole to at least remove the initial gate conductive layer located on the second sidewall, the fabrication method further includes: ion implanting the stacked structure adjacent to the channel region stack through the third through-hole to form a lightly doped drain region.

[0011] In some embodiments, after forming the target gate pillar, the fabrication method further includes filling the third through-hole with a second insulating layer.

[0012] In some embodiments, after forming the target gate pillar and before filling the third through-hole with the second insulating layer, the fabrication method further includes: forming an auxiliary gate layer in the third through-hole, the auxiliary gate layer being located at two opposite ends of the gate conductive layer disposed along the second direction, the work function of the auxiliary gate layer being less than the work function of the gate conductive layer.

[0013] In some embodiments, after forming the target gate pillar, the fabrication method further includes: connecting the gate conductive layers on two third sidewalls located on opposite sides of the same channel region stack and in contact with the channel region stack to form a word line structure.

[0014] In some embodiments, after forming the stacked structure, the fabrication method further includes: forming a bit line structure and a capacitor structure, wherein the bit line structure and the capacitor structure are respectively located at opposite ends of the channel region stack disposed in the second direction.

[0015] According to a second aspect of the present disclosure, a semiconductor structure is provided, comprising: a substrate; a stacked structure formed on the substrate by alternating stacking of a plurality of semiconductor layers and a plurality of insulating material layers, the stacked structure further comprising at least a channel region stack extending along a first direction perpendicular to the surface of the substrate; a target gate post extending through the stacked structure along the first direction, the target gate post comprising two opposing third sidewalls respectively contacting two adjacent channel region stacks, and a gate conductive layer having a first length and a gate dielectric layer having a second length located on the third sidewalls, the gate dielectric layer being located between the gate conductive layer and the channel region stack, the first length being less than the second length, the length directions of the first length and the second length being both the second direction, the second direction being parallel to the surface of the substrate and the surface of the third sidewalls.

[0016] In some embodiments, the channel region stack and the target gate pillar are alternately arranged along a third direction, which is parallel to the substrate surface and perpendicular to the second direction.

[0017] In some embodiments, the target gate post further includes a first insulating layer, and the gate conductive layers located on the same target gate post on two third sidewalls disposed opposite each other along the third direction are isolated by the first insulating layer.

[0018] In some embodiments, the channel region stack further includes an inversion-doped channel region located in the region where the channel region stack contacts the third sidewall of the target gate pillar; the stack structure further includes a lightly doped drain region stack adjacent to the channel region stack on opposite sides along the second direction, the lightly doped drain region stack further including a lightly doped drain region with the ion doping type opposite to that of the inversion-doped channel region.

[0019] In some embodiments, the semiconductor structure further includes an auxiliary gate layer, which is located on both sides of the gate conductive layer on the third sidewall of the target gate pillar disposed opposite each other along the second direction, and the work function of the auxiliary gate layer is less than the work function of the gate conductive layer.

[0020] In some embodiments, the semiconductor structure further includes: a word line structure including a gate conductive layer connecting two third sidewalls of the same channel region stack disposed opposite each other along the third direction and in contact with the channel region stack.

[0021] In some embodiments, the semiconductor structure further includes a bit line structure and a capacitor structure, wherein the bit line structure and the capacitor structure are respectively located on opposite sides of the channel region stack disposed along the second direction. Attached Figure Description

[0022] Figure 1 This is a schematic diagram illustrating the provision of a substrate according to an exemplary embodiment;

[0023] Figure 2 This is a schematic diagram illustrating the formation of a stacked structure according to an exemplary embodiment;

[0024] Figure 3 This is a schematic diagram illustrating the formation of a first through-hole and channel region stack according to an exemplary embodiment;

[0025] Figure 4 This is a schematic diagram illustrating the formation of a first sacrificial column according to an exemplary embodiment;

[0026] Figure 5 This is a schematic diagram illustrating the formation of a second through hole according to an exemplary embodiment;

[0027] Figure 6This is a schematic diagram illustrating the formation of an inversion-doped channel region according to an exemplary embodiment;

[0028] Figure 7 This is a schematic diagram illustrating the formation of an initial gate pillar according to an exemplary embodiment;

[0029] Figure 8 This is a schematic diagram illustrating the formation of a third through hole according to an exemplary embodiment;

[0030] Figures 9 to 10 This is a schematic diagram illustrating the formation of a lightly doped drain region stack and the removal of the initial gate dielectric layer and initial gate conductive layer on the second sidewall of the initial gate pillar through a third through-hole, according to an exemplary embodiment.

[0031] Figure 11 This is a schematic diagram illustrating the formation of a second insulating layer according to an exemplary embodiment;

[0032] Figure 12 This is a schematic diagram illustrating the formation of a second insulating layer according to another exemplary embodiment;

[0033] Figure 13 This is a schematic diagram illustrating the formation of an auxiliary gate and a second insulating layer according to yet another exemplary embodiment;

[0034] Figure 14 This is a schematic diagram illustrating the formation of a bit line structure and a capacitor structure according to an exemplary embodiment. Detailed Implementation

[0035] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0036] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0037] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0038] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0039] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0040] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0041] In related technologies, the fabrication process of 3D memory structures typically involves forming a stack of semiconductor and insulating materials, and then forming memory cell structures, such as storage transistors, storage capacitors, bit lines, and word lines, based on the semiconductor materials. Regarding the formation of word line structures in 3D memory structures, there are generally two mainstream formation methods: one is where the word line structure controls a vertical column of transistors perpendicular to the substrate, and the other is where the word line structure controls a horizontal row of transistors parallel to the substrate. Both word line structures have their advantages and disadvantages, and this disclosure mainly introduces the first type of word line structure and its fabrication method. The inventors of this application have discovered that during the formation of vertical word line structures in the stack of 3D memory structures, due to space constraints and a thinner gate oxide layer, the word line structure, acting as the gate of a transistor, connects to the channel region of the transistor structure at the overlap with the drain. This easily leads to gate-induced drain leakage (GIDL) effects, which can severely affect the performance of the storage transistors, memory cell structures, and even the entire memory device.

[0042] To address the aforementioned technical problems, this disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself, which will be discussed below. Figures 1 to 14 This disclosure provides a specific example of a semiconductor structure and a method for fabricating the semiconductor structure. Figures 1 to 11 This is a schematic diagram illustrating the steps of a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure. Figures 11 to 14 This is a schematic diagram of a semiconductor structure according to several exemplary embodiments of the present disclosure.

[0043] In an exemplary embodiment of this disclosure, a substrate 101 is provided, with reference to Figure 1 As shown, where, Figure 1 (c) is a top view facing the substrate 101 and along a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction). Figure 1 (a) and Figure 1 (b) respectively Figure 1 (c) Schematic diagrams along sections A-A' and B-B'. Section A-A' is parallel to the X direction and perpendicular to the Y direction, and section B-B' is parallel to the Y direction and perpendicular to the X direction.

[0044] The substrate 101 may be made of at least one of the following semiconductor materials or group III-V materials: silicon, germanium, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). In an exemplary embodiment of this disclosure, the substrate 101 is made of single-crystal silicon.

[0045] In an exemplary embodiment of this disclosure, a stacked structure 102 consisting of alternating layers of semiconductor material 1022 and multiple layers of insulating material 1021 is formed on a substrate 101, such as... Figure 2 As shown, where, Figure 2 (c) is a top view facing the substrate 101 and along a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction). Figure 2 (a) and Figure 2 (b) respectively Figure 2 (c) is a schematic diagram along sections A-A' and B-B'. Section A-A' is parallel to the X direction and perpendicular to the Y direction, while section B-B' is parallel to the Y direction and perpendicular to the X direction. In some embodiments, multiple semiconductor material layers 1022 and multiple insulating material layers 1021 are alternately interspersed, i.e., as shown in the diagram. Figure 2 (a) or Figure 2 As shown in (b), a single-layer insulating material layer 1021 is interspersed between any two adjacent single-layer semiconductor material layers 1022, and a single-layer semiconductor material layer 102 is interspersed between any two adjacent single-layer insulating layers 1021. In the semiconductor material layers, the first semiconductor material layer 1023 or the second semiconductor material layer 1022 is closer to the substrate, but this disclosure does not impose specific limitations.

[0046] In some embodiments, the material of the semiconductor material layer 1022 may be at least one or any combination of the following materials: silicon, germanium, silicon germanide (SiGe), III-V group materials, indium gallium zinc oxide (IGZO), and two-dimensional materials. In an exemplary embodiment of this disclosure, the semiconductor material layer 1022 is made of silicon. In some embodiments, the material of the insulating material layer 1021 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonoxide, silicon carbonitride, and silicon carbonitride. In an exemplary embodiment of this disclosure, the insulating material layer 1021 is made of silicon oxide.

[0047] In an exemplary embodiment of this disclosure, the method for forming the stacked structure 102 includes: using the surface of a single-crystal silicon (Si) substrate 101 as an initial base layer, and growing an initial stacked structure of alternating silicon-silicon germanide (Si-SiGe) layers on the substrate 101 using an epitaxial growth method. Specifically, a silicon germanide layer can be formed as a sacrificial layer by adding germanium source gas during the epitaxial growth of the silicon layers, followed by selective lateral etching to remove the sacrificial silicon germanide layer, and then depositing or growing an insulating material between the silicon layers to replace the silicon germanide layer, thereby forming an insulating material layer 1021.

[0048] In some embodiments, the number of insulating material layers 1021 in the stacked structure 102 is one more than the number of semiconductor material layers 1022, and both are greater than or equal to 4. In other embodiments, the number of insulating material layers 1021 and semiconductor material layers 1022 in the stacked structure 102 is the same, and both are greater than or equal to 4. In some embodiments, the bottom layer in the stacked structure 102, i.e., the single layer in direct contact with the substrate 101, is the insulating material layer 1021, to ensure that the subsequent formation of the underlying memory cell structure is isolated from the substrate 101. In some embodiments, the top layer in the stacked structure 102, i.e., the single layer farthest from the substrate 101, is the insulating material layer 1021, to protect the underlying memory cell structure from damage during subsequent processes.

[0049] In some embodiments, before or after forming the stacked structure 102 on the substrate 101, an isolation layer (not shown) is formed on other regions of the substrate 101, wherein the isolation layer is at the same height as the stacked structure 102.

[0050] In an exemplary embodiment of this disclosure, a plurality of first through holes 1030 are formed in the stacked structure 102. The first through holes 1030 extend along the Z direction and penetrate the stacked structure 102. The plurality of first through holes 1030 are spaced apart along the Y direction. The stacked structure 102 between adjacent first through holes 1030 serves as a channel region stack, such as... Figure 3 As shown, where, Figure 3(c) is a top view facing the substrate 101 and along a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction). Figure 3 (a) and Figure 3 (b) respectively Figure 3 (c) Schematic diagrams along sections A-A' and B-B'. Section A-A' is parallel to the X direction and perpendicular to the Y direction, and section B-B' is parallel to the Y direction and perpendicular to the X direction.

[0051] In some embodiments, the spacing between adjacent first through holes 1030 is equal. In some embodiments, the cross-sectional shape of the first through hole along the direction parallel to the surface of the substrate 101 is rectangular, rounded rectangular, or a rectangular shape with arc-shaped edges at both ends in the X direction and straight edges at both ends in the Y direction, so as to ensure that the channel region stack located between adjacent first through holes has a relatively flat sidewall surface.

[0052] In some embodiments, photolithography can be used to etch the stacked structure 102 to form the first through-hole 1030. Specifically, a photoresist mask layer can be formed on the stacked structure 102. By exposure and development, the pattern of the first through-hole 1030 is formed in the photoresist mask layer. Then, dry etching is performed to etch the stacked structure 102 along the pattern to form the first through-hole 1030. In some embodiments, before coating the photoresist mask layer, an anti-reflective layer and a hard mask layer (not shown) are formed on the top surface of the stacked structure 102, and both are removed after the first through-hole 1030 is formed.

[0053] In an exemplary embodiment of this disclosure, after forming the first through hole 1030, the first through hole is filled with sacrificial material to form a first sacrificial pillar 103, such as... Figure 4 As shown, where, Figure 4 (c) is a top view facing the substrate 101 and along a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction). Figure 4 (a) and Figure 4 (b) respectively Figure 4(c) shows schematic diagrams along sections A-A' and B-B'. Section A-A' is parallel to the X direction and perpendicular to the Y direction, while section B-B' is parallel to the Y direction and perpendicular to the X direction. Specifically, in some embodiments, a first sacrificial material layer 1031 is first deposited in the first through-hole 1030 to cover the inner wall (including the sidewalls and bottom wall) of the first through-hole 1030. Then, a second sacrificial material layer 1032 is deposited on the surface of the first sacrificial material layer 1031 to fill the first through-hole 1030. The first sacrificial material layer 1031 and the second sacrificial material layer 1032 together constitute the first sacrificial pillar 103. Since the first sacrificial material layer 1031 covers the sidewalls and bottom wall of the first through-hole 1030, it also covers the sidewalls of the channel region stack separated by the first through-hole 1030 and the surface of the substrate 101, thus providing a certain buffer protection for the sidewalls of the channel region stack and the surface of the substrate 101 in subsequent etching processes. In some other embodiments, the first sacrificial column 103 further includes a third sacrificial material layer (not shown) located between the first sacrificial material layer 1031 and the second sacrificial material layer 1032.

[0054] In some embodiments, the materials of the first sacrificial material layer 1031 and the second sacrificial material layer 1032 may be at least one or any combination of the following materials: silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, silicon carbonitride, and polycrystalline silicon. In an exemplary embodiment of this disclosure, the first sacrificial material layer 1031 is made of silicon oxide, and the second sacrificial material layer 1032 is made of polycrystalline silicon.

[0055] In some embodiments, the deposition method of the first sacrificial material layer 1031 and the second sacrificial material layer 1032 may employ at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), and atomic layer deposition (ALD).

[0056] In an exemplary embodiment of this disclosure, after forming the first sacrificial pillar 103, a first mask 1041 having a first opening 1040' is formed on the stacked structure 102. Etching is performed along the first opening 1040' to form a second through-hole 1040 in the first sacrificial pillar 103. The second through-hole 1040 penetrates the stacked structure 102, and at least in the Y direction, the size of the second through-hole 1040 is substantially the same as the size of the first through-hole 1030. (Refer to...) Figure 5As shown, where, Figure 5 (c) is a top view facing the substrate 101 and along a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction). Figure 5 (a) and Figure 5 (b) respectively Figure 5 (c) Schematic diagrams along sections A-A' and B-B'. Section A-A' is parallel to the X direction and perpendicular to the Y direction, and section B-B' is parallel to the Y direction and perpendicular to the X direction.

[0057] In some embodiments, viewed from a cross-section parallel to the surface of substrate 101, the second through-hole 1040 is located near the center of the first sacrificial pillar 103, equivalent to or approximately equivalent to a common central axis. It should be noted that the direction of this "central axis" is perpendicular to the surface of substrate 101. In some embodiments, the two sidewalls of the second through-hole 1040, which are oppositely disposed along the Y direction, expose the sidewalls of the channel region stack. In some embodiments, the dimension of the second through-hole 1040 along the X direction is smaller than the dimension of the first through-hole 1030 along the X direction, and greater than or equal to the dimension of the channel region stack in the X direction.

[0058] In some embodiments, the first opening 1040' is a single elongated strip with its long side extending along the Y direction, exposing a portion of the top surface of the first sacrificial pillar 103 and the top surface of the entire channel region stack. In some embodiments, the first opening 1040' can be formed by photolithography to etch the first mask 1041 to form the first opening 1040'. Specifically, a photoresist mask layer can be formed on the first mask 1041, and the pattern of the first opening 1040' can be formed in the photoresist mask layer by exposure and development. Then, dry etching can be performed to etch the first mask 1041 along the pattern to form the first opening 1040'. In some embodiments, before coating the photoresist mask layer, an anti-reflection layer (not shown) is formed on the top surface of the first mask 1041, and is removed after the first opening 1040' is formed.

[0059] In some embodiments, the material of the first mask 1041 may be any one or a combination of silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, and silicon carbonitride. In some embodiments, the deposition method of the first mask 1041 may employ at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), and atomic layer deposition (ALD).

[0060] In some embodiments, the etching process for forming the second through hole 1040 is basically the same as the etching process for forming the first through hole 1030 in the foregoing embodiments, and will not be described again here. However, unlike the formation of the first through hole 1030 in the foregoing embodiments, the first mask 1041 will not be removed temporarily after the second through hole 1040 is formed.

[0061] In an exemplary embodiment of this disclosure, after forming the second through-hole 1040, ion implantation L1 is performed through the second through-hole 1040 to form an inversion-doped channel region 1022a, as shown below. Figure 6 As shown, where, Figure 6 (c) is a top view facing the substrate 101 and along a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction). Figure 6 (a) and Figure 6 (b) respectively Figure 6 (c) shows schematic diagrams along sections A-A' and B-B'. Section A-A' is parallel to the X direction and perpendicular to the Y direction, while section B-B' is parallel to the Y direction and perpendicular to the X direction. Specifically, ion implantation L1 at an angle is performed from the second through-hole 1040 towards the sidewalls of the exposed channel region stack, using the first mask 1041 and the top insulating material layer 1021 exposed by the first opening 1040' as masks, to form inverse-doped channel regions 1022a on the two sidewalls of each channel region stack that are opposite each other in the Y direction. It should be noted that the "angle of inclination" here is tilted along the Y direction or the opposite direction of the Y direction with the Z direction (or its reverse) as the axis.

[0062] In some embodiments, the ions implanted into L1 can be boron ions.

[0063] In an exemplary embodiment of this disclosure, after forming the inversion-doped channel region 1022a, an initial gate dielectric layer 1051, an initial gate conductive layer 1052, and a first insulating layer are sequentially formed in the second through-hole 1040 to constitute an initial gate pillar 105. In the Y direction, the initial gate pillar 105 has two opposing first sidewalls that respectively contact the stacked layers of two adjacent channel regions, and in the X direction, the initial gate conductive layer 1052 located on the first sidewall of the initial gate pillar 105 has a third length D3, such as... Figure 7 As shown, where, Figure 7 (c) is a top view facing the substrate 101 and along a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction). Figure 7 (a) and Figure 7 (b) respectively Figure 7 (c) is a schematic diagram along sections A-A' and B-B', where section A-A' is parallel to the X direction and perpendicular to the Y direction, and section B-B' is parallel to the Y direction and perpendicular to the X direction. In some embodiments, the first insulating layer includes a plurality of insulator layers. In an exemplary embodiment of this disclosure, the first insulating layer includes a first insulator layer 1053 and a second insulator layer 1054, wherein the first insulator layer 1053 is located on the outer periphery of the second insulator layer 1054. In some embodiments, in the X direction, the sidewall of the initial gate dielectric layer 1051 in contact with the channel region stack at least covers the surface of the inversion-doped channel region 1022a.

[0064] In some embodiments, the materials of the first insulator layer 1053 and the second insulator layer 1054 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In an exemplary embodiment of this disclosure, the material of the first insulator layer 1053 is silicon nitride, and the material of the second insulator layer 1054 is silicon oxide. In some embodiments, the deposition method of the first insulating layer may employ at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), and atomic layer deposition (ALD).

[0065] In some embodiments, the initial gate dielectric layer 1051 may be made of silicon oxide, and the initial gate conductive layer 1052 may be made of titanium nitride or tungsten. In an exemplary embodiment of this disclosure, the initial gate dielectric layer 1051 is formed using an in-situ vapor deposition (ISSG) process, and the initial gate conductive layer 1052 is formed using an atomic layer deposition (ALD) process.

[0066] In an exemplary embodiment of this disclosure, after forming the initial gate pillar 105, a second mask 1061 having a second opening 1060' is formed on the stacked structure 102. Etching is performed along the second opening 1060' to form a third through-hole 1060 in the first sacrificial pillar 103. The third through-hole 1060 penetrates the stacked structure 102 and exposes the second sidewall of the initial gate pillar 105, wherein the second sidewall of the initial gate pillar 105 does not contact the channel region stack. (Refer to...) Figure 8 As shown, Figure 8 (c) is a top view facing the substrate 101 and along a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction). Figure 8 (a) and Figure 8 (b) respectively Figure 8 (c) is a schematic diagram along cross sections A-A' and B-B', where cross section A-A' is parallel to the X direction and perpendicular to the Y direction, and cross section B-B' is parallel to the Y direction and perpendicular to the X direction. In some embodiments, in a plane direction parallel to the surface of substrate 101, the location of the second opening 1060' is adjacent to the two ends of the location of the first opening 1040' in the X direction in the aforementioned embodiment. In some embodiments, the third through-hole 1060 removes all the remaining first sacrificial pillars 103 after the formation of the second through-hole 1040 in the aforementioned embodiment. In some embodiments, the initial gate dielectric layer 1051 on the second sidewall of the initial gate pillar 105 is also removed when forming the third through-hole 1060, such as... Figure 8 As shown in (a).

[0067] In some embodiments, viewed from a cross-section parallel to the surface of the substrate 101, the third through-hole 1060 is located near both ends of the first sacrificial pillar 103 in the X direction, i.e., the third through-hole 1060 is adjacent to both ends of the initial gate pillar 105 in the X direction. In some embodiments, the third through-hole 1060 is symmetrically arranged about the plane common to the central axis of the plurality of initial gate pillars 105 arranged in the Y direction. In some embodiments, the third through-hole 1060 exposes at least the sidewalls of the stacked structure 102 adjacent to the channel region stack.

[0068] In some embodiments, the second opening 1060' is in the form of two elongated strips, with the long side extending along the Y direction, exposing the top surface of the remaining first sacrificial pillar 103 and the top surface of the stacked structure 102 adjacent to the trench region stack. In some embodiments, the method of forming the second opening 1060' can be the same as the method of forming the first opening 1040' described in the foregoing embodiments, and will not be repeated here.

[0069] In some embodiments, the material and formation method of the second mask 1061 may be substantially the same as those described in the foregoing embodiments regarding the material and formation method of the first mask 1041, and will not be repeated here.

[0070] In some embodiments, the etching process for forming the third through hole 1060 is basically the same as the etching process for forming the first through hole 1030 in the foregoing embodiments, and will not be described again here. However, unlike the formation of the first through hole 1030 in the foregoing embodiments, the second mask 1061 will not be removed temporarily after the third through hole 1060 is formed.

[0071] In an exemplary embodiment of this disclosure, after forming the third through-hole 1060, ion implantation L2 is performed through the third through-hole 1060 on the stacked structure 102 adjacent to the channel region stack to form a lightly doped drain region 1022b (LDD), as shown below. Figure 9 As shown, where, Figure 9 (c) is a top view facing the substrate 101 and along a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction). Figure 9 (a) and Figure 9 (b) respectively Figure 9(c) is a schematic diagram along the A-A' and C-C' sections. The A-A' section is parallel to the X direction and perpendicular to the Y direction, and the C-C' section is parallel to the Y direction and perpendicular to the X direction. Specifically, from the third through-hole 1060 to the sidewalls of the stacked structure 102 exposed by the third through-hole 1060, using the second mask 1061 and the top insulating material layer 1021 exposed by the second opening 1060' as masks, ion implantation L2 is performed at an inclined angle to form lightly doped drain regions 1022b on the two sidewalls of the stacked structure 102 exposed by the third through-hole 1060 and at least located opposite each other in the Y direction. That is, lightly doped drain regions 1022b are formed on the surfaces of the two sidewalls of each semiconductor material layer 1022 in the stacked structure 102 exposed by the third through-hole 1060 and at least located opposite each other in the Y direction, so as to form a lightly doped drain region stack. It should be noted that the "tilt angle" here refers to tilting along the Y direction or the opposite direction of the Y direction with the Z direction (or its reverse) as the axis. In some embodiments, the lightly doped drain region 1022b is formed in a portion of the sidewall region of the stacked structure 102 exposed by the third through-hole 1060; while in other embodiments, the lightly doped drain region 1022b is formed in the entire sidewall region of the stacked structure 102 exposed by the third through-hole 1060. It should be noted that "partial region" and "entire region" here refer to the surface region of each semiconductor material layer 1022, and the lightly doped drain regions 1022b are not formed in the insulating material layers 1021 exposed by the third through-hole 1060 in the stacked structure 102.

[0072] In some embodiments, the dopant ion type of ion implantation L2 is opposite to that of ion implantation L1 in the foregoing embodiments. The ion implanted in L2 can be phosphorus ions or arsenic ions.

[0073] In some embodiments, after forming the lightly doped drain region 1022b, the stacked structure 102 adjacent to the two ends of the channel region stack disposed opposite to each other in the X direction is further doped to form a source / drain region, wherein the dopant ion type of the source / drain region is the same as the dopant ion type of the lightly doped drain region 1022b.

[0074] In an exemplary embodiment of this disclosure, after forming the lightly doped drain region 1022b, at least the initial gate conductive layer 1052 located on the second sidewall of the initial gate pillar 105 is removed along the third through-hole 1060 to form the target gate pillar 105'. In the Y direction, the target gate pillar 105' has two opposing third sidewalls that are respectively in contact with two adjacent channel region stacks, and a gate conductive layer 1052' with a first length and a gate dielectric layer 1051' with a second length located on the third sidewalls. The first length is less than the second length, such as... Figure 10 As shown, Figure 10(c) is a top view facing the substrate 101 and along a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction). Figure 10 (a) and Figure 10 (b) respectively Figure 10 (c) shows schematic diagrams along cross sections A-A' and B-B'. Cross section A-A' is parallel to the X direction and perpendicular to the Y direction, while cross section B-B' is parallel to the Y direction and perpendicular to the X direction. Specifically, wet chemical etching or lateral dry etching is used to etch from the third through-hole 1060 to the second sidewall exposed by the third through-hole 1060 of the initial gate pillar 105, at least removing the initial gate conductive layer 1052 located on the second sidewall.

[0075] In some embodiments, since the initial gate dielectric layer 1051 on the second sidewall of the initial gate pillar 105 was removed simultaneously during the formation of the third through-hole 1060 in the aforementioned embodiments, this side etching will only remove the initial gate conductive layer 1052 on the second sidewall. In other embodiments, after the formation of the third through-hole 1060 in the aforementioned embodiments, the initial gate dielectric layer 1051 on the second sidewall of the initial gate pillar 105 was not removed or was not completely removed. In this side etching, the initial gate dielectric layer 1051 on the second sidewall will be removed first, followed by the initial gate conductive layer 1052 on the second sidewall.

[0076] In some embodiments, after the initial gate conductive layer 1052 on the second sidewall of the initial gate pillar 105 is removed by side etching, a small amount of over-etching is performed on the initial gate conductive layer 1052 on the first sidewall of the initial gate pillar 105 that is in contact with the channel region stack to obtain the target gate pillar 105'.

[0077] In some embodiments, the initial gate conductive layer 1052 on the first sidewall of the initial gate pillar 105 in the foregoing embodiments has a third length in the X direction, which is greater than the first length and greater than or equal to the second length. That is, due to the etching of the initial gate dielectric layer 1051 and the initial gate conductive layer 1052 on the second sidewall of the initial gate pillar 105, the retained initial gate dielectric layer 1051 and the initial gate conductive layer 1052 on the first sidewall of the initial gate pillar 105 are also worn down to a certain extent. The final target gate pillar 105' has a shorter length in the X direction of the gate conductive layer 1052' on the third sidewall compared to the original initial gate conductive layer 1052. The overlapping area of ​​the gate conductive layer 1052' and the lightly doped drain region in the Y direction is reduced, thereby reducing the probability of gate-induced drain leakage (GIDL) effect, reducing the impact of GIDL, and thus improving the operating performance of the memory device.

[0078] In an exemplary embodiment of this disclosure, after forming the target gate pillar 105', a second insulating layer 107 is filled into the third through-hole 1060, such as... Figure 11 As shown, Figure 11 (c) is a top view facing the substrate 101 and along a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction). Figure 11 (a) and Figure 10 (b) respectively Figure 10 (c) is a schematic diagram along cross sections A-A' and B-B', where cross section A-A' is parallel to the X direction and perpendicular to the Y direction, and cross section B-B' is parallel to the Y direction and perpendicular to the X direction. In some embodiments, the second insulating layer 107 fills the third through-hole 1060, is located at the opposite ends of the target gate post 105' in the X direction, and is in seamless contact with the target gate post 105'.

[0079] In some embodiments, the material and formation method of the second insulating layer 107 may be the same as those described in the foregoing embodiments regarding the material and formation method of the first insulating layer, and will not be repeated here. In an exemplary embodiment of this disclosure, the material of the second insulating layer 107 is silicon oxide. The silicon oxide of the second insulating layer 107 has a low dielectric constant, and when it covers the two ends of the gate conductive layer 1052' that are disposed opposite each other in the X direction, it can further reduce the influence of the GIDL effect caused by band-to-band tunneling (BTBT).

[0080] In another exemplary embodiment of this disclosure, reference is made to Figure 12 As shown, Figure 12 (c) is a top view facing the substrate 101 and along a direction perpendicular to the surface of the substrate 201 (i.e., opposite to the Z direction). Figure 12 (a) and Figure 12 (b) respectively Figure 12 (c) is a schematic diagram along sections A-A' and B-B'. Section A-A' is parallel to the X direction and perpendicular to the Y direction, and section B-B' is parallel to the Y direction and perpendicular to the X direction, providing the same as in the aforementioned embodiments. Figure 10 The structure shown is basically the same as that shown. Figure 11 The difference between the structure and the formation steps shown is that... Figure 12 Before filling the third through hole with the second insulating layer 2072, the process also includes forming a third insulating layer 2071 to cover the inner wall (including the sidewall and bottom wall) of the third through hole. The third insulating layer 2071 is located between the subsequently filled second insulating layer 2072 and the substrate 201, the stacked structure 202 and the target gate pillar 205'.

[0081] In some embodiments, the materials and formation methods of the second insulating layer 2072 and the third insulating layer 2071 are described in the same way as those of the first insulating layer in the foregoing embodiments, and will not be repeated here. In an exemplary embodiment of this disclosure, the second insulating layer 2072 is made of silicon oxide, and the third insulating layer 2071 is made of silicon nitride. The silicon nitride of the third insulating layer 2071 has a good function of isolating oxygen and moisture. When it covers the two ends of the gate conductive layer 2052' and the gate dielectric layer 2051' that are disposed opposite each other in the X direction, it can protect the gate conductive layer 2052' and the gate dielectric layer 2051' from the influence of oxygen and moisture in the environment, thereby ensuring the working performance of the memory device to a certain extent.

[0082] In yet another exemplary embodiment of this disclosure, reference is made to... Figure 13 As shown, Figure 13 (c) is a top view facing the substrate 101 and along a direction perpendicular to the surface of the substrate 301 (i.e., opposite to the Z direction). Figure 13 (a) and Figure 13 (b) respectively Figure 13 (c) is a schematic diagram along sections A-A' and B-B'. Section A-A' is parallel to the X direction and perpendicular to the Y direction, and section B-B' is parallel to the Y direction and perpendicular to the X direction, providing the same as in the aforementioned embodiments. Figure 10 The structure shown is basically the same as that shown. Figure 11 The difference between the structure and the formation steps shown is that... Figure 13 Before filling the third through-hole with the second insulating layer 307, an auxiliary gate layer 308 is first formed. The auxiliary gate layer 308 is located at both ends of the gate conductive layer 3052' on the third sidewall of the target gate pillar 305, and the work function of the auxiliary gate layer 308 is less than that of the gate conductive layer 3052'. Specifically, an auxiliary gate material layer is first formed in the third through-hole to cover the inner wall of the third through-hole. Then, except for the positions at the two ends of the gate conductive layer 3052' that are relatively disposed in the X direction, the auxiliary gate material layer in other areas is etched, and the remaining auxiliary gate material layer serves as the auxiliary gate layer.

[0083] In some embodiments, the auxiliary gate layer 308 is made of doped polysilicon, and the gate conductive layer 3052' is made of titanium nitride. Compared with titanium nitride, doped polysilicon has a lower work function. The auxiliary gate layer 308 is located at both ends of the gate conductive layer 3052' on the third sidewall of the target gate pillar 305, which compensates for the problems of high gate resistance and poor electrical signal transmission caused by the short length of the gate conductive layer in the aforementioned embodiments. At the same time, since the auxiliary gate layer 308 is located in the region overlapping with the projection of the lightly doped drain region along the Y direction, the auxiliary gate layer with a low work function can also reduce the influence of the GIDL effect to a certain extent, thereby improving the operating performance of the memory device.

[0084] In some embodiments, the deposition method of the auxiliary gate layer 308 may employ at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), and atomic layer deposition (ALD).

[0085] In an exemplary embodiment of this disclosure, after forming the target gate pillar 105', two gate conductive layers 1052' located on opposite sides of the same channel region stack in the Y direction and in contact with the channel region stack are connected on the third sidewall to form a word line structure. Specifically, each word line structure corresponds one-to-one with each channel region stack, and the two gate conductive layers 1052' closest to each corresponding channel region stack are connected in pairs. The main body of the word line structure consists of two gate conductive layers 1052' adjacent to the same channel region stack, which jointly control the on or off of the inversion-doped channel region 1022a located in the same channel region stack.

[0086] In an exemplary embodiment of this disclosure, after forming the stacked structure 102, a bit line structure and a capacitor structure are further formed, respectively located at opposite ends of the channel region stack in the X direction. Specifically, at one end of the stacked structure 102 in the X direction, a portion of the semiconductor material layer 1022 can be selectively etched laterally to remove it, and then bit line material can be filled to form a bit line structure; at the other end of the stacked structure 102 in the X direction, a portion of the semiconductor material layer 1022 can be selectively etched laterally to remove it, and then capacitor material, including a first electrode material, a capacitor dielectric material, and a second electrode material, can be filled to form a capacitor structure. It should be noted that before forming the capacitor structure, an insulating isolation layer extending along the X and Z directions and penetrating the stacked structure 102 needs to be formed in the stacked structure 102 to space the channel region stacks and semiconductor material layers in the Y direction. See also... Figure 14 In (e), the structural and positional relationship between bit line structure 409 and capacitor structure 410 in stacked structure 402 is shown, wherein... Figure 14 (c) is a top view facing the substrate 101 and along a direction perpendicular to the surface of the substrate 401 (i.e., opposite to the Z direction). Figure 14 (a) Figure 14 (b) and Figure 14 (d) are respectively Figure 14(c) Schematic diagrams along sections A-A', B-B', and D-D'. Figure 14 (e) is Figure 14 (d) is a schematic diagram along the E-E' section. Figure 14 (f) is Figure 14 (e) is a magnified view of a portion of region F (dashed box). Sections A-A' and D-D' are parallel to the X direction and perpendicular to the Y direction, section B-B' is parallel to the Y direction and perpendicular to the X direction, and section E-E' is perpendicular to the Z direction. The bit line structure 409 is used to provide or sense induced charges stored or released in each capacitor structure 410 within the same horizontal layer via the semiconductor material layer 4022.

[0087] In some embodiments, the order in which the bit line structure 409, the capacitor structure 410, and the channel region stack are formed can be arranged in various ways. For example, the bit line structure 409 can be formed first, then the capacitor structure 410 can be formed, and finally the channel region stack can be formed, or the channel region stack can be formed first, then the bit line structure 409 can be formed, and finally the capacitor structure 410 can be formed. This disclosure does not impose any specific limitations.

[0088] In some embodiments, after selectively laterally etching a portion of the semiconductor material layer and before filling it with bit line material and / or capacitor material, the exposed end faces of the remaining semiconductor material layer are metallized to form bit line contact layers (not shown) and / or capacitor contact layers (not shown) to reduce the contact resistance between the bit line structure and / or capacitor structure and the semiconductor material layer.

[0089] In some embodiments, the method of selectively removing part of the semiconductor material layer 1022 by lateral etching can be a wet chemical etching process. Specifically, an ammonia-deionized water mixture (ADM), potassium hydroxide solution (KOH), or tetramethylammonium hydroxide (TMAH) is used as a silicon etching solution to selectively etch the semiconductor material layer 1022.

[0090] In some embodiments, the material of the bit line structure may be a combination of one or more of titanium nitride, titanium, tungsten, and tungsten nitride. In other embodiments, the material of the bit line structure may also be one or more of molybdenum, ruthenium, copper, platinum, tantalum, or their nitrides. In some embodiments, the electrode material in the capacitor structure may be a combination of one or more of titanium nitride, tantalum nitride, and silicon-doped titanium nitride; the capacitor dielectric material of the capacitor structure may be a combination of at least one or more of zirconium oxide (ZrO2) and aluminum oxide (Al2O3). In other embodiments, the capacitor dielectric material may also be a combination of at least one or more of silicon oxide (SiO2), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), and lead titanate (PZT).

[0091] In some embodiments, the method for forming the material of the bit line structure and the capacitor structure may employ at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and electroplating sputtering.

[0092] In the semiconductor structure fabrication method disclosed herein, in a first aspect, by first forming a stacked structure on a substrate, then forming a first sacrificial pillar in the stacked structure, then forming an initial gate pillar in the first sacrificial pillar, and then removing the remaining first sacrificial pillar and side etching the initial gate pillar to form a target gate pillar, a gate conductive layer on the third sidewall of the target gate pillar in contact with the channel region stack is obtained. This can reduce the overlap area with the lightly doped drain regions adjacent to both sides of the channel region stack, thereby reducing the influence of the GIDL effect. In a second aspect, the process steps for forming the gate conductive layer are relatively easy to implement, highly feasible, and do not require much additional cost to obtain a structure with high device performance.

[0093] Based on the above-described method for fabricating semiconductor structures, this disclosure also provides a semiconductor structure, such as... Figures 10 to 14As shown in any of the accompanying drawings, the structure includes at least: a substrate 101 (201 / 301 / 401); and a stacked structure 102 (202 / 302 / 402) consisting of alternating layers of semiconductor layers 1022 (2022 / 3022 / 4022) and insulating material layers 1021 (2021 / 3021 / 4021) located on the substrate 101 (201 / 301 / 401). 102 (202 / 302 / 402) includes at least a channel region stack extending along the Z direction perpendicular to the surface of substrate 101 (201 / 301 / 401); a target gate post 105' (205' / 305' / 405') penetrates the stack structure 102 (202 / 302 / 402) along the Z direction, and the target gate post 105' (205' / 305' / 405') has a connection with the channel region stack. The third sidewall of the channel stacked contact, the target gate pillar 105' (205' / 305' / 405') includes a gate conductive layer 1052' (2052' / 3052' / 4052') located on the third sidewall and a gate dielectric layer 1051' (2051' / 3051' / 4051') located on the outer surface of the gate conductive layer 1052' (2052' / 3052' / 4052'). The gate conductive layer 1052' (2052' / 3052' / 4052') has a first length, and the gate dielectric layer 1051' (2051' / 3051' / 4051') has a second length, the first length being less than the second length; wherein, the length direction of both the first length and the second length is the X direction, and the X direction is parallel to the surface of the substrate 101 (201 / 301 / 401) and the surface of the third sidewall.

[0094] In some embodiments, in the Y direction, the channel region stack and the target gate pillars 105' (205' / 305' / 405') are alternately arranged, and the Y direction is parallel to the surface of the substrate 101 (201 / 301 / 401) and perpendicular to the X direction.

[0095] In some embodiments, the same target gate pillar 105' (205' / 305' / 405') has two opposing third sidewalls that contact two adjacent channel region stacks respectively, and the gate conductive layers located on the two opposing third sidewalls are isolated by a first insulating layer. In some embodiments, the first insulating layer includes a first insulator layer 1053 (2053 / 3053 / 4053) and a second insulator layer 1054 (2054 / 3054 / 4054).

[0096] In some embodiments, the channel stack further includes an inversion-doped channel region 1022a (2022a / 3022a / 4022a), the inversion-doped channel region 1022a (2022a / 3022a / 4022a) being located in the region where the channel stack contacts the third sidewall of the target gate pillar 105' (205' / 305' / 405'), and the stack structure 102 (202 / 302 / 402) further includes The lightly doped drain region stack is adjacent to the channel region stack on both sides in the X direction. The lightly doped drain region stack also includes lightly doped drain regions 1022b (2022b / 3022b / 4022b), whose ion doping type is opposite to that of the inversion-doped channel region 1022a (2022a / 3022a / 4022a). In some embodiments, the dopant ions of the inversion-doped channel region 1022a can be boron ions, and the dopant ions of the lightly doped drain regions 1022b (2022b / 3022b / 4022b) can be phosphorus ions or arsenic ions.

[0097] In some embodiments, reference Figure 11 As shown, it also includes a second insulating layer 107 located on both sides of the target gate pillar 105' disposed opposite each other in the X direction. In some embodiments, the material of the second insulating layer 107 is silicon oxide.

[0098] In some embodiments, reference Figure 12 As shown, it also includes a second insulating layer 2072 and a third insulating layer 2071. The third insulating layer 2071 is located between the second insulating layer 2072 and the substrate 201, the stacked structure 202 and the target gate pillar 205'. In some embodiments, the material of the second insulating layer 2072 is silicon oxide, and the material of the third insulating layer 2071 is silicon nitride.

[0099] In some embodiments, reference Figure 13 As shown, it also includes an auxiliary gate layer 308, which is located on both sides of the gate conductive layer 3052' on the third sidewall of the target gate pillar 305'. The work function of the auxiliary gate layer 308 is less than the work function of the gate conductive layer 3052'. In some embodiments, the auxiliary gate layer 308 is made of doped polysilicon, and the gate conductive layer 3052' is made of titanium nitride.

[0100] In some embodiments, a word line structure (not shown) is also included. The word line structure includes a gate conductive layer 1052' (2052' / 3052' / 4052') on the third sidewall connecting two target gate pillars 105' (205' / 305' / 405') located on opposite sides of the same channel region stack in the Y direction and in contact with the channel region stack. Specifically, each word line structure corresponds one-to-one with each channel region stack, and connects the two gate conductive layers 1052' (2052' / 3052' / 4052') that are closest to each corresponding channel region stack in pairs. The main body of the word line structure consists of two gate conductive layers 1052' (2052' / 3052' / 4052') adjacent to the same channel region stack, which together control the on or off of the inversion-doped channel region 1022a (2022a / 3022a / 4022a) located in the same channel region stack.

[0101] In some embodiments, reference Figure 14 As shown, where, Figure 14 (c) is a top view facing the substrate 101 and along a direction perpendicular to the surface of the substrate 401 (i.e., opposite to the Z direction). Figure 14 (a) Figure 14 (b) and Figure 14 (d) are respectively Figure 14 (c) Schematic diagrams along sections A-A', B-B', and D-D'. Figure 14 (e) is Figure 14 (d) is a schematic diagram along the E-E' section. Figure 14 (f) is Figure 14(e) is a partially enlarged schematic diagram of region F (dashed box). Cross sections A-A' and D-D' are parallel to the X direction and perpendicular to the Y direction, cross section B-B' is parallel to the Y direction and perpendicular to the X direction, and cross section E-E' is perpendicular to the Z direction. In an exemplary embodiment of this disclosure, a bit line structure 409, a capacitor structure 410, and an insulating isolation layer 4024 are also included. The bit line structure 409 and the capacitor structure 410 are located on opposite sides of the channel region stack along the X direction. The insulating isolation layer 4024 is located in the stack structure 402, extends along the Z and X directions and penetrates the stack structure 402, and is used to space the channel region stack and the semiconductor material layer 4022 in the Y direction. In some embodiments, the semiconductor material layer 4022 has a source / drain region (not shown) at each end opposite to each other along the X direction. The source / drain regions have the same doping ion type as the lightly doped drain region 4022b. In some embodiments, bit line structures 409 connect the source / drain regions at one end of semiconductor material layers 4022 spaced apart along the Y direction in the same horizontal layer, and each capacitor structure 410 is correspondingly connected to the source / drain regions at the other end of each semiconductor material layer 4022 in the X direction. Each bit line structure 409 is used to provide or sense induced charges stored or released in each capacitor structure 410 in the same horizontal layer through the semiconductor material layer 4022. In some embodiments, each capacitor structure 410 further includes a first electrode layer 4101, a capacitor dielectric layer 4102, and a second electrode layer 4103 stacked sequentially, such as... Figure 14 As shown in (d) / (e) / (f), the first electrode layer 4101 is in contact with the semiconductor material layer 4022, the capacitor dielectric layer 4102 is located on the surface of the first electrode layer 4101, and the second electrode layer 4103 is located on the surface of the capacitor dielectric layer 4102. In some embodiments, the materials of the first electrode layer 4101 and the second electrode layer 4103 may be any combination of one or more of titanium nitride (TiN), titanium (Ti), and silicon-doped titanium nitride (TiSiN), and the material of the capacitor dielectric layer 4102 may be at least one or more of zirconium oxide (ZrO2) and aluminum oxide (Al2O3).

[0102] In some embodiments, the region where the semiconductor material layer 4022 contacts the bit line structure 409 or the capacitor structure 410 further includes a bit line contact layer (not shown) or a capacitor contact layer (not shown) to reduce the contact resistance at the contact interface. In some embodiments, the material of the bit line contact layer and / or the capacitor contact layer includes a metal silicide material, such as cobalt silicide (CoSi), nickel silicide (NiSi), tungsten silicide (WSi), molybdenum silicide (MoSi), titanium silicide (TiSi), tantalum silicide (TaSi), ruthenium silicide (RuSi), and platinum silicide (PtSi).

[0103] In some embodiments, such as Figure 14As shown in (f), Figure 14 (f) is Figure 14 (e) is a partially enlarged schematic diagram of region F (dashed box), which can be understood as a partially enlarged schematic diagram of a basic memory cell structure in a semiconductor structure provided in an exemplary embodiment of this disclosure. The memory cell structure includes at least: a transistor structure, namely a semiconductor material layer 4022 separated by an insulating isolation layer 4024; a word line structure (not shown), connecting the gate conductive layer 4052'-1 on the third sidewall adjacent to the channel region stack of two target gate pillars located on opposite sides of the same channel region stack along the Y direction. 4052'-2, wherein the lightly doped drain regions 4022b-1 and 4022b-2 on both sides of the channel region stacked opposite each other in the X direction have small or basically no overlap in the Y direction; bit line structure 409 and capacitor structure 410 are located at the two ends of the semiconductor material layer 4022 opposite each other in the X direction, wherein the capacitor structure 410 includes a first electrode layer 4101, a capacitor dielectric layer 4102 and a second electrode layer 4103 stacked sequentially.

[0104] Compared with related technologies, the semiconductor structure provided in this disclosure has a smaller overlap area between the gate conductive layer on the third sidewall of the target gate pillar and the lightly doped drain regions adjacent to both sides of the channel region stack, thereby reducing the influence of the GIDL effect to a certain extent and improving the working performance of the memory device.

[0105] It should be noted that the semiconductor structure in the embodiments of this disclosure can be used to fabricate 3D DRAM devices, or other 3D devices that require the formation of metal-semiconductor contacts in a stacked structure; no further limitations are imposed here.

[0106] The various semiconductor structures illustrated in this specific embodiment can be used in electronic devices with storage functions. These electronic devices can be terminal devices, such as mobile phones, tablets, and smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in these electronic devices can be implemented using the following types of memory: Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), Magnetic Random Access Memory (MRAM), or Resistive Random Access Memory (RRAM).

[0107] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A stacked structure consisting of alternating layers of semiconductor material and multiple layers of insulating material is formed on the substrate; In the stacked structure, a channel region stack and an initial gate pillar are formed along a first direction perpendicular to the surface of the substrate. The initial gate pillar includes at least an initial gate conductive layer and an initial gate dielectric layer. The initial gate pillar has two opposing first sidewalls that are in contact with two adjacent channel region stacks respectively and a second sidewall that is not in contact with either channel region stack. At least the initial gate dielectric layer and the initial gate conductive layer located on the second sidewall of the initial gate pillar are removed to form a target gate pillar. The target gate pillar includes two opposing third sidewalls that are respectively in contact with two adjacent channel region stacks, and a gate conductive layer with a first length and a gate dielectric layer with a second length located on the third sidewall. The gate dielectric layer is located between the gate conductive layer and the channel region stack. The first length is less than the second length. The length directions of the first length and the second length are both the second direction, which is parallel to the substrate surface and the surface of the third sidewall.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Forming a channel region stack extending along a first direction perpendicular to the substrate surface in the stacked structure, comprising: A plurality of first through holes are formed in the stacked structure. The first through holes extend along the first direction and penetrate the stacked structure. The plurality of first through holes are arranged at intervals along a third direction parallel to the surface of the substrate. The stacked structure between adjacent first through holes serves as the channel region stack. The third direction is perpendicular to the second direction.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, Forming an initial gate pillar extending along a first direction perpendicular to the substrate surface in the stacked structure includes: The first through hole is filled with sacrificial material to form a first sacrificial column; A first mask with a first opening is formed on the stacked structure, and a second through hole is formed in the first sacrificial pillar by etching along the first opening. The second through hole penetrates the stacked structure and, at least in the third direction, the size of the second through hole is substantially the same as the size of the first through hole. The initial gate dielectric layer, the initial gate conductive layer, and the first insulating layer are sequentially formed in the second through hole to form the initial gate pillar. In the third direction, the initial gate pillar has two opposing first sidewalls that are respectively in contact with two adjacent channel regions stacked together. In the second direction, the initial gate conductive layer on the first sidewall of the initial gate pillar has a third length, which is greater than the first length and is greater than or equal to the second length.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, After forming the second through-hole and before forming the initial gate pillar in the second through-hole, the fabrication method further includes: Ion implantation is performed on the channel region stack through the second through-hole to form an inverse-doped channel region.

5. The method for fabricating a semiconductor structure according to claim 3, characterized in that, Removing at least the initial gate dielectric layer and the initial gate conductive layer located on the second sidewall of the initial gate pillar to form the target gate pillar includes: A second mask with a second opening is formed on the stacked structure, and a third through hole is formed in the first sacrificial pillar by etching along the second opening. The third through hole penetrates the stacked structure and exposes the second sidewall of the initial gate pillar. The initial gate dielectric layer and the initial gate conductive layer located on the second sidewall are removed using the third through-hole to form the target gate pillar. In the third direction, the target gate pillar has two opposing third sidewalls that are respectively in contact with two adjacent channel region stacks.

6. The method for fabricating a semiconductor structure according to claim 5, characterized in that, After forming the third through-hole and before removing at least the initial gate conductive layer located on the second sidewall using the third through-hole, the fabrication method further includes: Ion implantation is performed through the third through-hole into the stacked structure adjacent to the channel region stack to form a lightly doped drain region.

7. The method for fabricating a semiconductor structure according to claim 5, characterized in that, After forming the target gate pillar, the fabrication method further includes filling the third through hole with a second insulating layer.

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, After forming the target gate pillar and before filling the third through-hole with the second insulating layer, the fabrication method further includes: An auxiliary gate layer is formed in the third through-hole. The auxiliary gate layer is located at both ends of the gate conductive layer that are disposed opposite to each other along the second direction. The work function of the auxiliary gate layer is less than the work function of the gate conductive layer.

9. The method for fabricating a semiconductor structure according to claim 2, characterized in that, After forming the target gate pillar, the fabrication method further includes: The gate conductive layers on the two third sidewalls located on opposite sides of the same channel region stack and in contact with the channel region stack are connected to form a word line structure.

10. A method for fabricating a semiconductor structure according to any one of claims 1-9, characterized in that, After forming the stacked structure, the manufacturing method further includes: A bit line structure and a capacitor structure are formed, wherein the bit line structure and the capacitor structure are respectively located at the two ends of the channel region stack that are disposed opposite to each other in the second direction.

11. A semiconductor structure, characterized in that, include: Substrate; A stacked structure is formed on the substrate by alternating stacking of multiple semiconductor layers and multiple insulating material layers, and the stacked structure further includes at least a channel region stack extending along a first direction perpendicular to the surface of the substrate; A target gate pillar extends through the stacked structure along the first direction. The target gate pillar includes two opposing third sidewalls that contact two adjacent channel regions stacked together, and a gate conductive layer with a first length and a gate dielectric layer with a second length located on the third sidewalls. The gate dielectric layer is located between the gate conductive layer and the channel region stacked together. The first length is less than the second length. The length directions of the first length and the second length are both the second direction, which is parallel to the substrate surface and the surface of the third sidewall.

12. The semiconductor structure according to claim 11, characterized in that, The channel region stack and the target gate pillar are arranged alternately along a third direction, which is parallel to the substrate surface and perpendicular to the second direction.

13. The semiconductor structure according to claim 12, characterized in that, The target gate post further includes a first insulating layer, and the gate conductive layers on the two third sidewalls disposed opposite each other along the third direction of the same target gate post are isolated by the first insulating layer.

14. The semiconductor structure according to claim 11, characterized in that, The channel region stack also includes an inversion-doped channel region located in the region where the channel region stack contacts the third sidewall of the target gate pillar; the stack structure also includes a lightly doped drain region stack, which is adjacent to the channel region stack on both sides disposed opposite to each other along the second direction, and the lightly doped drain region stack also includes a lightly doped drain region, the ion doping type of which is opposite to that of the inversion-doped channel region.

15. The semiconductor structure according to claim 11, characterized in that, The semiconductor structure further includes an auxiliary gate layer, which is located on both sides of the gate conductive layer on the third sidewall of the target gate pillar, which are disposed opposite each other along the second direction. The work function of the auxiliary gate layer is less than the work function of the gate conductive layer.

16. The semiconductor structure according to claim 12, characterized in that, The semiconductor structure also includes: The word line structure includes a gate conductive layer connecting two third sidewalls of the same channel region stack located on opposite sides disposed along the third direction and in contact with the channel region stack.

17. The semiconductor structure according to any one of claims 11-16, characterized in that, The semiconductor structure also includes: The bit line structure and the capacitor structure are respectively located on both sides of the channel region stack that are disposed opposite to each other along the second direction.

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