INTEGRATED CHIPS WITH RRAMS AND BARRIER LAYERS, AND A METHOD FOR MANUFACTURING THE SAME

Abstract

Integrated chip, including: a substrate (508); and a resistive random access memory cell, RRAM cell (102) overlying the substrate (508), the RRAM cell (102) comprising a bottom electrode (106) and a top electrode (108) and further comprising an alternating layer (110), a barrier layer (104), and an active metal layer (112) stacked between the bottom and top electrodes (106, 108), the barrier layer (104) being conductive and located between the alternating layer (110) and the active metal layer (112), and the barrier layer (104) having a lattice constant lower than that of the active metal layer (112), the barrier layer (104) having a lattice constant lower than 350 pm and a density higher than 10 g / cm 3 and wherein the active metal layer (112) has a lattice constant higher than 385 pm and a density lower than 5 g / cm 3 has.

Description

BACKGROUNDMany present day electronic devices include non-volatile memory. In a non-related embodiment, a power generating device is further provided for storing power data. Such promising candidates for the next generation of nonvolatile memories may include resistive random access memories (RRAM). RRAMs have a relatively simple structure and are compatible with complementary metal oxide semiconductor (CMOS) logic fabrication techniques.The publication US 2017 / 0 040 380 A1 discloses a memory device which has an electron supply layer, a barrier layer and a layer with alternating resistance between two electrode layers. The electron supply layer may include Ti, Zr, Al, Ta and / or Fe, and the barrier layer may include TiN, TaN, WN and / or TaSiN.The document EP 2 927 975 B1 describes a memory device which comprises a layer with alternating resistance, a metallic layer and a barrier layer between two electrode layers. The metallic layer may include Ti, Ta, Zr, Hf, Al and / or Ni. The barrier layer may comprise a metal oxynitride, in particular a tantalum oxynitride or titanium oxynitride.Further storage devices are known from the publications DE 102 97 191 B4, DE 10 2007 057 753 A1, US 2014 / 0 252 300 A1 and US 2019 / 0 013 465 A1.The object is to improve corresponding storage devices.SUMMARY OF THE INVENTIONOxynitride or titanium oxynitride. Further storage devices are known from the publications DE 102 97 191 B4, DE 10 2007 057 753 A1, US 2014 / 0 252 300 A1 and US 2019 / 0 013 465 A1. The object is to improve corresponding storage devices.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with common practice in the art, various elements are not drawn to scale. Indeed, the dimensions of the various elements may be arbitrarily increased or decreased to aid in the description. FIG. 1 shows a cross-sectional view of some embodiments of a resistive random access memory (RRAM) cell including a barrier layer. FIGS. 2A and 2B show cross-sectional views of some embodiments of the RRAM cell of FIG. 1 during the dissolving of a metal filament. FIG. 3 shows a cross-sectional view of some embodiments of the RRAM cell of FIG. 1, wherein the barrier layer is a multilayer film. FIGS. 4A through 4F show cross-sectional views of various embodiments of the RRAM cell of FIG. 1, wherein the RRAM cell is in an interconnect structure of an IC chip. FIGS. 5A and 5B show cross-sectional views of some embodiments of RRAM cells, wherein the RRAM cells include individual barrier layers and are integrated with individual on-transistor on-resistor (1T1R) cells. FIG. 6 shows a layout of some embodiments of the IC chip of FIGS. 5A and 5B in a plan view. FIGS. 7 through 17 show cross-sectional views of some embodiments of a method for manufacturing RRAM cells that include individual barrier layers and are integrated with 1T1R cells. FIG. 18 is a block diagram of some embodiments of the method of FIGS. 7-17. Figures 19-23 show a series of cross-sectional views of some alternative embodiments of the method of Figures 7-17, the method being performed with RRAM cell embodiments of Figure 4F. Figure 24 shows a block diagram of some embodiments of the method of Figures 19-23.DETAILED DESCRIPTIONIn the following disclosure, many different embodiments or examples for implementing different features of the subject matter of the present invention are presented. Specific examples of components and arrangements will be described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features are not in direct contact. In addition, in the present disclosure, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and clarity and, as such, does not determine a relationship between the various embodiments and / or configurations described.Further, for convenience of description herein, terms of spatial relationship such as "below", "below", "lower", "above", "upper", and the like may be used to describe the relationship of one element or feature to (one) other element(s) or feature(s) as illustrated in the figures. The terms spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or having different orientations) and the spatial relationship descriptors used herein may likewise be interpreted accordingly.In some embodiments, a resistive random access memory (RRAM) cell includes a bottom electrode, an alternating layer overlying the bottom electrode, an active metal layer overlying the alternating layer, and a top electrode layer overlying the active metal layer. During the fabrication of the RRAM cell, a fabrication voltage having a positive polarity is applied from the upper electrode to the lower electrode. The manufacturing voltage includes oxidation of metal in the active metal layer and thus results in metal cations. In addition, an electric field from the manufacturing voltage causes the metal cations to migrate towards the bottom electrode. Starting at the lower electrode, the metal cations are reduced and gradually grow a metal filament extending from the lower electrode to the upper electrode. During operation of the RRAM cell, a reset voltage having a negative polarity and a set voltage having the positive polarity are applied from the top electrode to the bottom electrode to reset the alternating layer to a high resistance state (HRS) and set the alternating layer to a low resistance state (LRS), respectively. By the reset voltage, the above-described manufacturing method is reversed and the metal thread is partially dissolved, while by the set voltage, the metal thread is newly formed according to the above-described manufacturing method.At least in embodiments where the active metal layer is aluminum or comprises aluminum, the lifetime may be poor. The resistance difference between the HRS and the LRS decreases with the number of set / reset cycles until the HRS and the LRS are substantially equal. Such a decrease results from more cations entering the alternating layer during the transition into the LRS than leaving the alternating layer during the transition into the HRS. Over time, this builds up the metal filament and makes it more difficult to pass over into the HRS within predetermined time limits and / or predetermined operating voltages. As a result, the HRS and LRS eventually become largely equal and the RRAM cell eventually fails.Various embodiments of the present application are directed to an RRAM cell that includes a barrier layer to limit the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further includes a bottom electrode, an alternating layer, an active metal layer, and a top electrode. The alternating layer, the barrier layer, and the active metal layer are stacked between the lower electrode and the upper electrode. The barrier layer lies over the alternating layer and the active metal layer lies over the alternating layer. Further, the barrier layer is configured to slow movement of metal ions from the active metal layer through the barrier layer when changing from an HRS to an LRS. For example, the barrier layer may have a lattice constant lower than that of the active metal layer. As another example, the barrier layer may have a density higher than that of the active metal layer.By disposing the barrier layer between the alternating layer and the active metal layer, the reliability of the switching cycles (i.e., the lifetime) can be increased. For example, if the active metal layer is aluminum or comprises aluminum, a tantalum or tantalum nitride barrier layer may reduce the number of metal cations that enter the alternating layer upon transition into the LRS. However, a different material or other materials are also possible. By reducing the number of metal cations entering the alternating layer, the build-up of the metal filament is slower over time and thus the reliability of the switching cycles (i.e. the lifetime) is increased.In addition, by disposing the barrier layer between the alternating layer and the active metal layer, the manufacturing, setting, and reset voltages can be reduced. For example, if the barrier layer comprises tantalum or titanium nitride and the switching layer comprises nitrogen or oxygen, the tantalum or tantalum nitride may migrate into the switching layer and may react with the nitrogen or oxygen. However, a different material or other materials are also possible. By the migration and reaction, a leakage current can be increased, and thus the fabrication, setting, and reset voltage can be decreased. For example, the manufacturing voltage may decrease by about 30%, or by another suitable percentage. By decreasing the manufacturing, setting and reset voltage, power consumption can be reduced. Further, the number of error bits can be reduced.Referring to FIG. 1, there is illustrated a cross-sectional view 100 of some embodiments of an RRAM cell 102 including a barrier layer 104. As will be discussed in more detail below, the barrier layer 104 limits the movement of metal cations (not shown) during set and reset operations of the RRAM cell 102 to improve the lifetime of the RRAM cell 102. For example, the RRAM cell 102 may be integrated with other devices in an integrated circuit (IC) chip and / or may be, for example, a cation-type RRAM cell or any other suitable type. Note that cation-type RRAM cells are sometimes referred to as programmable metallization cells (PMCs) or conductive-bridging random-access memory (CBRAM) cells.A bottom electrode 106, a top electrode 108, a switching layer 110, and an active metal layer 112 are stacked with the barrier layer 104 to define the RRAM cell 102. The alternating layer 110 overlies the lower electrode 106 and the barrier layer 104 overlies the alternating layer 110. Further, the active metal layer 112 overlies the barrier layer 104 and the top electrode 108 overlies the active metal layer 112. In some embodiments, the barrier layer 104 is tantalum or tantalum nitride or comprises tantalum or tantalum nitride and the active metal layer 112 is aluminum or comprises aluminum. However, other materials are also possible. For example, the active metal layer 112 may be copper, silver, or any other suitable material.During operation of the RRAM cell 102, a metal filament 114 is repeatedly formed and dissolved in the alternating layer 110. In forming the metal filament 114, the active metal layer 112 is oxidized to form metal cations. In addition, the metal cations migrate through the barrier layer 104 to the alternating layer 110 and are reduced to metal atoms 116 defining the metal filament 114. Upon dissolution of the metal filament 114, the metal filament 114 is oxidized and forms metal cations. In addition, the metal cations migrate through the barrier layer 104 to the active metal layer 112 and are reduced to the active metal layer 112. For example, by forming and dissolving the metal filament 114, the RRAM cell 102 may switch to an LRS.By disposing the barrier layer 104 between the alternating layer and the active metal layer 110, 112, the reliability of the switching cycles (i.e., the lifetime) may be increased. For example, the barrier layer 104 may reduce the number of aluminum cations that enter the alternating layer 110 upon transition into the LRS. In other words, the barrier layer 104 decreases the rate at which aluminum cations enter the alternating layer 110 upon transition into the LRS (as compared to the same RRAM cell without the barrier layer). By reducing the number of metal cations entering the alternating layer 110, the build-up of the metal filament 114 is slower over time and thus the reliability of the switching cycles (i.e., lifetime) is increased. In addition, by disposing the barrier layer 104 between the alternating layer and the active metal layer 110, 112, the fabrication, set, and reset voltages can be decreased. For example, material may migrate from the barrier layer 104 into the switching layer 110 and may react with the switching layer 110. By the migration and reaction, a leakage current can be increased, and thus the fabrication, setting, and reset voltage can be decreased. This in turn allows the power consumption and the number of error bits to be reduced.The lower and upper electrodes 106, 108 and the active metal layer 112 are conductive. However, the lower and upper electrodes 106, 108 are electrochemically inert compared to the active metal layer 112. In other words, the active metal layer 112 is electrochemically active compared to the lower and upper electrodes 106, 108. As a result, the lower and upper electrodes 106, 108 have a low reactivity with oxygen compared to the active metal layer 112, and thus a higher amount of energy is required to oxidize it than the active metal layer 112. For example, 5 or more electron volts (eV) may be required for the lower and upper electrodes 106, 108 to oxidize them, while 3 eV or less may be required for the active metal layer 112 to oxidize them. However, other eV values are also possible.In some embodiments, the bottom electrode 106 and the top electrode 108 are titanium nitride, tantalum nitride, any other suitable conductive material or materials, or any combination of the foregoing or electrodes include these. Further, in some embodiments, the bottom electrode 106 and the top electrode 108 are platinum and / or any other suitable noble metal or metals, or the electrodes comprise these. In some embodiments, the bottom electrode 106 and the top electrode 108 have electrode thicknesses T e, which are about 1 to 10 nanometers (nm), about 1 to 5 nm, or about 5 to 10 nm. However, other thicknesses are also possible. In some embodiments, the electrode thicknesses T e are the same. In other embodiments, the electrode thicknesses T e are different. In some embodiments, the active metal layer 112 is or comprises aluminum and / or any other suitable metal or metals. In some embodiments, the active metal layer 112 has an active metal thickness T am of about 10 to 500 nm, about 10 to 255 nm, or about 255 to 500 nm. However, other thicknesses are also possible. If the active metal layer 112 is too thin (e.g., thinner than about 10 nm or any other suitable value), the active metal layer 112 may not sufficiently provide metal threads to the switching layer 110. If the active metal layer 112 is too thick (e.g., thicker than about 500 nm or some other suitable value), the voltage drops across the active metal layer 112 may be high and thus the reliability may be poor. Additionally or alternatively, if the active metal layer 112 is too thick (e.g., thicker than about 500 nm or any other suitable value), the active metal layer 112 may make integration into existing methods more difficult.The alternating layer 110 and the barrier layer 104 are dielectric and conductive, respectively. Further, the alternating layer 110 and the barrier layer 104 are an electrolyte and a barrier, respectively, for metal cations resulting from oxidation of the active metal layer 112. For example, when the active metal layer 112 is or comprises aluminum, the alternating layer 110 and the barrier layer 104 are an electrolyte and a barrier, respectively, for aluminum cations resulting from the oxidation of the active metal layer 112.In some embodiments, the alternating layer 110 is or includes silicon oxide (e.g., SiO 2), hafnium oxide (e.g., HfO 2), silicon nitride (SiN x), aluminum oxide (e.g., Al 2 O 3), zirconium oxide (e.g., ZrO 2), any other dielectric or dielectrics, or any combination of the foregoing. In some embodiments, the alternating layer 110 has an alternating thickness T s of about 1 to 50 nm, about 1 to 25 nm, or about 25 to 50 nm. However, other thicknesses are also possible.In some embodiments, the barrier layer 104 has a lower lattice constant and / or a higher density than the active metal layer 112, thus it is more difficult for metal cations from the active metal layer 112 to diffuse or otherwise move through the barrier layer 104. For example, the active metal layer 112 may have a density of less than about 5 grams per cubic centimeter (g / cm 3) ( e.g., about 2.7 g / cm 3 or any other suitable value), while the barrier layer 104 may have a density of greater than about 10 g / cm 3 (e.g., about 16.69 g / cm 3, about 13.7 g / cm 3 or any other suitable value). As another example, the active metal layer 112 may have a lattice constant greater than 385 (e.g., about 404.95 or any other suitable value), while the barrier layer 104 may have a lattice constant less than about 350 (e.g., about 330.13 or any other suitable value). However, other values for the density and the lattice constant are also possible. By making it more difficult for metal cations to move through the barrier layer 104, the speed at which the metal cations move through the barrier layer 104 is decreased compared to the same RRAM cell 102 without the barrier layer 104. In some embodiments, the barrier layer 104 is or comprises tantalum, tantalum nitride, any other suitable barrier material or materials, or any combination of the foregoing.In some embodiments, the barrier layer 104 has a barrier thickness T b of about 1 to 10 nm, about 1 to 5 nm, or about 5 to 10 nm. However, other thicknesses are also possible. If the barrier layer 104 is too thin (e.g., thinner than about 1 nm or any other suitable value), the barrier layer 104 may not be able to slow the migration of metal cations through the barrier layer 104, and thereby not be able to extend the lifetime of the RRAM cell 102. On the other hand, if the barrier layer 104 is too thick (e.g., thicker than 10 nm or some other suitable value), the barrier layer 104 may completely block or retard the migration of metal cations through the barrier layer 104, thereby preventing a transition between the LRS and the HRS and / or altering the operation of the RRAM cell 102. For example, the RRAM cell 102 may change from a cation-type RRAM to a defect-type RRAM and thus may have other electrical and performance characteristics. As another example, a manufacturing voltage may be excessively high, thereby increasing power consumption and the likelihood of failure. Additionally or alternatively, if the barrier layer 104 is too thick (e.g., thicker than 10 nm or any other suitable value), the barrier layer 104 may make integration into existing methods more difficult. In some embodiments, a ratio of the barrier thickness T b to the active metal thickness T am is about 1:1-500, about 1:1-250, about 1:250-500, or any other suitable ratio. Further, in some embodiments, a ratio of the barrier thickness T b to the alternating thickness T s is about 1:0.1-50, about 1:0.1-25, about 1:0.5-50, or any other suitable ratio. In some embodiments, a total thickness variation (TTV) of the barrier layer 104 is less than about 0.1 nm, 0.2 nm, or any other suitable value. The TTV is the difference between a maximum value of the barrier thickness T b and a minimum value of the barrier thickness T b. If the TTV is too high (e.g., greater than 0.2 nm or any other suitable value), the uniformity of the electric field across the RRAM cell 102 may be poor. This in turn may reduce the crude yields for the RRAM cell 102 during manufacturing and / or may reduce the performance of the RRAM cell 102. Additionally or alternatively, if the TTV is too high (e.g., greater than 0.2 nm or any other suitable value), portions of the barrier layer 104 may be too thin (e.g., less than about 1 nm or any other suitable value). As noted above, barrier layer 104 may not be able to slow migration of metal cations through barrier layer 104 if barrier layer 104 is too thin.Referring to FIG. 2A, there is shown a cross-sectional view 200A of some embodiments of the RRAM cell 102 during the reset of the RRAM cell 102 to an HRS. From the upper electrode 108 to the lower electrode 106, a reset voltage having a negative polarity is applied. For example, a positive voltage is applied to the lower electrode 106 while the upper electrode 108 is grounded. The reset voltage induces oxidation of the metal filament 114 starting at a top of the metal filament 114 and extending toward a bottom of the metal filament 114. As the oxidation proceeds, metal atoms 116 of the metal filament 114 are converted to metal cations 202. In addition, the electric field generated by the reset voltage causes the metal cations 202 to migrate through the barrier layer 104 to the active metal layer 112 and be reduced to metal atoms of the active metal layer 112. Accordingly, the metal filament 114 is dissolved over time starting from the barrier layer 104 and extending to the bottom electrode 106.Referring to FIG. 2B, there is shown a cross-sectional view 200B of some embodiments of the RRAM cell 102 in setting the RRAM cell to an LRS. From the upper electrode 108 to the lower electrode 106, a setting voltage having a positive polarity is applied. For example, a positive voltage is applied to the upper electrode 108 while the lower electrode 106 is grounded. The adjustment voltage induces oxidation of the active metal layer 112 and thus converts metal atoms of the active metal layer 112 into metal cations 202. In addition, the electric field generated by the set voltage causes the metal cations 202 to migrate through the barrier layer 104 toward the bottom electrode 106 and be reduced to the metal atoms 116, thereby defining the metal filament 114. The metal cations 202, if present, are reduced to the metal atoms 116 at a top of the metal filament 114 and are reduced to the metal atoms 116 at a top of the bottom electrode 106 if there is no metal filament 114 yet present. Accordingly, the metal filament 114 grows over time, starting at the bottom electrode 106 and extending to the barrier layer 104.In some embodiments, the incorporation of the barrier layer 104 reduces the number of metal cations 202 migrating into the alternating layer 110 and / or reduces the migration rate into the alternating layer 110 during the adjustment of FIG. 2B. Some embodiments may arise, for example, when the barrier layer 104 is or comprises tantalum or tantalum nitride and the active metal layer 112 is or comprises aluminum. However, other materials are also possible. By reducing the number of metal cations 202 migrating into the alternating layer 110, the metal filament 114 may become thinner and the lifetime may be extended.The number of metal cations 202 migrating into the alternating layer 110 during the adjustment of FIG. 2B may be higher than the number of metal cations 202 migrating out of the alternating layer 110 during the reset of FIG. 2A. Over time, this may result in an increase in the metal filament 114 in the LRS, which may make it more difficult to transition to the HRS within predetermined time limits and / or predetermined operating voltages. Due to this enlargement of the metal filament, the HRS and the LRS eventually coincide and the RRAM cell 102 eventually fails. The incorporation of the barrier layer 104 reduces the number of metal cations 202 migrating into and out of the alternating layer 110, and thereby extends the time before failure and thus extends the lifetime of the RRAM cell 102.Referring to FIG. 3, there is shown a cross-sectional view 300 of some embodiments of the RRAM cell 102 of FIG. 1, wherein the barrier layer 104 is a multilayer film. In some embodiments, the barrier layer 104 includes a lower barrier layer 104 land an upper barrier layer 104 uthat overlies the lower barrier layer 104 l. The lower barrier layer 104 lmay be, for example, tantalum or may comprise it, while the upper barrier layer 104 umay be, for example, tantalum nitride or may comprise it, or vice versa. However, other materials are also possible.Referring to FIG. 4A, there is shown a cross-sectional view 400A of some embodiments of the RRAM cell 102 of FIG. 1, where the RRAM cell 102 is in an interconnect structure 402 of an IC chip and the bottom electrode 106 of the RRAM cell 102 has a T-shaped profile. The RRAM cell 102 overlies a top electrode wire 404 tand a top electrode via 406 t, and also overlies a bottom electrode wire 404 b.The top electrode via 406t extends downwardly from the top electrode wire 404t to the top electrode 108. In some embodiments (as shown), the top electrode via 406 textends through a hard mask 408 on top of the top electrode 108. In alternative embodiments, the hard mask 408 is omitted. The hard mask 408 may be, or may include, silicon nitride and / or any other suitable dielectric or dielectrics, for example. In some embodiments, the top electrode via 406 tand the top electrode wire 404 tare different materials and / or are independent of each other. In alternative embodiments, the top electrode via 406 tand the top electrode wire 404 tare the same material and / or are integrated with each other. The top electrode wire 404 t, the bottom electrode wire 404 b, and the top electrode via 406 tmay be, for example, or may include copper, aluminum copper, any other suitable metal or metals, or any combination of the foregoing.The lower electrode 106 extends downwardly to the lower electrode wire 404 b, thereby defining a lower electrode via 410 and electrically connecting the lower electrode 106 to the lower electrode wire 404 b. The lower electrode 106 includes a lower electrode trunk 106 band a lower electrode liner 106 lsurrounding a lower surface of the lower electrode trunk 106 b. In some embodiments, the bottom electrode liner 106 lis an adhesion layer to enhance the deposition of a layer from which the bottom electrode body 106 bis formed. Further, in some embodiments, the bottom electrode liner 106 lis a diffusion barrier to prevent material from diffusing from the bottom electrode wire 404 bto the bottom electrode body 106 b. The bottom electrode liner 106L may be, or may include, for example, tantalum nitride, titanium nitride, tantalum, any other suitable material or materials, or any combination of the foregoing. The bottom electrode body 106 bmay be, or may comprise, for example, platinum and / or any other suitable conductive material or materials.In alternative embodiments, the lower electrode liner 106L is omitted. In such alternative embodiments, the bottom electrode 106 may be a single conductive material over an entirety of the bottom electrode 106. For example, the bottom electrode 106 may be or may include tantalum nitride, titanium nitride, any other suitable conductive material or materials, or any combination of the foregoing. Forming the lower electrode 106 from a single conductive material improves flatness along an upper surface of the lower electrode 106 when the lower electrode is formed using chemical mechanical polishing (CMP), because the lower electrode 106 has a single hardness throughout and thus a single removal speed throughout. This in turn improves the uniformity of the electric field across the RRAM cell 102.A dielectric structure surrounds the RRAM cell 102, as well as the top electrode wire 404 t, the top electrode via 406 t, and the bottom electrode wire 404 b. The dielectric structure includes the hard mask 408 along a top surface of the top electrode 108, and further includes a sidewall spacer structure 412 on a sidewall or sidewalls of the RRAM cell 102. The sidewall spacer structure 412 is on opposite sides of the RRAM cell 102 and may be or may include silicon nitride and / or any other suitable dielectric or dielectrics. In some embodiments, the hard mask 408 and sidewall spacer structure 412 are the same material or comprise the same material. The dielectric structure also includes a plurality of intermetal dielectric (IMD) layers 414, a via dielectric layer 416, an etch stop layer 418, and an IMD liner 420.The IMD layers 414 surround the bottom electrode wire 404 band the top electrode wire 404 t, respectively, and the via dielectric layer 416, the etch stop layer 418, and the IMD liner 420 are stacked between the IMD layers 414. The via dielectric layer 416 surrounds the bottom electrode via 410 between the RRAM cell 102 and the bottom electrode wire 404 b. The etch stop layer 418 covers the via dielectric layer 416 and is wrapped around a top surface of the RRAM cell 102 along the sidewall spacer structure 412 and the hard mask 408. The IMD liner 420 lines a top surface of the etch stop layer 418, and separates the etch stop layer 418 from an adjacent one of the IMD layers 414. The IMD layers 414 may be, or may include, for example, an extreme low dielectric and / or any other suitable dielectric or dielectrics. The etch stop layer 418 and / or the via dielectric layer 416 may be, for example, silicon carbide and / or any other suitable dielectric or dielectrics, or may include these. The IMD layer 420 may be, or may include, tetraethylorthosilicate (TEOS) oxide and / or any other suitable dielectric or dielectrics, for example.Referring to FIG. 4B, there is illustrated a cross-sectional view 400B of some alternative embodiments of the RRAM cell 102 of FIG. 4A, wherein the sidewall spacer structure 412 overlies the barrier layer 104. In addition, sidewall spacer structure 412 lines sidewalls of active metal layer 112 and top electrode 108, respectively, but not sidewalls of barrier layer 104, switching layer 110, and bottom electrode 106, respectively.Referring to FIG. 4C, there is illustrated a cross-sectional view 400C of some alternative embodiments of the RRAM cell 102 of FIG. 4B, wherein the sidewall spacer structure 412 also lines a sidewall of the barrier layer 104.Referring to FIG. 4D, there is shown a cross-sectional view 400C of some alternative embodiments of the RRAM cell 102 of FIG. 4A, where the RRAM cell 102 is indented at the bottom electrode via 410 and does not include the bottom electrode liner 106 l(see FIG. 4A ). In alternative embodiments, the RRAM cell 102 further includes the bottom electrode liner 106L at the bottom electrode via 410.Referring to FIG. 4E, there is shown a cross-sectional view 400E of some alternative embodiments of the RRAM cell 102 of FIG. 4A, with the bottom electrode via 410 omitted and the RRAM cell 102 disposed directly on the bottom electrode wire 404 b. Further, the lower and upper electrodes 106, 108, the barrier layer 104, the alternating layer 110, and the active metal layer 112 have U-shaped profiles, and a plurality of elements of FIG. 4A are omitted. These omitted elements include sidewall spacer structure 412, hard mask 408, etch stop layer 418, and IMD liner 420. As will be described below, the RRAM cell 102 may be formed with a single photolithography / etching process, thereby reducing costs. In alternative embodiments, the bottom and top electrodes 106, 108, the barrier layer 104, the alternating layer 110, and the active metal layer 112 have a V-shaped profile or any other suitable profile.Referring to FIG. 4F, there is illustrated a cross-sectional view 400F of some alternative embodiments of the RRAM cell 102 of FIG. 4A, wherein the top surface of the bottom electrode liner 106 lis recessed a distance D relative to a top surface of the via dielectric layer 416. As will be described below, removing the top surface of the bottom electrode liner 106 lmay allow for improved planarity at a top surface of the bottom electrode 106, and thus may allow for improved uniformity of the electric field across the RRAM cell 102.Although FIGS. 4A-4F are depicted using embodiments of the RRAM cell 102 of FIG. 1, embodiments of the RRAM cell 102 of FIG. 3 may alternatively be used. That is, the barrier layer 104 of FIGS. 4A to 4F may be a multilayer film as illustrated in FIG. 3.Referring to FIG. 5A, there is illustrated a cross-sectional view 500A of some embodiments of the RRAM cells 102, where the RRAM cells 102 include individual barrier layers 104 and are integrated with individual on-transistor on-resistor (1T1R) cells 502 in an IC chip. The RRAM cells 102 can be configured, for example, in each case in the manner in which their counterpart is illustrated and described in FIG. 4A. The 1T1R cells 502 include individual drain regions 504 and individual drain-side conductive paths 506.The drain regions 504 are doped regions of a substrate 508 and have a doping type opposite to the main part 508 bof the substrate 508. For example, the drain regions 504 may be n-type and the main portion 508 bof the substrate 508 may be p-type, or vice versa. In alternative embodiments, the drain regions 504 are on a well region (not shown) of the substrate 508 and have a doping type opposite to the well region. Further, the drain regions 504 are electrically separated from each other by a trench isolation structure 510 and partially define access transistors 512 (partially shown) used to individually select the RRAM cells 102. The trench isolation structure 510 extends into a top surface of the substrate 508 and includes silicon oxide and / or any other suitable dielectric material or materials. The trench isolation structure 510 may be, for example, a shallow trench isolation (STI) structure or any other trench isolation structure. The substrate 508 may be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or any other suitable semiconductor substrate.The drain-side conductive paths 506 electrically connect the drain regions 504 to the bottom electrodes 106 of the RRAM cells 102. In addition, drain-side conductive paths 506 are defined by interconnect structure 402, which includes multiple wires 404 and multiple vias 406. The plurality of wires 404 includes the upper electrode wires 404 tand the lower electrode wires 404 b. In some embodiments, the top electrode wires 404 tcorrespond to bit lines BL that are shared with other RRAM cells (not shown). The plurality of vias 406 includes top electrode via 406 t, and a level of vias 406 closest to substrate 508 is in an interlayer dielectric (ILD) layer 514. Wires 404 and vias 406 may be, or may include, for example, copper, aluminum, aluminum copper, titanium, tungsten, titanium nitride, any other suitable conductive material or materials, or any combination of the foregoing.A border region 516 on one side of the 1T1R cells 502 houses a border device 518 (partially shown). The edge device 518 may be, for example, a metal oxide semiconductor field effect transistor (MOSFET) or any other suitable semiconductor device. Additionally, the edge device 518 may be, for example, one of many other edge devices (not shown) at the edge zone 516. The edge device 518 includes a pair of source / drain regions 520 (only one of which is shown) in the substrate 508 and further includes a gate structure (not shown) between the source / drain regions 520. The source / drain regions 520 are doped regions in a substrate 508 and have a doping type opposite to the main part 508 bof the substrate 508. In alternative embodiments, the source / drain regions 520 are on a well region (not shown) of the substrate 508 and have a doping type opposite to the well region.Referring to FIG. 5B, there is illustrated a cross-sectional view 500B of some alternative embodiments of the IC chip of FIG. 5A along an axis orthogonal to an axis along which the cross-sectional view 500A of FIG. 5A is plotted. The 1T1R cells 502 include individual RRAM cells 102, individual drain-side routes 506, individual access transistors 512, and individual source-side routes 522. The RRAM cells 102 can be configured, for example, in each case in the manner in which their counterpart is illustrated and described in FIG. 4A.The access transistors 512 are located on the substrate 508 between the substrate 508 and the interconnect 402. In addition, the access transistors 512 are electrically separated from each other by the trench isolation structure 510. The access transistors 512 include individual drain regions 504, individual source regions 524, individual gate dielectric layers 526, and individual gate electrodes 528. The gate electrodes 528 overlay the gate dielectric layers 526 and define word lines WL. The drain and source regions 504, 524 are doped regions of the substrate 508 and have a doping type opposite to the main portion 508 bof the substrate 508. In alternative embodiments, the drain and source regions 504, 524 are on a well region (not shown) of the substrate 508 and have a doping type opposite the well region. The drain regions 504 are adjacent to drain sides of the gate electrodes 528 and the source regions 524 are adjacent to source sides of the gate electrodes 528, respectively.Drain-side conductive paths 506 electrically connect drain regions 504 to bottom electrodes 106 of RRAM cells 102, and source-side conductive paths 522 electrically connect source regions 524 to source lines SL. The drain-side and source-side routings 506, 522 are defined by the plurality of wires 404 and the plurality of vias 406 in the interconnect structure 402.Although FIGS. 5A and 5B are depicted using the RRAM cell embodiments in FIG. 4A, alternatively, the RRAM cell embodiments in any of FIGS. 1, 3, and 4B- 4F may also be used. For example, the RRAM cells 102 of FIGS. 5A and 5B may each be configured as shown in FIG. 4B, and thus may include individual sidewall spacer structures 412 overlying the barrier layers 104.Referring to FIG. 6, a layout 600 of some embodiments of the IC chip of FIGS. 5A and 5B is depicted in a top view. For example, cross-sectional views 500A, 500B of FIGS. 5A and 5B may be respectively recorded along lines A and B or other suitable locations. The IC chip includes multiple RRAM cells 102 in multiple rows and multiple columns, thereby defining an RRAM array 602. For example, the RRAM cells 102 may be configured as shown and described in any of FIGS. 1, 3, 4A-4F, 5A, and 5B. Edge devices 518 surround the RRAM array 602 in an edge region 516 of the IC chip. The edge devices 518 may be or include, for example, transistors and / or another suitable semiconductor device or devices. Further, the edge devices 518 may implement read / write circuits and / or other suitable circuits for operating the RRAM cells 102, for example.Referring to FIGS. 7 through 17, there is shown a series of cross-sectional views 700 through 1700 of some embodiments of a method of forming RRAM cells, wherein the RRAM cells include individual barrier layers and are integrated with 1T1R cells in an IC chip. Cross-sectional views 700- 1700 may be plotted along line A or any other suitable location in FIG. 6, for example. Further, cross-sectional views 700- 1700 may correspond to FIG. 5A, for example, and thus may be configured, for example, as illustrated and described with respect to the IC chip of FIGS. 5A and 5B.As illustrated by cross-sectional view 700 of FIG. 7, a trench isolation structure 510 is formed extending into a top surface of the substrate 508. The trench isolation structure 510 individually surrounds and demarks zones of the substrate 508 in which 1T1R cells 502 are formed. In addition, the trench isolation structure 510 surrounds and demarks an edge zone 516 of the IC chip. A method of forming the trench isolation structure 510 may include, for example: 1) patterning the substrate 508 to form a trench having a layout in a plan view of the trench isolation structure 510 to be formed; and 2) filling the trench with oxide and / or any other suitable dielectric or dielectrics. However, other methods are also possible.As also illustrated by cross-sectional view 700 of FIG. 7, a plurality of semiconductor devices are formed on a substrate 508. The plurality of semiconductor devices include access transistors 512 individually for 1T1R cells 502 to be formed. In addition, the plurality of semiconductor devices includes an edge device 518 in an edge region 516 of the IC chip. Access transistors 512 include individual drain regions 504 and individual source regions (not shown) in substrate 508 overlying a major portion 508b of substrate 508. In addition, the access transistors 512 include individual gate structures (not shown). The gate structures have individual drain sides that respectively adjoin the drain regions 504, and further have individual source sides that respectively adjoin the source regions. The edge device 518 includes a pair of source / drain regions 520 (only one of which is shown) in the substrate 508 overlying the body 508 bof the substrate 508 and also includes a gate structure (not shown) between and adjacent to the source / drain regions 520.In some embodiments, a method of forming the plurality of semiconductor devices includes: 1) depositing a dielectric layer on the substrate 508; 2) depositing a conductive layer on the dielectric layer; 3) patterning the dielectric layer and the conductive layer into gate structures (not shown) for the access transistors 512 and the edge devices 518 and 4) doping the substrate 508 to form source / drain regions adjacent the gate structures. The source / drain regions include the drain regions 504 of the access transistors 512, the source regions (not shown) of the access transistors 512, and the source / drain regions of the edge device. However, other methods are also possible.As also illustrated by cross-sectional view 700 of FIG. 7, a interconnect structure 402 is partially formed over and electrically connected to the semiconductor devices (e.g., access transistor 512 and edge device 518). The interconnect structure 402 includes a dielectric structure and also includes a plurality of wires 404 and a plurality of vias 406 stacked in the dielectric structure. The dielectric structure includes an ILD layer 514 and a plurality of IMD layers 414 over the ILD layer 514. The plurality of wires 404 includes a plurality of lower electrode wires 404 balong an upper surface of the interconnect structure 402. The bottom electrode wires 404 bare individual to and located at the 1T1R cells 502 to be formed. Also, the bottom electrode wires 404b are respectively electrically connected to the drain regions 504 of the access transistor 512 by underlying wires and vias.In some embodiments, a method of partially forming interconnect structure 402 includes: 1) forming a lowermost level of vias 406 by a single damascene process; 2) forming a lowermost level of wires 404 by the single damascene process; and 3) repeatedly performing a dual damascene process to form other levels of wires and vias. However, other methods are also possible. The single damascene method may include, for example: 1) depositing a portion of the dielectric structure; 2) patterning the deposited portion of the dielectric structure to form openings with a layout for a single level of the wires or vias to be formed; 3) depositing a conductive layer in the openings; and 4) performing chemical mechanical polishing (CMP) in the conductive layer until a top surface of the conductive layer is level with a top surface of the deposited portion of the dielectric structure. For example, the dual damascene process may be configured as described for the single damascene process, except that openings are formed with a layout for a level of wires to be formed and a level of vias to be formed by patterning under 2). However, other methods are also possible for the single and the dual damascene method.As illustrated by cross-sectional view 800 of FIG. 8, a via dielectric layer 416 is formed on interconnect 402. Note that herein and in subsequent figures, a lower portion of the interconnect structure 402 is omitted. Via dielectric layer 416 may be, or may include, silicon carbide and / or any other suitable dielectric or dielectrics, for example. Additionally, via dielectric layer 416 may be formed, for example, by vapor deposition and / or any other suitable deposition method or methods.As illustrated by cross-sectional view 900 of FIG. 9, via dielectric layer 416 is patterned to form via openings 902 individually for and corresponding to 1T1R cells 502 to be formed. Via openings 902 extend through via dielectric layer 416 and respectively expose bottom electrode wires 404 b. Patterning may be performed, for example, by: 1) forming a photoresist mask 904 over the via dielectric layer 416 by photolithography; 2) performing an etching process into the via dielectric layer 416 while the photoresist mask 904 is positioned; and 3) removing the photoresist mask 904. However, other methods are also possible.As illustrated by cross-sectional view 1000 of FIG. 10, a liner layer 1002 lining and partially filling via openings 902 (see FIG. 9 ) is deposited over via dielectric layer 416. Additionally, a first conductive layer 1004 is deposited over the liner layer 1002, covering the liner layer 1002 and filling the via openings 902. In some embodiments, the liner layer 1002 is an adhesion layer to enhance adhesion of the first conductive layer 1004 to the via dielectric layer 416. Further, in some embodiments, the liner layer 1002 is a diffusion barrier for material of the bottom electrode wires 404 b. The liner layer 1002 may be, or may include, for example, tantalum nitride, titanium nitride, or any other suitable material. The first conductive layer 1004 has low reactivity with oxygen and may be or comprise tungsten and / or any other suitable material or materials. Such a low reactivity material may be, for example, a material for which 5 eV or more is required to react with oxygen. The liner layer 1002 and / or the first conductive layer 1004 may be formed, for example, by vapor deposition and / or any other suitable deposition method or methods.As illustrated by cross-sectional view 1100 of FIG. 11, planarization is performed into liner layer 1002 (see FIG. 10 ) and first conductive layer 1004 (see FIG. 10 ). Planarization forms lower electrode liners 106 land lower electrode first body segments 106 b, 1 in via openings 902 (see FIG. 9 ). The lower electrode liners 106 lbe under or encase the first lower electrode body segments 106 b 1 respectively. Further, the bottom electrode liners 106 land the first bottom electrode body segments 106 b, 1 respectively define bottom electrode vias 410 in the via openings 902. Planarization may be, for example, CMP and / or any other suitable planarization.As also illustrated by cross-sectional view 1100 of FIG. 11, a second conductive layer 1102 is deposited over the bottom electrode vias 410 and via dielectric layer 416. The second conductive layer 1102 has low reactivity with oxygen. Such a low reactivity material may be, for example, a material for which 5 eV or more is required to react with oxygen. Additionally, the second conductive layer 1102 may be or may comprise the same material as the first conductive layer 1004 (see FIG. 10 ) and / or any other suitable low reactivity material or materials. The second conductive layer 1102 may be formed, for example, by vapor deposition and / or any other suitable deposition method or methods.As illustrated by cross-sectional view 1200 of FIG. 12, a switching layer 1202, a barrier layer 1204, an active metal layer 1206, a third conductive layer 1208, and a hard mask layer 1210 are deposited over the second conductive layer 1102. The switching layer 1202 overlies the second conductive layer 1102, the barrier layer 1204 overlies the switching layer 1202, the active metal layer 1206 overlies the barrier layer 1204, the third conductive layer 1208 overlies the active metal layer 1206, and the hard mask layer 1210 overlies the third conductive layer 1208. The barrier layer 1204 may be deposited, for example, by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any other suitable deposition method or methods. The active metal layer 1206 may be deposited by, for example, PVD, CVD, or any other suitable deposition method or methods. The alternating layer 1202, the third conductive layer 1208, and the hard mask layer 1210 may be deposited, for example, by vapor deposition and / or any other suitable deposition method or methods.The alternating layer 1202 and the barrier layer 1204 are dielectric and conductive, respectively. In addition, the alternating layer 1202 and the barrier layer 1204 are an electrolyte and a barrier, respectively, for metal cations resulting from the oxidation of the active metal layer 1206. In some embodiments, the barrier layer 1204 has a lower lattice constant and / or a higher density than the active metal layer 1206, thus it is more difficult for metal cations from the active metal layer 1206 to move through the barrier layer 1204. Non-limiting examples are described above with respect to the barrier layer 104 of FIG. 1. As will be seen below, slowing the migration of metal cations through the barrier layer 1204 extends the lifetime of RRAM cells formed from the barrier layer 1204. In some embodiments, the barrier layer 1204 is or comprises tantalum, tantalum nitride, any other suitable barrier material or materials, or any combination of the foregoing. The barrier layer 1204 may be configured, for example, in the manner described with reference to the barrier layer 104 of FIG. 1.In some embodiments, the barrier layer 1204 has a barrier thickness T b of about 1 to 10 nm, about 1 to 5 nm, or about 5 to 10 nm. However, other thicknesses are also possible. If the barrier layer 1204 is too thin (e.g., thinner than about 1 nm or any other suitable value), the barrier layer 1204 may not be able to slow the migration of metal cations through the barrier layer 1204. On the other hand, if the barrier layer 1204 is too thick (e.g., thicker than 10 nm or some other suitable value), the barrier layer 1204 may completely block or retard the migration of metal cations through the barrier layer 1204. This in turn may prevent RRAM cells formed from the barrier layer 1204 from functioning or drive operating parameters of the RRAM cells out of specification range. Additionally or alternatively, if the barrier layer 1204 is too thick (e.g., 10 nm or any other suitable value), the barrier layer 1204 may make integration into existing methods more difficult. In some embodiments, a ratio of the barrier thickness T b to the active metal thickness T am of the active metal layer 1206 is about 1:1-500, about 1:1-250, about 1:250-500, or any other suitable ratio. Further, in some embodiments, a ratio of the barrier thickness T b to the alternating thickness T s of the alternating layer 1202 is about 1:0.1-50, about 1:0.1-25, about 1:0.5-50, or any other suitable ratio. In some embodiments, a TTV of the barrier layer 1204 is less than about 0.1 nm, 0.2 nm, or any other suitable value. If the TTV is too high (e.g., greater than 0.2 nm or any other suitable value), the uniformity of the electric field across the RRAM cells formed from the barrier layer 1204 may be poor. This in turn can reduce the crude yields for the RRAM cells during production and / or the performance of the RRAM cells. Additionally or alternatively, if the TTV is too high (e.g., greater than 0.2 nm or any other suitable value), portions of the barrier layer 1204 may be too thin (e.g., less than about 1 nm or any other suitable value). As noted above, barrier layer 1204 may not be able to slow migration of metal cations through barrier layer 1204 if barrier layer 1204 is too thin.The active metal layer 1206 is electrochemically active and has high reactivity with oxygen compared to the third conductive layer 1208. Such a material having high reactivity may be, for example, a material for which 3 eV or less is required to react with oxygen. In some embodiments, the active metal layer 1206 is or comprises aluminum and / or other suitable material or materials. The third conductive layer 1208 has a lower reactivity with oxygen compared to the active metal layer 1206. Such a low reactivity material may be, for example, a material for which 5 eV or more is required to react with oxygen. Additionally, the third conductive layer 1208 may be or may include the same material as the second conductive layer 1102, the same material as the first conductive layer 1004 (see FIG. 10 ) and / or any other suitable low reactivity material or materials.As illustrated by cross-sectional view 1300 of FIG. 13, hard mask layer 1210 is patterned to form individually for 1T1R cells 502 to be formed and hard masks 408, respectively. As described below, the hard masks 408 individually have structures for RRAM cells of the 1T1R cells 502. The patterning may be performed, for example, by: 1) forming a photoresist mask 1302 over the hard mask layer 1210 by photolithography; 2) performing an etching process in the hard mask layer 1210 while the photoresist mask 1302 is positioned; and 3) removing the photoresist mask 1302. However, other methods are also possible.As illustrated by cross-sectional view 1400 of FIG. 14, an etching process into second conductive layer 1102 (see FIG. 13 ), alternating layer 1202 (see FIG. 13 ), barrier layer 1204 (see FIG. 13 ), active metal layer 1206 (see FIG. 13 ), and third conductive layer 1208 (see FIG. 13 ) is performed while hard masks 408 are positioned. The etching process transfers patterns of hard masks 408 to the underlying layers to form RRAM cells 102 individually for and at 1T1R cells 502. The RRAM cells 102 include individual top electrodes 108, individual active metal layers 112, individual barrier layers 104, individual turning layers 110, and individual bottom electrodes 106. The individual upper electrodes 108 are formed from the third conductive layer 1208, the individual active metal layers 112 are formed from the active metal layer 1206, the individual barrier layers 104 are formed from the barrier layer 1204, the individual switching layers 110 are formed from the switching layer 1202, and the individual lower electrodes 106 are partially formed from the second conductive layer 1102. The individual lower electrodes 106 include the lower electrode liners 106 land the first lower electrode body segments 106 b 1. In addition, the individual lower electrodes 106 include second body segments 106 b 2 of the lower electrodes formed of the second conductive layer 1102.By arranging the individual barrier layers 104 between the individual alternating layers and active metal layers 110, 112, the reliability of the switching cycles can be increased. For example, if an active metal layer 112 of an RRAM cell 102 is or comprises aluminum and a barrier layer 104 of the RRAM cell 102 is or comprises tantalum or tantalum nitride, the barrier layer 104 may reduce the number of aluminum cations that enter the alternating layer 110 upon tuning the RRAM cell 102. As indicated above, filaments build up in the alternating layer 110 and thus become thicker over time. This eventually leads to failure. By reducing the number of aluminum cations entering the alternating layer 110, the rate at which filaments of the RRAM cell 102 build up or become thicker decreases and thus the lifetime increases.As illustrated by cross-sectional view 1500 of FIG. 15, sidewall spacer structures 412 are formed on sidewalls of the RRAM cells 102. The sidewall spacer structures 412 may be formed, for example, by: 1) depositing a first dielectric layer on the RRAM cells 102; 2) depositing a second dielectric layer on the first dielectric layer; and 3) etching back the first and second dielectric layers to remove lateral but non-vertical segments of the dielectric layer. However, other methods are also possible. The first dielectric layer may be, for example, silicon oxide and / or any other suitable dielectric or dielectrics, while the second dielectric layer may be, for example, silicon nitride and / or any other suitable dielectric or dielectrics. Note that the hatching of the sidewall spacer structures 412 is not varied to illustrate the different materials.As also illustrated by cross-sectional view 1500 of FIG. 15, an etch stop layer 418, an IMD liner 420, and an IMD layer 414 are deposited over the RRAM cells 102 and sidewall spacer structures 412. The etch stop layer 418, the IMD liner 420, and the IMD layer 414 may be formed by, for example, vapor deposition and / or any other suitable deposition method or methods.As illustrated by cross-sectional view 1600 of FIG. 16, multiple additional wires 404 and multiple additional vias 406 are formed over the RRAM cells 102, recessed into the IMD layer 414 over the RRAM cells 102. The plurality of additional wires 404 include top electrode wires 404 tthat respectively overlay the RRAM cells 102, and the plurality of additional vias 406 include top electrode vias 406 tthat extend from the top electrode wires 404 tto the RRAM cells 102. Forming may include, for example: 1) patterning the IMD layer 414, the etch stop layer 418, and the IMD liner 420 to form openings for the additional wires 404 and the additional vias 406; 2) depositing a conductive layer in the openings; and 3) performing a CMP in the conductive layer until a top surface of the conductive layer is level with the IMD layer 414. However, other methods are also possible.As illustrated by the cross-sectional view 1700 of FIG. 17, metal threads 114 are formed individually for the alternating layers 110 and in these alternating layers, respectively. Forming may include, for example, applying a fabrication voltage across each of the RRAM cells 102. For example, the bottom electrodes 106 of the RRAM cells 102 may be grounded while the top electrodes 108 are biased. However, other methods of forming the metal filaments 114 are also possible. In some embodiments, by disposing the individual barrier layers 104 between the individual alternating layers and active metal layers 110, 112, the manufacturing voltage may be lowered. For example, the manufacturing voltage may be lowered by about 20-40%, about 20-30%, about 30-40%, about 30%, or any other suitable value. However, other percentages are possible. By lowering the manufacturing voltage, power consumption is reduced and error bits are reduced.Although FIGS. 7 to 17 are described with reference to a method, it is understood that the structures illustrated in FIGS. 7 to 17 are not limited to the method, but may instead be separate from the method. Although FIGS. 7 through 17 are described as a series of acts, it should be appreciated that the order of the acts may be changed in other embodiments. Although FIGS. 7 through 17 illustrate and describe a particular group of acts, some acts illustrated and / or described may be omitted in other embodiments. Further, acts not illustrated or described may be incorporated into other embodiments. Although FIGS. 7 through 17 illustrate the method with embodiments of the RRAM cells 102 of FIG. 5A, alternative embodiments of the method with embodiments of the RRAM cells 102 may be performed by any one or a combination of FIGS. 4A through 4F.In some embodiments, to perform the method with embodiments of the RRAM cells 102 of FIG. 4B, the etching at FIG. 14 ends at the barrier layer 1204. This forms the individual top electrodes 108 and the individual active metal layers 112, examples of which are shown in FIG. 4B, respectively. Next, the sidewall spacer structures 412 are formed as described with reference to FIG. 15. Further, an additional etching process is selectively performed into the barrier layer 1204, the alternating layer 1202, and the second conductive layer 1102, using the hard masks 408 and the sidewall spacer structures 412 as a mask. The additional etching process is performed between forming the sidewall spacer structures 412 in FIG. 15 and depositing the etch stop layer 418 in FIG. 15. The additional etching forms the individual barrier layers 104, the individual alternating layers 110 and the individual lower electrodes 106, examples of which are shown in FIG. 4B. After the additional etching, the method continues with depositing the etch stop layer 418 in FIG. 15, as described above.In some embodiments, the method is performed with embodiments of the RRAM cells 102 of FIG. 4C in the same manner as described above for embodiments of the RRAM cells 102 of FIG. 4B, except that the etching of FIG. 14 ends at the alternating layer 1202. In some embodiments, the method is performed with embodiments of the RRAM cells 102 of FIG. 4D by omitting the acts of FIG. 10 and omitting the planarization of FIG. 11.In some embodiments, etching back is performed to perform the method with embodiments of the RRAM cells 102 of FIG. 4F between depositing the liner layer 1002 of FIG. 10 and depositing the first conductive layer 1004. The etch back forms the lower electrode liners 106 lwith top surfaces recessed relative to a top surface of the via dielectric layer 416. An example of such a lower electrode liner 106 lis illustrated in FIG. 4F. After the etch back, the method is continued with the deposition of the first conductive layer 1004, as described above. Because the top surfaces of the lower electrode liners 106 lare recessed, the planarization of FIG. 11 does not reach the lower electrode liners 106 l, and top surfaces of the lower electrode vias 410 have a single hardness. Because the top surfaces of the bottom electrode vias 410 have a single hardness, planarization is more uniform at the top surfaces of the bottom electrode vias 410 and an electric field generated by the bottom electrode vias 410 is more uniform.Referring to FIG. 18, a block diagram 1800 of some embodiments of the method of FIGS. 7-17 is shown.At 1802, a connection structure is partially formed over a substrate, the connection structure comprising a wire of a bottom electrode. See, for example, FIG. 7.At 1804, a via dielectric layer is formed over the interconnect structure. See, for example, FIG. 8.At 1806, a bottom electrode via is formed that extends through the via dielectric layer to the bottom electrode wire. See, for example, Figs. 9-11.At 1808, a multi-layer memory film is formed on the via dielectric layer and the bottom electrode via, the multi-layer memory film including an alternating layer, an active metal layer, and a barrier layer between the alternating layer and the active metal layer. See, for example, FIG. 12.At 1810, the multilayer memory film is patterned to form a memory cell overlying and electrically connected to the bottom electrode wire. See, for example, FIGS. 13 and 14.At 1812, the interconnect structure around the memory cell is completed. See, for example, Figs. 15 and 16.At 1814, a fabrication voltage is applied across the memory cell to form a metal filament in the alternating layer, wherein the barrier layer slows the migration of metal cations from the active metal layer to the alternating layer in forming the metal filament. See, for example, FIG. 17.Although the block diagram 1800 of FIG. 18 is illustrated and described herein as a series of acts or events, it should be understood that the illustrated order of such acts or events is not to be interpreted as limiting. For example, some acts may occur in orders other than those illustrated and / or described herein, or concurrently with other acts or events. Further, not all illustrated acts need be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts illustrated herein may be performed in one or more separate acts and / or phases.Referring to FIGS. 19-23, there is shown a series of cross-sectional views 1900-2300 of some alternative embodiments of the method of FIGS. 7-17, the method being performed with embodiments of the RRAM cells 102 of FIG. 4F. As with cross-sectional views 700- 1700 of FIGS. 7- 17, cross-sectional views 1900- 2300 may have been recorded along line A or other suitable location of FIG. 6, for example.As illustrated by cross-sectional view 1900 of FIG. 19, a connection structure 402 is partially formed. The interconnect structure 402 includes a dielectric structure, multiple wires 404, and multiple vias (not shown). The dielectric structure includes a plurality of IMD layers 414 and also includes a via dielectric layer 416 between the IMD layers 414. Further, the wires 404 and the vias are alternately stacked in the dielectric structure to define conductive paths. The connection structure 402 may be partially formed, for example, as illustrated and described in FIG. 7.Note that, for the sake of compactness of the drawing, only an upper part of the connection structure 402 is illustrated. A remainder of the connection structure 402 may be configured, for example, as illustrated in FIG. 7. It should also be noted that, although not shown, the interconnect structure 402 overlies and is electrically connected to a substrate and semiconductor devices. The substrate and / or the semiconductor devices may be configured, for example, as described in FIG. 7. Further, the substrate and / or the semiconductor devices may be formed, for example, as described in FIG. 7.As illustrated by cross-sectional view 2000 of FIG. 20, via dielectric layer 416 and IMD layer 414 are patterned on top of via dielectric layer 416 to form individually for 1T1R cells 502 to be formed and at these memory cell openings 2002, respectively. The patterning may be performed, for example, by: 1) forming a photoresist mask 2004 by photolithography; 2) performing an etching process into the via dielectric layer 416 and the IMD layer 414 while the photoresist mask 2004 is positioned; and 3) removing the photoresist mask 2004. However, other methods are also possible.As illustrated by cross-sectional view 2100 of FIG. 21, a first conductive layer 2102, a switching layer 1202, a barrier layer 1204, an active metal layer 1206, and a second conductive layer 2104 are deposited lining the memory cell openings 2002 (see FIG. 20 ). The first and second conductive layers 2102, 2104 have low reactivity with oxygen compared to the active metal layer 1206. Such a low reactivity material may be, for example, a material for which 5 eV or more is required to react with oxygen. The alternating layer 1202, the barrier layer 1204, and the active metal layer 1206 may be configured, for example, as described with respect to FIG. 12.The barrier layer 1204 may be deposited by, for example, PVD, CVD, ALD, or any other suitable deposition method or methods. The alternating layer 1202, the first conductive layer 2102, and the second conductive layer 2104 may be deposited, for example, by PVD, CVD, or any other suitable deposition method or methods.As illustrated by the cross-sectional view 2200 of FIG. 22, planarization is performed into the first conductive layer 2102 (see FIG. 21 ), the alternating layer 1202 (see FIG. 21 ), the barrier layer 1204 (see FIG. 21 ), the active metal layer 1206 (see FIG. 21 ), and the second conductive layer 2104 (see FIG. 21 ) to individually form for the 1T1R cells 502 and these RRAM cells 102, respectively. The RRAM cells 102 include individual top electrodes 108, individual active metal layers 112, individual barrier layers 104, individual turning layers 110, and individual bottom electrodes 106. The individual upper electrodes 108 are formed from the second conductive layer 2104, the individual active metal layers 112 are formed from the active metal layer 1206, the individual barrier layers 104 are formed from the barrier layer 1204, the individual alternating layers 110 are formed from the alternating layer 1202, and the individual lower electrodes 106 are formed from the first conductive layer 2102. The planarization may be, or include, for example, a CMP or any other suitable planarization.Because the planarization transfers a selective etch pattern of FIG. 20 into the various layers of the RRAM cells 102, the RRAM cells 102 may be formed by a single photolithography / etch process. This is in contrast to the multiple photolithography / etch processes used to form the RRAM cells 102 of FIGS. 7-17. By reducing the number of photolithography / etching processes, costs are reduced.As illustrated by cross-sectional view 2300 of FIG. 23, an IMD layer 414 is deposited over the RRAM cells 102. The IMD layer 414 may be formed, for example, by vapor deposition and / or any other suitable deposition method or methods.As also illustrated by cross-sectional view 2300 of FIG. 23, multiple additional wires 404 and multiple additional vias 406 are formed over the RRAM cells 102, recessed into the IMD layer 414 over the RRAM cells 102. For example, the plurality of additional wires 404 and the plurality of additional vias 406 may be formed as described in FIG. 16.As is likewise represented by the cross-sectional view 2300 of FIG. 23, metal threads 114 are formed individually for the alternating layers 110. The forming may be performed, for example, as described with reference to FIG. 17.Although FIGS. 19 to 23 are described with respect to a method, it is understood that the structures illustrated in FIGS. 19 to 23 are not limited to the method, but may instead stand separately from the method. Although FIGS. 19 through 23 are described as a series of acts, it should be appreciated that the order of the acts may be changed in other embodiments. Although FIGS. 19 through 23 illustrate and describe a particular group of acts, some acts illustrated and / or described may be omitted in other embodiments, and acts not illustrated or described may be incorporated in other embodiments.Referring to Figure 24, there is shown a block diagram 2400 of some alternative embodiments of the method of Figures 19 to 23.At 2402, a connection structure is partially formed over a substrate, the connection structure comprising a wire of a bottom electrode. See, for example, FIG. 19.At 2404, a via dielectric layer and an IMD layer are formed stacked over the interconnect structure. See, for example, FIG. 19.At 2406, the via dielectric layer and the IMD layer are patterned to form a memory cell opening overlying and exposing the bottom electrode wire. See, for example, FIG. 20.At 2408, a multilayer memory film is formed on the IMD layer and filling the memory cell opening, the multilayer memory film including an alternating layer, an active metal layer, and a barrier layer between the alternating layer and the active metal layer. See, for example, FIG. 21.At 2410, planarization is performed into the multilayer memory film until a top surface of the multilayer memory film is approximately level with a top surface of the IMD layer. See, for example, FIG. 22.At 2412, the interconnect structure around the memory cell is completed. See, for example, FIG. 23.At 2414, a fabrication voltage is applied across the memory cell to form a metal filament in the alternating layer, wherein the barrier layer slows the migration of metal cations from the active metal layer to the alternating layer in forming the metal filament. See, for example, FIG. 23.Although the block diagram 2400 of FIG. 24 is illustrated and described herein as a series of acts or events, it should be understood that the illustrated order of such acts or events is not to be interpreted as limiting. For example, some acts may occur in orders other than those illustrated and / or described herein and / or concurrently with other acts or events. Further, not all illustrated acts need be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts illustrated herein may be performed in one or more separate acts and / or phases.

Claims

An integrated chip comprising: a substrate (508); and a resistive random access memory, RRAM, cell (102) overlying the substrate (508), wherein the RRAM cell (102) comprises a bottom electrode (106) and a top electrode (108), and further comprises an alternating layer (110), a barrier layer (104), and an active metal layer (112) stacked between the bottom and top electrodes (106, 108), wherein the barrier layer (104) is conductive and is located between the alternating layer (110) and the active metal layer (112), and wherein the barrier layer (104) has a lattice constant that is lower than that of the active metal layer (112), wherein the barrier layer (104) has a lattice constant lower than 350 μm and a density higher than 10 g / cm 3, and wherein the active metal layer (112) has a lattice constant higher than 385 μm and a density lower than 5 g / cm 3.The integrated chip of claim 1, wherein the active metal layer (112) comprises aluminum and wherein the barrier layer (104) comprises tantalum.The integrated chip of claim 1 or 2, wherein the barrier layer (104) has a higher density than the active metal layer (112).The integrated chip of any of the preceding claims, wherein the active metal layer (112) comprises a main element and wherein the integrated chip is adapted to form a conductive thread (114) in the alternating layer (110), wherein the conductive thread consists essentially of the main element.The integrated chip of claim 4, wherein the conductive filament (114) extends upwardly from the bottom electrode (106) and terminates at a location spaced below the barrier layer (104).The integrated chip of any preceding claim, wherein the barrier layer (104) has a barrier thickness and the active metal layer (112) has an active metal thickness, and wherein the barrier thickness is greater than the active metal thickness.The integrated chip of any preceding claim, further comprising: a wire (404b); and a via dielectric layer (416) overlying the wire (404b), wherein the barrier layer (104) overlies a top surface of the via dielectric layer (416) and has an indentation on the wire (404b), wherein the indentation extends to a location below the top surface of the via dielectric layer (416).The integrated chip of any preceding claim, wherein the lower and upper electrodes (106, 108) and the barrier layer (104) each have a U-shaped or V-shaped profile.An integrated chip comprising: a bottom electrode (106); a dielectric layer (110) overlying the bottom electrode (106); a barrier layer (104) overlying the dielectric layer (110), the barrier layer (104) comprising a tantalum layer; an aluminum layer (112) overlying the barrier layer (104); and a top electrode (108) overlying the aluminum layer (112); wherein the bottom and top electrodes (106, 108), the dielectric layer, and the aluminum layer (112) form a memory cell (102).The integrated chip of claim 9, adapted to form an aluminum filament (114) in the dielectric layer, the aluminum filament (114) extending upwardly from the bottom electrode (106) to the barrier layer (104).The integrated chip of any of the preceding claims 9 to 10, wherein the barrier layer (104) comprises: a tantalum layer (104l); and a tantalum nitride layer (104t) overlying the tantalum layer (104l).The integrated chip of any of the preceding claims 9 to 11, further comprising: a wire (404b) underlying the bottom electrode (106); and a via dielectric layer (416) between the wire (404b) and the memory cell (102), wherein the bottom electrode (106) has a T-shaped profile overlying the via dielectric layer (416) and protruding through the via dielectric layer (416) to the wire (404b).The integrated chip of claim 12, wherein the bottom electrode (106) comprises: a conductive body (106b); and a conductive liner (106l) enclosing a bottom surface of the conductive body (106b), wherein a top surface of the conductive liner (1061) is recessed relative to a top surface of the via dielectric layer (416).A method comprising: depositing a bottom electrode layer (106) over and electrically connected to a conductive wire (404); depositing a dielectric layer (110) over the bottom electrode layer (106); depositing a conductive barrier layer (104) over the dielectric layer (110); depositing a metal layer (112) over the conductive barrier layer (104), wherein the metal layer (112) has a density less than the conductive barrier layer (104), wherein the barrier layer (104) has a lattice constant less than that of the active metal layer (112), wherein the barrier layer (104) has a lattice constant less than 350 μm and a density greater than 10 g / cm 3 and wherein the active metal layer (112) has a lattice constant greater than 385 μm and a density less than 5 g / cm 3; depositing an upper electrode layer (108) over the metal layer (112), the upper electrode layer (108) having a lower reactivity with oxygen than the metal layer (112); and patterning the lower and upper electrode layers (106, 108), the dielectric layer (110), the conductive barrier layer (104), and the metal layer (112) to form a memory cell (102).The method of claim 14, further comprising: applying a fabrication voltage across the memory cell (102), whereby metal cations (202) migrate from the metal layer (112) through the conductive barrier layer (104) to the dielectric layer (110), and slowing a rate through the conductive barrier layer (104) at which the metal cations (202) migrate through the conductive barrier layer (104) while the fabrication voltage is applied.The method of claim 14 or 15, wherein the patterning comprises: forming a mask over the top electrode layer (108); and performing an etching process into the top electrode layer (108) and the metal layer (112) while the mask is positioned.The method of claim 16, wherein the etching ends on the conductive barrier layer (104), and wherein the patterning further comprises: forming a sidewall spacer structure (412) on sidewalls of the mask; and performing a second etching process in the conductive barrier layer (104), the dielectric layer, and the bottom electrode layer (106) while the mask and the sidewall spacer structure (412) are positioned.The method of any of the preceding claims 14 to 17, further comprising: depositing a second dielectric layer covering the conductive wire (404b); and patterning the second dielectric layer to form an opening overlying and exposing the conductive wire (404b), wherein the bottom and top electrode layers (106, 108), the dielectric layer (110), the conductive barrier layer (104), and the metal layer (112) are deposited to cover the second dielectric layer and line the opening, and wherein patterning the bottom and top electrode layers (106, 108), the dielectric layer (110), the conductive barrier layer (104), and the metal layer (112) comprises planarization into the bottom and top electrode layers (106, 108) and the conductive barrier layer (104).The method of any of the preceding claims 14 to 17, further comprising: depositing a second dielectric layer covering the conductive wire (404b); patterning the second dielectric layer to form an opening overlying and exposing the conductive wire (404b); depositing a second bottom electrode layer covering the second dielectric layer and filling the opening; and performing planarization in the second bottom electrode layer (106), wherein the bottom electrode layer (106) is deposited over the second bottom electrode layer and the second dielectric layer after planarization.

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