Light-emitting indicator device

Abstract

Light-emitting display device comprising: a substrate (10); and a plurality of pixels (P) arranged in a pixel region of the substrate (10), each of the plurality of pixels (P) having: a first circuit layer (110) comprising a first pixel circuit (PC1) comprising a driver transistor (Tdr); a second circuit layer (150) overlapping the first circuit layer (110), wherein the second circuit layer (150) has a second pixel circuit (PC2) having a data input transistor (Tds) configured to supply a data signal to the first pixel circuit (PC1); a circuit insulation layer (130) between the first circuit layer (110) and the second circuit layer (150); and a light-emitting diode layer (170) comprising a light-emitting diode (ED) electrically connected to the first pixel circuit (PC1), wherein the first pixel circuit (PC1) is configured to supply a data stream corresponding to a gate-source voltage of the driver transistor (Tdr) to the light-emitting diode (ED) based on the data signal supplied by the second pixel circuit (PC2), wherein the driver transistor (Tdr) has a first source-drain electrode connected to a first node (N1), a second source-drain electrode connected to a second node (N2) and a gate electrode connected to a third node (N3), the first pixel circuit (PC1) has: a first light emission control transistor (Tec1) which is configured to switch on based on a light emission control signal, wherein the first light emission control transistor (Tec1) is configured to supply a pixel driver voltage to the first node (N1); a second light emission control transistor (Tec2) which is configured to switch on based on the light emission control signal, thereby forming a current path between the second node (N2) and a fourth node (N4); and a storage capacitor (Cst) having a first capacitor electrode (Ec1) corresponding to the gate electrode of the driver transistor (Tdr) and a second capacitor electrode (Ec2) overlapping the first capacitor electrode (Ec1), wherein the second capacitor electrode (Ec2) is configured to receive the pixel driver voltage, where the light-emitting diode (ED) is electrically connected to the fourth node (N4), the first circuit layer (110) has: a light emission control line (ECL) that is configured to supply the light emission control signal to the first pixel circuit (PC1); a pixel driver power line (PL) that is configured to supply the pixel driver voltage to the first pixel circuit (PC1); a first line contact hole (Hlc1) that electrically connects the pixel driver power line (PL) to a first source-drain electrode of the first light emission control transistor (Tec1); and a second conductor contact hole (Hlc2) that electrically connects the pixel driver power line (PL) to the second capacitor electrode (Ec2).

Description

BACKGROUND Technical area

[0001] The present invention relates to a light-emitting display device. Description of the related technique

[0002] A light-emitting diode (LED) displays an image using a self-illuminating diode. As such, LEDs offer high response speed, low power consumption, and minimal viewing angle issues. LEDs are of particular interest as next-generation display devices. A typical LED incorporates a pixel circuit configured for each pixel. The pixel circuit emits light from an LED by controlling the amount of current flowing to and from a driver power source, using a driver thin-film transistor to switch in response to a data voltage. The pixel circuit thus displays a predetermined image.

[0003] In a light-emitting diode (LED) display, the current flowing to each pixel's LED can vary due to fluctuations in the threshold voltage of a driver transistor caused by factors such as process variations. Therefore, the pixel circuitry of a typical LED display cannot achieve uniform image quality with a single data stream output by the driver transistor. The data stream can vary from pixel to pixel, even when the data voltage is the same.

[0004] Recently, there has been a trend to implement light-emitting diode (LED) displays in mobile electronic devices, virtual image displays, or head-mounted displays. The resolution of such displays has gradually increased. However, as the resolution of the LED display increases, the pixel size gradually decreases, and it can become difficult to form or arrange a pixel circuit, including internal compensation circuitry, within a single pixel. For this reason, implementing a high-resolution LED display can be challenging.

[0005] US 2018 / 0 026 218 A1 describes a display device comprising a pixel circuit and a driver circuit in a display section, wherein the driver circuit contains a plurality of pulse output circuits, each of the plurality of pulse output circuits has a function for driving a gate line, the pixel circuit is electrically connected to the gate line, each of the plurality of pulse output circuits contains a first transistor, the pixel circuit contains a second transistor, a layer containing the second transistor is located above a layer containing the first transistor, and the first transistor and the second transistor overlap each other.

[0006] US 2018 / 0197474A1 describes a light-emitting display device comprising an organic light-emitting diode, a switching transistor, a first light-emitting control transistor, and a drive transistor, wherein the organic light-emitting diode has an anode and a cathode for receiving a reference voltage, the switching transistor has a gate electrode for receiving an nth sampling signal and a source electrode for receiving a data signal and is an NMOS transistor, wherein the first light-emitting control transistor has a gate electrode for receiving a light-emitting control signal and is configured to be turned on upon receipt of the light-emitting control signal in order to determine a time for the flow of a drive current to the organic light-emitting diode, and is a PMOS transistor.wherein the control transistor is connected to the switching transistor and the first light emission control transistor and supplies the control current to the organic light-emitting diode. SUMMARY

[0007] Accordingly, the present invention relates to a light-emitting display device which substantially overcomes one or more of the problems caused by limitations and disadvantages of the related technology.

[0008] Additional features and advantages of the present invention are set forth in the following description and are partly evident from the description or can be ascertained by carrying out the present invention. The objectives and other advantages of the present invention are realized and achieved through the structure, which is particularly highlighted in the written description, the associated claims, and the accompanying drawings.

[0009] To achieve these and other aspects of the inventive concepts, as embodied and described in detail, a light-emitting display device according to claim 1 is provided. Further embodiments are described in the dependent claims.In some exemplary embodiments, the light-emitting display device comprises: a substrate; and a plurality of pixels arranged in a pixel region on the substrate, each of the plurality of pixels comprising: a first circuit layer comprising a first pixel circuit including a driver transistor; a second circuit layer overlapping the first circuit layer, the second circuit layer comprising a second pixel circuit including a data input transistor configured to supply a data signal to the first pixel circuit; a circuit isolation layer between the first circuit layer and the second circuit layer; and a light-emitting diode layer comprising a light-emitting diode electrically connected to the first pixel circuit.The driver transistor has a first source-drain electrode connected to a first node, a second source-drain electrode connected to a second node, and a gate electrode connected to a third node.Furthermore, the first pixel circuit comprises: a first light emission control transistor configured to switch on based on a light emission control signal, wherein the first light emission control transistor is configured to supply a pixel driver voltage to the first node; a second light emission control transistor configured to switch on based on the light emission control signal, thereby forming a current path between the second node and a fourth node; and a storage capacitor comprising a first capacitor electrode corresponding to the gate electrode of the driver transistor and a second capacitor electrode overlapping the first capacitor electrode, wherein the second capacitor electrode is configured to receive the pixel driver voltage, and the light-emitting diode is electrically connected to the fourth node.The first circuit layer comprises a light emission control line configured to supply the light emission control signal to the first pixel circuit; a pixel driver power line configured to supply the pixel driver voltage to the first pixel circuit; a first lead contact hole electrically connecting the pixel driver power line to a first source-drain electrode of the first light emission control transistor; and a second lead contact hole electrically connecting the pixel driver power line to the second capacitor electrode.

[0010] In some exemplary embodiments, the first circuit layer is located between the substrate and the circuit insulation layer. In some exemplary embodiments, the second circuit layer further comprises a plurality of circuit connectors configured to electrically connect the second pixel circuit to the first pixel circuit through the circuit insulation layer. In some exemplary embodiments, the first pixel circuit is configured to supply a data stream to the LED corresponding to a gate-source voltage of the driver transistor, based on the data signal supplied by the second pixel circuit.

[0011] In some exemplary embodiments, the first circuit layer comprises: a light emission control line configured to supply the light emission control signal to the first pixel circuit; a pixel driver power line configured to supply the pixel driver voltage to the first pixel circuit; a first line contact hole electrically connecting the pixel driver power line to a first source-drain electrode of the first light emission control transistor; and a second line contact hole electrically connecting the pixel driver power line to the second capacitor electrode.

[0012] In some exemplary embodiments, the second pixel circuit further comprises: the data input transistor, which is configured to switch on based on a scan control signal, thereby supplying the data signal to the first node; a sampling transistor, which is configured to switch on based on the scan control signal, thereby electrically connecting the second node to the third node; a first initialization transistor, which is configured to switch on based on an initialization control signal, thereby supplying an initialization voltage to the third node; and a second initialization transistor, which is configured to switch on based on the initialization control signal, thereby supplying the initialization voltage to the fourth node.

[0013] In some exemplary embodiments, the sampling transistor has a first and a second sampling transistor connected in series between the second node and the third node.In some exemplary embodiments, the second circuit layer further comprises: a data line configured to supply the data signal to the second pixel circuit; a scan control line configured to supply the scan control signal to the second pixel circuit; an initialization control line configured to supply the initialization control signal to the second pixel circuit; an initialization voltage line configured to supply the initialization voltage to the second pixel circuit; a third line contact hole electrically connecting the data line to a first source-drain electrode of the data supply transistor; and a fourth line contact hole electrically connecting the initialization voltage line to a first source-drain electrode of the first initialization transistor and a first source-drain electrode of the second initialization transistor.

[0014] In some exemplary embodiments, the first circuit layer further comprises: a first node interconnect structure electrically connected to the first node; a second node interconnect structure electrically connected to the second node; a third node interconnect structure electrically connected to the gate electrode of the driver transistor; and a fourth node interconnect structure electrically connected to the fourth node, each of the first to fourth interconnect structures being electrically connected to the second pixel circuit.

[0015] In some exemplary embodiments, the second circuit layer further comprises: a first, second, third, and fourth circuit connector, each electrically connected to the first through fourth node interconnect structure; a data input transistor configured to turn on based on a scan control signal supplied to a scan control line, thereby supplying the data signal supplied from a data line to the first circuit connector; and a sampling transistor configured to turn on based on the scan control signal, thereby electrically connecting the second circuit connector to the third circuit connector.to turn on a first initialization transistor, configured to do so based on an initialization control signal supplied to an initialization control line, thereby supplying an initialization voltage supplied by an initialization voltage line to the third circuit connector; and to turn on a second initialization transistor, configured to do so based on the initialization control signal, thereby supplying the initialization voltage to the fourth circuit connector.

[0016] In some exemplary embodiments, the initialization control line and the scan control line are parallel to each other, and the first through fourth circuit connectors are located between the initialization control line and the scan control line. In some exemplary embodiments, the light-emitting display device further comprises: a planarization layer covering the second circuit layer; and an encapsulation layer covering the light-emitting diode layer, the light-emitting diode comprising: a pixel driver electrode electrically connected to the first pixel circuit; a light-emitting layer on the pixel driver electrode; and a cathode electrode (or a common electrode layer) electrically connected to the light-emitting layer.

[0017] In the display device according to the present invention, since the pixel circuit of a pixel can be deposited in a two-layer structure, the pixel circuit can be sufficiently arranged in the pixel even if the size of the pixel is reduced due to high resolution, thereby enabling a high resolution to be achieved.

[0018] It should be understood that both the preceding description and the following detailed description are exemplary and explanatory and are intended to provide a further explanation of the present invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are included to provide a further understanding of the present invention and which are contained in and form part of this application, illustrate exemplary embodiments of the present invention and, together with the description, serve to explain the principles of the present invention. In the drawings: Fig. Figure 1 represents a light-emitting display device according to an exemplary embodiment. Fig. Figure 2 represents a pixel according to an exemplary embodiment. Fig. 3 is a cross-sectional view showing a layered structure of the material. Fig. 2 pixels shown. Fig. 4 represents one circuit configuration per in Fig. 3 shown layer. Fig. 5 represents a layout of a Fig. 4 shows the first circuit layer. Fig. 6 is a cross-sectional view along the in Fig. 5 shown line I-I'. Fig. 7 is a cross-sectional view along the in Fig. 5 shown line II-II'. Fig. 8 represents a layout of a in Fig. 4 shows the second circuit layer. Fig. 9 is a cross-sectional view along the in Fig. 8 shown line III-III'. Fig. 10 is a cross-sectional view along the in Fig. 8 shown line IV-IV'. Fig. 11 is a cross-sectional view along the in Fig. 8 shown line V-V'. Fig. 12 is a cross-sectional view along the in Fig. 8 shown line VI-VI'. Fig. 13 is a cross-sectional view along the in Fig. 8 shown line VII-VII'. Fig. 14 is a cross-sectional view along the in Fig. 8 shown line VIII-VIII'. Fig. 15 is a cross-sectional view along the in Fig. 8 shown line VX-VX'. DETAILED DESCRIPTION

[0020] The advantages and features of the present invention, as well as its implementation methods, are explained by the following exemplary embodiments, which are described with reference to the accompanying drawings. However, the present invention can be embodied in other forms and should not be interpreted as being limited to the exemplary embodiments presented here. Rather, these exemplary embodiments are provided so that this disclosure is thorough and complete and fully conveys the scope of the present invention to those familiar with the technology. Furthermore, the present invention is defined by the scope of the claims.

[0021] Extensive reference will now be made to embodiments of the present invention, examples of which may be shown in the accompanying drawings. In the following description, a detailed description of functions or configurations related to this document and which are well known to those familiar with the technology may be omitted. The sequence of described processing steps and / or operations is an example. The sequence of steps and / or operations is not limited to that set forth herein and may be modified as is known in the technology or is obvious to those familiar with the technology, with the exception of steps and / or operations that necessarily occur in a specific sequence.The names of the respective elements used in the following explanations have been chosen for the sake of simplicity in writing the description and may therefore differ from those used in actual products.

[0022] The advantages and features of the present invention, as well as methods of its implementation, are explained by the following exemplary embodiments, which are described with reference to the accompanying drawings. However, the present invention can be embodied in other forms and should not be interpreted as being limited to the exemplary embodiments presented here. Rather, these exemplary embodiments are provided so that this disclosure is sufficiently thorough and complete to assist those familiar with the technology in fully understanding the scope of the present invention. Furthermore, the present invention is defined only by the scope of the claims.

[0023] The shape, size, ratio, angle, and number disclosed in the drawings to describe embodiments of the present invention are merely examples. The present invention is therefore not limited to the details shown. Unless otherwise specified, identical reference numerals consistently denote the same elements. In the following description, if it is found that a detailed description of a known function or configuration would unnecessarily obscure an important aspect of the present invention, the detailed description of such a known function or configuration may be omitted. Where the terms "have," "comprising," and "contain" are used in the present description, an additional part may be added unless a more restrictive term, such as "only," is used.Singular expressions can include plural forms unless otherwise stated.

[0024] When interpreting an element, the element is interpreted as including a margin of error or tolerance, even if no such margin of error or tolerance is explicitly mentioned. When describing a positional relationship, for example, if a positional ratio between two parts is described as "on," "above," "below," or "next to," one or more parts may be positioned between the two parts unless a more restrictive expression such as "exactly" or "directly" is used. When describing a temporal relationship, if the temporal sequence is described as, for example, "after," "subsequently," "next," or "before," the non-continuous case may be included unless a more restrictive expression such as "exactly," "immediately," or "directly" is used. It is to be understood that although expressions such as "first," "second," etc.,The terms used herein to describe various elements should not be restricted by these terms, as they are not used to define a specific order. These terms are used only to distinguish one element from another. For example, a first element could be called a second element, and, likewise, a second element could be called a first element, without departing from the scope of the present invention.

[0025] In describing elements of the present invention, terms such as "first", "second", "A", "B", "(a)", and "(b)" may be used. These terms serve only to distinguish one element from another, and the essence, sequence, order, or number of any such element should not be limited by these terms. Furthermore, when an element or layer is described as "connected", "coupled", or "attached" to another element or layer, this element or layer may not only be directly connected or attached to the other element or layer, but may also be indirectly connected or attached to the other element or layer, with one or more intermediate elements or layers being "arranged" between the elements or layers, unless otherwise described.The phrase "at least one" should be understood to encompass any and all combinations of one or more of the listed elements. For example, the meaning of "at least one of a first element, a second element, and a third element" includes combinations of all elements composed of two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element alone.

[0026] When describing embodiments, if a structure is described as being arranged "on or above" or "below or below" another structure, this description should be interpreted to include both a case where the structures are in contact with each other and a case where a third structure is arranged between them. The size and thickness of each element shown in the drawings are chosen solely for the sake of simplicity of description, and embodiments of the present invention are not limited thereto unless otherwise stated. Features of different embodiments of the invention may be partially or completely coupled or combined with one another and may interact and be technically controlled in various ways, as those familiar with the technology can reasonably understand.Embodiments of the present invention can be carried out independently of one another or together in a dependent relationship. Detailed reference is made below to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used across the drawings to denote the same or identical parts.

[0027] Fig. Figure 1 represents a light-emitting display device according to one embodiment. As in Fig. As shown in Figure 1, the light-emitting display device comprises a light-emitting display panel 100, a timing controller 300, a data driver circuit 500, and a gate driver circuit 700. The light-emitting display panel 100 has a substrate, a display area AA defined on the substrate, and a non-display area IA surrounding the display area AA. The substrate can be a base substrate (or base layer) and can be made of a plastic or glass material. According to an exemplary embodiment, the substrate can be a two-dimensional rectangular shape, a rectangular shape with rounded corners and a specific radius of curvature, or a non-rectangular shape with at least six sides. The substrate with a non-rectangular shape can have at least one projection and / or at least one indentation area.

[0028] According to an exemplary embodiment, the substrate can comprise an opaque or colored polyimide material. For example, the polyimide substrate can be obtained by curing a polyimide resin coated with a specific thickness onto a front surface of a release layer provided in a relatively thick support substrate. The support glass substrate can be separated from the substrate by removing the release layer using a laser cutting process. The substrate according to the exemplary embodiment can further comprise a backplate coupled to a rear surface of the substrate along a thickness direction Z. The backplate can hold the substrate in a flat state. The backplate according to an exemplary embodiment can comprise a plastic material, for example, polyethylene terephthalate.The backplate can be laminated onto the rear surface of the substrate detached from the carrier glass substrate.

[0029] According to another exemplary embodiment, the substrate can be a flexible glass substrate. For example, the glass substrate can be a thin glass substrate with a thickness of 100 micrometers or less. Alternatively, the glass substrate can be a carrier glass substrate that has been etched by a substrate etching process performed after completion of the manufacturing process of the light-emitting display panel 100, so that it has a thickness of 100 micrometers or less. The display area AA can have a plurality of initialization control lines ICL, a plurality of scan control lines SCL, a plurality of light emission control lines, a plurality of data lines DL, a plurality of pixel driver power lines PL, a plurality of initialization voltage lines IVL, a common electrode layer, and a plurality of pixels P.

[0030] Each of the plurality of initialization control lines ICL can extend longitudinally along a first direction X, and the respective initialization control lines ICL can be separated from each other by a distance along a second direction Y that intersects the first direction X. The first direction X can be parallel to a horizontal direction of the substrate, and the second direction Y can be parallel to a vertical direction of the substrate. Each of the plurality of initialization control lines ICL can supply an initialization control signal, provided by the gate driver circuit 700, to the pixels P.

[0031] Each of the plurality of scan control lines (SCL) extends longitudinally along the first direction X and lies adjacent to one of the respective initialization control lines (ICL). One end of each of the plurality of scan control lines (SCL) can be electrically connected to one side of its adjacent initialization control line (ICL). For example, the display area AA can have a first to m+1 initialization control line (ICL) and a first to m scan control line (SCL). One end of the i-th scan control line (i being a natural number) can be electrically connected to one side of the i+1 initialization control line (ICL). Each of the plurality of scan control lines (SCL) supplies a scan control signal to the pixels (P) from the gate driver circuit 700.

[0032] Each of the multiple light emission control lines ECL extends longitudinally along the first direction X and is parallel to each of the initialization control lines ICL. Each of the multiple light emission control lines ECL can supply a light emission control signal, provided by the gate driver circuit 700, to the pixels P. Each of the multiple data lines DL can extend longitudinally along the second direction Y, and the respective data lines DL can be separated from each other by a distance along the first direction X. Each of the multiple data lines DL can supply a data signal (or pixel data voltage), provided by the data circuit 500, to the pixels P.

[0033] Each of the plurality of pixel driver power lines PL can be parallel to each of the data lines DL. Each of the plurality of pixel driver power lines PL can supply a pixel driver voltage, provided by a power supply circuit, to the pixels P. According to an exemplary embodiment, each of the plurality of pixel driver power lines PL can be arranged per pair of pixels adjacent to each other along the first direction X. That is, a pixel driver power line PL can be shared by two pixels that are adjacent to each other along the first direction X. Each of the plurality of initialization voltage lines IVL can be parallel to each of the data lines DL. Each of the plurality of initialization voltage lines ICL can supply an initialization voltage, provided by the data driver circuit 500 or the power supply circuit, to the pixels P.

[0034] The common electrode layer can be located throughout the entire display area AA. The common electrode layer can supply the pixels with a common power source Vss supplied by the data circuit 500 or the power supply circuit. The display area AA can have at least one common power supply line electrically connected to the common electrode layer. Each of the plurality of pixels P is located in a pixel area defined within the display area AA of the substrate. Each of the plurality of pixels P can be electrically connected to the initialization control line ICL, the scan control line SCL, the light emission control line ECL, the data line DL, the pixel driver power line PL, the initialization voltage line IVL, and the common electrode layer, each of which can traverse the pixel area or be located near it.To achieve a high resolution of the light-emitting display panel 100 according to the present invention, the initialization control line ICL, the scan control line SCL, and the light emission control line ECL can traverse the pixel area. Furthermore, the data line DL, the pixel driver power line PL, and the initialization voltage line ICL can be located outside the pixel area. Two pixels that are adjacent to each other along the first direction X can have a symmetrical structure with respect to the pixel driver power line PL.

[0035] According to one exemplary embodiment, the pixels P in the display area AA can have a striped structure. A unit pixel can contain one red pixel, one green pixel, and one blue pixel. Furthermore, a unit pixel can also contain one white pixel. According to another exemplary embodiment, the pixels P in the display area AA can have a pentile structure. A unit pixel can contain at least one red pixel, at least two green pixels, and at least one blue pixel, each of which can have a two-dimensional polygonal shape. For example, a unit pixel with a pentile structure can be arranged such that one red pixel, two green pixels, and one blue pixel have a two-dimensional octagonal shape. The blue pixel can have an aperture (or light-emitting area) that is relatively the largest, and the green pixel can have an aperture (or light-emitting area) that is relatively the smallest.

[0036] Each of the multitude of pixels P can be operated in the sequence of an initialization period, a sampling period, and a light emission period to emit light with a luminance corresponding to the data signal supplied to the data line DL. The non-display area IA can be provided along an edge of the substrate so that it surrounds the display area AA. One side of the non-display area IA can have a pad section. The pad section can be located on one side of the non-display area AA and can be electrically connected to lines in the display area AA along the second direction Y. The pad section can be electrically connected to the data driver circuit 500.

[0037] The timing controller 300 generates pixel data Pdata by ordering input image data Idata so that it is suitable for driving the light-emitting display panel 100, and generates a data control signal DCS based on a timing synchronization signal TSS to supply the generated data and signal to the data driver circuit 500. The timing controller 300 generates a gate control signal GCS, which contains a variety of gate shift clocks and a gate start signal, based on the timing synchronization signal TSS, and supplies the generated signals to the gate driver circuit 700. The gate control signal GCS can be supplied to the gate driver circuit 700 by traversing the pad area. The data driver circuit 500 is connected to the variety of data lines DL provided in the light-emitting display panel 100 by traversing the pad area.The data driver circuit 500 converts the pixel data Pdata provided by the timing controller 300 into analog-type data signals using the data control signal DCS and a variety of reference gamma voltages, and routes the converted data signals to the appropriate data line DL.

[0038] The gate driver circuit 700 can generate an initialization control signal, a scan control signal, and a light emission control signal. These signals can correspond to the initialization period, the scanning period, or the light emission period of each of the plurality of pixels P, based on the gate control signal DCS provided by the timing controller 300, and can supply the generated signals to the plurality of pixels P. According to one exemplary embodiment, the gate driver circuit 700 generates initialization control signals whose phases are sequentially shifted by the same period and supplies the generated signals sequentially to the plurality of initialization control lines ICL. The gate driver circuit 700 also generates light emission control signals whose phases are sequentially shifted by the same period and supplies the generated signals to the plurality of light emission control lines ECL.

[0039] The initialization control signal is fed to each of the other initialization control lines, except that the first of the plurality of initialization control lines (ICL) is used as the scan control signal fed to each of the plurality of scan control lines (SCL). For example, the scan control signal fed to the first scan control line can be used as the initialization control signal fed to the second initialization control line. The initialization control signal can be expressed as a preceding (or (i-1)th) scan control signal, and the scan control signal can be expressed as a current (or i-th) scan control signal. Therefore, since the 700 gate driver circuit does not require a separate circuit to feed the scan control signal to each of the plurality of scan control lines (SCL), the circuit configuration can be simplified.

[0040] The gate driver circuit 700 according to an exemplary embodiment can be formed in the non-display region on a left and / or right side of the substrate, together with a fabrication process for a thin-film transistor of the pixel P. As an example, the gate driver circuit 700 can be formed in the non-display region on the left side of the substrate and can supply the initialization control signal and the light emission control signal to one end of each of the initialization control line ICL and the light emission control line ECL according to a single-feed method. As another example, the gate driver circuit 700 can be formed in the non-display region on both the left and right sides of the substrate.In this example, the gate driver circuit 700 can supply the initialization control signal and the light emission control signal to both ends of each of the initialization control line ICL and the light emission control line ECL according to a dual-feed method.

[0041] Fig. Figure 2 represents a pixel according to an exemplary embodiment. Fig. 3 is a cross-sectional view showing a layered structure of the material. Fig. 2 pixels shown. Fig. 4 represents one circuit configuration per in Fig. 3 layers shown. As in Fig. 2, Fig. 3 to Fig. As shown in Figure 4, according to an exemplary embodiment, the pixel P can have a first circuit layer 110 with a first pixel circuit PC1, which includes a driver transistor Tdr, and a second circuit layer 150 with a second pixel circuit PC2, which overlaps the first circuit layer 110 and includes a data input transistor Tds for supplying a data signal to the first pixel circuit PC1. The pixel P can further have a circuit isolation layer 130 between the first circuit layer 110 and the second circuit layer 150, and a light-emitting diode layer 170 with a light-emitting diode ED, which is electrically connected to the first pixel circuit PC1. The first circuit layer 110 can be on an upper face (or surface) of the substrate 10. That is, the first circuit layer 110 can be located between the substrate 10 and the circuit isolation layer 130.

[0042] The first circuit layer 110 according to an exemplary embodiment can comprise a first pixel circuit PC1, a light emission control line ECL for supplying a light emission control signal to the first pixel circuit PC1, and a pixel driver power line PL for supplying a pixel driver voltage to the first pixel circuit PC1. The light emission control line ECL is located in a first region of the pixel P such that it is parallel to the first direction X. The first region of the pixel P can be defined as an upper region of the pixel based on the second direction Y. The pixel driver power line PL is located at a side corner of the pixel P such that it is parallel to the second direction Y. This side corner of the pixel P can be defined as a left corner region of the pixel based on the first direction X.

[0043] The first pixel circuit PC1 supplies the light-emitting diode ED with a data stream corresponding to a gate-source voltage of the driver transistor Tdr, based on the data signal supplied by the second pixel circuit PC2. The first pixel circuit PC1 (or the first circuit layer 110) according to an exemplary embodiment comprises a driver transistor Tdr, a first light emission control transistor Tec1, a second light emission control transistor Tec2, and a storage capacitor Cst.

[0044] The driver transistor Tdr outputs the data stream corresponding to the gate-source voltage based on the data signal supplied by the second pixel circuit PC2. According to an exemplary embodiment, the driver transistor Tdr has a gate electrode connected to a third node N3, a first source-drain electrode connected to a first node N1, and a second source-drain electrode connected to a second node N2. For example, in the driver transistor Tdr, the first source-drain electrode can be a source electrode, and the second source-drain electrode can be a drain electrode. The driver transistor Tdr can turn on based on the gate-source voltage to establish a current path between the first node N1 and the second node N2, and outputs the data stream corresponding to the gate-source voltage to the second node N2.

[0045] The first light emission control transistor Tec1 can switch on based on the light emission control signal to supply a pixel driver voltage to the first node N1. According to an exemplary embodiment, the first light emission control transistor Tec1 can have a gate electrode connected to the light emission control line ECL, a first source-drain electrode connected to the pixel driver power line PL, and a second source-drain electrode connected to the first node N1. The gate electrode of the first light emission control transistor Tec1 can be a first region of the light emission control line ECL or a first protrusion region projecting from the first region of the light emission control line ECL. In the first light emission control transistor Tec1, the first source-drain electrode can be a source electrode, and the second source-drain electrode can be a drain electrode.The first light emission control transistor Tec1 can be switched on based on the light emission control signal supplied by the light emission control line ECL to establish a current path between the pixel driver power line PL and the first node N1. The first light emission control transistor Tec1 can also supply the pixel driver power source supplied by the pixel driver power line PL to the first source-drain electrode of the driver transistor Tdr through the first node N1.

[0046] The second light emission control transistor Tec2 can switch on based on the light emission control signal to establish a current path between the second node N2 and the fourth node N4. According to an exemplary embodiment, the second light emission control transistor Tec2 can have a gate electrode connected to the light emission control line ECL, a first source-drain electrode connected to the second node, and a second source-drain electrode connected to the fourth node. The gate electrode of the second light emission control transistor Tec2 can be a second region of the light emission control line ECL separated from the first region of the light emission control line ECL by a distance, or a second protrusion region projecting from the second region of the light emission control line ECL.In the second light emission control transistor Tec2, the first source-drain electrode can be a source electrode, and the second source-drain electrode can be a drain electrode. Based on the light emission control signal supplied by the light emission control line ECL, the second light emission control transistor Tec2 can switch on to establish a current path between the second node N2 and the fourth node N4. The second light emission control transistor Tec2 can also feed the data current supplied by the driver transistor Tdr through the fourth node N4 to the LED ED.

[0047] The driver transistor Tdr, the first light emission control transistor Tec1, and the second light emission control transistor Tec2 can each have a semiconductor layer made of amorphous silicon, polysilicon, or an oxide semiconductor material. The driver transistor Tdr, the first light emission control transistor Tec1, and the second light emission control transistor Tec2 can each be a P-type thin-film transistor with a semiconductor layer doped with P-type defects. In other words, each of the transistors can be modified to an N-type thin-film transistor with a semiconductor layer doped with N-type defects. The polysilicon material exhibits excellent reliability under high bias loads and has high electron mobility.Therefore, the driver transistor Tdr, the first light emission control transistor Tec1 and the second light emission control transistor Tec2 can each be a P-type thin-film transistor having a semiconductor layer made of a polysilicon material doped with P-type defects.

[0048] The storage capacitor Cst stores a differential voltage between the gate electrode and the source electrode of the driver transistor Tdr. For example, the storage capacitor Cst stores a data voltage supplied by the second pixel circuit PC2 and a characteristic compensation voltage of the driver transistor Tdr. According to an exemplary embodiment, the storage capacitor Cst has a first capacitor electrode Ec1 connected to the gate electrode of the driver transistor Tdr and a second capacitor electrode Ec2 that overlaps the first capacitor electrode Ec1 and to which a pixel driver voltage is supplied.

[0049] The first capacitor electrode Ec1 can contain the gate electrode of the driver transistor Tdr within a capacitor region defined in the first circuit layer 110. The second capacitor electrode Ec2 can be located within the capacitor region defined in the first circuit layer 110, such that it overlaps the first capacitor electrode Ec1, and can be electrically connected to the pixel driver power line PL. The first capacitor electrode Ec1 and the second capacitor electrode Ec2 can overlap by the insertion of a gate isolation layer between them. Therefore, the storage capacitor Cst can be formed at the gate isolation layer between the first capacitor electrode Ec1 and the second capacitor electrode Ec2.

[0050] The first pixel circuit PC1 (or the first circuit layer 110) according to an exemplary embodiment can further comprise a first conductor contact hole Hlc1 and a second conductor contact hole Hlc2. The first conductor contact hole Hlc1 electrically connects the pixel driver power line PL to the first source-drain electrode of the first light emission control transistor Tec1. That is, the pixel driver power line PL can be electrically connected to the first source-drain electrode of the first light emission control transistor Tec1 through the first conductor contact hole Hlc1. The second conductor contact hole Hlc2 electrically connects the pixel driver power line PL to the second capacitor electrode Ec2. That is, the pixel driver power line PL can be electrically connected to the second capacitor electrode Ec2 through the second conductor contact hole Hlc2.

[0051] The first pixel circuit PC1 (or the first circuit layer 110) according to an exemplary embodiment can further comprise first to fourth node interconnection structures Pnc1, Pnc2, Pnc3, and Pnc4, which are electrically connected to the first to fourth nodes N1, N2, N3, and N4, respectively. Each of the first to fourth node interconnection structures Pnc1, Pnc2, Pnc3, and Pnc4 is located on the top surface of the circuit layer 110 and is covered by the circuit insulation layer 130. The first to fourth node interconnection structures Pnc1, Pnc2, Pnc3, and Pnc4 are each configured as islands, thus being electrically isolated from one another, and are made of the same conductive material as that of the pixel driver power line PL.

[0052] The first node connection structure Pnc1 is located on the top surface of the first circuit layer 110, overlapping the first node N1 and electrically connected to it. The second node connection structure Pnc2 is located on the top surface of the first circuit layer 110, overlapping the second node N2 and electrically connected to it. The third node connection structure Pnc3 is located on the top surface of the first circuit layer 110, overlapping the third node N3 and electrically connected to it. The fourth node connection structure Pnc4 is located on the top surface of the first circuit layer 110, overlapping the fourth node N4 and electrically connected to it.

[0053] The first pixel circuit PC1 (or the first circuit layer 110) according to an exemplary embodiment can be defined as a current supply circuit that supplies a data current to the light-emitting diode ED. In the first pixel circuit PC1 (or the first circuit layer 110), the storage capacitor Cst can be a voltage storage circuit for storing a voltage corresponding to the data current supplied to the light-emitting diode ED. The driver transistor Tdr can be a current output circuit for supplying the data current to the light-emitting diode ED. The first light emission control transistor Tec1 and the second light emission control transistor Tec2 can be current path forming circuits.

[0054] The circuit insulation layer 130 is located on the substrate 10, covers the first circuit layer 110, and electrically isolates (or separates) the first circuit layer 110 from the second circuit layer 150. The circuit insulation layer 130 can be made of an organic insulating material or an inorganic insulating material. According to one exemplary embodiment, the circuit insulation layer 130 can be relatively thick to provide a planar surface (or flat surface) on the first circuit layer 110. According to another exemplary embodiment, the circuit insulation layer 130 can be relatively thin to conform to a shape that follows the surface shape of the first circuit layer 110 as it is.

[0055] The second circuit layer 150 can overlap the first circuit layer 110 and include a data input transistor Tds for supplying the data signal to the first pixel circuit PC1 of the first circuit layer 110. The second circuit layer 150 can be located on top of the circuit insulation layer 130 to overlap the first circuit layer 110. The second circuit layer 150 can be located between the substrate 10 and the circuit insulation layer 130, i.e., below the first circuit layer 110. However, the semiconductor layer of the driver transistor Tdr is located on the second circuit layer 150, which may degrade the driver characteristics of the driver transistor Tdr. Therefore, the first circuit layer 110, which contains the first driver transistor Tdr, can be located between the substrate 10 and the circuit insulation layer 130 to form the semiconductor layer of the driver transistor Tdr in a planar structure.It is not necessary to provide the planar surface on the first circuit layer 110 by the circuit insulation layer 130. If the first circuit layer 110 is on top of the second circuit layer 150, the first circuit layer 110 provides a planar surface on the second circuit layer 150 by using the thickness of the circuit insulation layer 130 to form the semiconductor layer of the driver transistor Tdr in a planar structure.

[0056] The second circuit layer 150 according to an exemplary embodiment can comprise a second pixel circuit PC2, a data line DL for supplying a data signal to the second pixel circuit PC2, an initialization control line ICL for supplying an initialization control signal to the second pixel circuit PC2, and an initialization voltage line IVL for supplying an initialization voltage to the second pixel circuit PC2. The data line DL is located at a side corner of the pixel P such that it is parallel to the second direction Y. According to an exemplary embodiment, the data line DL can be located at a side corner of the pixel P such that it overlaps the pixel driver power line DL in the first circuit layer 110 two-dimensionally or without two-dimensional overlap.For example, the data line DL at a side corner of the pixel P can be positioned such that it does not overlap the pixel driver power line PL in the first circuit layer 110.

[0057] The initialization control line ICL is located in the first region of pixel P and is parallel to the first direction X. According to an exemplary embodiment, the initialization control line ICL can be located in the first region of pixel P such that it overlaps the light emission control line ECL in the first circuit layer 110 two-dimensionally or not two-dimensionally. For example, the initialization control line ICL can be located in the first region of pixel P such that it does not overlap the light emission control line ECL in the first circuit layer 110.

[0058] The scan control line SCL is located in a second region of pixel P such that it is separated from the initialization control line ICL by a distance and is parallel to the initialization control line ICL. The second region of pixel P can be defined as an intermediate region of the pixel based on the second direction Y. According to an exemplary embodiment, the scan control line SCL can be located in the second region of the pixel such that it either overlaps the light emission control line ECL in the first circuit layer 110 two-dimensionally or does not overlap it two-dimensionally. For example, the scan control line SCL in the second region of pixel P can be located such that it does not overlap the light emission control line ECL in the first circuit layer 110. The initialization voltage line IVL is located at the other corner of pixel P, so that it is parallel to the data line DL.The other corner of pixel P can be defined as a right corner region of the pixel based on the first direction X.

[0059] The second pixel circuit PC2 initializes a voltage at the third node N3 and the fourth node N4 of the first pixel circuit PC1 and supplies a data signal, fed from the data line DL, to the first pixel circuit PC1 of the first circuit layer 110. The second pixel circuit PC2 (or the second circuit layer 150) according to an exemplary embodiment can comprise a data input transistor Tds, a first initialization transistor Ti1, a second initialization transistor Ti2, and a sampling transistor Ts. The second pixel circuit PC2 (or the second circuit layer 150) according to an exemplary embodiment can further comprise first through fourth nodes N1', N2', N3', and N4'.The first to fourth nodes N1', N2', N3', and N4' can each overlap with the corresponding first to fourth nodes N1, N2, N3, and N4 of the first circuit layer 110, or they can overlap with the corresponding first to fourth node connection structure Pnc1, Pnc2, Pnc3, and Pnc4 of the first circuit layer 110. The first to fourth nodes N1, N2, N3, and N4 of the first circuit layer 110 can be defined as the first to fourth lower nodes, and the first to fourth nodes N1', N2', N3', and N4' can correspondingly be defined as the first to fourth upper nodes.

[0060] The data input transistor Tds can switch on based on the scan control signal to supply the data signal supplied by the data line DL to the first node N1 of the first pixel circuit PC1. According to an exemplary embodiment, the data input transistor Tds can have a gate electrode connected to the scan control line SCL, a first source-drain electrode connected to the data line DL, and a second source-drain electrode connected to the first node N1'. The gate electrode of the data input transistor Tds can be a first region of the scan control line SCL or a first protrusion region projecting from the first region of the scan control line SCL. In the data input transistor Tds, the first source-drain electrode can be a source electrode, and the second source-drain electrode can be a drain electrode.The data input transistor Tds can turn on based on the scan control signal supplied by the scan control line SCL to establish a current path between the data line DL and the first node N1. The data input transistor Tds can also supply the data signal supplied by the data line DL to the first source-drain electrode of the driver transistor Tdr via the first node N1'.

[0061] The first initialization transistor Ti1 can turn on based on the initialization control signal to supply the initialization voltage, provided by the initialization voltage line IVL, to the third node N3 of the first pixel circuit PC1. According to an exemplary embodiment, the first initialization transistor Ti1 can have a gate electrode connected to the initialization control line ICL, a first source-drain electrode connected to the initialization voltage line IVL, and a second source-drain electrode connected to the third node N3'. The gate electrode of the first initialization transistor Ti1 can be a first region of the initialization control line ICL or a first protrusion region projecting from the first region of the initialization control line ICL.In the first initialization transistor Ti1, the first source-drain electrode can be a source electrode, and the second source-drain electrode can be a drain electrode. Based on the initialization control signal supplied by the initialization control line ICL, the first initialization transistor Ti1 can turn on to establish a current path between the initialization voltage line IVL and the third node N3'. The first initialization transistor Ti1 can also supply the initialization control signal supplied by the initialization control line ICL to the gate electrode of the driver transistor Tdr, which is connected to the third node N3 of the first pixel circuit PC1.

[0062] The second initialization transistor Ti2 can turn on based on the initialization control signal to supply the initialization voltage, provided by the initialization voltage line IVL, to the fourth node N4 of the first pixel circuit PC1. According to one exemplary embodiment, the second initialization transistor Ti2 can have a gate electrode connected to the initialization control line ICL, a first source-drain electrode also connected to the initialization voltage line ICL, and a second source-drain electrode connected to the fourth node N4'. The gate electrode of the second initialization transistor Ti2 can be a second region of the initialization control line ICL or a second protrusion region extending from the second region of the initialization control line ICL.In the second initialization transistor Ti2, the first source-drain electrode can be a drain electrode, and the second source-drain electrode can be a source electrode. Based on the initialization control signal supplied by the initialization control line ICL, the second initialization transistor Ti2 can turn on to establish a current path between the initialization voltage line IVL and the fourth node N4'. The second initialization transistor Ti2 can also supply the initialization voltage supplied by the initialization voltage line IVL to the fourth node N4 of the first pixel circuit PC1 through the fourth node N4'.

[0063] The sampling transistor Ts can switch on based on the scan control signal to electrically connect the second node N2' to the third node N3'. That is, the sampling transistor Ts can switch on based on the scan control signal to connect the gate and drain electrodes of the driver transistor Tdr provided in the first pixel circuit PC1, thereby allowing the driver transistor Tdr to be configured as a diode. According to an exemplary embodiment, the sampling transistor Ts can have a gate electrode connected to the scan control line SCL, a first source-drain electrode connected to the second node N2', and a second source-drain electrode connected to the third node N3'. The gate electrode of the sampling transistor Ts can be a second region of the scan control line SCL or a second protrusion region extending from the second region of the scan control line SCL.In the sampling transistor Ts, the first source-drain electrode can be a source electrode, and the second source-drain electrode can be a drain electrode. Based on the scan control signal supplied by the scan control line SCL, the sampling transistor Ts can switch on to establish a current path between the second node N2' and the third node N3'. The sampling transistor Ts can electrically connect the second node N2' to the third node N3', thereby acting as a diode for the driver transistor Tdr of the first circuit layer 110.

[0064] The sampling transistor Ts (or compensation transistor) according to another exemplary embodiment can have a dual-channel structure. That is, since the sampling transistor Ts can be electrically connected to the gate electrode of the driver transistor Tdr, the sampling transistor Ts can have a dual-channel structure that can reduce and possibly minimize leakage current in order to maintain a uniform gate voltage of the driver transistor Tdr. As an example, the sampling transistor Ts can have a first sampling transistor Ts1 and a second sampling transistor Ts2 connected in series, such that the transistors can turn on simultaneously based on the scan control signal.

[0065] The first sampling transistor Ts1 can have a gate electrode connected to the scan control line SCL, a first source-drain electrode connected to the third node N3', and a second source-drain electrode connected to the second sampling transistor Ts2. In the first sampling transistor Ts1, the gate electrode can be a second region of the scan control line SCL or a second protrusion region projecting from the second region of the scan control line SCL. Furthermore, the first source-drain electrode can be a drain electrode, and the second source-drain electrode can be a source electrode.

[0066] The second sampling transistor Ts2 can have a gate electrode connected to the scan control line SCL, a first source-drain electrode connected to the second source-drain electrode of the first sampling transistor Ts1, and a second source-drain electrode connected to the second node N2'. In the second sampling transistor Ts2, the gate electrode can be a third region of the scan control line SCL or a third protrusion region projecting from the third region of the scan control line SCL. Furthermore, the first source-drain electrode can be a drain electrode, and the second source-drain electrode can be a source electrode.

[0067] Each of the data input transistor Tds, the first initialization transistor Ti1, the second initialization transistor Ti2, and the sampling transistor Ts can have a semiconductor layer containing an amorphous silicon material, a polysilicon material, or an oxide semiconductor material, and can be a P-type thin-film transistor having a semiconductor layer doped with P-type impurities. That is to say, each of the transistors can be modified to be an N-type thin-film transistor having a semiconductor layer doped with N-type impurities. Each of the transistors Tds, Ti1, Ti2, and Ts that form the second pixel circuit PC2 according to an exemplary embodiment can be a P-type thin-film transistor having a semiconductor layer made of a polysilicon material doped with P-type impurities.

[0068] The second pixel circuit PC2 (or the second circuit layer 150) according to an exemplary embodiment can further comprise a third line contact hole Hlc3 and a fourth line contact hole Hlc4. The third line contact hole Hlc3 electrically connects the data line DL to the first source-drain electrode of the data input transistor Tds. That is, the data line DL can be electrically connected to the first source-drain electrode of the data input transistor Tds through the third line contact hole Hlc3. The fourth line contact hole Hlc4 connects each of the first source-drain electrodes of the first initialization transistor Ti1 and the first source-drain electrode of the second initialization transistor Ti2 to the initialization voltage line IVL.This means that the initialization voltage line IVL can be electrically connected to each of the first source-drain electrodes of the first initialization transistor Ti1 and the first source-drain electrode of the second initialization transistor Ti2 through the fourth line contact hole Hlc4.

[0069] The second circuit layer 150 according to an exemplary embodiment can further comprise first to fourth circuit connectors Cc1 to Cc4, which connect the first pixel circuit PC1 to the second pixel circuit PC. The first to fourth circuit connectors Cc1 to Cc4 are each formed in the second circuit layer 150 in an island configuration such that they are electrically isolated from one another and are simultaneously formed from the same conductive material. The number of circuit connectors is not limited and can be multiple.

[0070] The first circuit connector Cc1 electrically connects the first node N1 of the first pixel circuit PC1 to the first node N1' of the second pixel circuit PC2. That is, one side of the first circuit connector Cc1 can be electrically connected to the first node N1' of the second pixel circuit PC2, and the other side of the first circuit connector Cc1 can be electrically connected to the first node connection structure Pnc1 of the first circuit layer 110 by passing through the circuit insulation layer 130. Therefore, the first node N1 of the first pixel circuit PC1 in the first circuit layer 110 can be electrically connected to the first node N1' of the second pixel circuit PC2 in the second circuit layer 150 via the first node connection structure Pnc1 and the first circuit connector Cc1.

[0071] The second circuit connector Cc2 electrically connects the second node N2 of the first pixel circuit PC1 to the second node N2' of the second pixel circuit PC2. That is, one side of the second circuit connector Cc2 can be electrically connected to the second node N2' of the second pixel circuit PC2, and the other side of the second circuit connector Cc2 can be electrically connected to the second node connection structure Pnc2 of the first circuit layer 110 by passing through the circuit insulation layer 130. Therefore, the second node N2 of the first pixel circuit PC1 in the first circuit layer 110 can be electrically connected to the second node N2' of the second pixel circuit PC2 in the second circuit layer 150 via the second node connection structure Pnc2 and the second circuit connector Cc2.

[0072] The third circuit connector Cc3 electrically connects the third node N3 of the first pixel circuit PC1 to the third node N3' of the second pixel circuit PC2. According to one exemplary embodiment, one side of the third circuit connector Cc3 can be electrically connected to the third node N3' of the second pixel circuit PC2. The other side of the third circuit connector Cc3 can be electrically connected to the third node connection structure Pnc3 of the first circuit layer 110 by passing through the circuit insulation layer 130. Therefore, the third node N3 of the first pixel circuit PC1 in the first circuit layer 110 can be electrically connected to the second node N2' of the second pixel circuit PC2 in the second circuit layer 150 via the third node connection structure Pnc3 and the third circuit connector Cc3.The other side of the third circuit connector Cc3 according to a further exemplary embodiment can be electrically connected to the first capacitor electrode Ec1 in the first circuit layer 110 by passing through the circuit insulation layer 130. The third node connection structure Pnc3 of the first circuit layer 110 can be omitted.

[0073] The fourth circuit connector Cc4 electrically connects the fourth node N4 of the first pixel circuit PC1 to the fourth node N4' of the second pixel circuit PC2. That is, one side of the fourth circuit connector Cc4 can be electrically connected to the fourth node N4' of the second pixel circuit PC2, and the other side of the fourth circuit connector Cc4 can be electrically connected to the fourth node connection structure Pnc4 of the first circuit layer 110 by passing through the circuit insulation layer 130. Therefore, the fourth node N4 of the first pixel circuit PC1 in the first circuit layer 110 can be electrically connected to the fourth node N4' of the second pixel circuit PC2 in the second circuit layer 150 via the fourth node connection structure Pnc4 and the fourth circuit connector Cc4.

[0074] The second pixel circuit PC2 (or the second circuit layer 150) according to an exemplary embodiment can electrically connect the second and third nodes N2 and N3 of the first pixel circuit PC1. The second pixel circuit PC2 (or the second circuit layer 150) can also supply the data signal to the first pixel circuit PC1 in response to the scan control signal and can initialize the voltage of each of the third and fourth nodes N3 and N4 of the first pixel circuit PC1 in response to the initialization control signal.Therefore, in the second pixel circuit PC2 (or the second circuit layer 150) the data input transistor Tds can be defined as a data input circuit, the first initialization transistor Ti1 and the second initialization transistor Ti2 can be defined as pixel initialization circuits, and the sampling transistor Ts can be defined as an internal compensation circuit.

[0075] The light-emitting diode layer 170 can include a light-emitting diode ED that is electrically connected to the first pixel circuit PC1 to emit light based on the data stream supplied by the first pixel circuit PC1. According to an exemplary embodiment, the light-emitting diode ED can include a pixel driver electrode AE ​​(or anode electrode) connected to the pixel circuit PC, a light-emitting layer EL formed on the pixel driver electrode AE, and a common electrode layer CE (or cathode electrode) electrically connected to the light-emitting layer EL.

[0076] The pixel driver electrode AE ​​is located in the aperture region of pixel P and can be electrically connected to the fourth node N4 of the first pixel circuit PC1, and in particular to the fourth node N4' of the second pixel circuit PC2. According to an exemplary embodiment, the pixel driver electrode AE ​​can be made of a high-reflectivity metal material. For example, the pixel driver electrode AE ​​can have a multilayer structure. The multilayer structure can be: a deposition structure (Ti / Al / Ti) of A1 and Ti, a deposition structure (ITO / Al / ITO) of A1 and ITO, an APC (Ag / Pd / Cu) alloy, or a deposition structure (ITO / APC / ITO) of an APC alloy and ITO. Alternatively, the pixel driver electrode AE ​​can have a single-layer structure consisting of any material or two or more alloy materials selected from Ag, Al, Mo, Au, Mg, Ca, and Ba. One corner of the pixel driver electrode AE ​​can be covered by a bank structure BNK.The bank structure BNK is located in the other pixel regions except for the aperture region of pixel P, so that it covers the corner of the pixel driver electrode AE, and thereby defines the aperture region of pixel P. According to an exemplary embodiment, the bank structure BNK can be defined in a pentile structure or a stripe structure.

[0077] The light-emitting layer EL according to an exemplary embodiment can be formed over the entire display area of ​​the substrate 10, such that it covers the pixel driver electrode AE ​​and the bank structure BNK 127. The light-emitting layer EL according to an exemplary embodiment has two or more light-emitting sub-regions for emitting white light. For example, the light-emitting layer EL according to an exemplary embodiment can have a first and a second light-emitting sub-region for emitting white light by mixing the first and second light. The first light-emitting sub-region emits the first light and can include any of the following: a blue light-emitting sub-region, a green light-emitting sub-region, a red light-emitting sub-region, a yellow light-emitting sub-region, and a cyan light-emitting sub-region.The second light-emitting sub-area can be a light-emitting sub-area for emitting the second light with a color complementary to the first light, derived from the blue light-emitting sub-area, the green light-emitting sub-area, the red light-emitting sub-area, the yellow light-emitting sub-area, and the cyan light-emitting sub-area.

[0078] The light-emitting layer EL according to a further exemplary embodiment can have any sub-region consisting of a blue light-emitting sub-region, a green light-emitting sub-region, and a red light-emitting sub-region to emit colored light corresponding to the color specified in the pixel. For example, the light-emitting layer EL according to a further exemplary embodiment can have any sub-region consisting of an organic light-emitting layer, an inorganic light-emitting layer, and a quantum dot light-emitting layer, or can have a deposited or mixed structure of the organic light-emitting layer (or inorganic light-emitting layer) and the quantum dot light-emitting layer.In addition, according to an exemplary embodiment, the light-emitting diode ED can further comprise a functional layer for improving the emission efficiency and / or lifetime of the light-emitting layer EL. The common electrode layer CE can be electrically connected to the light-emitting layer EL. The common electrode layer CE can be located across the entire display area of ​​the substrate 10, so that it is electrically connected to the light-emitting layer EL provided with each pixel area PA.

[0079] The common electrode layer CE according to an exemplary embodiment can comprise a transparent conductive material capable of transmitting light or a semi-transparent conductive material. If the common electrode layer CE is formed from a semi-transparent conductive material, the light emission efficiency of light emitted by the LED ED can be increased by a microcavity. The semi-transparent conductive material according to an exemplary embodiment can comprise Mg, Ag, or an alloy of Mg and Ag. Additionally, a cover layer for improving the light emission efficiency by controlling the refractive index of light emitted by the LED ED can also be formed on the common electrode layer CE.

[0080] The light emission layer EL according to a further exemplary embodiment can include a micro light-emitting diode (MILED) implemented as an integrated circuit. The MILED can have a first terminal electrically connected to the pixel driver electrode AE ​​and a second terminal electrically connected to the common electrode layer CE. The pixel P according to an exemplary embodiment can further include a planarization layer 160 covering the second circuit layer 150 and an encapsulation layer 190 covering the MILED layer 170. The planarization layer 160 is on the substrate 10 to cover the second circuit layer 150, thereby providing a planarized surface on the second circuit layer 150. The MILED layer 170 is on the planarization layer 160.The pixel driver electrode AE ​​of the light-emitting diode layer 170 can be electrically connected to the fourth node N4 of the first pixel circuit PC1, in particular to the fourth node N4' of the second pixel circuit PC2, through an electrode contact hole provided in the planarization layer 160.

[0081] The encapsulation layer 190 is applied to the substrate 10 to surround the light-emitting diode (LED) layer 170. The encapsulation layer 190 serves to prevent oxygen or water from penetrating the LED layer ED. According to an exemplary embodiment, the encapsulation layer 190 can comprise at least one inorganic film to prevent or minimize the ingress of oxygen or water, and an organic film to cover particles that may occur during the manufacturing process. For example, the encapsulation layer 190 can comprise a first inorganic film, an organic film on top of the first inorganic film, and a second inorganic film on top of the organic film.

[0082] In addition, according to an exemplary embodiment, pixel P can have a black matrix that overlaps with the bank structure BNK and a wavelength conversion layer in the aperture region. The black matrix is ​​located on the encapsulation layer 190 to overlap the bank structure BNK. According to an exemplary embodiment, the wavelength conversion layer has a color filter on the encapsulation layer 190 that overlaps with the aperture region of pixel P to transmit only one wavelength of a specific color of white light from the LED ED. For example, the wavelength conversion layer can transmit only one wavelength of red, green, or blue. The wavelength conversion layer can be omitted if the light-emitting layer EL of the LED ED has a light-emitting layer that emits red, green, and blue light.

[0083] According to an exemplary embodiment, the pixel P can further comprise a barrier film and a light path control layer 180. The barrier film can be attached to the encapsulation layer 190 by means of an adhesive layer. The barrier film prevents the ingress of water or oxygen and can be made of a material with low water permeability. The light path control layer 180 controls the path of incident light. According to an exemplary embodiment, the light path control layer 180 can comprise a plurality of refractive layers. The refractive layers can have different refractive indices. The light path control layer 180 can have a structure in which a high refractive index layer and a low refractive index layer are deposited alternately.The light path control layer 180 according to an exemplary embodiment minimizes a color shift according to a viewing angle by changing a path of incident light.

[0084] The light path control layer 180 according to another exemplary embodiment can be a polarization layer. The polarization layer improves visibility and contrast ratio by converting external light reflected from the thin-film transistor and / or traces provided in the pixel P into circularly polarized light. The operation of the pixel according to an exemplary embodiment is now described below.

[0085] The pixel according to an exemplary embodiment can operate in an initialization period, a sampling period, and a light emission period. For example, a frame of the light-emitting display device can have an initialization period to initialize the second node N2 and the third node N3. The frame can further have a sampling period to store a sampling voltage, corresponding to a characteristic value (or threshold voltage) of the driver transistor Tdr, in the third node N3. The frame can further have a light emission period to store a gate-source voltage of the driver transistor Tdr, containing a data signal and a sampling voltage, in the storage capacitor Cst. The light-emitting diode ED can emit light based on the data stream corresponding to the voltage of the storage capacitor Cst.

[0086] During the initialization period, the initialization control signal fed to the initialization control line ICL has a transistor-on voltage level, the light emission control signal fed to the light emission control line ECL has a transistor-off voltage level, and the scan control signal fed to the scan control line SCL has a transistor-off voltage level. Therefore, the first and second initialization transistors Ti1 and Ti2 can turn on for the initialization period based on the initialization control signal with the transistor-on voltage level, thereby initializing each of them to the initialization voltage by nodes N2 and N3, respectively.

[0087] During the sampling period, the initialization control signal fed to the initialization control line ICL has a transistor-off voltage level, the light emission control signal fed to the light emission control line ECL has a transistor-off voltage level, and the scan control signal fed to the scan control line SCL has a transistor-on voltage level. Therefore, the sampling transistor Ts can switch on for the sampling period based on the scan control signal at the transistor-on voltage level, connecting the second node N2 and the third node N3, and thus the driver transistor Tdr can be configured as a diode. Simultaneously, the data input transistor Tds can switch on based on the scan control signal at the transistor-on voltage level, allowing the data signal fed to the data line DL to be fed to the third node N3.During this sampling period, the potential of the second node N2 can rise due to a current flowing between the first source-drain electrode and the second source-drain electrode of the driver transistor Tdr, driven by the voltage of the third node N3. As such, the potential of the third node N3 can rise until a certain voltage is reached. This voltage is obtained by subtracting the voltage corresponding to the data signal and the characteristic voltage of the driver transistor Tdr from the initialization voltage and a voltage difference between the gate voltage and the source voltage of the driver transistor Tdr, corresponding to the potential of the third node N3 stored in the storage capacitor Cst. The initialization voltage has a voltage level equal to or less than the common voltage source Vss applied to the common electrode layer CE.

[0088] During the light emission period, the initialization control signal supplied to the initialization control line ICL has a transistor-off voltage level, the light emission control signal supplied to the light emission control line ECL has a transistor-on voltage level, and the scan control signal supplied to the scan control line SCL also has a transistor-off voltage level. Therefore, during the light emission period, the first and second light emission control transistors Tec1 and Tec2 can be switched on based on the light emission control signal with the transistor-on voltage level. The pixel driver power source supplied by the pixel driver power line can be applied to the first source-drain electrode of the driver transistor Tdr by the switched-on first light emission control transistor Tec1.Thus, the data stream can be supplied to the LED ED by the switched-on second light emission control transistor Tec2, according to the voltage difference between the gate voltage and the pixel driver voltage of the driver transistor Tdr. During the light emission period, the gate-source voltage Vgs of the driver transistor can be maintained by the storage capacitor Cst at "(Vdata-Vth)-Vdd". The current flowing through the driver transistor Tds is proportional to the square of the value (Vdata-Vdd). 2 a value obtained by a threshold voltage from the source-gate voltage Vsg of the driver transistor Tdr. The current flowing to the LED ED can be determined by the data voltage Vdata according to the data signal, independent of the threshold voltage Vth of the driver transistor Tdr.

[0089] Fig. Figure 5 illustrates a layout of a first circuit layer, which is located in Fig. 4 is shown. Fig. 6 is a cross-sectional view along the line I-I', which is in Fig. 5 is shown. Fig. 7 is a cross-sectional view along line II-II', which is in Fig. 5 is shown. As in Fig. 4, Fig. 5, Fig. 6 to Fig. As illustrated in Figure 7, the first circuit layer 110 of the pixel can have a substrate 10, a first semiconductor layer 11, a first gate insulation layer 13, a light emission control line ECL, a gate electrode GE, a first interlayer dielectric layer 15, a second capacitor electrode Ec2, a first protective layer 17, a first line contact hole Hlc1, a second line contact hole Hlc2, a first structure contact hole Hpc1, a second structure contact hole Hpc2, a fourth structure contact hole Hpc4, a pixel driver power line PL, a first node interconnect structure Pnc1, a second node interconnect structure Pnc2 and a fourth node interconnect structure Pnc4.

[0090] The substrate 10 can have a first light emission control transistor region, a second light emission control transistor region, a driver transistor region, and a capacitor region, all defined within the pixel region. The first semiconductor layer 11 can be located within the pixel region of the substrate 10 such that it extends through the first light emission control transistor region, the second light emission control transistor region, the driver transistor region, and the capacitor region. The first semiconductor layer 11 can be made of polysilicon. For example, the first semiconductor layer 11 in the pixel region of the substrate 10 can be configured as a two-dimensional "U" shape.

[0091] The first semiconductor layer 11 can have a first to third channel region CA1, CA2, and CA3. The first semiconductor layer 11 can further have a first and second lightly doped region LD1 and LD2, which are arranged parallel to each other, with the insertion of the first channel region CA1. The first semiconductor layer 11 can further have a third and fourth lightly doped region LD3 and LD4, which can be arranged parallel to each other, with the insertion of the third channel region CA3. The first semiconductor layer 11 can further have a first heavily doped region HD1 adjacent to the first lightly doped region LD1, and a second heavily doped region HD2, which is arranged between the second channel region CA2.The first semiconductor layer 11 can further comprise the second weakly doped region LD2, a third heavily doped region HD3 formed between the second channel region CA2 and the third weakly doped region LD3, and a fourth heavily doped region HD4 adjacent to the fourth weakly doped region LD4. The first and third channel regions CA1 and CA3 of the semiconductor layer 11 can be parallel to each other, so that it has a two-dimensional “|” shape, and the second channel region CA2 of the first semiconductor layer 11 can be formed between the first and third channel regions CA1 and CA3, so that it has a two-dimensional “U” shape.

[0092] Each of the first to fourth heavily doped regions HD1, HD2, HD3, and HD4 of the first semiconductor layer 11 can be defined as a region with an impurity doping concentration higher than that of each of the first to fourth lightly doped regions LD1, LD2, LD3, and LD4. The first heavily doped region HD1 of the first semiconductor layer 11 can be used as the first source-drain electrode of the first light emission control transistor Tec1. The second heavily doped region HD2 of the first semiconductor layer 11 can be used as the second source-drain electrode of the first light emission control transistor Tec1 and the first source-drain electrode of the driver transistor Tdr, and can be defined as the first node N1 of the first pixel circuit PC1.

[0093] The third heavily doped region HD3 of the first semiconductor layer 11 can be used as the second source-drain electrode of the driver transistor Tdr and the first source-drain electrode of the second light emission control transistor Tec2, and can be defined as the second node N2 of the first pixel circuit PC1. The fourth heavily doped region HD4 of the first semiconductor layer 11 can be used as the second source-drain electrode of the second light emission control transistor Tec2, and can be defined by the fourth node N4 of the first pixel circuit PC1.

[0094] The first gate insulation layer 13 can be formed on the entire substrate 10, covering the first semiconductor layer 11. According to an exemplary embodiment, the first gate insulation layer 13 can be formed from silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer layer of SiOx and SiNx. The light emission control line ECL can be formed on the first gate insulation layer 13, overlapping each of the first and third channel regions CA1 and CA3 of the first semiconductor layer 11, and extending longitudinally along the first direction X. The first region of the light emission control line ECL, which overlaps the first channel region CA1 of the first semiconductor layer 11, can serve as the gate electrode of the first light emission control transistor Tec1.The second region of the light emission control line ECL, which overlaps the third channel region CA3 of the first semiconductor layer 11, can serve as the gate electrode of the second light emission control transistor Tec2. Therefore, it is not necessary to form a separate gate electrode extending from the light emission control line ECL to form the gate electrodes of the light emission control transistors Tec1 and Tec2 in pixel P. Consequently, space can be saved in pixel P for forming the gate electrodes of the light emission control transistors Tec1 and Tec2.

[0095] The first region of the light emission control line ECL, the first channel region CA1 of the first semiconductor layer 11, the first lightly doped region LD1, the second lightly doped region LD2, the first heavily doped region HD1, and the second heavily doped region HD2 form the first light emission control transistor Tec1. The second region of the light emission control line ECL, the third channel region CA3 of the first semiconductor layer 11, the third lightly doped region LD3, the fourth lightly doped region LD4, the third heavily doped region HD3, and the fourth heavily doped region HD4 form the second light emission control transistor Tec2. The gate electrode GE can be arranged in an island configuration on the first gate insulation layer 13 such that it overlaps the second channel region CA2 of the first semiconductor layer 11.The gate electrode GE serves as the gate electrode of the driver transistor Tdr and the first capacitor electrode Ec1 of the storage capacitor Cst, and can be defined as the third node N3 of the first pixel circuit PC1. The gate electrode GE, the second channel region CA2 of the first semiconductor layer 11, the second heavily doped region HD2, and the third heavily doped region HD3 form the driver transistor Tdr.

[0096] The gate electrode GE further features a projection GEa. The projection GEa can extend from a top face of the gate electrode GE, adjacent to the light emission control line ECL, between the second heavily doped region HD2 and the third heavily doped region HD3. The projection GEa can be defined as a contact region between the third node N3 and the second pixel circuit PC2 of the second circuit layer 150 and can be used as the third node connection structure Pnc3. The light emission control line ECL and the gate electrode GE can be formed from a single layer or multiple layers comprising any of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu, or an alloy thereof. The first interlayer dielectric layer 15 can be formed over the entire substrate, covering the light emission control line ECL and the gate electrode GE.The first interlayer dielectric layer 15 according to an exemplary embodiment can be formed from a silicon oxide (SiOx), a silicon nitride (SiNx) or a multilayer layer of SiOx and SiNx.

[0097] The second capacitor electrode Ec2 can be located on the first interlayer dielectric layer 15, such that it overlaps the gate electrode GE of the driver transistor Tdr. According to an exemplary embodiment, the second capacitor electrode Ec2 can be formed from a single layer or multiple layers comprising any of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or an alloy thereof, or it can be formed from the same material as the gate electrode. The storage capacitor Cst is formed in an overlap region between the second capacitor electrode Ec2 and the gate electrode GE of the driver transistor Tdr. The first protective layer 17 can be formed over the entire substrate, covering the second capacitor electrode Ec2 and the first interlayer dielectric layer 15. The first protective layer 17 can be formed from silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer of SiOx and SiNx.

[0098] The first conduction contact hole Hlc1 exposes the first source-drain electrode of the first light emission control transistor Tec1, that is, the first heavily doped region HD1 of the first semiconductor layer 11. The first conduction contact hole Hlc1 can pass through the first gate insulation layer 13, the first interlayer dielectric layer 15, and the first protective layer 17. Each of these layers can be located on the first heavily doped region HD1 of the first semiconductor layer 11, thus partially exposing the first heavily doped region HD1 of the first semiconductor layer 11. The second conduction contact hole Hlc2 can be parallel to the first conduction contact hole Hlc1 based on the second direction Y and can partially expose the second capacitor electrode Ec2.The second conductor contact hole Hlc2 according to an exemplary embodiment can be designed such that it passes through the first protective layer 17 at a side corner of the second capacitor electrode Ec2, thereby exposing a side corner of the second capacitor electrode Ec2.

[0099] The first structural contact hole Hpc1 exposes the second source-drain electrode (or the first source-drain electrode of the driver transistor Tdr) of the first light emission control transistor Tec1, that is, the second heavily doped region HD2 (or the first node N1) of the first semiconductor layer 11. The first structural contact hole Hpc1 can pass through the first gate insulation layer 13, the first interlayer dielectric layer 15, and the first protective layer 17, which are located on the second heavily doped region HD2 of the first semiconductor layer 11, thereby partially exposing the second heavily doped region HD2 of the first semiconductor layer 11.

[0100] The second structural contact hole Hpc2 exposes the first source-drain electrode (or the second source-drain electrode of the driver transistor Tdr) of the second light emission control transistor Tec2, that is, the third heavily doped region HD3 (or the second node N2) of the first semiconductor layer 11. The second structural contact hole Hpc2 can pass through the first gate insulation layer 13, the first interlayer dielectric layer 15, and the first protective layer 17. These layers can be located on the third heavily doped region HD3 of the first semiconductor layer 11, thus partially exposing the third heavily doped region HD3 of the first semiconductor layer 11.

[0101] The fourth structural contact hole Hpc4 exposes the second source-drain electrode of the second light emission control transistor Tec2, that is, the fourth heavily doped region HD4 (or the fourth node N4) of the first semiconductor layer 11. According to an exemplary embodiment, the fourth structural contact hole Hpc4 can pass through the first gate insulation layer 13, the first interlayer dielectric layer 15, and the first protective layer 17. These layers can be located on the fourth heavily doped region HD4 of the first semiconductor layer 11, thus partially exposing the fourth heavily doped region HD4 of the first semiconductor layer 11.

[0102] The pixel driver power line PL can be formed on the first protective layer 17 along the second direction Y, passing through the first power contact hole Hlx1 and the second power contact hole Hlc2. The pixel driver power line PL can be electrically connected through the first power contact hole Hlc1 to the first heavily doped region HD1 of the first semiconductor layer 11 and thus electrically connected to the first source-drain electrode of the first light emission control transistor Tec1. The pixel driver power line PL can be electrically connected through the second power contact hole Hlc2 to a portion of a side corner of the second capacitor electrode Ec2. The pixel driver power line PL can further comprise a horizontal projection PLh extending along the first direction X from a lower region of the pixel P.The horizontal projection line PLh can be designed so that it is shared by two pixels P that are adjacent in the first direction X.

[0103] The first node connection structure Pnc1 can be configured in an island shape on the first protective layer 17 such that it overlaps the first structural contact hole Hpc1. The first node connection structure Pnc2 can be electrically connected through the first structural contact hole Hpc1 to the second heavily doped region HD2 of the first semiconductor layer 11 and thus electrically connected to the first node N1. That is, the first node connection structure Pnc1 can be electrically connected to each of the second source-drain electrodes of the first light emission control transistor Tec1 and the first source-drain electrode of the driver transistor Tdr. The second node connection structure Pnc2 can be configured in an island shape on the first protective layer 17 such that it overlaps the second structural contact hole Hpc2.The second node connection structure Pnc2 can be electrically connected to the third heavily doped region HD3 of the first semiconductor layer 11 via the second structure contact hole Hpc2, and thus electrically connected to the second node N2. That is, the second node connection structure Pnc2 can be electrically connected to either the second source-drain electrode of the driver transistor Tdr or the first source-drain electrode of the second light emission control transistor Tec2.

[0104] The fourth node interconnect Pnc4 can be configured in an island shape on the first protective layer 17 such that it overlaps the fourth structural contact hole Hpc4. The fourth node interconnect Pnc4 can be electrically connected via the fourth structural contact hole Hpc4 to the fourth heavily doped region HD4 of the first semiconductor layer 11 and thus electrically connected to the fourth node N4. That is, the fourth node interconnect Pnc4 can be electrically connected to each of the second source-drain electrodes of the second light emission control transistor Tec2. Each of the pixel driver power lines PL, the first node interconnect Pnc1, the second node interconnect Pnc2, and the fourth node interconnect Pnc4 can be formed from a single layer. The single layer can consist of any of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu, and / or their alloy(s).Alternatively, the single layer can be formed from a multilayer structure, such as a deposition structure (Ti / Al / Ti) of A1 and Ti, a deposition structure (ITO / Al / ITO) of A1 and ITO, an APC (Ag / Pd / Cu) alloy, and a deposition structure (ITO / APC / ITO) of an APC alloy and ITO.

[0105] The first circuit layer 110 is covered by the circuit insulation layer 130. According to one exemplary embodiment, the circuit insulation layer 130 can be formed from silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer layer of SiOx and SiNx. According to another exemplary embodiment, the circuit insulation layer 130 can be formed from an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0106] Fig. 8 represents a layout of a in Fig. 4 shows the second circuit layer. Fig. 9 is a cross-sectional view along the in Fig. 8 shown line III-III'. Fig. 10 is a cross-sectional view along the in Fig. 8 shown line IV-IV'. Fig. 1 is a cross-sectional view along the in Fig. 8 shown line V-V'. The second circuit layer 150 of the pixel can have a second semiconductor layer 31, a third semiconductor layer 41, a second gate insulation layer 33, an initialization control line ICL, a scan control line SCL, a second interlayer dielectric layer 35, a first to fourth electrode contact hole Hec1, Hec2, Hec3 and Hec4, a first to fourth node contact hole Hnc1, Hnc2, Hnc3 and Hnc4, a first to fourth circuit connector Cc1 to Cc4, a second protection layer 37, a third line contact hole Hlc3, a fourth line contact hole Hlc4, a data line DL and an initialization voltage line IVL.

[0107] The second circuit layer 150 can include a data input transistor region, a sampling transistor region, and a first initialization transistor and a second initialization transistor region, which are defined on the circuit insulation layer 130. The second semiconductor layer 31 is located in the data input transistor region defined on the circuit insulation layer 130. The second semiconductor layer 31 can be made of polysilicon. For example, the second semiconductor layer 31 can be located in the data input transistor region of the second circuit layer 130 such that it has a two-dimensional “┘” shape.The second semiconductor layer 31 can have a channel region CA, a first and second lightly doped region LD1 and LD2, which are arranged parallel to each other, with the channel region CA being inserted, a first heavily doped region HD1 adjacent to the first lightly doped region LD1, and a second heavily doped region HD2 adjacent to the second lightly doped region LD2. The third semiconductor layer 41 can be located on the circuit insulation layer 130 such that it passes through the sampling transistor region, the first initialization transistor region, and the second initialization transistor region. The third semiconductor layer 41 can be made of polysilicon. For example, the third semiconductor layer 41 can be located on the circuit insulation layer 130 and can have a two-dimensional "C" shape.

[0108] The third semiconductor layer 41 can have a first to fourth channel region CA1, CA2, CA3 and C4, a first and second lightly doped region LD1 and LD2, which are formed parallel to each other with the insertion of the first channel region CA1, a third and fourth lightly doped region LD3 and LD4, which are formed parallel to each other with the insertion of the second channel region CA2, a fifth and sixth lightly doped region LD5 and LD6, which are formed parallel to each other with the insertion of the third channel region CA3, a seventh and eighth lightly doped region LD7 and LD8, which are formed parallel to each other with the insertion of the fourth channel region CA4.The third semiconductor layer 41 can further comprise a first heavily doped region HD1 adjacent to the first lightly doped region LD1, a second heavily doped region HD2 formed between the second lightly doped region LD2 and the third lightly doped region LD3, a third heavily doped region HD3 formed between the fourth lightly doped region LD4 and the fifth lightly doped region LD5, a fourth heavily doped region HD4 formed between the sixth lightly doped region LD6 and the seventh lightly doped region LD7, and a fifth heavily doped region HD5 adjacent to the eighth lightly doped region LD8.

[0109] The channel region CA of the second semiconductor layer 31 and each of the first and second channel regions CA1 and CA2 of the third semiconductor layer 41 can be arranged parallel to each other and have a two-dimensional "|" shape. The third and fourth channel regions CA3 and CA4 of the third semiconductor layer 41 are also arranged parallel to each other and have a two-dimensional "|" shape. Each of the first and second heavily doped regions HD1 and HD2 of the second semiconductor layer 31 and each of the first to fifth heavily doped regions HD1 to HD5 of the third semiconductor layer can be defined as regions having an impurity doping concentration higher than that of each of the first to eighth lightly doped regions LD1 to LD8. The first heavily doped region HD1 of the second semiconductor layer 31 can be used as the first source-drain electrode of the data input transistor Tds.The second heavily doped region HD2 of the second semiconductor layer 31 can be used as the second source-drain electrode of the data input transistor Tds and can be defined as the first node N1' of the second pixel circuit PC2.

[0110] The first heavily doped region HD1 of the third semiconductor layer 41 can be used as the second source-drain electrode of the second sampling transistor Ts2 and can be defined as the second node N2' of the second pixel circuit PC2. The third heavily doped region HD3 of the third semiconductor layer 41 can be used as the first source-drain electrode of the first sampling transistor Ts1 and can be defined as the third node N3' of the second pixel circuit PC2. The fifth heavily doped region HD5 of the third semiconductor layer 41 can be used as the second source-drain electrode of the second initialization transistor Ti2 and can be defined as the fourth node N4' of the second pixel circuit PC2. The second gate insulation layer 33 can be formed on the entire circuit insulation layer 130 such that it covers the second and third semiconductor layers 31 and 41.The second gate insulation layer 33 according to an exemplary embodiment can be formed from a silicon oxide (SiOx), a silicon nitride (SiNx) or a multilayer layer of SiOx and SiNx.

[0111] The initialization control line ICL can be located on the second gate insulation layer 33 such that it overlaps each of the third and fourth channel regions CA3 and C4 of the third semiconductor layer 41, and extends longitudinally along the first direction X. The first region of the initialization control line ICL, which overlaps with the fourth channel region CA4 of the third semiconductor layer 41, can serve as the gate electrode of the second initialization transistor Ti2. The second region of the initialization control line ICL, which overlaps with the third channel region CA3 of the third semiconductor layer 41, can serve as the gate electrode of the first initialization transistor Ti1. Therefore, it is not necessary to form a separate gate electrode projecting from the initialization control line ICL to form the gate electrodes of the initialization transistors Ti1 and Ti2 in pixel P.For this reason, space can be saved in pixel P for forming the gate electrode of the initialization transistors Ti1 and Ti2.

[0112] The first region of the initialization control line ICL, the fourth channel region CA4 of the third semiconductor layer 41, the seventh lightly doped region LD7, the eighth lightly doped region LD8, the fourth heavily doped region HD4, and the fifth heavily doped region HD5 form the second initialization transistor Ti2. The second region of the initialization control line ICL, the third channel region CA3 of the third semiconductor layer 41, the fifth lightly doped region LD5, the sixth lightly doped region LD6, the third heavily doped region HD3, and the fourth heavily doped region HD4 form the first initialization transistor Ti1.

[0113] The scan control line SCL can be located on the second gate insulation layer 33 such that it overlaps each of the first and second channel regions CA1 and CA2 of the third semiconductor layer 41, and extends longitudinally along the first direction X parallel to the initialization control line ICL. The first region of the scan control line SCL, which overlaps with the first channel region CA4 of the third semiconductor layer 41, can serve as the gate electrode of the second scanning transistor Ts2. The second region of the scan control line SCL, which overlaps with the second channel region CA2 of the third semiconductor layer 41, can serve as the gate electrode of the first scanning transistor Ts1. Therefore, it may not be necessary to form a separate gate electrode projecting from the scan control line to form the gate electrodes of the scanning transistors Ts1 and Ts2 in the pixel.For this reason, space can be saved in pixel P for forming the gate electrode of the sampling transistors Ts1 and Ts2.

[0114] The first region of the scan control line SCL, the first channel region CA1 of the third semiconductor layer 41, the first lightly doped region LD1, the second lightly doped region LD2, the first heavily doped region HD1, and the second heavily doped region HD2 form the second scanning transistor Ts2. The second region of the scan control line SCL, the second channel region CA2 of the third semiconductor layer 41, the third lightly doped region LD3, the fourth lightly doped region LD4, the second heavily doped region HD2, and the third heavily doped region HD3 form the first scanning transistor Ts1. Therefore, the first and second scanning transistors Ts1 and Ts2 are connected in series, forming a dual-channel structure. The initialization control line ICL and the scan control line SCL can be formed from a single layer or multiple layers comprising any of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu, or an alloy thereof.

[0115] The second interlayer dielectric layer 35 can be formed over the entire substrate such that it covers the initialization control line ICL and the scan control line SCL. According to an exemplary embodiment, the second interlayer dielectric layer 35 can be formed from silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer of SiOx and SiNx. The first electrode contact hole Hec1 exposes the second source-drain electrode of the data input transistor Tds, i.e., the second heavily doped region HD2 of the second semiconductor layer 31.The first electrode contact hole Hec1 according to an exemplary embodiment can be configured to pass through the second gate insulation layer 33 and the second intermediate insulation layer 35, which are located on the second heavily doped region HD2 of the second semiconductor layer 31, thereby partially exposing the second heavily doped region HD2 of the second semiconductor layer 31. Therefore, the first node N1' of the second pixel circuit PC2 is exposed through the first electrode contact hole Hec1.

[0116] The second electrode contact hole Hec2 exposes the second source-drain electrode of the second sampling transistor Ts2, i.e., the first heavily doped region HD1 of the third semiconductor layer 41. According to an exemplary embodiment, the second electrode contact hole Hec2 can pass through the second gate insulating layer 33 and the second interlayer dielectric layer 35, which are located on the first heavily doped region HD1 of the third semiconductor layer 41, thereby partially exposing the first heavily doped region HD1 of the third semiconductor layer 41. Therefore, the second node N2' of the second pixel circuit PC2 is exposed through the second electrode contact hole Hec2.

[0117] The third electrode contact hole Hec2 exposes the second source-drain electrode of the first sampling transistor Ts1, i.e., the third heavily doped region HD3 of the third semiconductor layer 41. According to an exemplary embodiment, the third electrode contact hole Hec3 can pass through the second gate insulating layer 33 and the second interlayer dielectric layer 35, which are located on the third heavily doped region HD3 of the third semiconductor layer 41, thereby partially exposing the third heavily doped region HD3 of the third semiconductor layer 41. Therefore, the third node N3' of the second pixel circuit PC2 is exposed through the third electrode contact hole Hec3.

[0118] The fourth electrode contact hole Hec4 exposes the second source-drain electrode of the second initialization transistor Ti2, i.e., the fifth heavily doped region HD5 of the third semiconductor layer 41. According to an exemplary embodiment, the fourth electrode contact hole Hec4 can pass through the second gate insulating layer 33 and the second intermediate insulating layer 35, which are located on the fifth heavily doped region HD5 of the third semiconductor layer 41, thereby partially exposing the fifth heavily doped region HD5 of the third semiconductor layer 41. Therefore, the fourth node N4' of the second pixel circuit PC2 can be exposed through the fourth electrode contact hole Hec4.

[0119] The first node contact hole Hnc1 lays, as in Fig. Figure 12 shows that the first node connection structure Pnc1 in the first circuit layer 110 is partially exposed. According to an exemplary embodiment, the first node contact hole Hnc1 can pass through the second interlayer dielectric layer 35, the second gate insulation layer 33, and the circuit insulation layer 130, which are located on the first node connection structure Pnc1, thereby partially exposing the first node connection structure Pnc1. Therefore, the first node connection structure Pnc1, which is connected to the first node N1 of the first pixel circuit PC1, is exposed through the first node contact hole Hnc1.

[0120] The second node contact hole Hnc2, as in Fig. Figure 13 shows that the second node connection structure Pnc2 in the first circuit layer 110 is partially exposed. According to an exemplary embodiment, the second node contact hole Hnc2 can pass through the second intermediate layer insulation layer 35, the second gate insulation layer 33, and the circuit insulation layer 130, which are located on the second node connection structure Pnc2, thereby partially exposing the second node connection structure Pnc2. Therefore, the second node connection structure Pnc2, which is connected to the second node N2 of the first pixel circuit PC1, is exposed through the second node contact hole Hnc2.

[0121] The third node contact hole Hnc3, as in Fig. Figure 14 shows that the protruding electrode GEa (or the third node connection structure) in the first circuit layer 110, which projects from the gate electrode of the driver transistor Tdr, is partially exposed. The first node contact hole Hnc1 can pass through the second interlayer dielectric layer 35, the second gate insulating layer 33, the circuit insulating layer 130, the first protective layer 17, and the first interlayer dielectric layer 15. These layers may be on top of the third node connection structure Pnc3, thus partially exposing the third node connection structure Pnc3. Therefore, the third node connection structure Pnc3, which is connected to the third node N3 of the first pixel circuit PC1, is exposed through the third node contact hole Hnc3.

[0122] The fourth node contact hole Hnc4, as in Fig. Figure 15 shows that the fourth node connection structure Pnc4 in the first circuit layer 110 is partially exposed. According to an exemplary embodiment, the fourth node contact hole Hnc4 can pass through the second intermediate layer insulation layer 35, the second gate insulation layer 33, and the circuit insulation layer 130, which are located on the fourth node connection structure Pnc4, thereby partially exposing the fourth node connection structure Pnc4. Therefore, the fourth node connection structure Pnc4, which is connected to the fourth node N4 of the first pixel circuit PC1, is exposed through the fourth node contact hole Hnc4.

[0123] As in Fig. 4, Fig. 8 and Fig. As shown in Figure 12, the first circuit connector Cc1 electrically connects the first node N1 formed in the first circuit layer 110 with the first node N1' formed in the second circuit layer 150. According to an exemplary embodiment, the first circuit connector Cc1 can be formed in an island shape on the second interlayer dielectric layer 35 such that it overlaps each of the first electrode contact hole Hec1 and the first node contact hole Hnc1, thus electrically connecting the first node N1 of the first circuit layer 110 with the first node N1' of the second circuit layer 150.One side of the first circuit connector Cc1 can be electrically connected to the first node N1' of the second circuit layer 150 via the first electrode contact hole Hec1, and thus electrically connected to the second source-drain electrode of the data input transistor Tds via the first node N1' of the second circuit layer 150. The other side of the first circuit connector Cc1 can be electrically connected to the first node connection structure Pnc1 of the first circuit layer 110 via the first node contact hole Hnc1, and thus electrically connected to the first node N1 of the first circuit layer 110 via the first node connection structure Pnc1.

[0124] As in Fig. 4, Fig. 8 and Fig. As shown in Figure 13, the second circuit connector Cc2 electrically connects the second node N2 formed in the first circuit layer 110 with the second node N2' formed in the second circuit layer 150. According to an exemplary embodiment, the second circuit connector Cc2 can be formed in an island shape on the second interlayer dielectric layer 35 such that it overlaps each of the second electrode contact hole Hec2 and the second node contact hole Hnc2, thus electrically connecting the second node N2 of the first circuit layer 110 with the second node N2' of the second circuit layer 150.One side of the second circuit connector Cc2 can be electrically connected to the second node N2' of the second circuit layer 150 via the second electrode contact hole Hec2, thus electrically connecting the second source-drain electrode of the second sampling transistor Ts2 via the second node N2' of the second circuit layer. The other side of the second circuit connector Cc2 can be electrically connected to the second node connection structure Pnc2 of the first circuit layer 110 via the second node contact hole Hnc2, thus electrically connecting to the second node N2 of the first circuit layer 110 via the second node connection structure Pnc2.

[0125] As in Fig. 4, Fig. 8 and Fig. As shown in Figure 14, the third circuit connector Cc3 electrically connects the third node N3 formed in the first circuit layer 110 with the third node N3' formed in the second circuit layer 150. According to an exemplary embodiment, the third circuit connector Cc3 can be formed in an island shape on the second interlayer dielectric layer 35 such that it overlaps each of the third electrode contact hole Hec3 and the third node contact hole Hnc3, thus electrically connecting the third node N3 of the first circuit layer 110 with the third node N3' of the second circuit layer 150.One side of the third circuit connector Cc3 can be electrically connected to the third node N3' of the second circuit layer 150 via the third electrode contact hole Hec3, and thus electrically connected to the second source-drain electrode of the first sampling transistor Ts1 via the third node N3' of the second circuit layer 150. The other side of the third circuit connector Cc3 can be electrically connected to the third node connection structure Pnc3 of the first circuit layer 110 via the third node contact hole Hnc3, and thus electrically connected to the third node N3 of the first circuit layer 110. That is, the other side of the third circuit connector Cc3 can be electrically connected to the gate electrode of the driver transistor Tdr via the third node connection structure Pnc3.

[0126] As in Fig. 4, Fig. 8 and Fig. As shown in Figure 15, the fourth circuit connector Cc4 electrically connects the fourth node N4 formed in the first circuit layer 110 with the fourth node N4' formed in the second circuit layer 150. According to an exemplary embodiment, the fourth circuit connector Cc4 can be formed in an island shape on the second interlayer dielectric layer 35 such that it overlaps each of the fourth electrode contact hole Hec4 and the fourth node contact hole Hnc4, thus electrically connecting the fourth node N4 of the first circuit layer 110 with the fourth node N4' of the second circuit layer 150.One side of the fourth circuit connector Cc4 can be electrically connected to the fourth node N4' of the second circuit layer 150 via the fourth electrode contact hole Hec4, and thus electrically connected to the second source-drain electrode of the second initialization transistor Ti2 via the fourth node N4' of the second circuit layer 150. The other side of the fourth circuit connector Cc4 can be electrically connected to the fourth node connection structure Pnc4 of the first circuit layer 110 via the fourth node contact hole Hnc4, and thus electrically connected to the fourth node N4 of the first circuit layer 110 via the fourth node connection structure Pnc4.

[0127] The first to fourth interconnects Cc1, Cc2, Cc3, and Cc4 according to an exemplary embodiment can be formed from a single layer or a multilayer layer comprising any of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu, or an alloy thereof. The first to fourth interconnects Cc1, Cc2, Cc3, and Cc4 can be compactly positioned side-by-side between the initialization control line ICL and the scan control line SCL in pixel P to minimize interference with the transistors. In particular, the first to fourth interconnects Cc1, Cc2, Cc3, and Cc4 can electrically connect the first circuit layer 110 to the second circuit layer 150 without increasing the size of pixel P.

[0128] As in Fig. 8, Fig. 9, Fig. 10 to Fig. 11 and again Fig.As shown in Figure 4, the second protective layer 37 can be formed on the circuit insulation layer 130 such that it covers the first to fourth circuit connectors Cc1, Cc2, Cc3, and Cc4 and the second interlayer dielectric layer 35. The second protective layer 37 can be formed from silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer layer of SiOx and SiNx. The third conduction contact hole Hlc3 exposes the first source-drain electrode of the data input transistor Tds, that is, a portion of the first heavily doped region HD1 of the second semiconductor layer 31. According to an exemplary embodiment, the third conduction contact hole Hlc3 can pass through the second gate insulation layer 33, the second interlayer dielectric layer 35, and the second protective layer 37.These layers can be on the first heavily doped region HD1 of the second semiconductor layer 31, thereby exposing the first heavily doped region HD1 of the second semiconductor layer 31.

[0129] The fourth line contact hole Hlc4 exposes the first source-drain electrode of the first initialization control transistor Ti1, that is, a portion of the fourth heavily doped region HD4 of the third semiconductor layer 41. According to an exemplary embodiment, the fourth line contact hole Hlc4 can be configured to pass through the second gate insulation layer 33, the second interlayer dielectric layer 35, and the second protection layer 37. These layers can be located on the fourth heavily doped region HD4 of the third semiconductor layer 41, thus partially exposing the fourth heavily doped region HD4 of the third semiconductor layer 41. The data line DL can be configured on the second protection layer 37 along the second direction Y such that it passes through the third line contact hole Hlc3.The data line DL can be electrically connected to the first heavily doped region HD1 of the second semiconductor layer 31 through the third line contact hole Hlc3, and thus be electrically connected to the first source-drain electrode of the data input transistor Tds.

[0130] The initialization voltage line IVL can be configured on the second protection layer 37 along the second direction Y such that it passes through the fourth line contact hole Hlc3 and is parallel to the data line DL. The initialization voltage line IVL can be located between the third and fourth channel regions CA3 and CA4 of the third semiconductor layer 41, which are configured parallel to each other. The initialization voltage line ICL can be electrically connected to the fourth heavily doped region HD4 of the third semiconductor layer 41 through the fourth line contact hole Hlc4, thus supplying an initialization voltage to the first source-drain electrodes of the first and second initialization transistors Ti1 and Ti2.

[0131] Each of the data line DL and the initialization voltage line IVL can be formed from a single layer made of any of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu and / or their alloy(s). Alternatively, the single layer can be formed from a multilayer structure such as a deposition structure (Ti / Al / Ti) of Al and Ti, a deposition structure (ITO / Al / ITO) of Al and ITO, an APC (Ag / Pd / Cu) alloy, and / or a deposition structure (ITO / APC / ITO) of an APC alloy and ITO. In an exemplary embodiment, since the pixel circuit of pixel P is divided into the first circuit layer 110 and the second circuit layer 130, such that the first circuit layer 110 and the second circuit layer 130 are deposited on the pixel area, the pixel circuit can be sufficiently arranged in the pixel P, even if the size of pixel P may be reduced due to high resolution.In this exemplary embodiment, the high-resolution light-emitting display device can be implemented. All or some of the transistors can be modified to the N-type within the scope that does not deviate from the technical features of the present invention, which achieves ultra-high-resolution pixels by depositing two or more circuit layers, without being limited to the P-type. The light-emitting display device can be used in portable electronic devices such as a smartphone requiring high resolution, a mobile communication device, a mobile phone, a tablet PC (personal computer), a smartwatch, a watch phone, a wearable device, a television, a notebook computer, a monitor, a refrigerator, a virtual image display device, or a head-mounted display device.

Claims

[1] Light-emitting display device comprising: a substrate (10); and a plurality of pixels (P) arranged in a pixel region of the substrate (10), each of the plurality of pixels (P) having: a first circuit layer (110) comprising a first pixel circuit (PC1) comprising a driver transistor (Tdr); a second circuit layer (150) overlapping the first circuit layer (110), wherein the second circuit layer (150) has a second pixel circuit (PC2) having a data input transistor (Tds) configured to supply a data signal to the first pixel circuit (PC1); a circuit insulation layer (130) between the first circuit layer (110) and the second circuit layer (150); and a light-emitting diode layer (170) comprising a light-emitting diode (ED) electrically connected to the first pixel circuit (PC1), wherein the first pixel circuit (PC1) is configured to supply a data stream corresponding to a gate-source voltage of the driver transistor (Tdr) to the light-emitting diode (ED) based on the data signal supplied by the second pixel circuit (PC2), wherein the driver transistor (Tdr) has a first source-drain electrode connected to a first node (N1), a second source-drain electrode connected to a second node (N2) and a gate electrode connected to a third node (N3), the first pixel circuit (PC1) has: a first light emission control transistor (Tec1) which is configured to switch on based on a light emission control signal, wherein the first light emission control transistor (Tec1) is configured to supply a pixel driver voltage to the first node (N1); a second light emission control transistor (Tec2) which is configured to switch on based on the light emission control signal, thereby forming a current path between the second node (N2) and a fourth node (N4); and a storage capacitor (Cst) having a first capacitor electrode (Ec1) corresponding to the gate electrode of the driver transistor (Tdr) and a second capacitor electrode (Ec2) overlapping the first capacitor electrode (Ec1), wherein the second capacitor electrode (Ec2) is configured to receive the pixel driver voltage, where the light-emitting diode (ED) is electrically connected to the fourth node (N4), the first circuit layer (110) has: a light emission control line (ECL) that is configured to supply the light emission control signal to the first pixel circuit (PC1); a pixel driver power line (PL) that is configured to supply the pixel driver voltage to the first pixel circuit (PC1); a first line contact hole (Hlc1) that electrically connects the pixel driver power line (PL) to a first source-drain electrode of the first light emission control transistor (Tec1); and a second conductor contact hole (Hlc2) that electrically connects the pixel driver power line (PL) to the second capacitor electrode (Ec2). [2] Light-emitting display device according to claim 1, wherein the first circuit layer (110) is between the substrate (10) and the circuit insulation layer (130). [3] Light-emitting display device according to claim 1 or 2, wherein the second circuit layer (150) further comprises a plurality of circuit connectors (Cc1, ..., Cc4) configured to electrically connect the second pixel circuit (PC2) to the first pixel circuit (PC1) through the circuit insulation layer (130). [4] Light-emitting display device according to any one of claims 1 to 3, wherein the second pixel circuit (PC2) further comprises: the data input transistor (Tds) which is set up to switch on based on a scan control signal, thereby supplying the data signal to the first node (N1); a sampling transistor (Ts) which is configured to switch on based on the scan control signal, thereby electrically connecting the second node (N2) to the third node (N3); a first initialization transistor (Ti1) which is configured to switch on based on an initialization control signal, thereby supplying an initialization voltage to the third node (N3); and a second initialization transistor (Ti2) which is configured to switch on based on the initialization control signal, thereby supplying the initialization voltage to the fourth node (N4). [5] Light-emitting display device according to claim 4, wherein the scanning transistor (Ts) comprises a first and a second scanning transistor (Ts1, Ts2) connected in series between the second node (N2) and the third node (N3). [6] Light-emitting display device according to claim 4 or 5, wherein the second circuit layer (150) further comprises: a data line (DL) that is set up to supply the data signal to the second pixel circuit (PC2); a scan control line (SCL) which is set up to supply the scan control signal to the second pixel circuit (PC2); an initialization control line (ICL) that is set up to supply the initialization control signal to the second pixel circuit (PC2); an initialization voltage line (IVL) that is set up to supply the initialization voltage to the second pixel circuit (PC2); a third line contact hole (Hlc3) that electrically connects the data line (DL) to a first source-drain electrode of the data input transistor (Tds); and a fourth line contact hole (Hlc4) that electrically connects the initialization voltage line (IVL) to a first source-drain electrode of the first initialization transistor (Ti1) and a first source-drain electrode of the second initialization transistor (Ti2). [7] Light-emitting display device according to one of claims 1 to 2, wherein the first circuit layer (110) further comprises: a first node connection structure (Pnc1) that is electrically connected to the first node (N1); a second node connection structure (Pnc2) that is electrically connected to the second node (N2); a third node connection structure (Pnc3) that is electrically connected to the third node (N3); and a fourth node connection structure (Pnc4) that is electrically connected to the fourth node (N4), wherein each of the first to fourth node connection structure (Pnc1, ..., Pnc4) is electrically connected to the second pixel circuit (PC2). [8] Light-emitting display device according to claim 7, wherein the second circuit layer (150) further comprises: a first, second, third and fourth circuit connector (Cc1, ..., Cc4) which are electrically connected to each of the first to fourth node connection structure (Pnc1, ..., Pnc4) accordingly; to turn on the data input transistor (Tds), which is configured to be based on a scan control signal supplied to a scan control line (SCL), and thereby supply the data signal supplied by a data line (DL) to the first circuit connector (Cc1); a sampling transistor (Ts) which is configured to switch on based on the scan control signal, thereby electrically connecting the second circuit connector (Cc2) to the third circuit connector (Cc3); a first initialization transistor (Ti1) configured to switch on based on an initialization control signal supplied to an initialization control line (ICL), thereby supplying an initialization voltage supplied by an initialization voltage line (IVL) to the third circuit connector (Cc3); and a second initialization transistor (Ti2) which is configured to switch on based on the initialization control signal, thereby supplying the initialization voltage to the fourth circuit connector (Cc4). [9] Light-emitting display device according to claim 8, wherein the initialization control line (ICL) and the scan control line (SCL) are parallel to each other and the first to fourth circuit connectors (Cc1, ..., Cc4) are between the initialization control line (ICL) and the scan control line (SCL). [10] Light-emitting display device according to any one of claims 1 to 9, further comprising: a planarization layer (160) covering the second circuit layer (150); and an encapsulation layer (190) covering the light-emitting diode layer (170), the light-emitting diode (ED) features: a pixel driver electrode (AE) that is electrically connected to the first pixel circuit (PC1); a light emission layer (EL) on the pixel driver electrode (AE); and a cathode electrode (CE) that is electrically connected to the light emission layer (EL).

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