Parallel processing of noisy packets in Bluetooth and Bluetooth Low Energy systems

Abstract

A method comprising: simultaneous demodulation (302) of a modulated signal in a first demodulator (204) and a second demodulator (220); simultaneous dem-whitening (304) of a first demodulated signal from the first demodulator circuit (204) and a second demodulated signal from the second demodulator circuit (220); simultaneous performance (306) of a cyclic redundancy code (CRC) check (208, 224) on each of the first demodulated signal being de-whitened and the second demodulated signal being de-whitened; selection (310) of a first packet contained in the first demodulated signal being de-whitened for further processing if the first demodulated signal being de-whitened passes the CRC check (308);Selecting (314) a second packet contained in the second demodulated signal undergoing de-whitening for further processing if the second demodulated signal undergoing de-whitening passes the CRC check (312) and the first demodulated signal undergoing de-whitening fails the CRC check, wherein the first and second demodulator circuits (204, 220) include Bluetooth demodulator circuits, characterized in that the second demodulator circuit (220) is configured to operate in a phase range and to use a maximum likelihood sequence estimation (MLSE) to demodulate the modulated signal.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] This application claims the benefit of the priority pursuant to 35 USC 119(e) of the provisional US patent application Ser. No. 62 / 742,012, filed on October 5, 2018, which is incorporated herein by reference in its entirety. AREA OF INVENTION

[0002] This disclosure relates generally to communication systems and in particular to Bluetooth systems and methods for the parallel processing of received signals to improve signal sensitivity. STATE OF THE ART

[0003] In recent years, Bluetooth technology has expanded from a standard feature in mobile phones and personal computers to a wide range of applications, including IoT (Internet of Things) systems and devices such as wireless speakers and headphones, cars, wearables, and medical devices. When used in devices and systems that need to wirelessly transmit short bursts of data over short distances, Bluetooth (BT) and Bluetooth Low Energy (BLE) are unsurpassed.

[0004] One problem for conventional Bluetooth systems that use Gaussian Frequency-Shift Keying (GFSK) modulation is that a test specification written by the Bluetooth Special Interest Group™ requires any Bluetooth receiver to be able to receive noisy packets (noisy transmitter or noisy Tx), as specified in either a BT or a BLE test specification. In short, and as specified in the BT / BLE test specifications, in noisy packets, the modulation index changes constantly and rapidly from one noisy packet to the next over time. At a BT Basic Data Rate (BDR), the modulation index of noisy packets jumps every 20 ms or 16Packets up / down. In Bluetooth Low Energy (BLE), the modulation index of noisy packets jumps up / down every 50 packets. In addition to modulation index changes, a carrier frequency offset and a symbol timing error are also introduced into the profile of the noisy transmitter to create non-ideal noisy signals used in the test, which are within the specification limits but deviate from the ideal case.

[0005] One possible solution is to use a GFSK demodulator configured to employ an MLSE algorithm (Maximum Likelihood Sequence Estimation), which can provide improved receive sensitivity. The drawback of a GFSK demodulator using MLSE is that it requires a very accurate modulation index estimation, typically within ±2%, to achieve a sensitivity improvement compared to a conventional, non-MLSE demodulator. The test specification does not impose a strict requirement on the GFSK modulation index from the transmitter side. For BDRs, the required modulation index range is from 0.28 to 0.35. For BLE systems, the required modulation index range is from 0.45 to 0.55. Therefore, the MLSE demodulator requires a circuit for estimating the modulation index.However, due to the short length of the training sequence, especially near the receiver's sensitivity threshold, the per-packet estimates of the modulation index are not accurate. Furthermore, as noted above, the modulation index changes constantly and rapidly over time with noisy packets or an unclean transmission. Therefore, in cases where its increased sensitivity is most needed—i.e., with noisy packets—MLSE achieves results that are less accurate than those of conventional, non-MLSE-capable demodulators.

[0006] Accordingly, there is a need for a communication system and a method for operating it in order to improve receiver sensitivity that is not limited by the need for an accurate estimation of the modulation index. OVERVIEW

[0007] A communication system and a method for operating it are provided for the parallel processing of received signals in order to improve the sensitivity of the system.

[0008] In one embodiment, the method comprises the parallel (e.g., concurrent and / or simultaneous) demodulation of a modulated signal in a first demodulator circuit and a second demodulator circuit. The first and second demodulated signals are then subjected to dem-whitening, and a cyclic redundancy check (CRC) is performed on each. If the first demodulated signal passes the CRC, a first packet contained within the signal is selected for further processing. For example, the first packet can be transferred or sent to a central processing unit (CPU). If the second demodulated signal passes the CRC and the first demodulated signal fails, a second packet contained within the second demodulated signal is selected.If both the first and second demodulated signals fail the CRC, neither packet is selected for further processing or sent to the CPU; instead, both are discarded. Generally, one of the two demodulator circuits is configured to use MLSE. However, the operation of the MLSE demodulator circuit is not enabled by, nor dependent on, a signal based on an estimate of the uncertainty of the modulation index of the modulated signal.

[0009] Further features and advantages of embodiments of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. It should be noted that the invention is not limited to the specific embodiments described herein. Such embodiments are presented here for illustrative purposes only. Additional embodiments will be obvious to a person skilled in the art based on the teachings incorporated herein. List of characters

[0010] Embodiments of the invention are now described purely by way of example and with reference to the accompanying schematic drawings, in which corresponding reference symbols indicate corresponding parts. Furthermore, the accompanying drawings, which are included herein and form part of the patent description, illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the invention and to enable a person skilled in the art to implement and use the invention. Fig. Figure 1 is a block diagram representing an embodiment of a section of a communication system equipped with a demodulator circuit comprising dual demodulator circuits in parallel signal processing paths, according to the present disclosure; Fig. 2A is a block diagram illustrating an embodiment of a demodulation circuit comprising dual demodulator circuits in parallel signal processing paths, as disclosed herein; Fig. 2B is a block diagram representing another embodiment of a demodulator circuit comprising dual demodulator circuits according to the present disclosure; Fig. 2C is a block diagram representing another embodiment of a demodulator circuit comprising dual demodulator circuits in parallel signal processing paths, according to the present disclosure; Fig. Figure 3 is a flowchart of a procedure for operating a communication system equipped with a receive signal processor that includes parallel signal paths to improve sensitivity to received signals; and Fig. Figure 4 is a flowchart of a further method for operating a communication system equipped with dual demodulator circuits, comprising an MLSE-capable demodulator circuit, to improve sensitivity to received signals.

[0011] The features and advantages of embodiments of the present invention become more apparent from the detailed description set out below in conjunction with the drawings. In the drawings, identical reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0012] A communication system and a method for the parallel processing of received signals to improve the system's sensitivity are disclosed. The system and method of this disclosure are particularly useful in low-power, short-range, high-frequency (HF) wireless communication systems or radios, such as Bluetooth (BT) or Bluetooth Low Energy (BLE) systems, which are susceptible to reception interference or errors due to the transmission of noisy packets or noisy TX. In short, the system and method of this disclosure use a first and second Bluetooth demodulator circuit in parallel (e.g., concurrently and / or simultaneously) to demodulate the modulated signal. In one embodiment, the first demodulator circuit is a GFSK demodulator configured to operate in the frequency domain.The second demodulator circuit may also include a GFSK demodulator, but is configured to operate in the phase domain and to use MLSE to demodulate the modulated signal. The system further includes a number of CRC (Cyclic Redundancy Code) check circuits, a decision point, and a switching circuit or multiplexer (MUX) to select either a first packet contained in a demodulated signal from the first demodulator circuit or a second packet contained in a demodulated signal from the second demodulator circuit to be transmitted to a processor in the communication system. In Bluetooth demodulation, the use of phase-domain MLSE can provide an improvement in receive sensitivity of up to approximately 3 dB when received symbols are not independent and / or noticeable intersymbol interference (ISI) is present.

[0013] Before the various embodiments are described in more detail, further explanations will be given regarding certain terms that may be used throughout the patent description.

[0014] A "dirty packet" or "dirty TX" refers to a packet, as defined in BT test standards, in which the modulation index changes continuously and rapidly over time. For Basic Data (BDR), the modulation index jumps up / down every 20 ms or 16 packets. For Bluetooth Low Energy (BLE), the modulation index jumps up / down every 50 packets. In addition to modulation index changes, a carrier frequency offset and a symbol timing error are also introduced into the dirty transmitter profile to create non-ideal dirty signals used in the test. Modulation index refers to how much the frequency of a frequency-shifted keyed (FSK) modulated signal can deviate from an unmodulated level with respect to the symbol rate. For example, in a BLE system that uses a physical layer LE, the modulation index is... 1Mused and has a symbol rate of 1 megasymbol per second (Ms / s), the frequency deviation ±250 kHz when the modulation index is 0.5.

[0015] Maximum Probability Sequence Estimation (MLSE) is a mathematical algorithm for extracting useful data from a noisy data stream. MLSE techniques for data communication are used, for example, in Part 9.3 as described by JG Proakis, “Digital Communications, 5th Edition”, New York: McGraw-Hill, 2007. In general, an MLSE estimator applies a modulation index estimation to a presumed bit sequence of a GFSK-modulated signal and compares the results with the received data to see which presumed sequence shows the best match.

[0016] Intersymbol interference (ISI) is a form of signal distortion in which one symbol interferes with subsequent symbols.

[0017] Fig. Figure 1 is a simplified block diagram representing one embodiment of a communication system 100 , such as a Bluetooth (BT) or Bluetooth Low Energy (BLE) radio device equipped with a demodulation circuit comprising parallel signal processing paths, as described in the present disclosure. Since communication systems in general and radio devices in particular are well known to those skilled in the art, detailed descriptions of well-known functions and structures incorporated into the Fig. 1. Communication system shown 100 Included are omitted to avoid obscuring the subject matter of the present disclosure.

[0018] With reference to Fig. 1 includes the communication system 100 generally an antenna 102 , a high-frequency (HF) transceiver 104, a modem 106 , a central processing unit (CPU) 108), such as a microprocessor and memory unit (µPU), and one or more host interfaces 110 , through which the communication system communicates with a host computer or host device (not shown). The RF transceiver 104 includes a transmitter 112 , which is configured to receive signals from a modulating circuit 114 in the modem 106 be provided, to be transferred, and a recipient 116 , in order to receive modulated signals and to process the modulated signals for the demodulation circuit 118 to provide the modem for processing. Additionally, the communication system can 100 furthermore, they include a number of bandpass filters, amplifiers and analog-to-digital converters (ADCs) as well as digital-to-analog converters (DACs), within which and through which the signals between the antenna 102and components of the communication system are replaced.

[0019] In one embodiment, components of the transceiver 104 , of the modem 106 , the CPU 108 and the interfaces 110 integrally formed or incorporated on a single chip with an integrated circuit (IC). The antenna 102 can also be formed integrally on the same IC chip or on a separate chip or substrate that is packaged in a single multi-chip IC package, with the IC chip housing the transceiver 104 , the modem 106 , the CPU 108 and the interfaces 110 includes. Alternatively, the antenna can be 102 as well as other components of the communication system 100 be implemented separately on a printed circuit board (PCB), on which the IC chip that houses the transceiver 104 , the modem 106 , the CPU 108and the interfaces 110 includes, is mounted or attached.

[0020] Embodiments of a demodulation circuit comprising dual demodulator circuits in parallel signal processing paths, according to the present disclosure, are now described with reference to the Fig. 2A and Fig. 2B described. With reference to Fig. 2A includes the demodulation circuit 200 a first signal processing path 202 , which includes the following: a first demodulator circuit 204 , in order to receive one from the recipient 116 (shown in Fig. 1) to demodulate the received signal, a first de-whitening circuit 206 , to subject a first demodulated signal from the first demodulator circuit to de-whitening, and a first CRC test circuit 208, in order to perform a CRC check on a first demodulated signal that has undergone de-whitening. In general, the first signal processing path includes 202 furthermore, a first decryption circuit 210 , in order to decipher or decode packets in the first demodulated signal undergoing de-whitening, a first receive buffer (RXFIFO) 212 ), which is based on the first CRC test circuit 208 follows and between this and the subsequent CPU 108 is coupled.

[0021] In some embodiments, such as the one shown, where the demodulation circuit 200 The first signal processing path includes a device that is part of or contained within a Bluetooth (BT) or Bluetooth Low Energy (BLE) radio device. 202 furthermore, an FEC decoding circuit 216Forward Error Correction (FEC) is used to correct and decode the BT packet header of the first demodulated signal before de-whitening. It should be noted that error correction coding applies only to BT packet heads, and that the packet header must first be decoded to extract the payload length information. The MLSE demodulator circuitry is used only to demodulate the payload portion of the packet. If packet header decoding fails, the packet is removed from both signal processing paths.

[0022] In general, the first demodulator circuit 204 A Bluetooth demodulator circuit or a demodulator circuit capable of demodulating BT or BLE signals, such as a Gaussian frequency-shift keying (GFSK) demodulator. In one embodiment, the first demodulator circuit 204a GFSK demodulator that operates in the frequency domain to split the frequency estimation output in the frequency domain.

[0023] A second signal processing path 218 parallel to the first signal processing path 202 includes a second demodulator circuit 220 , in order to demodulate the modulated signal in parallel or simultaneously with the first, a second de-whitening circuit is used. 222 , in order to subject a second demodulated signal from the second demodulator circuit to de-whitening, a second CRC test circuit 224 and in the illustrated embodiment a second decryption circuit 226 , to decipher or decode packets in the first demodulated signal undergoing de-whitening, a second RXFIFO 228 , which is connected to the second CRC test circuit 224 follows and between this and the subsequent CPU 108 is coupled.

[0024] In general, the second demodulator circuit 220 also a Bluetooth demodulator circuit capable of demodulating BT or BLE signals, such as a GFSK demodulator or differential quadrature phase shift keying (DQPSK). In one embodiment, the second demodulator circuit 220 A GFSK demodulator configured to operate in the phase domain and to use MLSE techniques to demodulate the modulated signal. As noted above, using phase-domain MLSE in Bluetooth demodulation can provide an improvement in receive sensitivity of approximately 3 dB when received symbols are not independent and / or noticeable intersymbol interference (ISI) is present. It should also be noted that the operation of the second demodulator circuit 220is configured to be continuously enabled and does not require an enabling signal based on a potentially uncertain estimate of the modulation index of the modulated signal.

[0025] According to the present disclosure, the demodulation circuit comprises 200 furthermore, a switching circuit 230 , such as a multiplexer (MUX) that is connected between the first and second CRC test circuits 208 , 224 and is coupled to the CPU (not shown in this figure), and a decision circuit or decision point 232, which is coupled to the first and second CRC circuits to control the switching circuit so that it selects either a first packet contained in the first demodulated signal undergoing de-whitening, or a second packet contained in the second demodulated signal undergoing de-whitening, for further processing, to be transferred or sent to the CPU. In general, the decision-maker is 232It is configured to send the first packet to the CPU if the first demodulated signal undergoing de-whitening passes the CRC check. If the first demodulated signal undergoing de-whitening fails the CRC check and the second demodulated signal undergoing de-whitening passes the CRC check, the second packet is sent to the CPU. If neither the first nor the second demodulated signal undergoing de-whitening passes the CRC check, neither the first nor the second packet is sent to the CPU; instead, both are discarded.

[0026] In an alternative embodiment of the demodulation circuit 234 , which in Fig. The switching circuit shown in 2B is... 230 directly with outputs of the first and second CRC test circuits 208 , 224 connected and are the first and second decryption circuits 210 , 226 and the first and second RXFIO212 , 228 through a single common decryption circuit 236 and a single common RXFIO 238 It has been replaced, thereby reducing the cost, size and complexity of the demodulation circuit.

[0027] In another alternative embodiment of the demodulation circuit 240 , which in Fig. 2C is shown, the decision-maker is 232 and the switching circuit 230 through a direct connection between the outputs of the first and second test circuits 208 , 224 and the CPU 242 It has been replaced. Generally, the CPU is... 242 It is programmed or operated in such a way that, if the first demodulated signal undergoing de-whitening passes the CRC check, the CPU can directly access the first RXFIO. 212The CPU reads directly from the packet without requiring an intermediate switching circuit. However, if the first demodulated signal undergoing de-whitening fails the CRC check and the second demodulated signal undergoing de-whitening passes the CRC check, the CPU reads directly from the second RXFIO. 228 from the second packet. If neither the first demodulated signal undergoing de-whitening nor the second demodulated signal undergoing de-whitening passes the CRC check, both the first and second packets are discarded.

[0028] With reference to the flowchart from Fig. Section 3 now describes a method for operating a communication system equipped with a receiving signal processor that includes parallel signal paths to improve sensitivity to received signals. With reference to Fig. 3. The procedure begins with the parallel or simultaneous demodulation, in a first and a second demodulator circuit, of a modulated signal comprising a plurality of packets ( 302 ). As above with reference to the Fig. 2A to Fig. As described in Section 2C, the first demodulator circuit can include a GFSK demodulator operating in the frequency domain. The second demodulator circuit can include a GFSK demodulator operating in the phase domain and configured to use MLSE for demodulating the modulated signal. As noted above, the second demodulator circuit operates continuously and does not require an enabling signal based on an estimate of the uncertainty of the modulation index of the modulated signal.

[0029] The first and second demodulated signal outputs from the first and second demodulator circuits are then simultaneously subjected to de-whitening ( 304 ) and a CRC check is performed simultaneously on each of the first and second demodulated signals ( 306De-whitening is performed simultaneously or in parallel in a first and second de-whitening circuit and can be carried out using any known, standard de-whitening techniques, as described above. Similarly, the CRC check of the first demodulated signal undergoing de-whitening is performed in a first CRC circuit, and the CRC check of the second demodulated signal undergoing de-whitening is performed in parallel in a second CRC circuit.Following de-whitening and CRC checking, a decision point, coupled to the outputs of the first and second CRC circuits, compares the results of the CRC checks and controls a switching circuit or MUX, coupled between the outputs of the first and second CRC circuits and a central processing unit (CPU), to select either a first packet contained in the first demodulated signal undergoing de-whitening or a second packet contained in the second demodulated signal undergoing de-whitening, to be sent to the CPU by the switching circuit. The decision point is configured so that if the first demodulated signal undergoing de-whitening passes the CRC check ( 308 ), the first packet is selected to be sent to a CPU for further processing, for example ( 310). If the first demodulated signal undergoing de-whitening fails the CRC check and the second demodulated signal undergoing de-whitening passes the CRC check ( 312 ), the second packet is selected to be sent to the CPU for further processing ( 314 ).

[0030] If neither the first demodulated signal undergoing de-whitening nor the second demodulated signal undergoing de-whitening passes the CRC check, neither the first nor the second packet is sent to the CPU; instead, both are discarded. 316 Optionally, the decision-maker can signal to the CPU that a received packet has been removed, and the CPU can request that one or more packets, including the removed packet, be retransmitted.

[0031] With reference to the flowchart from Fig. Section 4 now describes a further method for operating a communication system equipped with dual demodulator circuits to improve sensitivity to received signals. With reference to Fig. 4. The process begins with demodulation, in a first demodulator circuit, of a modulated signal containing a multitude of packets ( 402 ). As above with reference to the Fig. 2A to Fig. As described in section 2C, the first demodulator circuit can include a GFSK demodulator operating in the frequency domain. The first demodulated signal output from the first demodulator circuit is then subjected to de-whitening ( 404 ) and a CRC check was performed on the first demodulated signal subjected to de-whitening ( 406 ). If the first demodulated signal subjected to de-whitening passes the CRC check ( 408), a first packet in the first demodulated signal undergoing de-whitening is selected to be sent to the CPU for further processing ( 410 ). If the first demodulated signal subjected to de-whitening fails the CRC check ( 408 ), the modulated signal is demodulated using a second demodulator circuit ( 412 As described above, the second demodulator circuit can also include a GFSK demodulator operating in the phase domain and configured to use MLSE for demodulating the modulated signal. The second demodulated signal output from the second demodulator circuit is then subjected to de-whitening ( 414 ) and a CRC check was performed on the second demodulated signal subjected to de-whitening ( 416 ). If the second demodulated signal undergoing de-whitening passes the CRC check ( 418), a second packet is selected in the second demodulated signal undergoing de-whitening to be sent to the CPU for further processing ( 420 If neither the first nor the second demodulated signal undergoing de-whitening passes its respective CRC check, neither the first nor the second packet is selected or sent to the CPU; instead, both are discarded. 422 ).

[0032] In a further embodiment, not shown, a receiving signal processor comprising dual demodulator circuits can be used, as above with reference to the Fig. 2A to Fig. As described in section 2C, the circuit can be operated in such a way that a signal path is selected based on criteria other than improving signal sensitivity through an internal or external switching circuit. For example, in a demodulation circuit 200, which comprise the first and second signal processing paths 202 , 218 includes, as in Fig. Figure 2A shows that either the first or the second signal processing path is selected for sending a packet of the demodulated signal to the CPU, and the circuits of the other signal processing path are switched off or put into standby mode to reduce power consumption.

[0033] Thus, a communication system and a method for operating it for the parallel processing of received signals to improve the system's sensitivity have been disclosed. Embodiments of the present invention have been described above with the aid of functional and schematic block diagrams that illustrate the implementation of specified functions and their relationships. The boundaries of these functional blocks have been arbitrarily defined here for the sake of simplicity. Other boundaries may be defined as long as the specified functions and their relationships are appropriately implemented.

[0034] The preceding description of the specific embodiments discloses the general nature of the invention so completely that others, by applying their expert knowledge, can easily modify and / or adapt such specific embodiments for various applications without excessive experimentation and without departing from the general concept of the present invention. Therefore, such adaptations and modifications, based on the teachings and instructions presented herein, are to be understood as being within the scope and meaning of equivalents of the disclosed embodiments. It is understood that the language and terminology used herein serve for descriptive purposes and should not be considered limiting; thus, the language and terminology of this patent description are to be interpreted by those skilled in the art in light of the teachings and instructions.

[0035] It is understood that the detailed description section should be used to interpret the claims, and not the overview and summary sections. The overview and summary sections may present one or more, but not all, embodiments of the present invention as envisioned by the inventor(s) and are therefore not intended to limit the present invention and the attached claims in any way.

[0036] The breadth and scope of the present invention should not be limited by any of the embodiments described above, but should only be defined according to the following claims and their equivalents. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 62742012

[0001]

Claims

[1] A procedure that includes the following: Simultaneous demodulation of a modulated signal in a first demodulator and a second demodulator; Simultaneous dem-whitening of a first demodulated signal from the first demodulator circuit and a second demodulated signal from the second demodulator circuit; Simultaneous performance of a cyclic redundancy code check (CRC check, CRC = Cyclic Redundancy Code) on each demodulated signal from the first demodulated signal and the second demodulated signal; Selecting a first packet contained in the first demodulated signal undergoing de-whitening for further processing, if the first demodulated signal undergoing de-whitening passes the CRC check; Selecting a second packet contained within the second demodulated signal undergoing de-whitening for further processing if the second demodulated signal undergoing de-whitening passes the CRC check and the first demodulated signal undergoing de-whitening fails the CRC check. [2] Method according to claim 1, wherein the first and second demodulator circuits include Bluetooth demodulator circuits. [3] Method according to claim 2, wherein the second demodulator circuit is configured to operate in a phase range and to use a maximum likelihood sequence estimation (MLSE) to demodulate the modulated signal. [4] Method according to claim 3, wherein operation of the second demodulator circuit is not enabled by a signal based on an estimate of the uncertainty of the modulation index of the modulated signal. [5] Method according to claim 1, wherein the first demodulated signal from the first demodulator circuit includes a Bluetooth(BT) head, and further comprising performing FEC decoding (FEC = Forward Error Correction) on the first demodulated signal prior to de-whitening. [6] Method according to claim 1, further comprising not transmitting either the first packet or the second packet to the CPU if both the first demodulated signal undergoing de-whitening and the second demodulated signal undergoing de-whitening fail the CRC check. [7] A communication system that includes the following: a receiver for receiving a modulated signal; a first signal path comprising: a first demodulator circuit to demodulate the modulated signal, a first de-whitening circuit to de-whiten a first demodulated signal from the first demodulator circuit, and a first CRC circuit to perform a CRC check on a first demodulated signal that has undergone de-whitening; a second signal path parallel to the first signal path, comprising: a second demodulator circuit to demodulate the modulated signal, a second de-whitening circuit to de-whiten a second demodulated signal from the second demodulator circuit, and a second CRC circuit to perform a CRC check on a second demodulated signal that has undergone de-whitening; a switching circuit that is coupled between the first and second CRC circuits (CRC = Cyclic Redundancy Check) and a central processing unit (CPU); and a decision point coupled to the first and second CRC circuits to control the switching circuit so that it selects either a first packet contained in the first demodulated packet undergoing de-whitening, or a second packet contained in the second demodulated signal undergoing de-whitening, to be passed through the switching circuit to the CPU, the decision point being configured as follows: Transferring the first packet to the CPU if the first demodulated signal undergoing de-whitening passes the CRC; Transferring the second packet to the CPU if the second demodulated signal undergoing de-whitening passes the CRC check and the first demodulated signal undergoing de-whitening fails the CRC check. [8] System according to claim 7, wherein the second demodulator circuit is a Gaussian Frequency-Shift Keying demodulator (GFSK demodulator, GFSK = Gaussian Frequency-Shift Keying) configured to operate in the phase domain and to use Maximum Probability Following Estimation (MLSE) to demodulate the modulated signal. [9] System according to claim 8, wherein the operation of the second demodulator circuit is configured to be capable of continuous operation without a signal based on an estimate of the uncertainty of the modulation index of the modulated signal. [10] System according to claim 7, wherein the decision-maker is further configured to transmit the first packet to the CPU if both the first demodulated signal undergoing de-whitening and the second demodulated signal undergoing de-whitening pass the CRC check. [11] System according to claim 7, wherein the decision-maker is further configured to remove the first and second packets if both the first demodulated signal undergoing de-whitening and the second demodulated signal undergoing de-whitening fail the CRC test. [12] System according to claim 7, wherein the first demodulated signal from the second demodulator circuit includes a Bluetooth (BT) head and the first signal path further includes an FEC decoding circuit between the first demodulator circuit and the first de-whitening circuit to decode the BT head. [13] System according to claim 7, further comprising a first decryption circuit and a first receive buffer memory (RXFIFO) in the first signal path between the first CRC circuit and the switching circuit and a second decryption circuit and a second RXFIFO in the second signal path between the second CRC circuit and the switching circuit. [14] System according to claim 7, further comprising a decryption circuit and a receive buffer memory (RXFIFO) between the switching circuit and the CPU. [15] A procedure that includes the following: Receiving and demodulating, in a first demodulator circuit, a modulated signal comprising a multitude of packets; De-whitening and performing a cyclic redundancy code check (CRC check) on a first demodulated signal from the first demodulator circuit; If the first demodulated signal passes the CRC check, select a first packet contained in the first demodulated signal for further processing and send the first packet to a central processing unit (CPU); If the first demodulated signal fails the CRC check, demodulate the received modulated signal in a second demodulator circuit, de-whiten it, and perform a CRC check on a second demodulated signal from the second demodulator circuit; and If the second demodulated signal passes the CRC check, select a second packet contained within the second demodulated signal for further processing and send the second packet to the CPU. [16] Method according to claim 15, wherein the first and second demodulator circuits include Bluetooth demodulators. [17] Method according to claim 16, wherein the second demodulator circuit is configured to operate in a phase range and to use maximum probability sequence estimation (MLSE) to demodulate the modulated signal. [18] Method according to claim 17, wherein operation of the second demodulator circuit is not enabled by a signal based on an estimate of the uncertainty of the modulation index of the modulated signal. [19] Method according to claim 15, wherein the first demodulated signal from the first demodulator circuit includes a Bluetooth(BT) head, and further comprising performing FEC decoding on the first demodulated signal prior to de-whitening. [20] Method according to claim 15, further comprising not transmitting either the first packet or the second packet to the CPU if both the first demodulated signal undergoing de-whitening and the second demodulated signal undergoing de-whitening fail the CRC check.