Semiconductor packages and methods for their manufacture

Abstract

Semiconductor package (10, 10A), comprising: a circuit board structure (CBS) wherein the circuit board structure (CBS) comprises a core layer (CL), a first build-up layer (BL1) on a first face of the core layer (CL) and a second build-up layer (BL2) on a second face of the core layer (CL) opposite the first face, wherein the first build-up layer (BL1) comprises a first dielectric layer (108A); a first redistribution layer structure (RDL1) above the circuit board structure (CBS), wherein the first redistribution layer structure (RDL1) comprises a second dielectric layer (114) made of a different material than the first dielectric layer (108A); a package structure (PKS) above the first redistribution layer structure (RDL1), comprising several package components (134A, 134B); and a bus die (120A, 120B) and several connectors (118), encapsulated by a first encapsulation (128) between the package structure (PKS) and the first redistribution layer structure (RDL1), wherein the bus die (120A, 120B) is electrically connected to two or more of the several package components (134A, 134B), and the package structure (PKS) is electrically connected to the first redistribution layer structure (RDL1) by the several connectors (118).

Description

GENERAL STATE OF THE ART

[0001] Semiconductor packages are used in a wide variety of electronic devices, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Regarding the packaging used for integrated circuit components or semiconductor dies, one or more chip packages are generally connected to a circuit carrier (e.g., a system board, a printed circuit board, and the like) for electrical connection to other external devices or electronic components.

[0002] High-performance computing (HPC) has recently become increasingly popular and is widely used in advanced networking and server applications, particularly for AI (artificial intelligence)-related products that require high data rates, increasing bandwidth, and lower latency. However, as the package size for packages containing the HPC component increases, communication between the dies has become more challenging.

[0003] US 2017 / 0053897 A1 discloses packages and chip stacking processes. WO 2018 / 063316 A1 discloses a device and a method for providing bridge structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood through the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. The critical dimensions of the various features may, in fact, be arbitrarily enlarged or reduced to clarify the explanation. Fig. 1A to Fig. Figure 1I are schematic section views of various stages in a process for manufacturing a semiconductor package according to some embodiments of this disclosure. Fig. Figure 2 is a cross-sectional view illustrating a semiconductor package according to some embodiments of the disclosure. DETAILED DESCRIPTION

[0005] The invention is defined by claim 1, which defines a semiconductor package, claim 8, which defines a semiconductor package, and claim 15, which defines a method for manufacturing a semiconductor package. Preferred embodiments of the invention are provided in the dependent claims, the description, and the drawings. The following disclosure provides many different embodiments or examples for implementing various functions of the presented content. Specific examples of components and arrangements are described below to simplify the present disclosure.For example, the formation of a second feature above or over a first feature in the following description may include embodiments in which the second and first features are formed in direct contact, and it may also include embodiments in which further features can be formed between the second and first features, so that the second and first features need not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples. This repetition serves for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "below," "underneath," "lower," "above," "upper," and the like may be used herein for a simpler description of the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. The spatially relative terms should encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative designators used herein may also be interpreted accordingly.

[0007] Furthermore, terms such as "first", "second", "third", "fourth" and the like may be used herein for a simpler description to describe one or more similar or different element(s) or feature(s) as illustrated in the figures, and may be used interchangeably depending on the order of presence or context of the description.

[0008] Other features and processes may also be included. For example, test structures may be included to assist in the verification testing of the 3D packaging or 3DIC devices. These test structures may include, for instance, test pads formed in a redistribution layer or on a substrate that allows for the testing of the 3D packaging or 3DIC, the use of probes and / or probe cards, and the like. The verification testing may be performed on intermediate structures as well as on the final structure. Furthermore, the structures and methods disclosed herein may be used in conjunction with testing methodologies that include intermediate verification of known good dies to increase yield and reduce costs.

[0009] Fig. 1A to Fig. Figure 1I are schematic section views of various stages in a process for manufacturing a semiconductor package according to some embodiments of this disclosure. With reference to Fig. 1A provides a circuit board structure CBS. In some embodiments, the circuit board structure CBS comprises a core layer CL and first and second buildup layers BL1 and BL2, each placed on two faces of the core layer CL. In some embodiments, the core layer CL comprises a core dielectric layer 102, core conductive layers 104A and 104B, conductive covers 106A and 106B, and plated through-holes TH. In some embodiments, the core dielectric layer 102 comprises prepreg (which includes epoxy, resin, silica filler, and / or glass fiber), Ajinomoto buildup film (ABF), resin-coated copper foil (RCC), polyimide, photoelectric dielectric (PID), ceramic core, glass core, molding compound, a combination thereof, or the like. However, the disclosure is not limited to these, and other dielectrics may also be used.The core conductive layers 104A and 104B are formed on opposite sides of the core dielectric layer 102. In some embodiments, the core conductive layers 104A and 104B comprise copper, gold, tungsten, aluminum, silver, a combination thereof, or the like. The conductive covers 106A and 106B are located above the core conductive layers 104A and 104B, respectively. In some embodiments, the conductive covers 106A and 106B comprise, for example, copper or another conductive material.

[0010] In some embodiments, the plated through-holes TH are arranged in and penetrate the core dielectric layer 102, providing an electrical connection between the core conductive layer 104A and the core conductive layer 104B. In other words, the plated through-holes TH provide electrical paths between the electrical circuits located on two opposite sides of the core dielectric layer 102. In some embodiments, the plated through-holes TH can be lined with a conductive material and filled with an insulating material. In some embodiments, the method of forming the plated through-holes TH comprises the following operations. First, through-holes (not shown) are formed at predetermined positions in the core dielectric layer 102, for example, by mechanical or laser drilling, etching, or another suitable removal technique.A degreasing treatment can be performed to remove any residue remaining in the through-holes. Subsequently, the sidewall of the through-holes can be plated with one or more conductive materials to a predetermined thickness, thus providing the plated through-holes TH. For example, the through-holes can be plated with copper or other conductive material using either electroplating or non-electroplating.

[0011] In some embodiments, the core conductive layers 104A and 104B, the conductive covers 106A and 106B, and the plated through-holes TH can be formed by the following steps. First, a first conductive material (not shown) is formed on each of two opposite faces of the core dielectric layer 102. Then, the plated through-holes TH are formed to penetrate the core dielectric layer 102, as previously mentioned, and to provide an electrical connection between the first conductive material formed on each of the two faces of the core dielectric layer 102. Afterward, a second conductive material is formed over the first conductive material on each of the opposite faces of the core dielectric layer 102, the second conductive material being able to differ from the first conductive material.In some embodiments, the first and second conductive materials can be formed by using any suitable method (e.g., chemical vapor deposition (CVD) sputtering, printing, plating, or the like). The first conductive materials and the second conductive materials can then be structured together to form the core conductive layers 104A and 104B, and the conductive lids 106A and 106B, respectively. In some embodiments, the first and second conductive materials can be partially removed using a photolithography and etching process or another suitable removal technique.

[0012] The first and second build-up layers BL1 and BL2 are arranged on opposite sides of the core layer CL. In particular, the first build-up layer BL1 is formed over the core conductive layer 104A of the core layer CL, and the second build-up layer BL2 is formed over the core conductive layer 104B of the core layer CL. In one embodiment, the formation of the first build-up layer BL1 can comprise the sequential formation of several first dielectric layers 108A and several first conductive structures 110A, wherein the first dielectric layers 108A and the first conductive structures 110A are stacked alternately over the first face of the core layer CL.Similarly, the formation of the second build-up layer BL2 can comprise the sequential formation of several second dielectric layers 108B and several second conductive structures 110B, wherein the second dielectric layers 108B and the second conductive structures 110B are stacked alternately over the second face of the core layer CL. In some embodiments, the material of the dielectric layers 108A, 108B can be ABF, prepreg, RCC, polyimide, PID, molding compound, a combination thereof, or the like. The dielectric layers 108A, 108B can be formed by a lamination process, a coating process, or the like. The scope of the disclosure is not limited to the formation of only three conductive layers and three dielectric layers for each of the first build-up layer BL1 and the second build-up layer BL2.In other embodiments, the number of dielectric layers (108A / 108B) and the number of conductive structures (110A / 110B) can be adapted to the design requirements. In some embodiments, the thickness of the core layer CL is approximately in the range of 30 µm to 2000 µm. In some embodiments, the thickness of the dielectric layer 108A, 108B is in the range of 10 µm to 20 µm, and the thickness of the conductive structure 110A, 110B is approximately in the range of 10 µm to 20 µm. The conductive structure 110A, 110B comprises metal conductors and vias. In some embodiments, the critical dimension of the via is in the range of 60 µm to 70 µm.In some embodiments, the total number of layers in the first build-up layer BL1 can be from 1 to 8 layers for the conductive structures and dielectric layers, and the total number of layers in the second build-up layer BL2 can also be from 1 to 8 layers for the conductive structures and dielectric layers. In some embodiments, the number of layers in the first build-up layer BL1 is the same as the number of layers in the second build-up layer BL2. In some alternative embodiments, the total number of layers in the first build-up layer BL1 and the second build-up layer BL2 can be different. In some embodiments, the total number of layers in the first build-up layer BL1 and the second build-up layer BL2 in the circuit board structure CBS is less than the total number of layers in the build-up layer in the conventional circuit board structure, which can comprise 28 to 36 layers.Therefore, in some examples, the circuit board structure CBS can also be considered a semi-finished circuit substrate or a semi-finished circuit carrier.

[0013] In some embodiments, a structured mask layer 112 is formed over the second build-up layer BL2. As shown in Fig. As illustrated in Figure 1A, the structured mask layer 112 is formed over the outermost second dielectric layer 108B and the outermost second conductive structures 110B. In some embodiments, the structured mask layer 112 includes multiple openings that partially cover the outermost second conductive structures 110B. In some embodiments, the structured mask layer 112 can be formed from materials having a chemical composition of silica, barium sulfate, and epoxy resin, and / or the like. For example, the structured mask layer 112 can be used as a solder mask and selected to withstand the temperatures of molten conductive materials (e.g., solder, metals, and / or metal alloys) to be subsequently arranged within the openings.In some alternative embodiments, a material of the structured mask layer 112 can be a molding compound or other suitable materials.

[0014] With reference to Fig. 1B The circuit board structure CBS is placed on a support C. In some embodiments, the support C is a glass substrate or any suitable support for carrying a semiconductor wafer or a reconstituted wafer for the semiconductor package fabrication process. In some embodiments, the second build-up layer BL2 is arranged between the core layer CL and the support C. In some alternative embodiments, an adhesive layer (not shown) on the structured mask layer 112 can be formed between the circuit board structure CBS and the support C.

[0015] With reference to Fig. In 1C, a redistribution layer structure RDL1 is formed above and in electrical connection with the first build-up layer BL1. In some embodiments, the formation of the redistribution layer structure RDL1 can include the sequential formation of several dielectric layers 114 and several conductive structures 116, wherein the dielectric layers 114 and the several conductive structures 116 are stacked alternately above the outermost first dielectric layer 108A of the first build-up layer BL1. In some embodiments, the bottommost dielectric layer 114 is in contact with the outermost second dielectric layer 108A, and the bottommost conductive structures 116 are in contact with the outermost first conductive structures 110A to electrically connect the redistribution layer structure RDL1 and the first build-up layer BL1. In some embodiments, the thickness of the dielectric layer 114 is in the range of 2 µm to 10 µm.In some embodiments, the dielectric layer material 114 is polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a molding compound, a combination thereof, or the like. In some alternative embodiments, the organic dielectric layers 114 and the molding compound dielectric layers 114 may be arranged alternately. In some embodiments, the dielectric layers 114 are formed by suitable manufacturing techniques such as spin-on coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or the like. The disclosure is not limited thereto. The conductive structures 116 comprise metal conductors and vias.In some embodiments, the critical dimension of the through-hole of the redistribution layer structure RDL1 lies in the range of 7 µm to 35 µm. In some embodiments, the conductive structures 116 comprise metal, such as aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof. In some embodiments, the conductive structures 116 can be formed by deposition followed by a photolithography and etching process. In some embodiments, the conductive structures 116 can be formed by electroplating or electroless plating.

[0016] In some embodiments, the material of the dielectric layer 114 of the redistribution layer structure RDL1 differs from the material of the dielectric layer 108A of the first build layer BL1. The thickness of the dielectric layer 114 of the redistribution layer structure RDL1 can be less than or substantially the same as the thickness of the dielectric layer 108A of the first build layer BL1. Furthermore, the critical dimension of the via of the redistribution layer structure RDL1 is smaller than the critical dimension of the via of the first build layer BL1. By forming the redistribution layer over the semi-finished circuit substrate, the resulting structure exhibits a high coefficient and reduced thickness. Additionally, the stiffness, inductance, and resistance of the entire semiconductor package are improved, and the cost is reduced.

[0017] With reference to Fig. In 1D, several connectors 118 and several dies 120A, 120B are arranged above the redistribution layer structure RDL1. In some embodiments, the connectors 118 are formed on the uppermost conductive structures 116 of the redistribution layer structure RDL1 to provide an electrical connection for the redistribution layer structure RDL1 to other components arranged thereon. The connectors 118 can be conductive columns and can be formed by electroplating or non-electroplating.

[0018] In some embodiments, after the formation of the connectors 118, the dies 120A, 120B can each be mounted on the uppermost conductive structures 116 between two adjacent connectors 118. In some embodiments, the dies 120A, 120B can be bus dies, providing a shorter electrical connection path between other semiconductor dies mounted in a wafer-level package. In some embodiments, the die 120A, 120B includes a connection structure and can be free of one or more active and / or passive devices. The die 120A (or 120B) can also include a substrate 122 and several conductive structures 124 on the substrate 122. In some embodiments, the substrate 122 is a semiconductor substrate, such as a silicon substrate or the like.The die 120A (or 120B) may also include conductive structures or traces (not shown) in the substrate 122, and the conductive structures or traces may be electrically connected to the conductive structures 124 of the die 120A (or 120B). In some embodiments, the conductive structures or traces may be arranged in or on the substrate 122. In some embodiments, the conductive structures 124 may be densely packed, so that the die 120A, 120B can provide a high density of interconnects. In some embodiments, the conductive structure 124 may have a single or multiple layered structure. A material of the conductive structure 124 includes copper, aluminum, a combination thereof, or the like. In some embodiments, the thickness of the die 120A, 120B is in a range of 10 µm to 100 µm, and the xy dimension of the die 120A, 120B is in a range of 2 mm x 3 mm to 40 mm x 80 mm.In some embodiments, the die 120A, 120B can be mounted on the conductive structures 116 by an adhesive layer 126, such as a die fixation film (DAF). In some embodiments, the die 120A, 120B is not electrically connected to the redistribution layer structure RDL1. However, the disclosure is not limited to these. In some alternative embodiments, the die 120A, 120B may not have silicon vias, and the die 120A, 120B may be connected to the redistribution layer structure RDL1 by solder beads to directly connect the redistribution layer structure RDL1 electrically. In some embodiments, the upper surfaces of the connector 118 may be substantially coplanar with the upper surfaces of the conductive structures 124 of the die 120A, 120B.In some alternative embodiments, the upper surfaces of the connector 118 may be lower or higher than the upper surfaces of the conductive structures 124 of the dies 120A, 120B.

[0019] With reference to Fig. In embodiment 1E, an encapsulation 128 is formed over the redistribution layer structure RDL1 to encapsulate the connector 118 and the dies 120A, 120B. In some embodiments, an insulating material is formed over the redistribution layer structure RDL1 to cover the connector 118 and the dies 120A, 120B. The insulating material is then ground away until the connectors 118 and the conductive structures 124 of the dies 120A, 120B are exposed to form the encapsulation 128. The encapsulation 128 encapsulates the lateral sidewalls of the dies 120A, 120B and the conductive structures 124 arranged thereon, and exposes the upper surfaces of the conductive structures 124 of the dies 120A, 120B. In other words, the dies 120A, 120B are embedded in the encapsulation 128 with their upper surfaces exposed. In some embodiments, the conductive structures 124 of the dies 120A, 120B can be encapsulated and in contact with the encapsulation 128.The connectors 118 are arranged within and penetrate the encapsulation 128. In some embodiments, the encapsulation 128 comprises a molding compound, such as an epoxy resin, formed by a molding process. In some alternative embodiments, the encapsulation 128 may comprise an epoxy resin or the like. In some embodiments, the thickness of the encapsulation 128 is in the range of 5 µm to 100 µm. The upper surfaces of the connector 118 and the dies 120A, 120B are substantially coplanar with the upper surface of the encapsulation 128.

[0020] With reference to Fig. 1F After the formation of the encapsulation 128, a redistribution layer structure RDL2 is formed over the encapsulation 128, establishing an electrical connection with the connectors 118 and the dies 120A, 120B. In some embodiments, the redistribution layer structure RDL2 may comprise the sequential formation of several dielectric layers 130 and several conductive structures 132, 132a, which are stacked alternately over the encapsulation 128. In some embodiments, the thickness of the dielectric layer 130 is in the range of 2 µm to 50 µm. In some embodiments, the uppermost conductive structures 132a are conductive terminals, which may comprise several conductive columns and several subball metallurgy (UBM) structures for ball assembly. In some embodiments, the diameter of the uppermost conductive structure 132a is smaller than the diameter of the lower conductive structure 132.In some embodiments, the spacing between the topmost conductive structures 132a can be from 20 µm to 80 µm, and the diameter of the topmost conductive structure 132a can be from 10 µm to 25 µm. In some embodiments, the materials of the dielectric layers 130 can be similar to the materials of the dielectric layers 114 and are different from the encapsulation material 128. At this point, an integrated package substrate 100 is fabricated. In some embodiments, the integrated package substrate 100 comprises the circuit board structure CBS (i.e., a semi-finished circuit substrate), the redistribution layer structures RDL1, RDL2, and the structured mask layer 112, wherein the redistribution layer structures RDL1, RDL2, and the structured mask layer 112 are arranged on two opposite faces of the circuit board structure CBS.In some embodiments, the integrated package substrate 100 has a high coefficient, such as in a range of 15 GPa to 50 GPa.

[0021] With reference to Fig. 1G comprises several package components 134A, 134B, 134C with the redistribution layer structure RDL2 of the integrated package substrate 100. In some embodiments, the package components 134A, 134B, 134C can be connected to the exposed conductive structures 132a of the redistribution layer structure RDL2 by connecting elements 140. In some embodiments, the connecting elements 140 can be formed on the redistribution layer structure RDL2 or on the package components 134A, 134B, 134C. In some embodiments, the connecting elements 140 are solder regions such as microbumps. In some embodiments, the spacing between the connecting elements 140 can be from 20 µm to 80 µm, and the diameter of the connecting elements 140 can be from 5 µm to 55 µm. After connection, the connecting elements 140 are in electrical connection with the connectors 118 and the dies 120A, 120B through the redistribution layer structure RDL2.

[0022] In some embodiments, each of the package components 134A, 134B, 134C is a package, a device die, a die stack, and / or the like. The device die can be a high-performance integrated circuit, such as a system-on-a-chip (SoC) die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, a field-programmable gate array (FPGA) die, a mobile application die, a memory die, or a die stack. In some embodiments, the memory die is a memory cube such as a high-bandwidth memory (HBM) cube. The package components 134A, 134B, 134C can include the respective semiconductor substrates (not shown) in the respective dies. In some embodiments, a rear face of the semiconductor substrates is a face that, after orientation, points upwards, which is in Fig. 1G is illustrated. The package components 134A, 134B, 134C further include integrated circuit devices (such as active devices including transistors, not shown) on a front surface (e.g., a downward-facing surface in Fig. 1G) the respective semiconductor substrates. In one embodiment, the package components 134A, 134B are SoC dies and the package component 134C is an HBM cube. In this embodiment, the package component 134C comprises a die stack 136 and a controller 138 located at the bottom of the die stack 136, where underfills can be formed between the dies of the die stack 136 and between the die stack 136 and the controller 138. The package components 134A, 134B, 134C described above are for illustrative purposes only, but the disclosure is not to be considered a limitation in this respect. In some other embodiments, the package components 134A, 134B, 134C may comprise a combination of any type of device or die as described above. Furthermore, the package components 134A, 134B, 134C can have the same or different sizes and functions as the design requirements.

[0023] In some embodiments, the package components 134A, 134B, 134C each have several connectors 142 such as bonding pads. In some embodiments, as in Fig. As shown in Figure 1H, after the connectors 142 are electrically connected to the redistribution layer structure RDL2, the sidewalls of the connector 142 can be exposed. In some alternative embodiments, the package components 134A, 134B, 134C can further comprise an insulating layer, and the connectors 142 can be embedded in an insulating layer, the insulating layer covering the sidewalls of each connector 142. In some alternative embodiments, an underfill can be formed next to the package components 134A, 134B, 134C after the package components 134A, 134B, 134C are connected to the redistribution layer structure RDL2, and the underfill covers the sidewalls of the connector 142. In some embodiments, the package components 134A, 134B, 134C are connected to the redistribution layer structure RDL2 by using flip-chip bonding.In detail, the connectors 142 of the package components 134A, 134B, 134C are connected to the connecting elements 140 and the active surfaces of the package components 134A, 134B, 134C point to the circuit board structure CBS.

[0024] In some embodiments, the package components 134A, 134B, 134C are also referred to as a first package component 134A, a second package component 134B, and a third package component 134C, wherein the first package component 134A is adjacent to the second package component 134B and the second package component 134B is adjacent to the third package component 134C. The dies 120A, 120B are arranged below and between the package components 134A, 134B, 134C and are electrically connected to them. For example, in some embodiments, the die 120A is located below and between the package components 134A, 134B to provide or establish short and fast electrical connections between the first and second package components 134A, 134B.Similarly, the die 120B can be positioned below and between the second and third package components 134B, 134C to provide or establish short and fast electrical connections between them. Specifically, the first package component 134A can communicate with the second package component 134B via an electrical (or communication) path that communicates through the connectors 142, the connecting element 140, and the conductive structure 124 of the die 120A. In some embodiments, the die 120A, 120B extends as a beam, for example, between two adjacent columns of the package components 134A, 134B, 134C. In other embodiments, the dies 120A, 120B connect package components that are not adjacent to each other.For example, the die 120A can connect the first package component 134A to the third package component 134C via the second package component 134B, which is placed in between.

[0025] With reference to Fig. In embodiment 1H, an encapsulation 144 is formed over the redistribution layer structure RDL2 to encapsulate the package components 134A, 134B, 134C, to form a package structure PKS. In some embodiments, an insulating material is formed over the redistribution layer structure RDL2 to cover the package components 134A, 134B, 134C. The insulating material is then ground away until the package components 134A, 134B, 134C are exposed to form the encapsulation 144. In some embodiments, the encapsulation 144 may include a mold underfill. The encapsulation 144 may be a molding compound, an epoxy, a resin, or the like. The encapsulation 144 encapsulates the side walls of the package components 134A, 134B, 134C, and exposes the rear surfaces of the package components 134A, 134B, 134C.In some embodiments, the encapsulation 144 extends over an entire upper surface of the redistribution layer structure RDL2, and one side wall of the encapsulation 144 is substantially flush with a side wall of the redistribution layer structure RDL2. In some embodiments, the encapsulation 144 can be a molding compound formed by a molding process. The thickness of the package structure PKS can range from 50 µm to 1500 µm, and the width of the package structure PKS can range from 30 mm to 500 mm. In some embodiments, the encapsulation 144 is formed after the package components 134A, 134B, 134C are connected to the redistribution layer structure RDL2 above the circuit board structure CBS. In other words, the package structure PKS is formed after the package components 134A, 134B, 134C and the encapsulation 144 are sequentially formed over the circuit board structure CBS.However, the disclosure is not limited thereto. In some alternative embodiments, a pre-formed package structure PKS can be connected to the redistribution layer structure RDL2 above the circuit board structure CBS.

[0026] With reference to Fig. 1I The circuit board structure CBS with the package above it is detached from the carrier C. Then, several conductive connections 146 are formed in the openings of the structured mask layer 112 above the second build-up layer BL2. The conductive connections 146 are in electrical contact with the outermost second conductive structures 110B in the second build-up layer BL2 of the circuit board structure CBS. The conductive connections 146 can be ball grid array (BGA) connectors, solder beads, metal columns, and / or the like. In some embodiments, the conductive connections 146 can be formed by an assembly process and a reflow process. In some embodiments, as in Fig. In one embodiment, the opening of the structured mask layer 112 is filled with the conductive terminals 146, and the upper surfaces of the structured mask layer 112 are covered with the conductive terminals 146, while the conductive terminals 146 are separated from one another. However, the disclosure is not limited to this. In some alternative embodiments, the upper surfaces of the structured mask layer 112 may be partially uncovered by the conductive terminals 146. For example, the opening of the structured mask layer 112 may be partially filled with the conductive terminals 146. That is, a gap may be formed between the conductive terminal 146 and the structured mask layer 112. In certain embodiments, the conductive terminals 146 are available for mounting on other electrical components (e.g., circuit carriers, system boards, motherboards, etc.).In some alternative embodiments, pads can be formed in the openings of the structured mask layer 112 between the conductive terminals 146 and the outermost second conductive structures 110B.

[0027] At this point, a semiconductor package 10 is fabricated. In some embodiments, the semiconductor device 10 comprises the circuit board structure CBS, the package structure PKS, and the redistribution layer structures RDL1, RDL2, as well as the connectors 118 and the dies 120A, 120B between the circuit board structure CBS and the package structure PKS. In some embodiments, two directly adjacent package components (134A / 134B or 134B / 134C) communicate with each other via the die 120A or 120B located between and below them. However, the disclosure is not limited to this, and in some alternative embodiments, the die can be located at any position between the package structure and the circuit board structure so that the package components, whether adjacent or not, can communicate.In some embodiments, the requirements for high-performance computing and high-bandwidth communication between the package components are met, and the reliability of the semiconductor package is improved. Accordingly, the technique can be applied to create super-large semiconductor packages, such as 70 mm x 70 mm or larger, like 100 mm x 100 mm. Furthermore, the semiconductor package is manufactured through a one-stop-shop process in an environment similar to a standard silicon fabrication environment. This improves the manufacturing efficiency and increases the yield of the semiconductor package. Additionally, the final substrate exhibits a high coefficient and reduced thickness due to the formation of RDLs over the semi-finished circuit substrate, improving the stiffness, inductance, and resistance of the entire semiconductor package and reducing costs.

[0028] Fig. Figure 2 is a schematic sectional view of a semiconductor package according to some exemplary embodiments of this disclosure. The semiconductor package 10A, which is described in Fig. Figure 2 is similar to the semiconductor package 10 shown in Figure 10. Fig. Figure 1I illustrates this, and the same reference numbers are therefore used to refer to the same and similar parts, and the detailed description is omitted here. The difference between semiconductor package 10 and semiconductor package 10A lies in the die configuration, the package structure, and the redistribution layer structure. For example, in the embodiment shown in Fig. Figure 1I shows that dies 120A and 120B are designed to connect electrically to the adjacent package components 134A / 134B and 134B / 134C. In the Fig. In the embodiment shown in section 2, however, the die 120' can be electrically connected to the entire package structure PKS instead of to adjacent package components 134A, 134B, 134C. In some embodiments, the die 120' can be located at any position between the redistribution layer structures RDL1 and RDL2 in the encapsulation 128. The die 120' is electrically connected to the package structure PKS through the redistribution layer structure RDL2. In some embodiments, the die 120' comprises a substrate 122 and the conductive structures 124 on it. The Die 120' is a device die and the device die is an integrated voltage regulator (IVR) Die, an integrated passive device (IPD) Die, a memory die such as a static random access memory (SRAM) Die or the like, which is a component to implement a system on a wafer package with the package components 134A, 134B, 134C of the package structure PKS.In some embodiments, the die 120' can be arranged on the redistribution layer structure RDL1 by means of an intervening adhesive layer 126, and the die 120' may not be directly connected to the redistribution layer structure RDL1 by a conductor. In some alternative embodiments, however, the die 120' can be electrically connected to the redistribution layer structure RDL1. In some embodiments, the redistribution layer structure RDL2 is formed above the encapsulation 128 to electrically connect the connector 118 and the die 120'. In some embodiments, the uppermost conductive structures 132a of the redistribution layer structure RDL2 can be UBM structures for ball mounting. The diameter of the uppermost conductive structure 132a can be similar to the diameter of the lower conductive structure 132.

[0029] In some embodiments, the package structure PKS may include system-on-chip (SoC) packages, chip-on-wafer (CoW) packages, integrated fan-out (InFO) packages, chip-on-wafer-on-substrate (CoWoS) packages, other three-dimensional integrated circuit (3DIC) packages, and / or the like. In some embodiments, the package structure PKS may be pre-formed prior to interconnection with the redistribution layer structure RDL2. Specifically, the package structure PKS comprises two or more package components, for example, the three package components 134A, 134B, and 134C as shown in [reference missing]. Fig. Figure 2 shows the encapsulation 144 encapsulating the package components 134A, 134B, 134C, and a redistribution layer structure 150. In some embodiments, the connectors 142 of the package components 134A, 134B, 134C can be enclosed by the encapsulation 144 as shown in Figure 2. Fig.2 shown, or alternatively, arranged in a dielectric layer (not shown), which is then encapsulated by the encapsulation 144. In some embodiments, the package components 134A, 134C can be memory cubes, and the package component 134B can be a CPU, GPU, FPGA, or other suitably integrated high-performance circuit. In some embodiments, the redistribution layer structure 150 lies transversely to the package components 134A, 134B, 134C and the encapsulation 144 and is electrically connected to the package components 134A, 134B, 134C. The redistribution layer structure 150 comprises several dielectric layers 152 and several conductive structures 154 and 154a, which are stacked alternately over the package components 134A, 134B, and 134C.The outermost conductive structures 154a are used as conductive connections, which may include multiple conductive pillars and multiple subball metallurgy (UBM) structures for ball mounting on the redistribution layer structure RDL2. In some embodiments, the package structure PKS may be connected to the uppermost conductive structures 132a of the redistribution layer structure RDL2 by connecting elements 140. In some embodiments, the connecting elements 140 are solder regions such as controlled collapse chip connection (C4) bumps. The connecting elements 140 may be formed on the uppermost conductive structures 132a of the redistribution layer structure RDL2 or on the outermost conductive structures 154a of the package structure PKS. After bonding, an underfill 156 may be dispensed to protect the connection structure between the package structure PKS and the redistribution layer structure RDL2.In some embodiments, the encapsulation 144 is formed before being connected to the redistribution layer structure RDL2, and a side wall of the encapsulation 144 is therefore essentially flush with a side wall of the redistribution layer structure 150 instead of a side wall of the redistribution layer structure RDL2. In some embodiments, the total thickness from a bottom of the underfill 156 to a top of the package structure PKS can be in a range of 50 µm to 1500 µm.

[0030] In some embodiments, the die 120' is embedded in the encapsulation 128 between the redistribution layer structures RDL1 and RDL2, similar to an IVR die, an IPD die, or an SRAM die, and is electrically connected to the package structure PKS. In other words, the die 120' is integrated into the package structure PKS, and a system-on-a-wafer or a system-in-a-package (SiP) can thus be implemented.

[0031] In some embodiments, the semiconductor package comprises the circuit substrate, the redistribution layer structures above the circuit substrate, the die and the interconnects embedded in the encapsulation between the redistribution layer structures, and the package structure, which includes multiple package components above the redistribution layer structures. In some embodiments, the die is a bus die or a device such as an IVR die, IPD die, or SRAM, and the die is embedded between the redistribution layer structures by forming the encapsulation around it. In some embodiments, the die is electrically connected to the adjacent package components by the above configuration, enabling the package components to communicate without chip-to-package interaction, and high-bandwidth communication between the chips can be performed.Furthermore, since the requirements for high data rate, increased bandwidth, and reduced latency are met, and the reliability between components is enhanced, this high-bandwidth communication can also be applied to an extra-large package. In some embodiments, the die is electrically connected to the package structure to be integrated and provide additional functionality, thus enabling a system-on-a-wafer or system-in-a-package architecture. Accordingly, the above configuration can be used in high-performance computing applications.

[0032] According to some embodiments of this disclosure, a semiconductor package comprises a first redistribution layer structure, a package structure, a bus die, and multiple connectors. The package structure is arranged above the first redistribution layer structure and comprises multiple package components. The bus die and the connectors are encapsulated by a first encapsulation between the package structure and the first redistribution layer structure. The bus die is electrically connected to two or more of the multiple package components, and the package structure is electrically connected to the first redistribution layer structure through the multiple connectors.

[0033] According to various embodiments of this disclosure, a semiconductor package comprises a first redistribution layer structure, several connectors and a die, a second redistribution layer structure, and a package structure. The connector and the die are encapsulated by a first encapsulation and arranged above the first redistribution layer structure. The second redistribution layer structure is arranged above the first encapsulation. The package structure comprises several package components and is arranged above the second redistribution layer structure. The die is electrically connected to the package structure through the second redistribution layer structure, and the several connectors electrically connect the first redistribution layer structure and the second redistribution layer structure.

[0034] According to some embodiments of this disclosure, a method for fabricating a semiconductor package comprises the following steps: several connectors are formed over a first redistribution layer structure. A die is mounted onto the first redistribution layer structure. A first encapsulation is formed to encapsulate the die and the several connectors. A second redistribution layer structure is formed over the first encapsulation to establish an electrical connection with the die and the connectors. Several package components are connected onto the second redistribution layer structure, the die being in electrical contact with at least two of the several package components.

Claims

[1] Semiconductor package (10, 10A), comprising: a circuit board structure (CBS), the circuit board structure (CBS) comprising a core layer (CL), a first build-up layer (BL1) on a first surface of the core layer (CL), and a second build-up layer (BL2) on a second surface of the core layer (CL) opposite the first surface, the first build-up layer (BL1) comprising a first dielectric layer (108A); a first redistribution layer structure (RDL1) over the circuit board structure (CBS), the first redistribution layer structure (RDL1) comprising a second dielectric layer (114) made of a different material than the first dielectric layer (108A); a package structure (PKS) above the first redistribution layer structure (RDL1), comprising a plurality of package components (134A, 134B); and a bus die (120A, 120B) and a plurality of connectors (118) encapsulated by a first encapsulation (128) between the package structure (PKS) and the first redistribution layer structure (RDL1), wherein the bus die (120A, 120B) is in electrical connection with two or more of the plurality of package components (134A, 134B), and the package structure (PKS) is in electrical connection with the first redistribution layer structure (RDL1) through the plurality of connectors (118). [2] The semiconductor package (10, 10A) of claim 1, wherein the first redistribution structure (RDL1) comprises a plurality of sequentially arranged second dielectric layers (114) and conductive structures (116), and wherein the plurality of second dielectric layers (114) are arranged alternately from molding compound and organic compound. [3] The semiconductor package (10, 10A) of claim 1 or 2, wherein the first encapsulation (128) comprises a molding compound. [4] The semiconductor package (10, 10A) of any preceding claim, further comprising a second encapsulation (144), wherein the plurality of package components (134A, 134B) are encapsulated by the second encapsulation (144). [5] The semiconductor package (10, 10A) of claim 4, wherein a sidewall of the second encapsulation (144) is flush with a sidewall of the first encapsulation (128). [6] The semiconductor package (10, 10A) of any preceding claim, further comprising a second redistribution layer structure (RDL2) and a plurality of solder regions (140) between the first encapsulation (128) and the plurality of package components (134A, 134B), the second redistribution layer structure (RDL2) being disposed between the first encapsulation (128) and the plurality of solder regions (140), and the bus die (120A, 120B) being in electrical connection with the plurality of package components (134A, 134B) through the second redistribution layer structure (RDL2) and the plurality of solder regions (140). [7] Semiconductor package (10, 10A) according to one of the preceding claims, wherein the bus die (120A, 120B) is bonded to the first redistribution layer structure (RDL1) by an adhesive layer. [8] Semiconductor package (10, 10A), comprising: a circuit board structure (CBS), the circuit board structure (CBS) comprising a core layer (CL), a first build-up layer (BL1) on a first surface of the core layer (CL), and a second build-up layer (BL2) on a second surface of the core layer (CL) opposite the first surface, the first build-up layer (BL1) comprising a first dielectric layer (108A); a first redistribution layer structure (RDL1), the first redistribution layer structure (RDL1) being disposed over the circuit board structure (CBS), the first redistribution structure (RDL1) comprising a second dielectric layer (114) made of a different material than the first dielectric layer (108A); a plurality of connectors (118) and a die (120A, 120B) encapsulated by a first encapsulant (128) disposed over the first redistribution layer structure (RDL1); a second redistribution layer structure (RDL2) disposed over the first encapsulation (128); and a package structure (PKS) comprising a plurality of package components (134A, 134B) and arranged over the second redistribution layer structure (RDL2), wherein the die (120A, 120B) is in electrical connection with the package structure (PKS) through the second redistribution layer structure (RDL2) and the plurality of connectors (118) electrically connect the first redistribution layer structure (RDL1) and the second redistribution layer structure (RDL2). [9] The semiconductor package (10, 10A) of claim 8, wherein the die (120A, 120B) is disposed between and below two of the plurality of package components (134A, 134B). [10] The semiconductor package (10, 10A) of claim 8 or 9, wherein the package structure (PKS) further comprises a second encapsulation (144) encapsulating the plurality of package components (134A, 134B). [11] The semiconductor package (10, 10A) of any one of claims 8 to 10, wherein the package structure (PKS) further comprises a third redistribution layer structure (150) between the plurality of package components (134A, 134B) and the second redistribution layer structure (RDL2). [12] Semiconductor package (10, 10A) according to one of claims 8 to 11, wherein the die (120A, 120B) is in electrical connection with the first redistribution layer structure (RDL1). [13] The semiconductor package (10, 10A) of any one of claims 8 to 12, wherein the first redistribution structure comprises a plurality of sequentially arranged second dielectric layers (114) and conductive structures (116), and wherein the plurality of second dielectric layers (114) are arranged alternately from molding compound and organic compound. [14] The semiconductor package of any one of claims 8 to 13, wherein the die (120A, 120B) is an integrated voltage regulator die, an integrated passive device die, or a memory die. [15] A method for producing a semiconductor package (10, 10A), comprising: Forming a circuit board structure (CBS), the circuit board structure (CBS) comprising a core layer (CL), a first build-up layer (BL1) on a first surface of the core layer (CL), and a second build-up layer (BL2) on a second surface of the core layer (CL) opposite the first surface, the first build-up layer (BL1) comprising a first dielectric layer (108A), Forming a first redistribution layer structure (RDL1) over the circuit board structure (CBS), wherein the first redistribution layer structure (RDL1) is arranged over the circuit board structure (CBS), wherein the first redistribution structure (RDL1) comprises a second dielectric layer (114) made of a different material than the first dielectric layer (108A); Forming a plurality of connectors (118) over the first redistribution layer structure (RDL1); Mounting a die (120A, 120B) on the first redistribution layer structure (RDL1); Forming a first encapsulation (128) for encapsulating the die (120A, 120B) and the plurality of connectors (118); Forming a second redistribution layer structure (RDL2) over the first encapsulation (128) to establish an electrical connection with the die (120A, 120B) and the plurality of connectors (118); and Connecting a plurality of package components (134A, 134B) on the second redistribution layer structure (RDL2), wherein the die (120A, 120B) is in electrical connection with at least two of the plurality of package components (134A, 134B). [16] The method of claim 15, further comprising forming a second encapsulation (144) for encapsulating the plurality of package components (134A, 134B). [17] The method of claim 15 or 16, wherein the die (120A, 120B) is in electrical connection with two adjacent ones of the plurality of package components (134A, 134B). [18] The method of any one of claims 15 to 17, wherein connecting a plurality of package components (134A, 134B) on the second redistribution layer structure (RDL2) comprises connecting a package structure (PKS) on the second redistribution layer structure (RDL2), and the package structure (PKS) comprises the plurality of package components (134A, 134B), a second encapsulation (144) encapsulating the plurality of package components (134A, 134B), and a third redistribution layer structure (150) over the plurality of package components (134A, 134B) and the second encapsulation (144). [19] The method of any one of claims 15 to 18, further comprising forming a plurality of interconnect elements (140) over the second redistribution layer structure (RDL2), wherein the plurality of package components (134A, 134B) are connected to the second redistribution layer structure (RDL2) by the plurality of interconnect elements. [20] The method of claim 19, further comprising forming a second encapsulation (144) for encapsulating the plurality of package components (134A, 134B) and the interconnecting elements (140).

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