METHOD AND HIGH-FREQUENCY SEMICONDUCTOR COMPONENTS

Abstract

Procedures, with: Forming a first redistribution layer (221, 421) over a first surface (212, 412) of a semiconductor chip (110, 210, 410), wherein the first redistribution layer (221, 421) has at least one antenna ground plate (222); Forming a first dielectric material (220A, 420A) such that it surrounds the semiconductor chip (110, 210, 410) and mechanically connects the semiconductor chip (110, 210, 410) to the first redistribution layer (221, 421); Forming a second redistribution layer (223, 423) such that it is in contact with a second surface (213, 413) of the semiconductor chip (110, 210, 410), wherein the second surface (213, 413) is opposite the first surface (212, 412); and Forming a metallization structure (230, 430) in a second dielectric material (220B, 420B), wherein the metallization structure (230, 430) comprises one or more antenna structures (135A-135C, 235A-235D, 435A-435D) and a connecting structure, and wherein the connecting structure electrically connects the one or more antenna structures (135A-135C, 235A-235D, 435A-435D) to the first redistribution layer (221, 421) and / or the second redistribution layer (223, 423), where forming the metallization structure (230, 430) includes: Formation of a first region of the metallization structure (230, 430) prior to the formation of the second dielectric material (220B, 420B) and Formation of a second area of ​​the metallization structure (230, 430) after the formation of the second dielectric material (220B, 420B).

Description

BACKGROUND 1. FIELD OF THE INVENTION

[0001] In general, the present invention relates to semiconductor devices having radio frequency (RF) components to be connected to their antenna structures to establish a wireless connection to the periphery of the semiconductor device. 2. DESCRIPTION OF THE STATE OF THE ART

[0002] There is a drive in the field of semiconductor products to integrate an increasing number of circuit elements into a single semiconductor chip, thereby offering the possibility of implementing complete systems on a single chip. As the demand for wireless connectivity in electronic components in general increases, there is also a steadily increasing drive to incorporate corresponding wireless connectivity into individual semiconductor chips, thereby significantly expanding the flexibility and application areas for electronic components. For example, for low-cost sensor components, wireless signal transmission offers increased flexibility in creating complex systems that operate based on information from sensor components and the like.On the other hand, even extremely complex systems on a single chip must be equipped with complex wireless connectivity capabilities to communicate with other components, such as sensors, a higher-level control system, and the like.

[0003] When implementing wireless connectivity at the chip level, not only must appropriate RF components, such as amplifiers, local oscillators, phase-locked loop components, and the like, be provided in the semiconductor chip, but an appropriate antenna structure must also be arranged near these RF components to achieve suitable performance in terms of power losses, robustness to interference, and the like. Due to the increasing reduction in wavelength and thus the increase in frequency of the corresponding communication channels typically used in wireless connectivity in current developments, frequencies in the range of approximately 20 to 110 GHz must be handled, requiring considerable effort in the overall design of the analog radio frequency domain of a corresponding electronic component.For example, at shorter wavelengths in the millimeter range, the interface between the respective antenna structures and the actual electronic components, such as the final high-frequency amplifier for a transmitter or the input amplifier for a receiver, becomes a highly critical component area, since excessively long feed lines can lead to significant signal loss, interference, or the like. Therefore, significant efforts are being made in this field of technology to create extremely efficient intermediate structures that electrically connect the antenna structures and the actual electronic components in the semiconductor chip.For example, special substrates based on special materials with a suitable contact structure have been developed to efficiently connect to the semiconductor chip and thus achieve efficient overall performance of the finished electronic device, which includes the semiconductor chip, a corresponding package or housing, a specially designed substrate with antenna structures formed therein, and the like. In other conventional approaches, the antenna structures are provided within the semiconductor chip, yet they result in a significant additional chip area, thereby contributing to significantly higher overall manufacturing costs.

[0004] In general, there is an effort in the field of semiconductor technology according to which the insertion of the semiconductor chips into a package or packaging substrate can be accomplished at the wafer level, ie the semiconductor chip is inserted into or attached to a package before the semiconductor wafer is actually divided into individual semiconductor chips, thereby achieving a highly cost-effective package attachment process.

[0005] Document DE 10 2017 202 578 A1 describes a semiconductor device comprising a semiconductor chip, a redistribution layer on a first side of the semiconductor chip, a dielectric layer, and an antenna on the dielectric layer. The redistribution layer is electrically coupled to the semiconductor chip, and the dielectric layer is located between the antenna and the semiconductor chip.

[0006] Since wafer-level package connection is a very promising approach for the manufacture of semiconductor devices due to performing corresponding process steps on wafers instead of individual chips, thereby reducing yield losses in a final phase of the overall manufacturing process, the present invention relates to semiconductor devices and manufacturing techniques in which antenna structures are incorporated, avoiding or at least limiting the effects of the aforementioned problems. OVERVIEW

[0007] In a first aspect of the invention, a method is provided according to claim 1. More advantageous embodiments thereof are defined in dependent claims 2 to 8.

[0008] In a second aspect of the invention, an RF semiconductor device is provided according to claim 9. More advantageous embodiments thereof are defined in dependent claims 10 and 11.

[0009] In a third aspect of the invention, an RF semiconductor device according to claim 12 is provided.

[0010] The following is a simplified overview of the invention to provide a basic understanding of some aspects of the invention. This overview is not an exhaustive overview of the invention. It is not intended to identify essential or key elements of the invention or to delimit the scope of the invention. The sole purpose is to provide some concepts in a simplified form as an introduction to the more detailed description that follows.

[0011] Fundamentally, the present invention considers the concept of wafer-level package interconnection for radio frequency (RF) semiconductor devices by applying molding techniques based on suitable materials that have been identified as superior materials for RF applications. Furthermore, antenna structures can be incorporated into the corresponding dielectric material, e.g., the molding material, in conjunction with other suitable interconnect structures, such as metallization layers for redistributing the electrical connections of the semiconductor chip to an off-chip level with less critical lateral dimensions, thereby enabling connection to the periphery of the semiconductor chip, such as to another carrier substrate, a printed circuit board, and the like. Typically, such redistributing orLine restructuring interconnect structures in the form of metal lines, metal surfaces and vias or contact elements are referred to as a redistribution layer and represent an interface between the typically densely packed contact areas of the last metal layer of the semiconductor chip and external components, such as substrate packages, printed circuit boards, and the like.It has been recognized that, in principle, the packaging technology based on dielectric materials that enclose the semiconductor chip and that are used, for example, on the basis of a casting process can be advantageously utilized to integrate the respective antenna structures in an extremely space-saving manner, thereby achieving extremely short electrical connections between the semiconductor chip and the antenna structures, while at the same time the superior properties of the dielectric material can contribute to better performance of the RF semiconductor chip located in the housing. For example, in some illustrative embodiments, in addition to forming a redistribution layer on the basis of a first casting process, a further casting process or molding process is used to incorporate the required antenna structures and corresponding connections, thereby making a packaging process orPackaging process at the wafer level, and wherein the antenna structures are provided in the package material with a very short conduction path between the antenna structures and the actual semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The invention can be better understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals designate like elements, and in which: Fig. 1 is a schematic top view of a semiconductor chip being packaged at the wafer level, with a plurality of antenna structures incorporated in the package material within the outline of the semiconductor chip, according to illustrative embodiments; Fig. 2A and Fig. 2B are schematic cross-sectional views of semiconductor devices with antenna structures in the housing material, ie, in the molding material, wherein the semiconductor chip is shown “pointing down” in an example not belonging to the invention in Fig. 2A is provided to provide a highly efficient continuation for chip-internal contact areas to a contact structure for a package substrate, and wherein the semiconductor chip is “pointing up” in embodiments of the invention in Fig. 2B is provided to provide very short electrical connections between the semiconductor chip and the antenna structures formed in the housing material; Fig. 3A - 3D schematically show cross-sectional views of a semiconductor device during various manufacturing stages for incorporating antenna structures into the housing material provided on the basis of a two-stage casting process, wherein contact elements are formed in an upper region of the housing material, for example by laser drilling, according to examples not belonging to the invention; and Fig. 4A-4E schematically illustrate cross-sectional views of the semiconductor device during various manufacturing stages when performing a two-stage molding process, wherein contact elements are formed by patterning the second level of the package material by lithography, according to yet further illustrative embodiments.

[0013] Specific embodiments are shown by way of example in the drawings and described in detail herein. DETAILED DESCRIPTION

[0014] Various illustrative embodiments of the invention are described below. For the sake of clarity, not all features of an actual implementation may be included in this description. However, it should be appreciated that in developing such an actual embodiment, numerous implementation-specific decisions must be made to meet the particular goals of the developers, such as compatibility with system-related and company-related constraints that may be different for different implementations. Furthermore, it should be appreciated that such a development effort may be complex and time-consuming, but nevertheless represents a routine activity for one skilled in the art given this disclosure.

[0015] The present subject matter will now be described with reference to the accompanying drawings. Various structures, systems, and components are shown schematically in the drawings for purposes of illustration only, and are not intended to obscure the present disclosure with details that would be apparent to those skilled in the art. Nevertheless, the appended drawings are intended to describe and explain illustrative examples of the present invention. The terms and concepts used herein should be understood and construed to have a meaning consistent with the understanding of those terms and concepts to those skilled in the art.

[0016] No specific definition of a term or phrase is intended, i.e., a definition that differs from the usual and typical understanding of one skilled in the art when the term or phrase is used consistently herein. If a term or phrase is intended to have a specific meaning, i.e., a meaning that differs from that of one skilled in the art, such a specific definition will be explicitly stated in the description in a defining manner, thereby directly and unambiguously providing the specific definition for the term or phrase.

[0017] The present invention is based on the concept that antenna structures can be efficiently arranged close to the actual semiconductor chip by incorporating the respective antenna structures, ie, antenna regions, and a corresponding reflector or ground plane in the package material that can be used to enclose the semiconductor chip and a corresponding wafer-level redistribution system.For this purpose, the housing material can be provided in a two-stage sequence, wherein in the first step the required redistribution layer is provided in conjunction with a reflector or a ground plane for the entire antenna system, while the remaining housing material is produced in a second step, wherein before or after the formation of the second region of the housing material at least contact elements of a metallization structure for electrically connecting the structure are produced.

[0018] In some illustrative embodiments, the antenna structures, i.e., the antenna regions, the ground plane for the antenna system, and the semiconductor chip, are provided as a stacked structure, wherein at least some of these components overlap laterally when viewed from a height direction of the corresponding component stack. That is, when viewing the packaged semiconductor device in plan view, i.e., along the corresponding height direction, at least one of the one or more antenna structures is arranged laterally within the outline of the semiconductor chip, thereby contributing to an extremely space-saving structure that enables wafer-level packaging and further ensures short electrical connections between the antenna structures and the semiconductor chip.

[0019] Manufacturing the wafer-level chip package based on a two-step process, for example, through a two-step molding process, enables suitable control of dimensions, in particular a thickness, of the corresponding cavity that accommodates the semiconductor chip. Furthermore, the antenna structures or antenna regions can be positioned on the package in an extremely precise manner, while the flatness of the respective antenna structures is also controlled in a very precise process, since the two-step process allows for intermediate leveling steps to reduce the height deviations between the planes of the antenna structures as well as intra-plane deviations of the antenna structures with respect to the ground plane. In this way, a high-performance antenna system with superior directional properties can be implemented due to the extremely planar design of the antenna structures and the one or more ground planes.In particular, if a plurality of individually controllable antenna structures are provided, extremely precise control of the direction of the emitted radiation can be achieved, since the efficiency of such control strategies depends significantly on the flatness of the individual antenna structures. Furthermore, by incorporating the antenna structures into the housing material, the corresponding superior material properties can be advantageously utilized, while further flexibility is obtained by using at least two separate process steps for applying the housing material, since a thickness thereof, i.e., a distance between the antenna structures and the one or more ground planes, can be precisely adjusted depending on the material properties, the wavelength of the radiation(s) to be emitted, and the like.

[0020] Fig. 1 schematically shows a top view of a semiconductor device 100 in a packaged state, or in a state in which it is in a housing. The semiconductor device 100 is further part of a substrate or wafer 101 that may contain multiple semiconductor devices of the same type (not shown). This means that the semiconductor device 100 located in the housing still needs to be separated in order to be connected to another housing substrate (not shown) or a printed circuit board (not shown).

[0021] In this phase, the packaged semiconductor device 100 includes a semiconductor chip 110, which is to be understood as a component that may have corresponding electronic components therein, such as transistors, resistors, capacitors, inductors, and the like, which, depending on the overall circuit design of the semiconductor chip 110, form at least one circuit to be connected to an antenna system. Depending on the complexity of the semiconductor chip 110, even a complete system, i.e., several functional circuit regions that together represent the function of a specific electronic system, may be incorporated into the semiconductor chip 110. As previously explained, radio frequency (RF) components in particular are to be integrated in order to impart wireless connectivity to the packaged semiconductor device 100.Consequently, the semiconductor chip 110 may include fast switching transistor elements that include signal processing for signals in the frequency range of approximately 20-110 GHz depending on the requirements for wireless communication of the semiconductor device 100 with peripheral components.

[0022] Furthermore, the semiconductor device 100 may comprise a package material 120, which may be provided in the form of any suitable dielectric material, such as epoxy resin-based materials and the like, as is typically used in the incorporation of semiconductor chips into a wafer-level package. It should be noted that in some illustrative embodiments, the package material 120 may be a substantially continuous material composition, regardless of the fact that the package material 120 is applied in at least two separate process steps, while in other cases, the package material 120 may have a different material composition in lateral directions, i.e., in Fig. 1, in the horizontal and vertical direction, and / or in a height direction, ie, in Fig. 1, a direction perpendicular to the plane of the Fig. 1.

[0023] The housing material 120 may include therein, on or near a corresponding surface, one or more antenna structures or regions 135A..., 135F made of a suitable conductive material, such as copper, copper alloys, aluminum, silver, gold, and the like. Although the present invention includes the possibility of a single antenna region or structure 135 in some illustrative embodiments, in other illustrative embodiments, two or more antenna structures 135A..., 135F are provided with a lateral position such that at least one of the plurality of antenna structures 135A..., 135F lies within an outline 111 of the semiconductor chip 110. That is, at least one of the antenna structures 135A..., 135F lies within the outline 111, while in another illustrative embodiment, as shown, for example, in Fig. 1, each of the plurality of antenna structures 135A..., 135F lies at least partially within the outline 111 and thus overlaps the chip area delimited by the outline 111 when viewed in the height direction. Furthermore, it should be noted that although six antenna structures 135A..., 135F are shown in Fig. 1, a different suitable number of antenna structures may be configured, depending on the overall component requirements. Furthermore, the specific lateral shape of the antenna structures 135A..., 135F and their size may also be adjusted according to the overall requirements. As will become apparent from the following description, the present invention provides techniques in which a high degree of flexibility is achieved in the design and positioning of corresponding antenna structures.

[0024] Corresponding manufacturing techniques for producing the semiconductor component 100 located in the housing, as described in Fig. 1 are described below in the context of Fig. 3A - 3D and 4A - 4E explained.

[0025] Fig. 2A schematically shows a cross-sectional view of a semiconductor device 200 which has basically the same structure as the semiconductor device 100 shown in Fig. 1, except for the size and number of antenna structures provided in a corresponding housing material. As shown, the semiconductor device 200 may include a semiconductor chip 210 having a first surface 212 and an opposite second surface 213. With regard to the overall structure of the semiconductor chip 210, reference is also made to the semiconductor chip 110, which was previously described in connection with the Fig. 1 is explained.

[0026] Furthermore, in the embodiment shown, the second surface 213 may represent a "functional" or "active" surface, which may include a plurality of contact pads (not shown) that may represent respective "endpoints" of a metallization system (not shown) that provides electrical connection to the electronic components in the semiconductor chip 210. The semiconductor chip 210 may be enclosed by a package material 220, such as a plastic material based on epoxy resin, polymer materials, and the like, to provide mechanical strength, electrical integrity, and the like to the semiconductor chip 210. As shown, the package material 220 may include a first region of a first dielectric material 220A surrounding and thus in contact with the semiconductor chip 210, while a second region or second dielectric material 220B is formed "over" the first region 220A.The first and second regions 220A, 220B may represent the same housing material and may thus have substantially identical properties with regard to high-frequency response, mechanical robustness, thermal behavior, and the like. Consequently, in such cases, the "response" of the housing material 220 as a whole to corresponding thermal, mechanical, electrical, or other stimuli is efficiently predictable. It should be noted that the material properties of the housing material 220 can be efficiently tailored by creating any type of composite material, for example, by blending an appropriate base material, such as an epoxy resin or other polymer material, with other components, such as inorganic components in the form of silicon dioxide and the like.

[0027] As can be seen, in some illustrative embodiments, the semiconductor chip 210, the first region of the package material 220A and the second region 220B form a stacked structure, wherein the stacking direction is also referred to as a height direction denoted by 202, ie, the height direction in the vertical direction of the Fig. 2A is located.

[0028] A first redistribution layer 221 may be formed in the package material 220 “over” the first surface 212 of the semiconductor chip 210.

[0029] It should generally be noted that a reference to a relative position along the height direction 202 is to be understood as referring to this position relative to the first surface 212 of the semiconductor chip 210. For example, in this regard, the second surface 213 is arranged "below" the first surface 212.

[0030] The first redistribution layer 221 may represent a layer of conductive material with a suitable structure formed therein to provide contact areas where needed, wherein at least one or more ground layers or ground planes 222 are provided to laterally overlap the semiconductor chip 210. The one or more ground planes 222 may be understood as a two-dimensional conductive region formed to oppose corresponding antenna structures or regions 235A, 235B, 235C, and 235D that form part of a metallization structure 230. That is, the metallization structure 230 is formed in the package material 220 and in particular within the second region 220B.The metallization structure 230 may additionally include corresponding metal lines or regions 236 for connecting the respective antenna structures 235A-235D to corresponding contact elements 237, which in turn connect to a second redistribution layer 223 formed beneath the second surface 213 and electrically connect to the respective on-chip contact pads (not shown) formed in or near the second surface 213. The metal lines or regions 236 and the contact elements may also be referred to as an interconnect structure of the metallization structure 230.Consequently, the antenna structures 235A-235D can be electrically connected to the on-chip components of the semiconductor chip 210 via the respective metal lines 236 and the contact elements 237 of the metallization structure and the second redistribution layer 223, thereby enabling a corresponding individual control of the antenna structures 235A-235D.

[0031] Furthermore, the second redistribution layer 223 is suitably structured to provide an electrical connection to a contact structure 240, which may include solder balls, metal pillars, and the like, for establishing a connection to a further carrier substrate (not shown) or a printed circuit board (not shown). Therefore, in the Fig. 2A, the semiconductor chip 210 is arranged "downward," meaning that electrical contact with the periphery of the semiconductor chip 210 is made via the second surface 213 and the second redistribution layer 223, which further electrically connects to the first redistribution layer 221, for example, to the ground plane 222, and to the metallization structure 230 and thus to the antenna structures 235A-235D. This configuration provides short connections from the chip 210 to the contact structure 240, which is advantageous in the context of fast-operating electronic components that require fast I / O (input / output) capabilities.On the other hand, the antenna structures 235A-235D can further be provided in an extremely space-saving manner, since at least some or all of the antenna structures 235A-235D overlap with the outline of the semiconductor chip 210 and / or are located in the interior thereof with respect to the height direction 202, as was previously described in connection with the semiconductor device 100 of FIG. Fig. 1 is explained.

[0032] Fig. 2B schematically shows a semiconductor device 200A which has essentially the same structure as the semiconductor device 200 of Fig. 2A, except for the orientation of the semiconductor chip 210 along the height direction 202. Consequently, corresponding components are designated by the same reference numerals and repeated explanations of such components are omitted.

[0033] Thus, the semiconductor device 200A includes the package material 220 with the first and second regions 220A, 220B, with the first redistribution layer 221 formed over the first surface 212 of the semiconductor chip 210, which, in contrast to the semiconductor device 200 shown in Fig. 2A, has corresponding on-chip contact pads (not shown) formed in and near the surface 210. Consequently, the first redistribution layer 221, including one or more ground planes 222, may be further structured to suitably connect to the first surface 212. On the other hand, the second redistribution layer 223, formed beneath the second surface 213 of the semiconductor chip 210, may connect to the contact structure 240 by means of suitably patterned and routed lines and may connect to the metallization structure 230 by means of the respective contact elements 237.On the other hand, the contact elements 237 may also establish an electrical connection to the antenna structures 235A-235D, whereby an even shorter length may be established between respective components in the semiconductor chip 210 and the antenna structures 235A-235D, thereby further reducing any negative effects that may be caused by feed lines for the antenna structures 235A-235D.

[0034] With reference to Fig. 3A-3C and Fig. 4A-44E, corresponding manufacturing techniques and strategies are now described that are suitable for manufacturing a packaged semiconductor device, such as the devices 100, 200, 200A previously described in connection with the Fig. 1, Fig. 2A and Fig. 2B can be used.

[0035] Fig. 3A schematically shows a cross-sectional view of a semiconductor device 300 in a manufacturing stage in which a semiconductor chip 310 is embedded in a first region 320A of a package material. With regard to the properties of the region 320A, reference is made to the semiconductor devices 100, 200, and 200A. Furthermore, a first redistribution layer 321 is formed in or on the first region 320A and has a suitable structure so that a connection to a first surface 312 of the semiconductor chip 310 is established. As previously described in connection with the Fig. 2B, the semiconductor chip 310 may have an "upward-facing" configuration such that corresponding electrical connections from the semiconductor chip 310 to the periphery, and in particular into the corresponding package material, may be accomplished by means of the first redistribution layer 321 connecting to the first surface 312. Furthermore, the first redistribution layer 321 may include at least one ground plane 322 overlapping the outline of the semiconductor chip 310 and / or being laterally contained therein when viewed along a height direction 302. Corresponding contact vias 337A, which are to be understood as a first part of corresponding contact elements yet to be formed, may be provided in the first region 320A such that they connect to the first redistribution layer 321.

[0036] The Fig. The semiconductor device 300 illustrated in Figure 3A may be formed according to the following process strategies. In some approaches, the redistribution layer 321 may be formed on the basis of any suitable sacrificial material (not shown), such as a glass material and the like, wherein known patterning techniques may be applied to provide corresponding trenches and openings that may be filled with a suitable conductive material, such as copper, a copper alloy, silver, aluminum, and the like. In this regard, the vias 337A may also be formed, for example, by forming corresponding openings and filling them based on suitable deposition recipes, such as by a plating technique and the like.After forming the first redistribution layer 321 and the vias 337A, the semiconductor chip 310 may be attached to the first redistribution layer 321 using a suitable technique, for example, using an adhesive tape, etc. It should be noted that the attachment of the semiconductor chip 310 is performed at the wafer level, ie, a corresponding wafer containing a plurality of semiconductor chips is attached to a corresponding structure containing a plurality of first redistribution layers 321.

[0037] Subsequently, a suitable dielectric material, i.e., the region 320A of the housing material, is produced, for example, by a casting process, using suitable precursor materials, such as epoxy resin, polymer materials, and the like, and wherein suitable material properties can be adjusted by adding further materials, such as inorganic components in the form of silicon dioxide and the like. During the production of the region 320A, for example, by a casting process, such as a type of injection molding process, the semiconductor chip 310 can be reliably embedded in the material 320A, wherein corresponding cavities within the material 320A can also be filled, for example, corresponding "gaps" between lines and regions of the first redistribution layer 321 and the contact vias 337A are filled.

[0038] Fig. 3B schematically shows the semiconductor device 300 in a more advanced manufacturing phase. That is, after the formation of the region 320A, for example, by a first casting process, the surface of the material 320A in the vicinity of the second surface 313 may be ground and thus planarized and may, if necessary, be patterned, for example, by lithography, such that a second redistribution layer 323 based on a suitable conductive material is formed. In this way, a connection between the first redistribution layer 321 and the second redistribution layer 323 may be established by means of the contact vias 337A. A corresponding electrical connection may be required, for example, to provide a suitable contact structure below the surface 313 for connection to external components.

[0039] Fig. 3C schematically illustrates the semiconductor device 300 in a more advanced manufacturing stage, in which a second region 320B of a package material is formed on and above the first redistribution layer 321. For this purpose, a second molding process based on any suitable precursor material may be performed. As previously explained, the first and second regions 320A, 320B may have substantially identical material properties, thereby providing a cost-efficient manufacturing process based on a material system having highly controllable and predictable material properties.

[0040] The thermal response and mechanical response of the package material 320A, 320B can be determined in advance or during the manufacturing process under certain operating conditions of the device 300, and a correlation between one or more material parameters, such as the material composition, the material thickness, and the like, can be determined to enable a prediction of mechanical stress conditions in the package material 320A, 320B for given operating conditions. Furthermore, a correlation between a thickness of the first and / or second redistribution layer 321, 323 and corresponding stress conditions in the package material 320A, 320B can be determined, thereby providing an efficient technique for controlling the stress in the package material 320A, 320B during operation of the semiconductor device 300 under various operating conditions.That is, upon determining an appropriate correlation, the stress behavior of the package material 320A, 320B can be controlled by adjusting the thickness of one or both of the redistribution layers 321 and 323. Since the package material 320A, 320B can be provided in a two-step deposition process, such as a casting process sequence, the final thickness and flatness for a given material composition can be adjusted very precisely, thereby contributing to improved performance of the finished semiconductor device 300.

[0041] After providing the second region 320B, a patterning process may be applied to form openings through the material 320B, for example, based on laser drilling techniques and the like, to thereby connect to the contact vias 377A. Corresponding openings may then be filled with a suitable conductive material, such as copper, a copper alloy, and the like, which may be accomplished based on plating techniques and the like.

[0042] Fig. 3D schematically illustrates the semiconductor device 300 in a further advanced manufacturing stage. As shown, a metallization structure 330 may be formed in the second region 320B, including respective contact elements 337B, which may be formed by laser drilling and plating, as previously explained, wherein respective antenna structures 335A, 335B may be provided on the uppermost surface of the second region 320B. The antenna structures 335A, 335B and the respective further metal lines and regions may be formed by appropriately patterning the second region 320B, e.g., by lithography and the like, with a subsequent deposition process for depositing a conductive material and a subsequent removal of unnecessary portions thereof. Any known process strategies may be applied in this regard.

[0043] Thereafter, the entire arrangement, including the semiconductor device 300, may be processed to obtain a contact structure 340, which may be accomplished by known process strategies for providing a dielectric material, if required, and for forming suitable contact elements in the form of solder balls, metal pillars, and the like, as is known for flip-chip contact schemes. Thereby, the contact structure 340 is electrically connected to the semiconductor chip 310 by means of the second redistribution layer 323, the contact vias 337A, and the first redistribution layer 321, which also includes the one or more ground planes 322 (see Fig. 3A), electrically connected.

[0044] Fig. 4A schematically illustrates a cross-sectional view of a semiconductor device 400 during various manufacturing stages in the fabrication of a packaged semiconductor device, wherein the package material includes corresponding antenna structures. It should be noted that components of the semiconductor device 400 that are similar or identical to previously described components are designated by the corresponding like reference numerals, except for a leading numeral "4" instead of a "3" or "2" or "1," and corresponding redundant explanation of such components is omitted.

[0045] In Fig. 4A, the semiconductor device 400 has basically the same structure as the semiconductor device 300 in Fig. 3A and thus includes the semiconductor chip 410, which is connected by its first surface 412 to the first redistribution layer 421 formed in and above the first region 420A of a package material. Fig. The device 400 shown in Figure 4A can be manufactured according to the process strategy previously described in connection with the Fig. 3A is explained.

[0046] Fig. 4B schematically shows the semiconductor device 400 in a further advanced manufacturing stage, in which the second redistribution layer 423 may be formed under the second surface 413 of the semiconductor chip 410 and may be connected to the first redistribution layer 421 by means of the contact vias 437A. With regard to a process strategy for producing the in Fig. 4B, reference is made to the semiconductor device 300.

[0047] Fig. 4C schematically shows the semiconductor device 400, wherein contact elements 437B are formed on the first redistribution layer 421 with a suitable height and dimensions to establish an electrical connection from antenna structures yet to be formed to the first redistribution layer 421. The contact elements 437B may be formed on the basis of a sacrificial material 406, which may be provided in the form of a thick resist layer having a thickness that generally corresponds to a desired height of the contact elements 437B. The sacrificial material 406 may be patterned on the basis of a lithography process, wherein the material 406 itself may be a radiation-sensitive material, or it may be patterned on the basis of a radiation-sensitive resist material.By applying a lithography process to pattern at least the contact elements 437B, the dimensions, positions, and in particular the shapes of the contact elements in the height direction can therefore be adjusted very precisely. This means that corresponding openings formed in the sacrificial material 406 can be given any desired shape; for example, very steep sidewalls can be created during the patterning process by applying well-established etching techniques with anisotropic etching behavior. Furthermore, the sidewalls can have a reduced surface roughness compared to, for example, laser-drilled openings, which can also lead to reduced transmission losses, since high-frequency currents typically flow on the surface regions of the conductors, i.e., the contact elements. Therefore, a smooth design of the sidewalls of the contact elements can reduce this "skin effect."Consequently, the electrical properties of the contact elements 437B can be well controlled based on the shape of the contact elements 437B and / or the surface properties, since these contact elements represent an essential part of the feed line of the corresponding antenna structures that are yet to be manufactured.

[0048] Subsequently, the sacrificial material 406 can be removed based on known ablation techniques, such as plasma ashing, wet chemical etching and the like.

[0049] Fig. 4D schematically shows the semiconductor device 400 in a more advanced manufacturing phase in which the second region 420B is provided, for example, by a further casting process, wherein also in this case material properties, the thickness and the like can be suitably adjusted during the deposition process and / or during a subsequent planarization process, such as a grinding process, and the like.

[0050] Fig. 4E schematically shows the semiconductor device 400 with the metallization structure 430, which includes the antenna structures 435A-435D and other metal lines, and the contact elements 437A, which establish the electrical connection between the antenna structures 435A-435D and the first redistribution layer 421 and thus the semiconductor chip 410. Furthermore, the contact structure 440 is provided below the semiconductor chip 410 and is connected thereto by means of the second redistribution layer 423, the contact vias 437A, and the first redistribution layer 421, as also previously explained.

[0051] It should be noted that the Fig. 3A-3D and 4A-4E are described with reference to a "top-up" configuration of the respective semiconductor chips. It should be noted that the previously explained process techniques are also applicable in the context of a "bottom-down" configuration, for example Fig. 2A for the semiconductor device 200. In this case, the corresponding first and second redistribution layers are formed with a suitable structure. Also in this case, at least a part of the connection between the second redistribution layer 223 ( Fig. 2A) and the corresponding antenna structures 235A-235D may be fabricated on the basis of contact vias or contact elements formed on the basis of laser drilling or on the basis of well-controllable patterning strategies with a lithography process and a corresponding anisotropic etching process.

[0052] Thus, the present invention provides manufacturing techniques and corresponding packaged semiconductor devices, wherein the insertion into the package or attachment to the package at the wafer level is accomplished based on a package material applied in a two-step process, thereby achieving increased flexibility in adjusting the overall material parameters. Furthermore, the corresponding antenna structures can be arranged above the semiconductor chip, enabling efficient packaging technology at the wafer level and also ensuring very short electrical connections between the semiconductor chip and the antenna structures.

[0053] It should be noted that the use of terms such as "first," "second," "third," or "fourth" to describe various processes or structures in this application and the appended claims is merely a shorthand reference to such steps / structures, and these terms do not necessarily imply that such steps / structures are manufactured in that order. However, depending on the precise language in the claims, an ordered sequence of such processes may be required.

Claims

[1] Procedure with: Forming a first redistribution layer (221, 421) over a first surface (212, 412) of a semiconductor chip (110, 210, 410), the first redistribution layer (221, 421) comprising at least one antenna ground plane (222); Forming a first dielectric material (220A, 420A) such that it encloses the semiconductor chip (110, 210, 410) and mechanically connects the semiconductor chip (110, 210, 410) to the first redistribution layer (221, 421); Forming a second redistribution layer (223, 423) such that it is in contact with a second surface (213, 413) of the semiconductor chip (110, 210, 410), the second surface (213, 413) being opposite the first surface (212, 412); and Forming a metallization structure (230, 430) in a second dielectric material (220B, 420B), wherein the metallization structure (230, 430) comprises one or more antenna structures (135A-135C, 235A-235D, 435A-435D) and a connection structure, and wherein the connection structure electrically connects the one or more antenna structures (135A-135C, 235A-235D, 435A-435D) to the first redistribution layer (221, 421) and / or the second redistribution layer (223, 423), wherein forming the metallization structure (230, 430) comprises: Forming a first region of the metallization structure (230, 430) before forming the second dielectric material (220B, 420B) and Forming a second region of the metallization structure (230, 430) after forming the second dielectric material (220B, 420B). [2] The method of claim 1, wherein at least one of the one or more antenna structures (135A-135C, 235A-235D, 435A-435D) is laterally arranged to lie within a contour (111) of the semiconductor chip (110) when viewed in a height direction. [3] The method of claim 1, wherein forming the first portion of the metallization structure (430) comprises: patterning a sacrificial material (406) formed over the first redistribution layer (421), and performing a deposition process in the presence of the patterned sacrificial layer (406) such that a conductive material is deposited to form contact elements (437B) of the interconnect structure. [4] The method of claim 3, wherein patterning the sacrificial material (406) comprises performing a lithography process. [5] The method of claim 3, wherein forming the second portion of the metallization structure (430) comprises: forming the second dielectric material (420B) in the presence of the contact elements (437B) and forming at least the one or more antenna structures (435A-435D) in the second dielectric material (420B). [6] The method of claim 1, wherein the first dielectric material (220A, 420A) is formed by a first molding process. [7] The method of claim 6, wherein the second dielectric material (220B, 420B) is formed by a second molding process performed independently of the first molding process. [8] The method of claim 1, wherein the method is performed on an entire semiconductor wafer (101) prior to separation into individual chips (110). [9] RF semiconductor component (100, 200, 300, 400) with: a semiconductor chip (110, 210, 310, 410) configured to process RF signals, the semiconductor chip (110, 210, 310, 410) having a first surface (212, 312, 412) and a second surface (213, 313, 413) opposite thereto; a dielectric housing material enclosing the semiconductor chip (110, 210, 310, 410); a first redistribution layer (221, 321, 421) formed over the first surface (212, 312, 412) of the semiconductor chip (110, 210, 310, 410), wherein the first redistribution layer (221, 321, 421) comprises at least one antenna ground plane (222, 322), and wherein the antenna ground plane (222, 322) is laterally positioned to lie at least partially within a contour (111) of the semiconductor chip (110) when viewed along a height direction; a second redistribution layer (223, 323, 423) formed under the second surface (213, 313, 413) of the semiconductor chip (110, 210, 310, 410); and a metallization structure (230, 330, 430) formed over the first surface (212, 312, 412) and spaced from the first redistribution layer (221, 321, 421) along the height direction and containing one or more antenna structures (135A-135C, 235A-235D, 335A-335B, 435A-435D), wherein at least one of the one or more antenna structures (135A-135C, 235A-235D, 335A-335B, 435A-435D) lies within the outline (111) of the semiconductor chip (110) when viewed along the height direction, wherein the first surface (212, 312, 412) of the semiconductor chip (110, 210, 310, 410) includes contact areas that are electrically connected to the first redistribution layer (221, 321, 421). [10] The RF semiconductor device (100, 200, 300, 400) of claim 9, further comprising contact elements (237, 337A, 437A) extending between the first redistribution layer (221, 321, 421) and the second redistribution layer (223, 323, 423), the contact elements (237, 337A, 437A) electrically connecting the contact pads to a package contact structure for connection to a substrate or a printed circuit board. [11] RF semiconductor component (100, 200, 300, 400) according to claim 9, wherein two or more antenna structures (135A-135C, 235A-235D, 335A-335B, 435A-435D) are provided and each of the two or more antenna structures (135A-135C, 235A-235D, 335A-335B, 435A-435D) is arranged at least partially laterally within the outline (111) of the semiconductor chip (110) when viewed along the height direction. [12] RF semiconductor device (100, 200, 300, 400), with: a semiconductor chip (110, 210, 310, 410) having at least one RF component, wherein the semiconductor chip (110, 210, 310, 410) has a first surface (212, 312, 412) and a second surface (213, 313, 413) opposite thereto; a dielectric housing material enclosing the semiconductor chip (110, 210, 310, 410); a first redistribution layer (221, 321, 421) formed over the first surface (212, 312, 412) of the semiconductor chip (110, 210, 310, 410), wherein the first redistribution layer (221, 321, 421) comprises at least one antenna ground plane (222, 322), and wherein the antenna ground plane (222, 322) is laterally arranged to lie at least partially within a contour (111) of the semiconductor chip (110) when viewed along a height direction; a second redistribution layer (223, 323, 423) formed under the second surface (213, 313, 413) of the semiconductor chip (110, 210, 310, 410); and a metallization structure (230, 330, 430) formed over the first surface (212, 312, 412) and the first redistribution layer (221, 321, 421) along the height direction, wherein the metallization structure (230, 330, 430) includes a plurality of antenna structures (135A-135C, 235A-235D, 335A-335B, 435A-435D), wherein each of the plurality of antenna structures (135A-135C, 235A-235D, 335A-335B, 435A-435D) lies at least partially within the outline (111) of the semiconductor chip (110) when viewed along the height direction, wherein the first surface (212, 312, 412) of the semiconductor chip (110, 210, 310, 410) includes contact pads electrically connected to the first redistribution layer (221, 321, 421), wherein the semiconductor device (100, 200, 300, 400) further comprises contact elements (237, 337A, 437A) extending between the first redistribution layer (221, 321, 421) and the second redistribution layer (213, 313, 413), and wherein the contact elements (237, 337A, 437A) electrically connect the contact pads to a package contact structure for connection to a substrate or a printed circuit board.

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