Semiconductor component, method for manufacturing a semiconductor component and multi-programmable storage device

Abstract

Semiconductor component with: a substrate (110, 210, 310, 410); a gate oxide layer (120, 220, 320, 420) formed on the substrate (110, 210, 310, 410); a gate (130, 230, 330, 430) formed on the gate oxide layer (120, 220, 320, 420); and a spacer that is adjacent to the gate (130, 230, 330, 430) and above the substrate (110, 210, 310, 410), wherein the spacer has a pore (162, 164, 262, 264, 362, 364, 462, 464) that is filled with air; wherein the spacer has the following: a first oxide layer in contact with the gate (130, 230, 330, 430); a first nitride layer in contact with the first oxide layer, wherein the air-filled pore (162, 164, 262, 264, 362, 364, 462, 464) is formed in the nitride layer; a second oxide layer in contact with the first nitride layer; and a second nitride layer in contact with the second oxide layer.

Description

background

[0001] The present invention relates generally to semiconductor devices and methods for their manufacture, and in particular to the manufacture of multi-programmable memory devices (MTP memory devices) with improved data storage.

[0002] Semiconductor devices are used in many different areas of electronics, and improvements in their fabrication and performance are generally desirable. MTP memory devices using high-k spacer materials can exhibit centers with a high charge-trapping effect, potentially creating a path for leakage current and reduced data retention. Therefore, there is a need for an improved MTP memory device and a method for its fabrication.

[0003] DE 10 2017 113 681 A1 discloses a semiconductor device with a gate and a spacer, wherein an adjacent layer is removed to form a trench in which the side walls of the spacer and a CES layer are exposed.

[0004] US 2019 / 0 334 008 A1 describes a semiconductor component with a gate and a spacer.

[0005] US 2013 / 0 020 629 A1 describes a semiconductor component with a spacer made of spaced oxide layers.

[0006] US 2015 / 0 054 054 A1 discloses a semiconductor device with a gate, spacers and an insulating layer between two gates.

[0007] The invention is defined in the claims. Brief description of the drawings

[0008] Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. Fig. Figure 1A is a drawing showing a sectional view of an exemplary semiconductor device with a spacer having an air void according to some embodiments. Fig. Figure 1B is a drawing showing various dimensional features of the exemplary semiconductor device of Fig. 1A according to some embodiments. Fig. Figure 2A is a drawing showing a sectional view of another exemplary semiconductor device with a spacer having an air void according to some embodiments. Fig. 2B is a flowchart illustrating a process for manufacturing the exemplary semiconductor device of Fig. 2A according to some embodiments. The Fig. 2C to 2K are a series of drawings that illustrate the steps of the process of Fig. 2B according to some embodiments. Fig. Figure 3A is a drawing showing a sectional view of another exemplary semiconductor device with a spacer having an air void according to some embodiments. Fig. 3B is a flowchart illustrating a procedure for manufacturing the exemplary semiconductor device of Fig. 3A according to some embodiments. The Fig. 3C to 3K are a series of drawings that illustrate the steps of the process of Fig. 3B according to some embodiments. Fig. Figure 4 is a drawing showing a sectional view of another exemplary semiconductor device with a spacer having an air void according to some embodiments. Fig. Figure 5 is a flowchart showing a method for manufacturing a semiconductor device with a spacer containing an air pore according to some embodiments. Detailed description

[0009] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0010] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0011] The present invention provides various embodiments of a semiconductor device in which one or more spacers with an air void created therein are used, which advantageously leads to better insulation and thus to improved data storage. The air voids can have the effect of giving the spacer a lower effective dielectric constant. This, in turn, can advantageously reduce stray / overlap capacitances, and thus also reduce the creepage distance between a floating gate and the spacer.

[0012] Now let's move on to... Fig. Figure 1A shows a semiconductor device 100 with an air-filled spacer according to some embodiments. The semiconductor device 100 can generally be a memory device that enables data storage. For example, the semiconductor device 100 can be a non-volatile memory that retains its data even without power. In some embodiments, the semiconductor device 100 is a multi-programmable memory device (MTP memory device) that allows more than one write operation. In general, MTP memory cells can include transistors, capacitors, conductors, and other suitable materials and components. For example, CMOS devices (CMOS: complementary metal-oxide semiconductor), metal-oxide-semiconductor field-effect transistors (MOSFETs), fin field-effect transistors (FinFETs), and silicon-on-insulator (SOI) devices can be used to fabricate MTP memory cells.However, other similar types of materials and components are also being considered.

[0013] It is shown that the semiconductor device 100 comprises a substrate 110, a gate oxide layer 120, and a gate 130. The substrate 110 can be implemented as an n-substrate or a p-substrate. For example, the substrate 110 can be made from a silicon material (e.g., crystalline silicon) doped with an n-doped element such as arsenic, phosphorus, and other similar dopants. The substrate 110 can also be doped with p-doped elements such as boron and other similar dopants. The substrate 110 can be implemented using a SOI structure, a silicon-on-sapphire (SOS) structure, a solid semiconductor structure, an alloy semiconductor, a compound semiconductor, germanium, and various other suitable materials and combinations thereof. Furthermore, source and drain regions can be fabricated in the substrate 110.In some embodiments, the source and drain regions can be fabricated using ion implantation processes. Any suitable doping materials, including n- and p-precursor materials, such as phosphorus, phosphine, boron, gallium, indium, and other suitable materials, can be used to fabricate the source and drain regions. The substrate 110 can also incorporate insulating structures at its outer periphery to prevent cross-coupling between devices.

[0014] The gate oxide layer 120 is generally a dielectric layer that is produced on the substrate 110 and separates the gate 130 from the substrate 110 and the source and drain terminals produced therein. Accordingly, in some embodiments, the gate oxide layer 120 is produced between the source and drain terminals produced in the substrate 110. The gate oxide layer 120 can be produced on the substrate 110 by processes such as thermal oxidation, protective deposition, structuring, and etching. The gate oxide layer 120 can be produced from a material with a high dielectric constant, such as silicon nitride, aluminum oxide, silicon dioxide, and other suitable materials. In some embodiments, the gate oxide layer 120 has a dielectric constant of about 3.5 or more.

[0015] As in Fig. As shown in Figure 1A, the gate 130 is fabricated on the gate oxide layer 120. In some embodiments, the gate 130 is a floating gate structure that is electrically insulated and made of polysilicon material. In this case, the gate 130 can only be capacitively connected to other regions of the semiconductor device 100, such as the source and drain regions. The gate 130 can also be a metal gate and can have various structures, such as capping layers, etch stop layers, barrier layers, dielectric gate layers, exit work layers, filler metal layers, and other suitable materials. In general, the operation of the semiconductor device 100 can be controlled by a voltage applied to the gate 130.

[0016] Furthermore, it is shown that the semiconductor device 100 has different spacer structures for electrically insulating the gate 130. In general, memory devices can suffer data loss as a consequence of charge loss. The design and structure of the entire spacer structure surrounding the gate 130 can reduce or prevent charge loss and can increase the overall data storage performance of the semiconductor device 100. Some previous approaches considered a domed gate head extending over the surrounding spacer structure. With this structure, poor shielding can occur, particularly at the immediate boundary where the spacer structure contacts the gate. With these approaches, electrical charge can dissipate from the gate through the spacer structure into adjacent electrodes (e.g.,Source and drain terminals) and from the adjacent electrodes back into the gate. Using a gate and / or spacer structure with materials having high dielectric constants can result in a structure with high parasitic capacitances, high (internal and external) stray capacitances, and high overlap capacitances. These phenomena can cause charge loss and data loss.

[0017] It is shown that the semiconductor device 100 has a spacer structure with four main layers on each layer of the gate 130. The entire spacer structure is fabricated adjacent to the gate 130 and above the substrate 110 to prevent charge loss and improve data storage. On the left side of the gate 130, a spacer layer 154 is in contact with the gate 130, a spacer layer 144 is in contact with spacer layer 154, a spacer layer 152 is in contact with spacer layer 144, and a spacer layer 142 is in contact with spacer layer 152.On the right side of gate 130, a spacer layer 156 is in contact with gate 130, a spacer layer 146 is in contact with spacer layer 156, a spacer layer 158 is in contact with spacer layer 146, and a spacer layer 148 is in contact with spacer layer 158. Specifically, spacer layer 144 contains a pore 162, and spacer layer 146 contains a pore 164. These materials together form the entire spacer, which is fabricated adjacent to the gate and over substrate 110 to prevent charge loss and improve data storage. Specifically, gate 130 has a flat or nearly flat head that is flush or nearly flush with a top surface of the spacer.

[0018] In some embodiments, the spacer layers 152, 154, 156, and 158 are oxide layers. These layers can, for example, each be made of a silicon oxide material having a dielectric constant of approximately 3.9. In some embodiments, the spacer layers 142, 144, 146, and 148 are nitride layers. These layers can, for example, each be made of a silicon nitride material having a dielectric constant of approximately 7.5. Together, these materials provide a so-called high-k spacer, which has a relatively high dielectric constant. As in the Fig. 1A and Fig. As shown in Figure 1B, spacer layers 152, 154, 156, and 158 are in contact with the top surface of substrate 110, while spacer layers 142, 144, 146, and 148 are not in contact with the top surface of substrate 110. Although oxide and nitride layers are listed here, it should be understood that other suitable materials can also be used to fabricate a spacer structure for electrically insulating gate 130.

[0019] Pores 162 and 164 are filled with air, which, especially compared to the surrounding spacer materials, has a much lower dielectric constant of approximately 1.0. As explained above and in the Fig. 1A and Fig. As shown in Figure 1B, pore 162 is created in spacer layer 144, and pore 164 is created in spacer layer 146. In some embodiments, pore 162 is completely enclosed by the nitride material of spacer layer 144, and pore 164 is completely enclosed by the nitride material of spacer layer 146. In some embodiments, pores 162 and 164 are created using a dry etching process. Since pores 162 and 164 are filled with air, the overall dielectric constant of the spacer structure is reduced, and therefore the associated stray capacitances, parasitic capacitances, and overlap capacitances are also reduced. These phenomena enable improved data storage and reduced charge loss for a device structure.

[0020] In Fig. 1B is another exemplary semiconductor device 100 shown according to some embodiments. Fig. Section 1B explains relevant dimensions associated with the semiconductor device 100. The variable H G represents the height of gate 130, measured vertically from the top of substrate 110. The variable H SP represents the height of the spacer layer 154, measured vertically from the substrate 110. The variable H SP1 represents the thickness of the spacer layer 156, measured horizontally (i.e., in a direction parallel to the top surface of the substrate 110). The variable H SP2 represents the thickness of the spacer layer 146, measured horizontally, and includes the thickness of the pore 162. The variable H SP3 represents the thickness of the spacer layer 158, measured horizontally. The variable H SP4 represents the thickness of the spacer layer 148, measured horizontally. The variable H SP1+3represents the thickness of a combined material of the spacer layers 156 and 158, located beneath a bottom surface of the spacer layers 146 and 148 and above the substrate 110, the thickness being measured vertically from the top surface of the substrate 110. It should be understood that the semiconductor device 100 is inherently symmetrical or nearly symmetrical, and accordingly, the thickness of the spacer layer 154 is equal to or nearly equal to, for example, the thickness of the spacer layer 156 (T). SP1 ) is.

[0021] What H G and H SP As regards, in some embodiments a ratio of H SP to H Ggreater than 0.95. If it is ensured that the gate 130 has a flat or nearly flat head with respect to the entire spacer structure fabricated adjacent to the gate 130 and above the substrate 110, a structure can be provided to effectively reduce charge loss. What T SP1 Regarding the thickness, in some embodiments it is approximately 1 nm to 15 nm, but thicknesses outside this range are also being considered. What T SP3 Regarding the thickness, in some embodiments it is approximately 5 nm to 30 nm, but thicknesses outside this range are also being considered. Accordingly, T SP3 normally larger than T SP1 , and a ratio of T SP1 to T SP3 In some embodiments, the thickness is approximately 0.025 to 0.5 mm, but thicknesses outside this range are also considered. What T SP1+3As regards, in some embodiments this thickness is equal to or approximately equal to a sum of T SP1 and T SP3 (and is, for example, within 10% of this total), but thicknesses outside this range are also considered.

[0022] If one considers T VRegarding the size of the pore 164 in general, the cross-sectional area of ​​the pore 164 in some embodiments is 5% to 80% of the cross-sectional area of ​​the spacer layer 146, but cross-sectional areas outside this range are also considered. In some embodiments, the pore 164 is completely enclosed by the spacer layer 146 and is entirely formed within it. However, the pore 164 can also be formed such that it is only partially enclosed by the spacer layer 146 and is in contact with the spacer layer 156, the spacer layer 158, and / or the substrate 110. The vertical height of the pore 164 in some embodiments is 10% to 80% of the height of the spacer layer 146, but heights outside this range are also considered.Similarly, in some embodiments, the pore 162 is completely enclosed by and entirely formed within the spacer layer 144. However, the pore 162 can also be formed such that it is only partially enclosed by the spacer layer 144 and is in contact with the spacer layer 152, the spacer layer 154, and / or the substrate 110. In some embodiments, the cross-sectional area of ​​the pore 162 is 5% to 80% of the cross-sectional area of ​​the spacer layer 144, but cross-sectional areas outside this range are also considered. In some embodiments, the vertical height of the pore 162 is 10% to 80% of the height of the spacer layer 144, but heights outside this range are also considered. The positions of the pore 162 and the pore 164 within the spacer layer 144 and the spacer layer 154, respectively, are determined by the following criteria:The spacer layer 146 can be adjusted depending on the intended use (e.g., closer to the substrate 110, closer to the gate 130, etc.). A ratio of T. V to T SP2 In some embodiments, the value is 0.1 to 1, but values ​​outside this range are also considered.

[0023] In Fig. Figure 1B also shows an enlarged view of the top surface of the semiconductor device 100. In particular, it shows that a recess 147 is created in the top surface of the spacer layer 146. In some embodiments, as shown, the recess 147 is etched into the top surface of the spacer layer 146 to reduce stray capacitance and prevent charge loss. A similar recess can be etched into the top surface of the spacer layer 144. It should be understood that these dimensions are only examples and may vary depending on the specific implementation of the semiconductor device 100.

[0024] Now let's move on to the Fig. 2A to 2K, in which an exemplary semiconductor device 200 and an exemplary method 290 for manufacturing the semiconductor device 200 according to some embodiments are shown. The semiconductor device 200 is similar to the semiconductor device 100 in many respects. In particular, Fig. Figure 2A shows a semiconductor device 200 with a substrate 210, a gate oxide layer 220, and a gate 230. These structures are similar to the substrate 110, the gate oxide layer 120, and the gate 130 described above. It is also shown that the semiconductor device 200 has a spacer structure comprising, to the left of the gate 230, spacer layers 254, 244, 252, and 242, and to the right of the gate 230, spacer layers 256, 246, 258, and 248. The spacer layers 242, 244, 246, and 248 are nitride layers and are made, for example, from a silicon nitride material. The spacer layers 252, 254, 256 and 258 are oxide layers and are made, for example, from a silicon oxide material.An air-filled pore 262 is created in the spacer layer 244, and an air-filled pore 264 is created in the spacer layer 246. These structures are similar to the spacer layers 142, 144, 146, 148, 152, 154, 156 and 158 and the pores 162 and 164 described above.

[0025] In particular, in Fig. Figure 2B shows a flowchart illustrating the steps of procedure 290. In particular, the following are shown: Fig. Figures 2C to 2K show various drawings illustrating the steps of Process 290. Process 290 is a method for generating pores in a spacer during the fabrication of the spacer itself. Process 290 is an example of a possible method for fabricating a semiconductor device with air pores in a spacer structure. Further examples will be given later with reference to the Fig. 3A to 3K and Fig. 4 described.

[0026] In step 291, a gate is fabricated on a semiconductor substrate ( Fig. 2C). Step 291 can include fabricating a gate oxide layer 220 on a substrate 210 and fabricating a gate 230 on the gate oxide layer 220. In some embodiments, the gate 230 is made of a polysilicon material, and the gate oxide layer 220 is a dielectric material that separates the gate 230 from source and drain terminals fabricated in the substrate 210. The gate oxide layer 220 can be fabricated by a thermal oxidation process and can have different thicknesses. In some embodiments, the gate 230 is a floating gate that is electrically isolated, for example, as part of a floating-gate MOSFET or, more generally, a floating-gate transistor. As shown, the gate oxide layer 220 is produced on the substrate 210, and the gate 230 is produced on the gate oxide layer 220.

[0027] In step 292, a first oxide layer is deposited over the gate and over the substrate ( Fig. 2D). Step 292 may include the deposition of an oxide layer forming the spacer layers 254 and 256. The first oxide layer is the first layer in contact with the gate 230 as part of a larger spacer structure designed to electrically insulate the gate 230 and prevent charge loss. In some embodiments, the first oxide layer deposited in step 292 has a thickness of 8 nm. However, the first oxide layer may also be somewhat thicker or thinner, for example, from about 6.5 nm to 9.5 nm. Depending on the intended use, thicknesses outside this range are also considered. The first oxide layer may be made of silicon oxide or another oxide material. As shown, the first oxide layer is deposited over the gate 230 and over the substrate 210.

[0028] In step 293, a first nitride layer is deposited over the first oxide layer ( Fig. 2E). Step 293 may include the deposition of a silicon nitride layer forming the spacer layers 244 and 246. The first nitride layer can thus be in contact with the first oxide layer, and it forms a second layer of the larger spacer structure that electrically insulates the gate 230. In some embodiments, the first nitride layer deposited in step 293 has a thickness of 15 nm. However, the first nitride layer may also be somewhat thicker or thinner and may, for example, have a thickness of about 12 nm to 18 nm. Depending on the intended use, thicknesses outside this range are also considered. The first nitride layer may be made of silicon nitride or another similar material. As explained above, silicon nitride has a dielectric constant of about 7.5, which is higher than the dielectric constant of silicon oxide.As shown, the first nitride layer is deposited over the first oxide layer.

[0029] In step 294, the first nitride layer is etched ( Fig. 2F). As in Fig. As shown in Figure 2F, step 294 can include shaping the first nitride layer such that two vertical portions of the first nitride layer remain. As shown, one top surface of these vertical portions is flush or nearly flush with a top surface of the first oxide layer. Due to the etching process performed in step 294, the thickness of the remaining vertical portions of the first nitride layer is approximately 12 nm in some embodiments. However, the thicknesses of these vertical portions can also be larger or smaller, for example, approximately 10 nm to 14 nm. Depending on the intended use, thicknesses outside this range are also considered. In some embodiments, the etching process performed in step 294 is a dry etching process.

[0030] In step 295, a second oxide layer is deposited over the first oxide layer and the etched first nitride layer ( Fig. 2G). Step 295 may include the deposition of an oxide layer forming the spacer layers 252 and 258. In some embodiments, the second oxide layer deposited in step 295 has a thickness of 50 nm. However, the second oxide layer may also be somewhat thicker or thinner and may, for example, have a thickness of approximately 30 nm to 70 nm. Depending on the intended use, thicknesses outside this range are also considered. Like the first oxide layer, the second oxide layer may also be made of silicon oxide or another similar oxide material. As in Fig. As shown in 2G, the second oxide layer is deposited over the first oxide layer and the etched first nitride layer.

[0031] In step 296, the second oxide layer is etched ( Fig. 2H). As in Fig. As shown in Figure 2H, step 296 can include shaping the second oxide layer such that two vertical portions of the second oxide layer remain. As shown, one top surface of these vertical portions is flush or nearly flush with the top surfaces of the etched first nitride layer and the first oxide layer. Due to the etching process performed in step 296, the thickness of the remaining vertical portions of the second oxide layer is approximately 30 nm in some embodiments. However, the thicknesses of these vertical portions can also be larger or smaller, for example, approximately 25 nm to 35 nm. Depending on the intended use, thicknesses outside this range are also considered. In some embodiments, the etching process performed in step 296 is a dry etching process.

[0032] In step 297, the first nitride layer is etched to create pores (see Fig. 2I). Step 297 may include generating the pores 262 and 264 in the spacer layer 244 and 246, respectively. In some embodiments, the etching process performed in step 297 is a wet etching process. In the etching process performed in step 297, the etched first nitride layer, located between the first oxide layer and the etched second oxide layer, may be completely or partially removed to generate the pores 262 and 264. In some embodiments, the cross-sectional area of ​​pore 262 is 5% to 80% of the cross-sectional area of ​​the spacer layer 244, and the cross-sectional area of ​​pore 264 is 5% to 80% of the cross-sectional area of ​​the spacer layer 246, but depending on the intended use, cross-sectional areas outside this range are also considered.In some embodiments, the vertical height of pore 262 is 10% to 80% of the height of spacer layer 244, and the vertical height of pore 264 is 10% to 80% of the height of spacer layer 246. However, depending on the intended use, heights outside this range are also considered. Both pores 262 and 264 can be either completely or partially enclosed by spacer layer 244 or spacer layer 246, respectively. Both pores 262 and 264 are filled with air to prevent charge loss and to enable improved data storage for the semiconductor device 200.

[0033] In step 298, a second nitride layer is deposited over the first oxide layer, the etched second oxide layer, and the now twice etched first nitride layer with the pores created therein ( Fig. 2J). Step 298 may include the deposition of a nitride layer forming the spacer layers 242 and 248. In some embodiments, the second nitride layer deposited in step 298 has a thickness of 15 nm. However, the second nitride layer may also be somewhat thicker or thinner, for example, having a thickness of approximately 10 nm to 20 nm. Depending on the intended use, thicknesses outside this range are also considered. Like the first nitride layer, the second nitride layer may also be made of silicon nitride or another similar nitride material. As in Fig. As shown in Figure 2J, the second nitride layer is deposited over the first oxide layer, the etched second oxide layer, and the now twice-etched first nitride layer with the pores 262 and 264 created therein. Step 298 generally completes the generation of pores throughout the entire spacer structure.

[0034] In step 299, the second nitride layer is etched ( Fig. 2K). Step 299 may include forming the second nitride layer, the first oxide layer, the second oxide layer, and the first nitride layer to produce the spacer layers 242, 252, 244, 254, 256, 246, 258, and 248. As in Fig. As shown in Figure 2K, step 299 involves reducing the height of each of these layers so that the top surface of each layer is flush or nearly flush with the others. As also shown in Figure 2K, step 299 involves reducing the height of each of these layers so that one top surface of each layer is flush or nearly flush with the other. Fig. As shown in Figure 2K, step 299 involves removing horizontal portions of the second nitride layer to create two vertical portions that form the spacer layers 242 and 248. Additionally, the spacer layers 242 and 248 are formed with a beveled top surface that slopes downwards and away from the gate 230.

[0035] Now let's move on to the Fig. 3A to 3K, in which an exemplary semiconductor device 300 and an exemplary method 390 for fabricating the semiconductor device 300 according to some embodiments are shown. The semiconductor device 300 is similar to the semiconductor device 100 in many respects. In particular, in Fig. Figure 3A shows a semiconductor device 300 with a substrate 310, a gate oxide layer 320, and a gate 330. These structures are similar to the substrate 110, the gate oxide layer 120, and the gate 130 described above. It is also shown that the semiconductor device 300 has a spacer structure comprising, to the left of the gate 330, a spacer layer 354, a spacer layer 244, a pore 362, and a spacer layer 352, and to the right of the gate 330, a spacer layer 356, a pore 364, and a spacer layer 358. The spacer layers 352, 354, 356, and 358 are oxide layers and are made, for example, from a silicon oxide material. The pores 362 and 364 are filled with air. These structures are similar to the spacer layers 152, 154, 156 and 158 and the pores 162 and 164 described above.

[0036] However, as also in Fig. As shown in Figure 3A, a contact etch stop layer (CESL) 370 and electrodes 382, ​​384, and 386 are fabricated. In the semiconductor device 300, the CESL 370 largely replaces the spacer layers 142, 144, 146, and 148 of the semiconductor device 100. The CESL 370 can be fabricated from materials such as silicon nitride, silicon oxide and silicon nitride, silicon nitride and / or silicon carbide, and from other suitable materials and combinations thereof. The electrodes 382, ​​384, and 386 can be fabricated from nickel silicide or other suitable materials, or from combinations of other suitable materials. In some embodiments, electrode 382 provides a conductive connection for a source region of the semiconductor device 300, electrode 384 provides a conductive connection for the gate 330, and electrode 386 provides a conductive connection for a drain region of the semiconductor device 300.As will be explained in more detail later, unlike in process 290, the pores 362 and 364 in process 390 are created by depositing the CESL 370 instead of by depositing the second nitride layer as in process 290. Furthermore, in process 390, the pores 362 and 364 are created after the electrodes 382, ​​384 and 386 have been manufactured, as will be explained in more detail later.

[0037] In particular, in Fig. Figure 3B shows a flowchart illustrating the steps of procedure 390. In particular, the following are shown: Fig. Figures 3C to 3K show various drawings illustrating the steps of Process 390. Process 390 is a method for creating pores in a spacer after the fabrication of the spacer itself and after metallization of the source, gate, and drain regions of the semiconductor device. Process 390 is an example of another possible method for fabricating a semiconductor device with air pores in a spacer structure. Another exemplary structure that can be fabricated using a similar method will be described later with reference to Fig. 4 described.

[0038] In step 391, a gate is fabricated on a semiconductor substrate, a first oxide layer is deposited over the gate and the substrate, and a first nitride layer is deposited over the first oxide layer ( Fig. 3C). Step 391 is similar to steps 291, 292, and 293 of process 290. Step 391 may include fabricating a gate oxide layer 320 on a substrate 310, fabricating a gate 330 on the gate oxide layer 320, depositing an oxide layer forming the spacer layers 354 and 356 over the gate 330 and the substrate 310, and depositing, over the oxide layer, a nitride layer (ultimately forming layers 344 and 346 on opposite sides of the gate 330) similar to the nitride layer deposited in step 293 of process 290. In some embodiments, the first oxide layer deposited in step 391 has a thickness of 8 nm. However, the first oxide layer can also be somewhat thicker or thinner, for example, with a thickness of approximately 6.5 nm to 9.5 nm. Depending on the intended use, thicknesses outside this range are also considered.The first oxide layer can be made from silicon dioxide or another similar oxide material. As explained above, silicon dioxide has a dielectric constant of about 3.9. As in . Fig. As shown in Figure 3C, the first oxide layer is deposited over the gate 330 and over the substrate 310. In some embodiments, the first nitride layer, deposited in step 391, has a thickness of 15 nm. However, the first nitride layer can also be somewhat thicker or thinner, for example, having a thickness of about 12 nm to 18 nm. Depending on the intended use, thicknesses outside this range are also considered. The first nitride layer can be made of silicon nitride or another similar material. As explained above, silicon nitride has a dielectric constant of about 7.5, which is higher than the dielectric constant of silicon oxide. As shown in Fig. As shown in 3C, the first nitride layer is deposited over the first oxide layer.

[0039] In step 392, the first nitride layer is etched ( Fig. 3D). Step 392 is similar to step 294 of procedure 290. As in Fig. As shown in 3D, step 392 can include shaping the first nitride layer such that two vertical portions of the first nitride layer remain. As shown, one top surface of the vertical portions is flush or nearly flush with a top surface of the first oxide layer. Due to the etching process performed in step 392, the thickness of the remaining vertical portions of the first nitride layer is approximately 12 nm in some embodiments. However, the thicknesses of these vertical portions can also be larger or smaller, for example, approximately 10 nm to 14 nm. Depending on the intended use, thicknesses outside this range are also considered. In some embodiments, the etching process performed in step 392 is a dry etching process.

[0040] In step 393, a second oxide layer is deposited over the etched first layer of silicon nitride and the first oxide layer ( Fig. 3E). Step 393 is similar to step 295 of method 290. Step 393 may include the deposition of an oxide layer forming the spacer layers 352 and 358. In some embodiments, the second oxide layer deposited in step 393 has a thickness of 50 nm. However, the second oxide layer may also be somewhat thicker or thinner, for example, having a thickness of about 30 nm to 70 nm. Depending on the intended use, thicknesses outside this range are also considered. Like the first oxide layer, the second oxide layer may be made of silicon oxide or another similar oxide material. As shown, the second oxide layer is deposited over the first oxide layer and the etched first nitride layer.

[0041] In step 394, the second oxide layer is etched ( Fig. 3F). Step 394 is similar to step 296 of method 290. Step 394 may include shaping the second oxide layer such that two vertical portions of the second oxide layer remain. As shown, one top surface of these vertical portions is flush or nearly flush with the top surfaces of the etched first nitride layer and the first oxide layer. Due to the etching process performed in step 394, in some embodiments, the thickness of the remaining vertical portions of the second oxide layer is approximately 30 nm. However, the thicknesses of these vertical portions may also be larger or smaller, for example, approximately 25 nm to 35 nm. Depending on the intended use, thicknesses outside this range are also considered. In some embodiments, the etching process performed in step 394 is a dry etching process.

[0042] In step 395, a second nitride layer is deposited over the first oxide layer, the etched first nitride layer, and the etched second oxide layer ( Fig. 3G). In particular, unlike in process 290, the second nitride layer is deposited before the first nitride layer is etched to create pores. Accordingly, unlike in process 290, the deposition of the second nitride layer generally does not terminate the creation of the pores. In some embodiments, the second nitride layer deposited in step 395 has a thickness of 15 nm. However, the second nitride layer deposited in step 395 may also be somewhat thicker or thinner, for example, having a thickness of about 10 nm to 15 nm, but depending on the intended use, thicknesses outside this range are also considered. Like the first nitride layer, the second nitride layer may also be made of silicon nitride or another similar nitride material. As in Fig. As shown in Figure 3G, the second nitride layer is deposited over the first oxide layer, the etched second oxide layer, and the etched first nitride layer.

[0043] In step 396, the second nitride layer and the first oxide layer are etched ( Fig. 3H). Step 396 may include forming the second nitride layer, the first oxide layer, the second oxide layer, and the first nitride layer to produce the spacer layers 342, 352, 344, 354, 356, 346, 358, and 348. As shown, step 396 includes reducing the height of each of these layers such that one top surface of each of these layers is flush or nearly flush with the others. As further shown in Fig. As shown in Figure 3H, step 396 involves removing horizontal portions of the second nitride layer to produce the spacer layers 342 and 348. Additionally, the spacer layers 342 and 348 are formed with a beveled top surface that slopes downwards and away from the gate 330.

[0044] In step 397, a silicide metallization is created on the gate and on the source and drain areas of the substrate ( Fig. 3I). Step 397 can include fabricating the electrodes 382, ​​384, and 386 described above. The source and drain regions can be fabricated in the substrate 310 using methods such as implantation, deposition, doping, heat treatment, and other suitable methods or combinations thereof. Subsequently, a salicidal treatment process can be performed to create conductive connections across these regions and the gate. In particular, step 397 is performed prior to the creation of the pores in the spacer structure.

[0045] In step 398, the first nitride layer is etched to create pores ( Fig. 3J). Step 398 is similar to step 297 of method 290. Step 398 comprises generating the pores 362 and 364. In some embodiments, the etching process performed in step 398 is a wet etching process. In the etching process performed in step 398, the spacer layers 344 and 346 may be completely or partially removed to generate the pores 362 and 364. In some embodiments, the cross-sectional area of ​​pore 362 is 5% to 80% of the cross-sectional area of ​​spacer layer 344, and the cross-sectional area of ​​pore 364 is 5% to 80% of the cross-sectional area of ​​spacer layer 346, but depending on the intended use, cross-sectional areas outside this range are also considered.In some embodiments, the vertical height of pore 362 is 10% to 80% of the height of spacer layer 344, and the vertical height of pore 364 is 10% to 80% of the height of spacer layer 346. However, depending on the intended use, heights outside this range are also considered. Both pores 362 and 364 can be either completely or partially enclosed by spacer layer 344 and CESL 370, or by spacer layer 346 and CESL 370, respectively. Both pores 362 and 364 are filled with air to prevent charge loss and to enable improved data storage for the semiconductor device 300.

[0046] In step 399, a contact etch stop layer is produced over the component structure ( Fig. 3K). Step 399 may include the deposition of the CESL 370 discussed above. After step 399, the formation of pores 362 and 364 is generally complete. After step 398, when all the nitride material used to produce the first and second nitride layers has been removed, in some embodiments the CESL material may fill the gaps around the pores produced in step 398, so that the pores are completely enclosed by the CESL material. In other embodiments, some of the nitride material remains after step 398, and the CESL material is applied over the remaining nitride material, so that the pores are completely enclosed by the remaining nitride material. In still other embodiments, after step 399 the pores are enclosed by a combination of the nitride and CESL materials.

[0047] Now let's move on to... Fig. Figure 4, in which another exemplary semiconductor device 400 with an air-pore spacer according to some embodiments is shown. The semiconductor device 400 is similar to the semiconductor device 100. As shown, the semiconductor device 400 has, for example, a substrate 410, a gate oxide layer 420, and a gate 430. These structures are similar to the substrate 110, the gate oxide layer 120, and the gate 130, respectively, described above. It is also shown that the semiconductor device 400 has a spacer structure comprising, to the left of the gate 430, a spacer layer 454, a pore 462, and a spacer layer 452, and to the right of the gate 430, a spacer layer 456, a pore 464, and a spacer layer 458. The spacer layers 452, 454, 456 and 458 are oxide layers and are made, for example, from a silicon oxide material.Pores 462 and 464 are filled with air. These structures are similar to the spacer layers 152, 154, 156 and 158 and the pores 162 and 164 described above.

[0048] As shown, the semiconductor device 400, like the semiconductor device 300, has a contact etch stop layer (CESL) 470. Similar to the CESL 370, the CESL 470 largely replaces the spacer layers 142, 144, 146, and 148 of the semiconductor device 100. The CESL 470 can be made from materials such as silicon nitride, silicon oxide and silicon nitride, silicon nitride and / or silicon carbide, and from other suitable materials and combinations thereof. Unlike the semiconductor device 300, however, the semiconductor device 400 does not have electrodes similar to electrodes 382, ​​384, and 386. It should be understood that electrodes such as electrodes 382, ​​384, and 386 can be fabricated after the CESL 470 has been deposited, as shown in Fig. 4 is proposed. Procedure 390 can, for example, be modified so that steps 398 and 399 are carried out before step 397.

[0049] In Fig. Figure 5 shows a flowchart illustrating an exemplary process 500 for fabricating a semiconductor device with an air-filled spacer according to some embodiments. Process 500 is similar to processes 290 and 390 described above, but it provides a more general process flow that can be implemented to fabricate a semiconductor device with an air-filled spacer.

[0050] In step 501, a gate oxide layer is fabricated on a semiconductor substrate. Step 501 can, for example, include fabricating the gate oxide layer 120 on the substrate 110 of the semiconductor device 100. In step 502, a gate is fabricated on the gate oxide layer. Step 502 can, for example, include fabricating the gate 130 on the gate oxide layer 120. In step 503, a first spacer layer is fabricated over the gate and the substrate. Step 503 can, for example, include depositing a spacer layer that, during etching, forms the spacer layers 154 and 156 on opposite sides of the gate 130. In step 504, a second spacer layer is fabricated over the first spacer layer.Step 504 can, for example, include the deposition of a spacer layer, which during etching forms the spacer layers 144 and 146 on opposite sides of the gate 130.

[0051] In step 505, a pore is created in the second spacer layer by an etching process. As explained above, in some embodiments, the pore is created in the second spacer layer by a wet etching process. In the example described for process 290, pores 262 and 264 are created during the fabrication of the spacer itself and before salicidalization or deposition of the CESL. In the example described for process 390, pores 362 and 364 are created after salicidalization but before deposition of the CESL 370. In the example described for semiconductor device 400, pores 462 and 464 are created before salicidalization and before deposition of the CESL 470.As explained above, a third and fourth spacer layer (and possibly further layers) can also be deposited once the fabrication of the entire spacer structure is complete. It should be understood that many different methods can be used to fabricate a semiconductor device with an air-filled spacer.

[0052] As explained above, creating an air-filled pore in a spacer of a semiconductor device can improve data storage in memory devices, such as MTP memory devices. As also explained above, various methods can be used to fabricate such a semiconductor device. Because the air-filled pore has a lower dielectric constant than other materials that can be used to fabricate a spacer, parasitic, stray, and overlap capacitances can be reduced. These phenomena can lead to reduced charge loss and improved data storage.

Claims

[1] Semiconductor component with: a substrate (110, 210, 310, 410); a gate oxide layer (120, 220, 320, 420) formed on the substrate (110, 210, 310, 410); a gate (130, 230, 330, 430) formed on the gate oxide layer (120, 220, 320, 420); and a spacer that is adjacent to the gate (130, 230, 330, 430) and above the substrate (110, 210, 310, 410), wherein the spacer has a pore (162, 164, 262, 264, 362, 364, 462, 464) that is filled with air; wherein the spacer has the following: a first oxide layer in contact with the gate (130, 230, 330, 430); a first nitride layer in contact with the first oxide layer, wherein the air-filled pore (162, 164, 262, 264, 362, 364, 462, 464) is formed in the nitride layer; a second oxide layer in contact with the first nitride layer; and a second nitride layer in contact with the second oxide layer. [2] Semiconductor component according to claim 1, wherein the gate (130, 230, 330, 430) is a floating gate. [3] Semiconductor device according to claim 1 or 2, wherein the air-filled pore (162, 164, 262, 264, 362, 364, 462, 464) is completely enclosed by the first nitride layer. [4] Semiconductor device according to claim 1, further comprising a silicide electrode over the gate (130, 230, 330, 430) over a source region and over a drain region of the substrate (110, 210, 310, 410). [5] Semiconductor component according to one of claims 2 to 4, wherein the nitride layer has a depression (147) formed in a top side of the nitride layer opposite the substrate (110, 210, 310, 410). [6] Semiconductor device according to any one of claims 2 to 5, wherein the ratio of the height of the first oxide layer, measured from a top surface of the substrate (110, 210, 310, 410), to the height of the gate (130, 230, 330, 430), measured from the top surface of the substrate (110, 210, 310, 410), is greater than 0.

95. [7] Method for manufacturing a semiconductor device according to any of the preceding claims comprising the following steps: Forming the gate oxide layer (120, 220, 320, 420) on the substrate (110, 210, 310, 410); Manufacturing the gate (130, 230, 330, 430) on the gate oxide layer (120, 220, 320, 420); Deposition of the first oxide layer (154, 156; 254, 256; 354, 356; 454; 456) over the gate (130, 230, 330, 430) and over the substrate (110, 210, 310, 410); Deposition of the first nitride layer (144, 146; 244, 246; 344, 346; 470) over the first oxide layer (154, 156; 254, 256; 354, 356; 454; 456); Deposition of the second oxide layer in contact with the first nitride layer; Deposition of the second nitride layer in contact with the second oxide layer; Positioning the silicide electrode over the source area or over the drain area of ​​the substrate (110, 210, 310, 410); and then Creating the air-filled pore (162, 164, 262, 264, 362, 364, 462, 464) in the first nitride layer (144, 146; 244, 246; 344, 346; 470) by an etching process. [8] Method according to claim 7, wherein generating the air-filled pore (162, 164, 262, 264, 362, 364, 462, 464) in the first nitride layer (144, 146; 244, 246; 344, 346; 470) comprises generating the air-filled pore (162, 164, 262, 264, 362, 364, 462, 464) in the first nitride layer (144, 146; 244, 246; 344, 346; 470) by a wet etching process. [9] The method of claim 7 or 8, further comprising: After creating the air-filled pore (162, 164, 262, 264, 362, 364, 462, 464) in the first nitride layer (144, 146; 244, 246; 344, 346; 470), a contact etch stop layer is deposited over the gate (130, 230, 330, 430), over the first oxide layer (154, 156; 254, 256; 354, 356; 454; 456) and over the second oxide layer (152, 158; 252, 258; 352, 358; 452; 458). [10] Method according to claim 7 or 8, comprising, prior to the production of the silicide electrode, the deposition of the second oxide layer (152, 158; 252, 258; 352, 358; 452; 458) in contact with the first nitride layer (144, 146; 244, 246; 344, 346; 470) and the deposition of the second nitride layer in contact with the second oxide layer (152, 158; 252, 258; 352, 358; 452; 458). [11] Multi-programmable memory device with: a substrate (110, 210, 310, 410); a gate oxide layer (120, 220, 320, 420) formed on the substrate (110, 210, 310, 410); a gate (130, 230, 330, 430) formed on the gate oxide layer (120, 220, 320, 420); and a spacer which has the following features: an oxide layer that forms adjacent to the gate (130, 230, 330, 430) and above the substrate (110, 210, 310, 410), and a nitride layer in contact with the oxide layer and having an air-filled pore (162, 164, 262, 264, 362, 364, 462, 464); wherein the oxide layer comprises a first oxide layer and the nitride layer comprises a first nitride layer and the spacer further comprises a second oxide layer in contact with the first nitride layer and a second nitride layer in contact with the second oxide layer. [12] Device according to claim 11, wherein the air-filled pore (162, 164, 262, 264, 362, 364, 462, 464) is completely enclosed by the nitride layer. [13] Device according to claim 11 or 12, wherein the nitride layer has a depression (147) formed in a top side of the nitride layer opposite the substrate (110, 210, 310, 410). [14] Device according to any one of claims 11 to 13, wherein the gate (130, 230, 330, 430) comprises a floating gate and the ratio of the height of the first oxide layer, measured from the top of the substrate (110, 210, 310, 410), to the height of the floating gate (130, 230, 330, 430), measured from the top of the substrate (110, 210, 310, 410), is greater than 0.

95. [15] Device according to any one of claims 11 to 14, wherein the ratio of the thickness of the first oxide layer, measured in a direction parallel to the top of the substrate (110, 210, 310, 410), to the thickness of the second oxide layer, measured in a direction parallel to the top of the substrate (110, 210, 310, 410), is 0.025 to 0.5.

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