DISPLAY DEVICE

Abstract

Display device (100), comprising: a display panel (110) in which a plurality of gate lines (GL), a plurality of data lines (DL) and a plurality of subpixels (SP) are arranged; at least one hole area (HA, HA1, HA2) located in an active area (A / A) of the display panel (110); and a border area (BA) that is arranged in such a way that it touches an outer perimeter of the at least one hole area (HA, HA1, HA2), which features a multitude of data lines (DL): a plurality of first data lines (DL1) through which a data voltage (Vdata) is provided to first color subpixels from the plurality of subpixels (SP), wherein a portion of each of the plurality of first data lines (DL1) is arranged in the border region (BA); and a plurality of second data lines (DL2) through which the data voltage (Vdata) is provided to second color subpixels from the plurality of subpixels (SP), wherein a portion of each of the plurality of second data lines (DL2) is arranged in the boundary region (BA), wherein the plurality of second data lines (DL2) are arranged on a layer above a layer on which the plurality of first data lines (DL1) are arranged; where the multitude of first data lines (DL1) provide the data voltage (Vdata) to further third color subpixels, and a peak wavelength of light emitted by the second color subpixels is smaller than a peak wavelength of light emitted by the first color subpixels, and larger than a peak wavelength of light emitted by the third color subpixels.

Description

BACKGROUND area

[0001] The embodiments relate to a display device. Description of the related technique

[0002] With the development of the information society, the demand for a variety of image display devices has increased. In this context, a number of display devices, such as liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs), have become widely used.

[0003] Such a display device may include a display panel with a multitude of subpixels for displaying images and a multitude of control circuits for controlling the subpixels arranged on the display panel.

[0004] Furthermore, the display device can provide a function of detecting an object approaching the display panel, performing input processing based on detection information, or capturing an image of the object approaching the display panel and displaying the captured image on the display panel.

[0005] Therefore, depending on the required function, the display device can incorporate sensors, such as a proximity sensor and a camera sensor. Furthermore, such a sensor can be located in a border area of ​​the display panel where no images are shown.

[0006] Alternatively, in some cases a camera sensor or similar may be located in a sub-area of ​​an active area of ​​the display panel where images are displayed, in order to prevent the display panel's border area from becoming larger.

[0007] In this case, since a sensor area in which a sensor is located is in an active area in which display operating components such as signal lines and subpixels are located, it can be difficult to arrange the display operating components in the active area, which is problematic.

[0008] Furthermore, the presence of the sensor area can cause the structure of signal lines, subpixels, and the like, arranged around the sensor area, to differ from those in other areas. Consequently, the presence of a sensor in the active area can degrade the quality of the display panel.

[0009] EP 3 176 771 A2 discloses a display device with a through-hole arranged in the pixel area. The through-hole is surrounded by a circular first non-display area in which data lines and gate lines, connected to pixels adjacent to the through-hole and curved around the through-hole, are arranged. BRIEF SUMMARY

[0010] The invention provides a solution capable of improving the uniformity of images displayed by the subpixels located in the active area surrounding the sensor area.

[0011] The invention provides a display device according to claim 1 and a display device according to claim 12. Further embodiments are described in the dependent claims.

[0012] A weakening of the luminance, which would be caused by an increase in the load on data lines through which the subpixels located around the hole area are driven, can be prevented, thereby improving the uniformity of images displayed by subpixels around the hole area. DESCRIPTION OF THE DRAWINGS

[0013] The above and other objectives, features and advantages of the present invention will be more clearly understood from the following detailed description, together with the accompanying drawings, in which: Fig. 1 schematically represents a configuration of a display device according to embodiments; Fig. 2 represents a circuit structure of a subpixel in the display device according to embodiments, as well as control times of the subpixel; Fig. 3 structures in which a hole area is provided in an active area of ​​the display device according to embodiments; Fig. 4 represents a structure in which signal lines are arranged in a border area that is located around the hole area provided in the active area of ​​the display device according to embodiments; Fig. 5 represents a further structure in which signal lines are arranged in a border area located around the hole area provided in the active area of ​​the display device according to embodiments; Fig. 6 represents an arrangement structure of data lines that control subpixels located around the hole area provided in the active area of ​​the display device according to embodiments; Fig. 7 represents another structure in which data lines are arranged in the border area surrounding the hole area provided in the active area of ​​the display device according to embodiments; Fig. 8 represents a structure in which data lines are arranged outside and inside the border area surrounding the one in Fig. The area of ​​holes shown is located around 7; Fig. 9 represents a structure in which data lines are arranged in the border area located between two hole areas; and Fig. 10 and Fig. Present 11 examples where the uniformity of luminance in the active region is improved by the in Fig. 7. Illustrated arrangement structure of the data lines. DETAILED DESCRIPTION

[0014] In the following description of examples or embodiments of the present invention, reference is made to the accompanying drawings, which illustrate certain examples or embodiments that can be implemented and in which the same reference numbers and symbols may be used to designate the same or similar components, even if they are shown in different accompanying drawings. Furthermore, in the following description of examples or embodiments of the present invention, detailed descriptions of well-known functions and components included herein are omitted where it is found that such a description may make the subject matter rather unclear in some embodiments of the present invention.In the case of expressions such as "containing," "exhibiting," "encompassing," "forming," "made of," "formed of," used herein, it is generally intended that other components may be added, unless the expressions are used with the phrase "only." As used herein, singular forms are intended to include plural forms, unless the context clearly indicates otherwise.

[0015] Terms such as “first”, “second”, “A”, “B”, “(A)” or “(B)” may be used herein to describe elements of the present invention. Each of these terms is not used to define the essentiality, arrangement, sequence or number of elements, etc., but is used solely to distinguish the corresponding element from other elements.

[0016] When it is mentioned that a first element is "connected or coupled with" a second element, "contacts or overlaps" the second element, etc., this should be interpreted to mean that the first element can not only be "directly connected or coupled" with the second element, or that the second element can "directly contact or overlap," but that a third element can also be "inserted" between the first and second elements, or that the first and second elements can be "connected or coupled" via a fourth element, "contact or overlap" each other via the fourth element, etc. In this context, the second element can be contained within at least one of two or more elements that are "connected or coupled" to each other, "contact or overlap" each other, etc.

[0017] When temporally relating expressions such as "after", "following", "next", "before", and the like are used to describe processes or activities of elements or configurations, or flows or steps in operating, processing, or manufacturing procedures, these expressions can be used to describe non-consecutive or non-sequential processes or activities unless the expression "directly" or "immediately" is used with them.

[0018] Furthermore, whenever any dimensions, relative sizes, etc., are mentioned, it should be noted that numerical values ​​for elements or features, or corresponding information (e.g., level, range, etc.), contain a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no corresponding description is provided. Additionally, the term "may" fully encompasses all meanings of the term "can."

[0019] Fig. Figure 1 schematically represents a configuration of a display device 100 according to embodiments.

[0020] Referring to Fig. 1 The display device 100 according to embodiments has a display panel 110 with a plurality of subpixels SP, and a gate driver 120, a data driver 130, a controller 140 and the like for controlling the display panel 110.

[0021] The display panel 110 can have an active area A / A, which serves as an image display area, with the plurality of subpixels SP arranged in the active area A / A, and a non-active area N / A, which is located outside the active area A / A, with signal lines or the like arranged in the non-active area N / A.

[0022] In the active area A / A of display panel 110, a multitude of gate lines GL and a multitude of data lines DL are arranged. The subpixels SP can be arranged in areas where the gate lines GL cross the data lines DL.

[0023] Each of the subpixels SP can have an emission device ED, and two or more subpixels SP can form a single pixel.

[0024] The gate driver 120 is controlled by the controller 140 and controls the drive times of the multitude of subpixels SP by sequentially outputting a scan signal to the multitude of gate lines GL, which are arranged in the display panel 110.

[0025] The gate driver 120 can have one or more integrated gate driver circuits (GDICs) and can be located on one side or both sides of the display panel 110, depending on the control method.

[0026] The data driver 130 receives image data from the controller 140 and converts the image data into an analog data voltage Vdata. Furthermore, the data driver 130 outputs the data voltage Vdata to each of the data lines DL at the times when the scan signal is applied via the gate lines GL, so that the subpixels SP have light intensities corresponding to the image data.

[0027] The Data Driver 130 can have one or more integrated source driver circuits (SDICs).

[0028] The controller 140 provides a variety of control signals to the gate driver 120 and the data driver 130 to control the operations of the gate driver 120 and the data driver.

[0029] Controller 140 controls gate driver 120 to output the scan signal at times defined by frames. Controller 140 converts image data into a data signal format readable by data driver 130 by receiving image data from an external source and outputting the converted image data to data driver 130.

[0030] The Controller 140 receives a variety of timing signals, in addition to the image data, from an external source (e.g., a host system). These timing signals can include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data release signal (DE), a clock signal (CLK), and the like.

[0031] The controller 140 can generate a variety of control signals according to the variety of timing signals received from the external source and output the control signals to the gate driver 120 and the data driver 130.

[0032] For example, the controller 140 outputs a variety of gate control signals GCS, including a gate start pulse GSP, a gate shift clock signal, a gate output enable signal GOE, and the like, to control the gate driver 120.

[0033] Here, the gate start pulse (GSP) controls the start-up times of one or more GDICs at gate 120. The gate shift clock (GSC) is a clock signal that is input to one or more GDICs to control the shift times of the scan signal. The gate output enable signal (GOE) determines the timing information of one or more GDICs.

[0034] Furthermore, the controller 140 outputs a variety of data control signals DCS, including a source start pulse SSP, a source sample clock SSC, a source output enable signal SOE, and the like, to control the data driver 130.

[0035] Here, the source start pulse (SSP) controls the data sampling start times of one or more SDICs of the data driver 130. The source sampling clock (SSC) is a clock signal that controls the sampling times of data in each of the SDICs.

[0036] The display device 100 may further include an integrated power management circuit (PMIC) that supplies various forms of voltage or current to the display panel 110, the gate driver 120, the data driver 130, and the like, or controls various types of voltage or current to be supplied thereto.

[0037] Voltage lines, through which a variety of signals or voltages are supplied, may be arranged on the display panel 110, in addition to the gate lines GL and the data lines DL. An emission device ED, transistors for driving the emission device ED, and the like, may be arranged in each of the subpixels SP.

[0038] Fig. 2 represents a circuit structure of each of the subpixels SP in the display device 100 according to embodiments, as well as control times of the subpixels SP.

[0039] Referring to Fig. 2. An emission device ED can be arranged in the subpixel SP of the display panel 110. Furthermore, a driver transistor DRT can be arranged in the subpixel SP, which controls the emission device ED by means of current control.

[0040] The emission device ED arranged in the subpixel SP can be an organic light-emitting diode (OLED) and, in some cases, can be a light-emitting diode (LED), a micro-light-emitting diode (µLED), or the like.

[0041] Furthermore, in addition to the driver transistor DRT, one or more transistors can be arranged in the subpixel SP. A storage capacitor Cstg or similar component for maintaining the voltage of the gate node of the driver transistor DRT can also be arranged in the subpixel SP.

[0042] Fig. Figure 2 represents a 7T1C structure in which 7 transistors, including the driver transistor DRT, and 1 storage capacitor Cstg are arranged in the subpixel SP. However, the structure of the subpixel SP in the display device 100 according to embodiments is not limited to this. Furthermore, although Fig. 2 If the subpixel SP is represented as being implemented by P-type metal oxide semiconductor (PMOS) transistors, at least one of the transistors arranged in the subpixel SP can be implemented as an N-type metal oxide semiconductor (NMOS).

[0043] The emission device ED can have an anode electrically connected to the driver transistor DRT, and a cathode to which a base voltage Vss is applied.

[0044] The driver transistor DRT can connect a driver voltage line DVL, through which a driver voltage Vdd is applied, to the emission device ED. Furthermore, the driver transistor DRT can be electrically connected to a data line DL, through which the data voltage Vdata is applied. Additionally, the gate node of the driver transistor DRT can be electrically connected to the storage capacitor Cstg and an initialization voltage line IVL.

[0045] A first transistor T1 can be controlled by a scan signal SCAN(N) and electrically connects a first node N1 and a second node N2 of the driver transistor DRT. The first transistor T1 can control a voltage obtained by compensating the data voltage Vdata with a threshold voltage Vth of the driver transistor DRT, in order to be applied to the gate node of the driver transistor DRT.

[0046] A second transistor T2 can be controlled by a scan signal SCAN (N-1) and electrically connects the first node N1 of the driver transistor DRT and the initialization voltage line IVL. The second transistor T2 can be used to initialize the voltage of the gate node of the driver transistor DRT.

[0047] A third transistor T3 can be controlled by the scan signal SCAN(N) and electrically connect a third node N3 of the driver transistor DRT and the data line DL. Furthermore, a fourth transistor T4 can be controlled by a scan signal EM and electrically connect the third node N3 of the driver transistor DRT and the driver voltage line DVL.

[0048] A fifth transistor, T5, can be controlled by the scan signal EM and electrically connects the second node, N2, of the driver transistor DRT and the emission device ED. The fifth transistor, T5, can control the emission timing of the emission device ED.

[0049] A sixth transistor, T6, can be controlled by the scan signal SCAN(N) and electrically connects the anode of the emission device ED and the initialization voltage line IVL. This sixth transistor, T6, can be used to initialize the voltage at the anode of the emission device ED.

[0050] Describing the control method of the subpixel SP: The subpixel SP can be controlled in such a way that its control period is divided into an initialization period, a data writing period and an emission period during a single-image frame period.

[0051] During the initialization period, the scan signal SCAN(N-1) can be fed to subpixel SP at a low level, thereby turning on the second transistor T2. With the second transistor T2 turned on, an initialization voltage Vini can be applied to the gate node of the driver transistor DRT.

[0052] After initialization is complete, during the data write period, the scan signal SCAN (N-1) at a high level and the scan signal SCAN(N) at a low level can be fed to subpixel SP. Furthermore, the second transistor T2 can be switched off, while the first transistor T1, the third transistor T3, and the sixth transistor T6 can be switched on.

[0053] Since the first transistor T1 is switched on, the first node N1 and the second node N2 of the driver transistor DRT are electrically connected.

[0054] Furthermore, since the third transistor T3 is switched on, the data voltage Vdata can be applied to the first node N1, the gate node, of the driver transistor DRT via the driver transistor DRT and the first transistor T1. The voltage obtained by reflecting the threshold voltage Vth of the driver transistor DRT in the data voltage Vdata can then be applied to the gate node of the driver transistor DRT, thus compensating for the threshold voltage of the driver transistor DRT.

[0055] Furthermore, since the sixth transistor T6 is switched on during the data write period, the anode of the emission device ED can be initialized using the initialization voltage Vini. This means that both the process of applying a voltage to the gate node of the driver transistor DRT and the process of initializing the anode of the emission device ED can be performed simultaneously during the data write period.

[0056] During the emission period, the scan signal SCAN(N-1) at a high level and the scan signal SCAN(N) at a high level can be fed to subpixel SP, and the scan signal EM at a low level can be fed to subpixel SP. Consequently, the first transistor T1, the third transistor T3, and the sixth transistor T6 can be switched off, while the fourth transistor T4 and the fifth transistor T5 can be switched on.

[0057] Since the fourth transistor T4 is switched on, the driver voltage Vdd can be supplied to the third node N3 of the driver transistor DRT, and through the data voltage Vdata and the driver voltage Vdd a voltage difference can be generated between the first node N1 and the third node N3 of the driver transistor DRT, so that in response to the data voltage Vdata a current can flow through the driver transistor DRT.

[0058] Since the fifth transistor T5 is switched on, current can be supplied to the emission device ED in response to the data voltage Vdata, and the emission device ED can have a light intensity corresponding to the data voltage.

[0059] Furthermore, according to embodiments, the display device 100 can have an area for sensors, such as a camera sensor, in the active area A / A of the display panel 110 in which the subpixels SP described above are arranged.

[0060] For example, it is possible that none of the subpixels SP are located in an area of ​​the active area A / A of the display panel 110. Furthermore, the area in which none of the subpixels SP are located can be open, so that sensors, such as a camera sensor, can be located in the open area. That is, a perforated area HA can be provided in the active area A / A, and sensors can be located in the perforated area HA.

[0061] In this case, it is possible that during the process of arranging display operating components, such as electrodes or signal lines, no display operating components are actually placed in the corresponding area. That is, the electrodes, signal lines, and the like can be arranged in the active area A / A in such a way that images are displayed in the active area A / A, except in a sub-area of ​​the active area A / A where the hole area is to be provided.

[0062] Since the hole area HA is provided in the sub-area of ​​the active area A / A and sensors are arranged in the hole area HA, it is possible to prevent the width of the entire non-active area N / A of the display panel 110 from being increased by arranging the sensors.

[0063] Fig. Figure 3 represents structures in which the hole area HA is arranged in the active area A / A of the display device 100 according to embodiments.

[0064] Referring to Fig. 3. A sub-area of ​​the active area A / A of the display panel 110 can be the perforated area HA, in which camera sensors or the like are arranged. Furthermore, a boundary area BA can be provided around the perforated area HA.

[0065] The boundary area BA can touch the outer perimeter of the hole area HA and be located between the hole area HA and a sub-area of ​​the active area A / A in which the subpixels SP are arranged.

[0066] The boundary area BA can have a first boundary area BA1 in which signal lines for controlling a camera sensor or the like located in the hole area HA are arranged, and a second boundary area BA2 in which signal lines for controlling the subpixels SP arranged around the hole area HA are arranged.

[0067] In this context, the hole region HA and the first boundary region BA1 can be open areas in which the camera sensor is located. That is, in a situation where the hole region HA and the first boundary region BA1 are open, the area in which a sensor unit of the camera sensor is located can be called the hole region HA, while the area in which a frame of the camera sensor is located can be called the first boundary region BA1.

[0068] The second boundary region BA2, located around the perforated area HA, can be an area containing signal lines for driving the subpixels SP in the active area A / A. Since the perforated area HA is located within the active area A / A, it is possible that none of the signal lines associated with specific subpixels SP surrounding the perforated area HA are located within the perforated area HA itself. Accordingly, the second boundary region BA2 can be provided around the perforated area HA, and display operating signal lines, such as gate lines GL and data lines DL, can be located within the second boundary region BA2.

[0069] The hole area HA provided in the active area A / A can be a single area or multiple areas, depending on the type, number, and the like of sensors arranged in the active area A / A.

[0070] For example, referring to BSP 1 in Fig. 3. A single perforation HA may be located within the active area A / A of the display panel 110. The first boundary area BA1 and the second boundary area BA2 may be located around the perforation HA. Furthermore, the subpixels SP or the like may be located outside the second boundary area BA2. That is, the outer perimeter of boundary area BA may be set back from the outer perimeter of the active area A / A.

[0071] In another example, referring to BSP 2 in Fig. 3. Two hole areas HA can be arranged in the active area A / A of the display panel 110. The first hole area HA1 and the second hole area HA2 can have the same shape and size, or, as in Example 2, they can have different shapes and sizes.

[0072] The first boundary area BA1, containing signal lines or similar components for controlling a sensor located in the first hole area HA1, can be situated around the first hole area HA1. The second boundary area BA2, containing signal lines or similar components for controlling a sensor located in the second hole area HA2, can be situated around the second hole area HA2.

[0073] The second boundary area BA2 can be located outside the first boundary area BA1. Furthermore, the subpixels SP can be arranged in the remaining sub-areas of the active area A / A, excluding the hole area HA and the boundary area BA, in order to display images.

[0074] Accordingly, since it is possible that none of the signal lines for controlling the subpixels SP located around the hole area HA are located in the hole area HA, such signal lines can be located in the boundary area BA that is located around the hole area HA and be connected to the subpixels SP that are located outside the boundary area BA.

[0075] Fig. Figure 4 represents a structure in which signal lines are arranged in the boundary area BA, which is located around the hole area HA, which is provided in the active area A / A of the display device 100 according to embodiments.

[0076] Referring to Fig. 4. Gate lines GL (including, for example, gate lines GL1 and GL2) can be arranged in one direction in the active area A / A of the display panel 110, and data lines DL (including, for example, data lines DL1 and DL2) can be arranged in a direction that crosses the gate lines GL.

[0077] Furthermore, in a case where the hole area HA is located in the active area A / A, signal lines such as the gate lines GL and the data lines DL can be arranged so that they pass through the boundary area BA, which is located around the hole area HA.

[0078] For example, the gate lines GL, through which the scan signal is applied, can be arranged in the boundary region BA, which is located around the hole region HA. The gate lines GL can be arranged in the boundary region BA in a shape that is curved along the shape of the outer perimeter of the hole region. Furthermore, a portion of each of the gate lines GL, extending outwards from the boundary region BA, can have an angled shape.

[0079] This means that each of the gate lines GL located in the boundary region BA can have a curved shape, with the curved portion connected to the subpixel SP while maintaining a constant distance to the other gate lines.

[0080] Furthermore, the data lines DL, through which the data voltage Vdata is applied, can be arranged in the boundary region BA, which is located around the perforated region HA. The data lines DL arranged in the boundary region BA can also have a curved shape. Additionally, a portion of each of the data lines DL, extending outwards from the boundary region, can have an angled shape.

[0081] The gate lines GL and the data lines DL as described above can be arranged on different layers in the display panel 110.

[0082] For example, referring to the schematic cross-sectional structure of sub-area II' in Fig. 4. A buffer layer BUF or the like may be arranged on a substrate SUB, and the gate lines GL (including, for example, gate lines GL and GL2) may be arranged on the buffer layer BUF. An insulating layer ILD may be arranged on the gate lines GL, and the data lines DL (including, for example, data lines DL1 and DL2) may be arranged on the insulating layer ILD. Furthermore, a passivation layer PAS may be arranged on the data lines DL.

[0083] Since the gate lines GL and the data lines DL are located on different layers and are curved in the boundary region BA, the gate lines GL and the data lines can be connected to the subpixels SP that are located outside the hole region HA.

[0084] Since the gate lines GL and the data lines DL are located in the boundary region BA along the outer perimeter of the hole region HA, the gate lines GL and the data lines DL can be longer than the other signal lines located outside the boundary region BA. Furthermore, the increased length of the signal lines can increase the load on the signal lines. In particular, the increased load on the data lines DL, which supply the data voltage Vdata, can cause the luminance of the subpixel SP to decrease.

[0085] Embodiments provide a solution capable of preventing deterioration in the quality of an image displayed around the hole area HA, while the hole area HA, in which sensors or the like may be arranged, is contained within the active area A / A.

[0086] Fig. 5 represents another structure in which signal lines are arranged in the boundary area BA around the hole area HA provided in the active area A / A of the display device 100 according to embodiments.

[0087] Referring to Fig. 5. The perforated area HA, in which sensors or the like are arranged, can be located in the active area A / A of the display panel 110. The boundary area BA can be located around the perforated area HA and touch the outer perimeter of the perforated area HA.

[0088] The gate lines (including, for example, gate lines GL1 and GL2), the data lines (including, for example, data lines DL1 and DL2), and the like for controlling subpixels SP located around the hole region HA can be arranged in the boundary region BA.

[0089] For example, the gate lines GL, through which the scan signal is applied, can be arranged in one direction and each have a curved section and an angled section in the boundary region BA. Furthermore, the data lines DL, through which the data voltage Vdata is supplied, can be arranged in a direction intersecting the gate lines GL and each have a curved section and an angled section in the boundary region BA.

[0090] In this context, certain data lines DL from the multitude of data lines located in the border area BA can be arranged on different layers.

[0091] Referring to the schematic cross-sectional structure of a sub-area JJ' in Fig. 5. The insulating layer ILD can be arranged on the gate lines GL (including, for example, gate lines GL1 and GL2), and first data lines DL1 can be arranged on the insulating layer ILD. A first passivation layer PAS1 can be arranged on the first data lines DL1, and second data lines DL2 can be arranged on the first passivation layer PAS1. Furthermore, a second passivation layer PAS2 can be arranged on the second data lines DL2.

[0092] In this case, the first data lines DL1 and the second data lines DL2 can be made of the same material.

[0093] Furthermore, since the second data lines DL2 are located above the first data lines DL2, a vertical distance d2 between the second data lines DL2 and the gate lines GL can be greater than a vertical distance d1 between the first data lines DL1 and the gate lines GL.

[0094] By increasing the distance between the second data lines DL2 and the gate lines GL, which are located below the second data lines DL2, a parasitic capacitance that can be generated between the second data lines DL2 and the gate lines GL can be reduced, and the load on the second data lines DL2 can be reduced.

[0095] This means that in embodiments, the distance between certain data lines DL from the plurality of data lines DL located in the boundary region BA surrounding the hole region HA, and signal lines, such as the gate lines GL located on a layer different from the layer on which the data lines DL are located, can be increased, thereby preventing an increase in the load caused by an increase in the length of the data lines DL.

[0096] Consequently, the luminance of the subpixels SP located in an area adjacent to the hole region HA can be prevented from being reduced by increasing the load on the data lines DL, through which the data voltage Vdata is supplied to the subpixels SP.

[0097] Furthermore, the load on certain data lines DL, from the multitude of data lines DL that drive the subpixels SP, which have a significant influence on the luminance, can be reduced, thereby increasing the effect of improving the luminance of the area surrounding the hole region HA.

[0098] Fig. Figure 6 represents an arrangement structure of the data lines DL that control the subpixels SP located around the hole area HA provided in the active area A / A of the display device 100 according to embodiments.

[0099] Referring to Fig. 6. Red subpixels R SP, green subpixels G SP, and blue subpixels B SP can be arranged in the active area A / A of the display panel 110. The red subpixels R SP and the blue subpixels B SP can be arranged alternately so that they are addressed by the first data lines DL1. Furthermore, the green subpixels G SP can be arranged in the same columns so that they are addressed by the second data lines DL2.

[0100] The peak wavelength of light emitted by the green subpixels G SP can be smaller than the peak wavelength of light emitted by the red subpixels R SP, and larger than the peak wavelength of light emitted by the blue subpixels B. Furthermore, the luminance can be changed by the intensity of light emitted by the green subpixels G SP.

[0101] Accordingly, the second data lines DL2, which drive the green subpixels G SP, can be placed on a layer above the first data lines DL1, which drive the red subpixels R SP and the blue subpixels B, in order to reduce the load on the second data lines DL2 and increase the luminance of the area driven by the corresponding data lines DL.

[0102] As described above, in the structure where the signal lines that control the subpixels SP located around the hole region HA can be arranged in the boundary region BA and connected to the subpixels SP, a layer on which certain signal lines are arranged can be adapted, thereby preventing the image quality from being reduced by an increase in load.

[0103] Furthermore, the above-described arrangement structure of the data lines DL can be applied in a case where a large number of hole areas HA are arranged in the active area A / A of the display device 110.

[0104] Fig. Figure 7 represents another structure in which the data lines DL are arranged in the border area BA, which is located around the hole area HA provided in the active area A / A of the display device 100 according to embodiments.

[0105] Referring to Fig. 7. The first hole area HA1 and the second hole area HA2 can be arranged in the active area A / A.

[0106] The boundary region BA can be arranged around the first hole region HA1 and the second hole region HA2 such that it touches the outer perimeter of the first hole region HA1 and the outer perimeter of the second hole region HA2. Within the boundary region BA, the gate lines GL can be arranged, which are connected to the subpixels SP located on one side (e.g., to the left of) and the other side (e.g., to the right of) the hole region HA.

[0107] Furthermore, in the border area BA, the data lines DL can be arranged, which are connected to the subpixels SP that are located on one side (e.g. above) and the other side (e.g. below) of the hole area HA.

[0108] A portion of each of the data lines DL located within the boundary region BA may have a section with a curved shape. Furthermore, a portion of each of the data lines extending outwards from the boundary region BA may have a section with an angled shape.

[0109] The first data lines DL1, which control the red subpixels R SP and the blue subpixels B, and the second data lines DL2, which control the green subpixels G SP, can be arranged to alternate. Furthermore, the second data lines DL2 can be located on a layer above the first data lines DL1.

[0110] This consequently increases the distance between the second data line DL2 and the signal lines located on a layer below the data line DL. Furthermore, increasing the distance between the second data line DL2 and the signal lines located on the layer below the data line DL can reduce the load on the second data line DL2.

[0111] Accordingly, the increased length of the second data lines DL2, which are located in the border area BA, can prevent the load from being increased, thus preventing the luminance of the subpixels SP, which are driven by the second data lines DL2, from being reduced.

[0112] Furthermore, the first data lines DL1 and the second data lines DL2 can be arranged in a predetermined pattern in a specific area, e.g. an area outside the boundary area BA or a sub-area of ​​the boundary area BA between the hole areas HA1 and HA2, for the purpose of uniform luminance or easy arrangement of the signal lines.

[0113] Fig. Figure 8 represents a structure in which the data lines DL are arranged outside and inside the border area BA, which surrounds the area shown in Fig. The area shown in section 7 is HA.

[0114] Referring to Fig. Figure 8 shows an exemplary structure of the data lines DL, which are located in the boundary area BA, which is to the left of the first hole area HA1, and in a sub-area of ​​the active area A / A outside the boundary area BA.

[0115] The data lines DL, which are connected to the subpixels SP located above the first hole region HA1 and the subpixels SP located below the first hole region HA1, can be arranged to bypass the first hole region HA1. The length of the curved segments of the data lines DL can increase when closer to the outer perimeter of the first hole region HA1. Furthermore, the length of the curved segments of the data lines DL can decrease when closer to the outer perimeter of the boundary region BA.

[0116] In this case, although the distance between the curved sections of the data lines DL may be reduced due to the width of the boundary area BA, the distance between the linear sections of the data lines DL that are located outside the boundary area BA can be constant.

[0117] Accordingly, the data lines DL can be arranged in the boundary area BA, with the structure passing by the hole area HA, and connected to the subpixels SP that are arranged above and below the hole area HA to address the corresponding subpixels SP.

[0118] Furthermore, since the second data lines DL2, which control the green subpixels G SP, are located on the upper layer, the load on the second data lines DL2, through which the data voltage Vdata is supplied to the green subpixels SP, can be reduced, thus preventing a decrease in the luminance of the area controlled by the data lines, parts of which are located in the boundary area.

[0119] Furthermore, for the sake of simple arrangement of the signal lines, the data lines DL located outside the boundary area BA can be arranged in the same pattern as the data lines DL located within the boundary area BA. That is, the first data lines DL1 and the second data lines DL2, located outside the boundary area BA, can be arranged on different layers.

[0120] Accordingly, the display device 100 can provide an arrangement structure in which two data lines DL, which are adjacent to each other, are arranged on different layers.

[0121] Fig. Figure 9 represents a structure in which the data lines DL are arranged in the border area BA, which is located between two hole areas HA.

[0122] Referring to Fig. Figure 9 shows an exemplary structure in which the data lines DL are arranged in the border area BA, which is located between the first hole area HA1 and the second hole area HA2.

[0123] In the area between the first hole area HA1 and the second hole area HA2, certain data lines DL can have a shape curved along the outer perimeter of the first hole area HA1, while other data lines DL can have a shape curved along the outer perimeter of the second hole area HA2. Thus, data lines DL curved in opposite directions can be located in the boundary area BA, which lies between the first hole area HA1 and the second hole area HA2.

[0124] The data lines DL can be arranged in a curved shape in the boundary region BA between the first hole region HA1 and the second hole region HA2, such that the distance between the data lines DL in the boundary region BA can be reduced. Furthermore, the linear segments of the data lines DL extending outwards from the boundary region BA can be connected to the subpixels SP located outside the boundary region BA and maintain a constant distance.

[0125] In the boundary region BA between the first hole region HA1 and the second hole region HA2, two adjacent data lines DL can be curved in opposite directions. Furthermore, since the first data lines DL1 and the second data lines DL2 are arranged to alternate, the adjacent data lines DL that are curved in opposite directions can be located on different layers.

[0126] As described above, the display device 100, according to embodiments, provides the structure that includes the hole region HA in the active region A / A, thereby enabling the sensors to be arranged in the active region A / A. Furthermore, the structure provides the signal lines for display operation in the boundary region BA, which is located outside the hole region HA, thus providing a signal line structure capable of driving the subpixels SP located around the hole region HA.

[0127] Furthermore, the layer on which the data lines DL are arranged, which control the subpixels SP that have a specific color, can be adapted to reduce the load on the data lines DL, thus reducing the increase in load caused by the data lines being arranged to bypass the hole region HA, and improving the uniformity of the luminance around the hole region HA.

[0128] Fig. 10 and Fig. 11 provide examples where the uniformity of luminance in the active area A / A is improved by the arrangement structure of the data lines DL, which are in Fig. 7 is shown.

[0129] Referring to Fig. Figure 10 illustrates an exemplary situation where the data driver 130, which supplies the data voltage Vdata to the data lines DL, is located under the active region A / A. Since the data lines DL are located in the boundary region BA, which surrounds the perforated region HA, a low-luminance region can occur with increasing load as the length increases. This low-luminance region is indicated by the subpixels SP driven by the data lines DL.

[0130] This means that in a case where the hole area HA, the boundary area BA, and the like are arranged at distances from the outer perimeter of the active area A / A, certain subpixels SP can be addressed by the data lines DL, which are arranged in the boundary area BA between the hole area HA or the like and the outer perimeter of the active area A / A.

[0131] Furthermore, since the data lines DL that control such subpixels SP are located in the border region BA, with increasing load from them the area in which the subpixels SP, controlled by the corresponding data lines DL, are located can have a low luminance.

[0132] According to embodiments, the second data lines DL2, which control the green subpixels G SP, can be located on the layer that is able to reduce the load of the second data lines DL2, thus preventing a decrease in luminance in the area surrounding the hole region HA, from being arranged in the boundary region BA.

[0133] Furthermore, even in a case where the hole area HA is located adjacent to the outer perimeter of the active area A / A, embodiments are applicable in a case where the subpixels SP, which are controlled by the data lines DL, are located in the boundary area BA between the hole area HA and the outer perimeter of the active area A / A.

[0134] For example, as in Fig. Figure 11 shows that the border area BA is located around the hole area HA, such that a part of the border area BA touches the outer perimeter of the active area A / A.

[0135] In this case, if the outer perimeter of the boundary area BA has a curved section, image-representing subpixels SP can be located between the outer perimeter of the boundary area BA and the outer perimeter of the active area A / A. Furthermore, the data lines DL, which control the corresponding subpixels SP, can be located in the boundary area BA and pass by the gap area HA.

[0136] In this case, the second data lines DL2, which control the green subpixels G SP, can be located on a different layer than the layer on which the first data lines DL1 are located, which control the red subpixels R SP and the blue subpixels B, thus preventing a reduction in luminance that would otherwise be caused by an increase in the load on the data lines DL in the corresponding area.

[0137] According to embodiments set out above, a structure in which sensors can be arranged in the active area A / A can be provided by arranging the hole area HA in a sub-area of ​​the active area A / A of the display panel 110.

[0138] Furthermore, embodiments can provide an arrangement structure of signal lines that is able to control the subpixels SP located around the hole area HA by providing the boundary area BA outside the hole area HA and allowing the display operating signal lines arranged in the boundary area BA to have a curved shape.

[0139] Furthermore, embodiments can provide a structure in which certain data lines DL, which control the green subpixels G SP, are arranged on a layer different from the layer on which the other data lines DL are arranged, for controlling the subpixels SP located outside the boundary region BA, from the data lines DL arranged in the boundary region BA.

[0140] Accordingly, a solution can be provided that is able to prevent an increase in the load of the data lines DL that drive the green subpixels G SP, thereby preventing a decrease in the luminance of the subpixels SP driven by the corresponding data lines DL, and reducing the luminance non-uniformity that occurs around the hole area HA.

Claims

[1] Display device (100), comprising: a display panel (110) in which a plurality of gate lines (GL), a plurality of data lines (DL) and a plurality of subpixels (SP) are arranged; at least one hole area (HA, HA1, HA2) located in an active area (A / A) of the display panel (110); and a border area (BA) that is arranged in such a way that it touches an outer perimeter of the at least one hole area (HA, HA1, HA2), which features a multitude of data lines (DL): a plurality of first data lines (DL1) through which a data voltage (Vdata) is provided to first color subpixels from the plurality of subpixels (SP), wherein a portion of each of the plurality of first data lines (DL1) is arranged in the border region (BA); and a plurality of second data lines (DL2) through which the data voltage (Vdata) is provided to second color subpixels from the plurality of subpixels (SP), wherein a portion of each of the plurality of second data lines (DL2) is arranged in the boundary region (BA), wherein the plurality of second data lines (DL2) are arranged on a layer above a layer on which the plurality of first data lines (DL1) are arranged; where the multitude of first data lines (DL1) provide the data voltage (Vdata) to further third color subpixels, and a peak wavelength of light emitted by the second color subpixels is smaller than a peak wavelength of light emitted by the first color subpixels, and larger than a peak wavelength of light emitted by the third color subpixels. [2] Display device (100) according to claim 1, wherein the gate lines (GL) are arranged on a layer that is different from the layers in which the first and second data lines (DL1, DL2) are arranged, and a vertical distance (d2) between the second data lines (DL2) and the gate lines (GL) is greater than a vertical distance (d1) between the first data lines (DL1) and the gate lines (GL). [3] Display device (100) according to claim 1 or 2, wherein the first data lines (DL1) alternate with the second data lines (DL2). [4] Display device (100) according to any one of claims 1 to 3, wherein the first data lines (DL1) and the second data lines (DL2) are made of the same material. [5] Display device (100) according to any one of claims 1 to 4, wherein at least a partial area of ​​the part of each of the first data lines (DL1) and of the part of each of the second data lines (DL2) that is arranged in the boundary area (BA) is curved. [6] Display device (100) according to any one of claims 1 to 5, wherein at least a partial area of ​​the part of each of the first data lines (DL1) and of the part of each of the second data lines (DL2) that is arranged in the boundary area (BA) is bent. [7] Display device (100) according to any one of claims 1 to 6, wherein the boundary area (BA) is located at a distance from a boundary of the active area (A / A). [8] Display device (100) according to any one of claims 1 to 7, wherein at least one of the first data lines (DL1) and the second data lines (DL2) provides the data voltage (Vdata) to at least one subpixel from the plurality of subpixels (SP) that is arranged on one side of the at least one hole region (HA, HA1, HA2), and to at least one subpixel from the plurality of subpixels (SP) that is arranged on the other side of the at least one hole region (HA, HA1, HA2). [9] Display device (100) according to any one of claims 1 to 8, wherein the plurality of subpixels (SP) are arranged in the active area (A / A), excluding the at least one hole area (HA, HA1, HA2) and the boundary area (BA). [10] Display device (100) according to one of claims 1 to 9, wherein the at least one hole area (HA1, HA2) has a first hole area (HA1) and a second hole area (HA2) which is arranged adjacent to the first hole area (HA1), and at least two data lines from the plurality of data lines (DL) which are arranged in the boundary area (BA) which is located between the first hole area (HA1) and the second hole area (HA2) are curved in opposite directions. [11] Display device (100) according to claim 10, wherein the two data lines, which are arranged adjacent to each other and are curved in opposite directions, are arranged on different layers. [12] Display device (100), comprising: at least one hole area (HA, HA1, HA2) located in an active area (A / A); a border area (BA) arranged in such a way that it touches an outer perimeter of the at least one hole area (HA, HA1, HA2); and a plurality of data lines (DL), each having a part that is located in the border area (BA), wherein at least one part of the part is curved, where two adjacent data lines (DL1, DL2) are arranged from the multitude of data lines (DL) on different layers; the display device (100) further comprising a plurality of gate lines (GL) arranged on a layer different from the layers on which the plurality of data lines (DL) are arranged, each of the plurality of gate lines (GL) having a part arranged in the boundary region (BA), wherein at least one part of the part is curved, wherein two adjacent gate lines (GL1, GL2) are arranged from the plurality of gate lines (GL) in a single layer; wherein one data line from the two adjacent data lines (DL1, DL2), which has a larger vertical distance to the gate lines (GL), provides a data voltage (Vdata) to green subpixels (G SP). [13] Display device (100) according to claim 12, wherein at least one data line from the plurality of data lines (DL) is electrically connected to a circuit element located in at least one subpixel located on one side of the boundary area (BA) and is electrically connected to a circuit element located in at least one subpixel located on the other side of the boundary area (BA). [14] Display device (100) according to claim 12 or 13, wherein the boundary area (BA) is located at a distance from a boundary of the active area (A / A). [15] Display device (100) according to one of claims 12 to 14, wherein a data line from the two adjacent data lines (DL1, DL2), which has a smaller vertical distance to the gate lines (GL), provides a data voltage (Vdata) to red subpixels (R SP) and blue subpixels (B SP).

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