Multilayer high-k gate dielectric structure and method

Abstract

Device comprising: a substrate (110); a first gate dielectric layer (350) disposed over the substrate (110), the first gate dielectric layer (350) containing a first material composition; and a second gate dielectric layer (390) disposed over the first gate dielectric layer (350) and in direct physical contact with the first gate dielectric layer (350), the second gate dielectric layer (390) containing a second material composition, wherein the first material composition is different from the second material composition, and wherein the first material composition and the second material composition each have a greater dielectric constant than a dielectric constant of silicon oxide, wherein the second material composition has a greater dielectric constant than the first material composition, and wherein the first gate dielectric layer (350) has a first thickness (360), the second gate dielectric layer (390) has a second thickness (400), and wherein the ratio of the first thickness (360) to the second thickness (400) is between about 1.3:1 and about 5.6:1.

Description

BACKGROUND

[0001] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and IC design have spawned generations of ICs, with each generation featuring smaller and more complex circuits than the previous generation. As ICs have evolved, functional density (i.e., the number of interconnected components per chip area) has generally increased while geometry size (i.e., the smallest component (or lead) that can be produced using a manufacturing process) has decreased. This downsizing process generally offers advantages by increasing production efficiency and decreasing associated costs. However, this downsizing has also increased the complexity of IC processing and manufacturing.

[0002] For example, as the gate size of a transistor continues to shrink at each technology node, gate leakage can become a problem. Gate leakage is undesirable because it can degrade device performance, such as speed and / or power consumption. Conventional semiconductor manufacturing methods have not yet provided a satisfactory solution to this problem. Therefore, while conventional semiconductor device manufacturing methods are generally suitable, they are not satisfactory in all aspects.

[0003] US 2013 / 0 280 902 A1 discloses a gate dielectric consisting of several different layers. US 2011 / 0 193 180 A1, US 2008 / 0 305 597 A1, US 2019 / 0 164 767 A1, and US 2005 / 0 148 127 A1 also show multilayer gate dielectrics with different structuring features. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] This disclosure is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale and are for purposes of illustration only. Indeed, the dimensions of the various features may be exaggerated or reduced as desired for clarity of explanation. Fig. 1A is a perspective view of an IC device according to various aspects of the present disclosure. Fig. 1B is a planar top view of an IC device according to various aspects of the present disclosure. Fig. 2-13 are cross-sectional views of an IC device at various stages of manufacture according to various aspects of the present disclosure. Fig. 14 is a cross-sectional view of a portion of an IC device and a graph indicating material concentration values ​​along the IC device, according to various aspects of the present disclosure. Fig. 15-16 are cross-sectional views of an IC device at a stage of manufacture according to various aspects of the present disclosure. Fig. 17 is a cross-sectional view of a portion of an IC device and a graph indicating material concentration values ​​adjacent to the IC device, according to various aspects of the present disclosure. Fig. 18 is a schematic of an SRAM circuit cell according to various aspects of the present disclosure. Fig. 19 is a block diagram of a semiconductor manufacturing system according to various aspects of the present disclosure. Fig. 20 is a flowchart of a method of manufacturing a semiconductor device according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples of implementing various features of the disclosure. Specific examples of components and arrangements are described below. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, reference numerals may be repeated throughout the various examples of the present disclosure. This repetition is for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed herein.

[0006] Furthermore, the present disclosure may repeat reference numerals in the various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed herein. Further, in the following disclosure, the formation of a feature on, in conjunction with, and / or coupled to another feature may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed sandwiching the features between them, such that the features may not be in direct contact. Further, spatially relative terms, for example, "bottom," "top," "horizontal," "vertical," "over," "upward," "under," "downward," "above," "beneath," "on," etc., as well as derivatives thereof (for example, "horizontal," "down," "up," etc.), are used.) is used to facilitate the reference of one feature to another feature in the present disclosure. The spatially relative terms are intended to cover various orientations of the device having these features. Furthermore, when a number or range of numbers is described with "about," "approximately," "ca.", and the like, the term is intended to include numbers that are within a reasonable range inclusive of the described number, for example, within + / - 10% of the described number or other values ​​as understood by one of ordinary skill in the art. For example, the term "about 5 nm" encompasses the dimensional range from 4.5 nm to 5.5 nm.

[0007] The present disclosure relates generally to semiconductor devices, and more particularly to field-effect transistors (FETs), such as planar FETs or three-dimensional fin-line FETs (FinFETs). One aspect of the present disclosure relates to the fabrication of a multilayer high-k gate dielectric. In this regard, conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) include a source component, a drain component, a channel component disposed between the source component and the drain component, and a gate component disposed over the channel component. The gate component may include a gate dielectric and a gate electrode. The gate dielectric serves as an electrically insulating pad. Transistor performance may be improved by reducing the thickness of the gate dielectric.

[0008] As the thickness of the gate dielectric decreases with the downsizing process, transistors may experience current leakage and excessive heat, which can be referred to as gate leakage. Gate leakage can lead to problems such as excessive power consumption, lower reliability, and / or degraded device performance. The recent use of high-k materials to implement the gate dielectric has allowed the gate dielectric to become significantly thicker, achieving the same capacitance equivalent thickness (CET) of an entire gate structure as a much thinner conventional silicon oxide gate dielectric. In this respect, the use of a high-k gate dielectric can be advantageous in terms of equivalent oxide thickness (EOT).In this regard, the equivalent oxide thickness is a distance, usually expressed in nanometers (nm), that indicates how thick a silicon oxide layer would need to be to achieve the same effect as the high-k material used. Materials with larger dielectric constants allow for the use of thicker layers (which still have a low equivalent oxide thickness) while maintaining fast transistor switching. As such, high-k dielectric materials have become good candidates for implementing a transistor's gate dielectric. Unfortunately, high-k dielectric materials also exhibit narrower band gaps, which are associated with higher gate leakage. As the semiconductor technology node evolves toward a 7-nanometer generation or smaller, the problems discussed above are exacerbated.

[0009] To overcome the problems discussed above, the present disclosure forms a gate structure comprising not just one, but multiple different gate dielectric layers containing different material compositions. In a dual-layer gate dielectric embodiment, the gate dielectric comprises a lower gate dielectric layer implemented closer to a channel of the transistor and an upper gate dielectric layer overlying the lower gate dielectric layer. The lower gate dielectric layer and the upper gate dielectric layer have different properties and / or physical characteristics.For example, the upper gate dielectric layer may have a higher dielectric constant than the lower gate dielectric layer (although both have a high-k material composition) to ensure that the overall dielectric constant of the gate structure is still sufficiently high so that a low equivalent oxide thickness can be maintained. The upper gate dielectric layer also has fewer traps than the lower gate dielectric layer, which can lead to a lower noise level and higher speed. Meanwhile, the gate dielectric layer contains a material composition configured to provide a better interface (or better integration) with a layer, such as an interfacial oxide layer, disposed beneath the gate structure.The thicknesses and material compositions of the upper gate dielectric layer and the lower gate dielectric layer are adjusted to achieve a desired high-k dielectric value for the gate structure to increase speed without causing excessive gate leakage.

[0010] In an embodiment with a three-layer gate dielectric, the gate dielectric comprises a lower gate dielectric layer (for example, similar to the lower layer of the two-layer gate dielectric scheme) capable of forming a good interface with the underlying interface layer, a middle layer (for example, similar to the upper layer of the two-layer gate dielectric scheme) capable of providing a high dielectric constant and / or fewer traps, and an upper layer capable of forming a good interface with the overlying metal gate electrode and / or facilitating the adjustment of threshold voltages. The details of the gate structure are described below with reference to Fig. 1-20 explained.

[0011] Fig. 1A and Fig. 1B show a three-dimensional perspective view and a top view of a portion of an integrated circuit (IC) device 90. The IC device 90 may be an intermediate device fabricated during processing of an IC, or a portion thereof, and may include static random access memory (SRAM) and / or other logic circuitry, passive components such as resistors, capacitors, and inductors, and active components such as p-type FETs (PFETs), n-type FETs (NFETs), FinFETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS), bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other memory cells. The present disclosure is not limited to any particular number of devices or device regions, or to any particular device configurations unless otherwise stated.For example, although the IC device 90 is illustrated as a three-dimensional FinFET device, the concepts of the present disclosure may also be applied to planar FET devices.

[0012] With reference to Fig. 1A, the IC device 90 includes a substrate 110. The substrate 110 may include an elemental (single element) semiconductor such as silicon, germanium, and / or other suitable materials; a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 110 may be a single-layer material with a uniform composition. Alternatively, the substrate 110 may include multiple layers of material with similar or different compositions suitable for fabricating IC devices. In one example, the substrate 110 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer.In another example, substrate 110 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof. Various doped regions, such as source / drain regions, may be formed in or on substrate 110. The doped regions may be doped with n-type dopants such as phosphorus or arsenic and / or with p-type dopants such as boron, depending on design requirements. The doped regions may be formed directly on substrate 110, in a p-well structure, in an n-well structure, in a dual-well structure, or using a raised structure. Doped regions may be formed by implanting dopant atoms, in-situ doped epitaxial growth, and / or other suitable techniques.

[0013] Three-dimensional active regions 120 are formed on the substrate 110. The active regions 120 are elongated, fin-like structures that protrude upward from the substrate 110. Thus, the active regions 120 may be interchangeably referred to as fin structures 120 or fin structures 120 hereinafter. The fin structures 120 may be formed by suitable processes, including photolithography and etching processes. The photolithography process may include forming a photoresist layer over the substrate 110, exposing the photoresist to form a pattern, performing post-exposure baking processes, and developing the photoresist into a masking element (not shown) including the resist. The masking element is then used to etch recesses into the substrate 110, leaving the fin structures 120 on the substrate 110.The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the fin structure 120 may be formed by double or multiple patterning processes. Generally, double or multiple patterning processes combine photolithography and self-aligned processes and enable the creation of structures that have, for example, smaller pitches than those otherwise obtained by a single, direct photolithography process. For example, a layer may be formed over a substrate and patterned by a photolithography process. A self-aligned process forms spacers adjacent to the patterned layer. The layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fin structures 120.

[0014] The IC device 90 further includes source / drain features 122 formed over the fin structures 120. The source / drain features 122 may include epi layers epitaxially grown on the fin structures 120.

[0015] The IC device 90 further includes isolation structures 130 formed on the substrate 110. The isolation structures 130 electrically separate various components of the IC device 90 from each other. The isolation structures 130 may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable materials. In some embodiments, the isolation structures 130 may include shallow trench isolation (STI) features. In one embodiment, the isolation features 130 are formed by etching trenches into the substrate 110 during the formation of the fin structures 120. The trenches may then be filled with an insulating material described above, followed by a chemical mechanical planarization (CMP) process.Other isolation structures such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures may also be implemented as isolation structures 130. Alternatively, isolation structures 130 may have a multi-layer structure, for example, with one or more thermal oxide liner layers.

[0016] The IC device 90 further includes gate structures 140 formed over and engaging the fin structures 120 on three sides in a channel region of each fin structure 120. In some embodiments, the gate structures 140 may be HKMG structures including a high-k gate dielectric and a metal gate electrode, where the HKMG structures are formed by replacing the dummy gate structures. Although not illustrated herein, the gate structure 140 may include additional material layers, such as an interface layer over the fin structures 120, a cap layer, other suitable layers, or combinations thereof.

[0017] With reference to Fig. 1B, a plurality of fin structures 120 are aligned longitudinally along the X-direction and a plurality of gate structures 140 are aligned longitudinally along the Y-direction, i.e., substantially perpendicular to the fin structures 120. In many embodiments, the IC device 90 includes additional features such as gate spacers disposed along sidewalls of the gate structures 40, hard mask layer(s) disposed over the gate structures 40, and numerous other features. For simplicity, the processing steps of the present disclosure are described in one embodiment with reference to cross-sectional views according to Fig. 2-15, wherein the cross sections of the IC device 90 are taken along dashed lines AA' and BB', as in Fig. 1A-1B. Specifically, the cross-sections along the dashed line AA' correspond to an XZ cross-section (for example, a plane passing through the X-direction and the Z-direction in Fig. 1A) and the cross sections along the dashed line BB' correspond to a YZ cross-section (for example, a plane passing through the Y-direction and the Z-direction in Fig. 1A is defined).

[0018] With reference to Fig. 2-3, the IC device 90 at this stage of fabrication includes the substrate 110 described above. Dummy gate structures 40 are formed over the substrate 110 in the Z-direction, which is orthogonal to the horizontal plane defined by the X-direction and the Y-direction. The dummy gate structures 40 lie between each source region and a drain region (e.g., the source / drain regions having the source / drain features 122), with a channel region defined in the substrate 110 between the source region and the drain region. The dummy gate structures 40 engage the channel regions so that a current can flow between the source / drain regions during operation. In some implementations, dummy gate structures 40 are formed over fin structures (e.g., the fin structures 120 in Fig. 1A-1B), so that the dummy gate structures 40 are each wrapped around a portion of the fin structures 120. For example, the dummy gate structures 40 are wrapped around channel regions of the fin structures 120 and are thus located between the source regions and drain regions of the fin structure 120.

[0019] The dummy gate structures 40 may each include a dummy gate dielectric and a dummy gate electrode formed over the dummy gate dielectric. In some embodiments, the dummy gate dielectric may include silicon oxide (SiO2), and the dummy gate electrode may include polysilicon. As shown in the YZ cross-sectional view in Fig. 3, each dummy gate structure 40 may be at least partially wrapped around a plurality of the fin structures 120.

[0020] With reference to Fig. 2, the source / drain features 122 are further formed in the source / drain regions of the substrate 110. In some embodiments, the source / drain features 122 may be formed by epitaxial processes. For example, a semiconductor material is epitaxially grown on the substrate 110, thereby forming the source / drain features 122 as epitaxially grown structures. In the illustrated embodiment, the dummy gate structures 40 lie between the respective source / drain features 122, and respective channel regions are defined in the substrate 110 between the epitaxial source / drain features 122 beneath the respective dummy gate structures 40. The IC device 90 may thus be configured to include transistors having gate structures subsequently formed to replace the dummy gate structures 40 and their respective source / drain features 122 and channel regions.In some implementations, the dummy gate structures 40 are each arranged around source / drain regions of the fin structures (for example, the fin structures 120 in . Fig. 1A-1B) extending from the substrate 110, so that the transistors are configured as FinFETs.

[0021] An epitaxial process may implement CVD deposition techniques (e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and / or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors that interact with the composition of the substrate 110. The source / drain features 122 are doped with n-type dopants and / or p-type dopants. In some implementations where a transistor is configured as an n-type device, the source / drain features 122 may be silicon-containing epitaxial layers or silicon-carbon-containing epitaxial layers doped with phosphorus, other n-type dopants, or combinations thereof (e.g., to form Si:P epitaxial layers or Si:C:P epitaxial layers).In some implementations where the transistor is configured as a p-type device, the source / drain features 122 may be silicon- and germanium-containing epitaxial layers doped with boron, another p-type dopant, or combinations thereof (e.g., to form Si:Ge:B epitaxial layers). In some implementations, the source / drain features 122 include materials and / or dopants that provide the desired tensile and / or compressive stress in the channel region. In some implementations, the source / drain features 122 are doped during deposition by adding impurities to a starting material of the epitaxial process. In some implementations, the source / drain features 122 are doped after a deposition process through an ion implantation process.In some implementations, annealing processes are performed to activate dopants in the source / drain features 122 and / or other source / drain regions of the IC device 90.

[0022] As in Fig. 3, an isolation structure 130 may also be formed over and / or within the substrate 110 to isolate various regions of the IC device 90. For example, the isolation structure 130 may define active device regions and / or passive device regions and electrically isolate them from each other. In some implementations, the isolation structure 130 may be configured to isolate transistors (corresponding to the gate structures formed to replace the dummy gate structures 40 and the source / drain features 122) from other transistors, devices, and / or regions of the IC device 90. The isolation structure 130 includes an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, another suitable insulating material (e.g., including silicon, oxygen, nitrogen, carbon, and / or another suitable insulating component), or combinations thereof.The isolation structure 130 may include various structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and / or local oxidation of silicon (LOCOS) structures.

[0023] In some implementations, STI structures (as an example of isolation structure 130) may be formed by etching trenches into substrate 110 (e.g., using a dry etch and / or wet etch process) and filling the trenches with isolation material (e.g., using a chemical vapor deposition process or a spin-on-glass process). A chemical mechanical polishing (CMP) process may be performed to remove excess isolation material and / or planarize a top surface of the STI structures. In some implementations, STI structures may be formed by depositing an isolation material over substrate 110 after fin formation so that the isolation material layer fills gaps (trenches) between the fin structures, and then etching back the isolation material layer.In some implementations, the isolation structure 130 may include multi-layer structures that fill trenches, such as a bulk dielectric layer disposed over a dielectric liner layer, where the bulk dielectric layer and the dielectric liner layer may contain materials depending on design requirements (e.g., a bulk dielectric layer containing silicon nitride disposed over a dielectric liner layer containing thermal oxide). In some implementations, the isolation structure 130 may include a dielectric layer disposed over a doped liner layer (containing, for example, borosilicate glass or phosphosilicate glass).

[0024] As in Fig. 2, gate spacers 230 may be formed adjacent to the gate structures 40, for example, on the sidewalls of the gate structures 40 in the X-direction. The gate spacers 230 may be formed by depositing a dielectric material and patterning the dielectric material. The deposited dielectric material may include silicon, oxygen, carbon, nitrogen, another suitable material, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). For example, in the illustrated embodiment, a dielectric layer including silicon and nitrogen, such as a silicon nitride layer, may be deposited over the substrate 110 and subsequently anisotropically etched to form the gate spacers 230.

[0025] Although not separately illustrated herein for simplicity, in some embodiments, the gate spacers 230 may have a multi-layer structure. For example, the gate spacers 230 may each include a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. In some implementations, the gate spacers 230 may include more than one set of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers formed adjacent to the gate structures 40. In such implementations, the different sets of spacers may include materials having different etch speeds (etch rates).For example, a first dielectric layer containing silicon and oxygen may be deposited over the substrate 110 and then anisotropically etched to form a first set of spacers adjacent to the gate stacks, and a second dielectric layer containing silicon and nitrogen may be deposited over the substrate 110 and then anisotropically etched to form a second set of spacers adjacent to the first set of spacers. Implant, diffusion, and / or annealing processes may be performed to form lightly doped source and drain (LDD) features and / or heavily doped source and drain (HDD) features in the source / drain (S / D) regions 122 before and / or after the formation of the gate spacers 230.

[0026] An interlayer dielectric (ILD) layer 250 is disposed over the substrate 110 and the gate structures 40 in the Z-direction and surrounds the dummy gate structures 40 laterally, for example, in the X-direction. In some embodiments, the ILD layer 250 may include a dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, TEOS-shaped oxide, PSG, BPSG, low-k dielectric, other suitable dielectric material, or combinations thereof. Examples of low-k dielectric materials include FSG, carbon-doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB, SiLK (Dow Chemical, Midland, Michigan), polyimide, other low-k dielectric material, or combinations thereof. In some implementations, the ILD layer 250 may have a multi-layer structure with multiple dielectric materials.The ILD layer 250 may be formed over the substrate 110 by a deposition process (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable processes, or combinations thereof). In some implementations, the ILD layer 250 is formed by a flowable CVD (FCVD) process, which includes, for example, depositing a flowable material (such as a liquid compound) over the substrate 110 and converting the flowable material into a solid material by a suitable technique, such as thermal annealing and / or ultraviolet radiation treatment. After the ILD layer 250 is deposited, one or more CMP processes and / or other planarization processes may be performed such that the ILD layer 250 has a substantially planar top surface.

[0027] With reference now to Fig. 4 and Fig. 5, one or more etch processes 270 are performed on the IC device 90 to remove the dummy gate structures 40. The one or more etch processes 270 may comprise wet or dry etch processes and may be performed with sufficient etch selectivity between the materials of the dummy gate structures 40 and the remaining materials of the IC device 90, such as the ILD layer 250, the gate spacers 230, and the fin structures 120. In other words, the dummy gate electrode (e.g., comprising polysilicon) and the dummy gate dielectric (e.g., comprising silicon oxide) may be etched away by the one or more etch processes 270, while the ILD layer 250, the gate spacers 230, and the fin structures 120 remain substantially intact. As a result of performing the one or more etching processes 270, trenches 280 (or recesses) are formed at the location of the removed dummy gate structures 40.The trenches 280 may, for example, expose the top surfaces of the fin structures 120 and the side surfaces of the gate spacers 230.

[0028] With reference now to Fig. 6 and Fig. 7, a deposition process 290 is performed on the IC device 90 to form an interface layer 300 within the trenches 280. The deposition process 290 may include various types of CVD, PVD, or ALD processes, or combinations thereof. The interface layer 300 is formed on the exposed surfaces of the fin structures 120. Portions of the interface layer 300 are also formed on the side surfaces of the gate spacers 230 and the top surfaces of the ILD layer 250. Thus, the portion of the interface layer 300 formed within the trenches 280 may have a U-shape. In some embodiments, the interface layer 300 includes silicon oxide.

[0029] With reference now to Fig. 8 and Fig. 9, a deposition process 310 is performed on the IC device 90 to form a gate dielectric layer 350 over the interface layer 300. The deposition process 290 may include an ALD process. The gate dielectric layer 350 includes a high-k dielectric material. High-k dielectric material generally refers to dielectric materials having a dielectric constant greater than the dielectric constant of silicon oxide (such as a dielectric constant of about 3.9 or k≈3.9). In the illustrated embodiment, the high-k dielectric of the gate dielectric layer 350 is hafnium oxide (HfO2), which has a dielectric constant of about 22. Hafnium oxide is chosen as the material composition for the gate dielectric layer 350 at least in part because of its ability to form a good interface with the underlying interface layer 300.In other words, the hafnium oxide material composition of the gate dielectric layer 350 enables good integration with the interface layer 300, so that the interface is substantially free of defects. Furthermore, the hafnium oxide material composition of the gate dielectric layer 350 exhibits a higher band gap than most other types of high-k dielectric materials. The band gap represents the minimum energy required to excite an electron to a state in the conduction band where it can participate in conduction. The composition of the hafnium oxide material allows the overall gate dielectric structure to achieve a reasonably high dielectric constant (thus contributing to reducing the equivalent oxide thickness) without causing excessive gate leakage, since gate leakage typically increases with decreasing band gap.

[0030] The gate dielectric layer 350 is formed to have a thickness 360. The value of the thickness 360 can be flexibly configured by adjusting the process parameters of the deposition process 310, for example, by adjusting the process duration of the deposition process 310. In some embodiments, the thickness 360 is configured in a range between about 0.9 nm (9 angstroms) and about 1.4 nm (14 angstroms). As explained in detail below, such a range of the thickness 360 is not randomly chosen, but is specifically configured to optimize the performance of the IC device 90. For example, such a range of values ​​of the thickness 360 contributes to optimizing a trade-off between the gate leakage and the effective gate thickness.If the thickness 360 is too high, the overall gate dielectric constant may not be sufficiently high, which may affect device performance, such as speed. If the thickness 360 is too small, the overall gate leakage may be too high because the gate dielectric layer to be formed over the gate dielectric layer 350 will have a higher dielectric constant (and therefore a larger gate leakage), as explained in detail below.

[0031] With reference now to Fig. 10 and Fig. 11, a deposition process 380 is performed on the IC device 90 to form a gate dielectric layer 390 over the gate dielectric layer 350. The deposition process 380 may include another ALD process. In some embodiments, the ALD process of the deposition process 380 and the ALD process of the deposition process 290 may be performed in a same deposition chamber. The gate dielectric layer 390 includes a different type of high-k dielectric material that is different from the high-k dielectric material of the gate dielectric layer 350. In other words, although both the gate dielectric layer 350 and the gate dielectric layer 390 may each be a high-k dielectric material, they include different high-k material compositions from each other. For example, the gate dielectric layer 390 has a larger dielectric constant than the gate dielectric layer 350.As a result, gate dielectric layer 390 can help increase the overall dielectric constant of the gate dielectric as a whole, thereby achieving a lower equivalent oxide thickness without excessively increasing the overall thickness of the gate dielectric. With the higher dielectric constant, IC device 90 can achieve higher speed.

[0032] As another example, gate dielectric layer 390 has fewer traps than gate dielectric layer 350. Traps can be considered defects. Traps within a film can be induced by incomplete atom-to-atom bonding of the film. If the traps trap ionic chargers (e.g., electrons or holes), this can have negative electrical effects on mobility / velocity, noise, and / or threshold voltage. Trap content within a particular material can be measured using various techniques, for example, a 1 / f noise measurement method. Such techniques can be used to determine the material composition of a layer by measuring the trap content of such a layer.By having a lower trap content, the gate dielectric layer 390 can help reduce the noise introduced by the gate structure, which in turn helps to increase a window for circuit design or reduce the chip area.

[0033] However, the higher dielectric constant of gate dielectric layer 390 may exhibit a smaller band gap, which could lead to increased gate leakage, as discussed above. Therefore, gate dielectric layer 390 should not be the sole gate dielectric layer of the gate structure. Instead, gate dielectric layer 390 is used in conjunction with the underlying gate dielectric layer 350 to optimize the performance of the entire gate structure. In other words, gate dielectric layer 350 and gate dielectric layer 390 are selected or configured for different purposes or roles.For gate dielectric layer 350, as a lower layer in direct physical contact with interface layer 300 (and also closer to the channel region of the transistor), it is more important that gate dielectric layer 350 can form a good interface or have good integration with interface layer 300 and the underlying channel region. In comparison, for gate dielectric layer 390, as an upper layer farther from interface layer 300 and the channel region of the transistor, it is of less importance whether gate dielectric layer 390 can form a good interface with the interface layer. Instead, it is more important that gate dielectric layer 390 has a larger dielectric constant (to increase the overall dielectric constant of the gate dielectric structure).The reduced trapping of gate dielectric layer 390 also contributes to noise reduction and can improve speed and increase the circuit design window. The increased gate leakage associated with the higher dielectric constant of gate dielectric layer 390 is offset by the decreased gate leakage associated with the lower dielectric constant (still greater than that of silicon oxide) of the underlying gate dielectric layer 350.

[0034] In some embodiments, the gate dielectric layer 390 does not contain hafnium oxide, but may contain zirconium oxide (ZrOx), titanium oxide (TiO2), lanthanum oxide (La2O3), or combinations thereof. Zirconium oxide has a dielectric constant of about 29, titanium oxide has a dielectric constant of about 80, and lanthanum oxide has a dielectric constant of about 30. In other words, all of these material candidates for the gate dielectric layer 390 have dielectric constants that are not only greater than the dielectric constant of silicon oxide, but also greater than the dielectric constant of hafnium oxide, which is about 22. Again, such a high dielectric constant of the gate dielectric layer 390 allows the overall dielectric constant of the gate dielectric structure to be increased, thereby enabling a thinner equivalent oxide thickness and higher speed.

[0035] The gate dielectric layer 390 is formed with a thickness 400. The value of the thickness 400 can be set by adjusting the process parameters of the deposition process 380, for example, by adjusting the process duration of the deposition process 380. According to embodiments of the present disclosure, the thickness 360 of the gate dielectric layer 350 is substantially greater than the thickness 400 of the gate dielectric layer 390. For example, in some embodiments, the thickness 360 is in a range between about 0.9 nm (9 angstroms) and about 1.4 nm (14 angstroms), while the thickness 400 is in a range between about 0.25 nm (2.5 angstroms) and about 0.7 nm (7 angstroms). In some embodiments, the ratio of the thickness 360 to the thickness 400 is in a range between about 1.3:1 and about 5.6:1. In some embodiments, the ratio of thickness 360 to thickness 400 is in a range between about 2:1 and about 3.6:1.Again, these ranges of thickness 360 and thickness 400 and their ratios are not randomly chosen, but are specifically designed to optimize the performance of the IC device 90, such that the speed and / or gate leakage of the IC device 90 is optimized without compromising the effective gate thickness. For example, if the gate dielectric layer 350 is too thick compared to the gate dielectric layer 390, the overall dielectric constant of the gate dielectric structure may not be large enough to achieve a low equivalent oxide thickness, meaning that the gate structure may not be able to be downsized as much as desired. On the other hand, if the gate dielectric layer 350 is too thin compared to the gate dielectric layer 390, the gate leakage could be greater than desired and / or the integration between the overall dielectric structure and the interface layer 300 could suffer.The ranges discussed above ensure that the gate dielectric structure can continue to have good integration with the underlying layers while achieving sufficient equivalent oxide thickness without having to make the gate dielectric thicker and without unduly increasing the gate leakage.

[0036] With reference to Fig. 12 and Fig. 13, one or more deposition processes 420 are performed on the IC device 90 to form gate electrodes 430 over the gate dielectric layer 390. The gate electrodes 430 include metal and may include multiple layers, such as one or more capping layers, work function layers, adhesion / barrier layers, and / or metal fill (or bulk) layers. A capping layer may include a material that prevents and / or eliminates the diffusion and / or reaction of constituents between the gate dielectric layers 350 and 390 and other layers of the gate electrodes 430. In some implementations, the capping layer includes a metal and nitrogen, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (W2N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or combinations thereof.A work function layer includes a conductive material tuned to have a desired work function (e.g., an n-type work function or a p-type work function), such as n-type work function materials and / or p-type work function materials. P-type work function materials include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other p-type work function materials, or combinations thereof. N-type work function materials include Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other n-type work function materials, or combinations thereof.An adhesion / barrier layer may include a material that promotes adhesion between adjacent layers, such as the work function layer and the metal fill layer, and / or a material that blocks and / or reduces diffusion between gate layers, such as the work function layer and the metal fill layer. The adhesion / barrier layer includes, for example, metal (e.g., W, Al, Ta, Ti, Ni, Cu, Co, other suitable metals, or combinations thereof), metal oxides, metal nitrides (e.g., TiN), or combinations thereof. A metal fill layer serves as the main conduction portion of the gate electrode 430 and may include a suitable conductive material, such as Al, W, and / or Cu. For simplicity, the various layers of the gate electrodes 430 are not illustrated in detail herein.

[0037] After all layers of the gate electrodes 430 are deposited, a planarization process, such as a chemical mechanical polishing (CMP) process, may be performed on the IC device 90. The planarization process may remove the excess portions of the interface layer 300, the gate dielectric layer 350, the gate dielectric layer 390, and the gate electrodes 430 outside the trenches 280 until the remaining portions of the interface layer 300, the gate dielectric layer 350, the gate dielectric layer 390, and the gate electrodes 430 have top surfaces that are substantially coplanar (e.g., horizontally flat) with the ILD layers 250. At this stage of fabrication, HKMG structures are formed that include the remaining portions of the interface layer 300, the gate dielectric layer 350, the gate dielectric layer 390, and the gate electrodes 430 that fill the trenches 280.

[0038] It should be understood that additional manufacturing processes may be performed to complete the fabrication of the IC device 90. For example, a multilayer interconnect (MLI) structure may be formed. The MLI structure electrically couples various devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or components (e.g., gate structures and / or source / drain features) of the IC device 90 to one another such that the various devices and / or components operate as specified by the design requirements of the IC device 90. The MLI structure may include a combination of dielectric layers and electrically conductive layers (e.g., metal lines, vias, and contacts) configured to form various interconnect structures.The conductive layers are configured to form vertical (intermediate) interconnect features (providing, for example, a vertical connection between features and / or vertical electrical routing) such as contacts and / or vias and / or horizontal (intermediate) interconnect features (providing, for example, horizontal electrical routing) such as conductive traces. Vertical (intermediate) interconnect features typically interconnect horizontal interconnect features in different layers (or different levels) of the MLI structure. During operation, the MLI structure routes signals between the devices and / or components of the IC device 90 and / or distributes signals (for example, clock signals, voltage signals, and / or ground signals) to the devices and / or components of the IC device 90.

[0039] Fig. 14 shows a portion of the IC device 90 and a diagram 500 shown adjacent to the portion of the IC device 90. In this regard, the illustrated portion of the IC device 90 includes portions of the fin structure 120, the interface layer 300, the gate dielectric layer 350, the gate dielectric layer 390, and the gate electrode 430. The portion of the IC device 90 as shown in Fig. 14 may also correspond to a cross-sectional view of the IC device 90, for example, the XZ cross-sectional view or the YZ cross-sectional view.

[0040] The diagram 500 has an H-axis as the horizontal axis and the Z-axis as the vertical axis. The Z-axis corresponds to the same Z-axis (or the Z-direction) of the IC device 90. In other words, movements up and down along the Z-axis in the diagram 500 correspond to vertical movements of the IC device 90 up and down (for example, into and out of different layers). The H-axis represents a concentration level of a material. Movement to the "left" along the H-axis means an increase in the concentration level of the material, and movement to the "right" along the H-axis means a decrease in the concentration level of the material.

[0041] The diagram 500 includes a curve 510 and a curve 520. The curve 510 represents the concentration level of a material of the gate dielectric layer 350 as a function of its position along the Z-axis, and the curve 520 represents the concentration level of a material of the gate dielectric layer 390 as a function of its position along the Z-axis. In an embodiment where the gate dielectric layer 350 includes a hafnium oxide material composition and the gate dielectric layer 390 includes a zirconium oxide material composition (for example, only as a non-limiting exemplary material of the layer 390), the curve 510 represents how the concentration level of hafnium oxide varies as a function of the vertical position within the IC device 90 (i.e.,up and down along the Z-axis), and curve 520 represents how the concentration level of zirconium oxide varies as a function of vertical position within the IC device 90 (i.e., up and down along the Z-axis). It should be understood that the vertical positions along the Z-axis of the graph 500 correspond to the vertical positions along the Z-axis of the IC device 90 in . Fig. 14. It should also be noted that the hafnium oxide composition and the zirconia composition for layers 350 and 390 are merely non-limiting examples, and that in alternative embodiments, other suitable materials may be used to implement layers 350 and 390.

[0042] From the diagram 500, it can be seen that the concentration level of the material of the gate dielectric layer 350 (e.g., hafnium oxide) starts at a negligibly low level at the fin structures 120 (since the fin structures 120 do not contain, or at least are not intended to contain, hafnium oxide) and gradually increases into the interface layer 300, exhibiting a sharp peak in the gate dielectric layer 350 until a peak level 530 near a midpoint of the gate dielectric layer 350 is reached, and then gradually decreases. In some embodiments, the peak level 530 may be a function of the thickness of the layer 350. In other words, as the layer 350 becomes thicker, the peak level 530 may increase, and vice versa.

[0043] Meanwhile, the concentration level of the material of the gate dielectric layer 390 (e.g., zirconium oxide) also starts at a negligibly low level at the fin structures 120 (the fin structures 120 are also not zirconium oxide, or at least are not intended to be), remains relatively low in the interface layer 300 and the gate dielectric layer 350, and increases in the gate dielectric layer 390 until it reaches a peak level 540 near the center of the gate dielectric layer 390, after which it gradually decreases. In some embodiments, the peak level 540 may be a function of the thickness of the layer 390. In other words, as the layer 390 becomes thicker, the peak level 540 may increase, and vice versa. In some embodiments, the ratio between the peak value 530 and the peak value 540 ranges between about 6:1 and about 22:1.It should be understood that the ranges and ratios pertaining to peak level 530 and peak level 540 are not chosen randomly, but are specifically established to optimize the performance of IC device 90. For example, these ranges and ratios allow gate dielectric layer 350 to effectively form a good interface with underlying interface layer 300 and allow gate dielectric layer 390 to simultaneously increase the overall dielectric constant of the gate dielectric structure without contributing too much to gate leakage.

[0044] The diagram 500 may also depict the conditions or characteristics of the IC device 90 in an exemplary real-world environment. For example, although the drawings discussed above depict a distinct boundary between the gate dielectric layer 350 and the gate dielectric layer 390, such a distinct boundary may be absent in the real-world IC device 90. Instead, the materials of the gate dielectric layers 350 and 390 may blend or diffuse into each other to some extent, making any boundary between the two layers difficult to discern.However, using equipment such as transmission electron microscopy (TEM) tools and / or energy dispersive x-ray spectroscopy (EDS or EDX) tools, the concentration levels of the various materials of gate dielectric layer 350 and gate dielectric layer 390 can be identified as a function of vertical position within IC device 90. Thus, by using the TEM tools or the EDS tools to reverse engineer an IC device, one may determine that an IC device has implemented a multilayer gate dielectric similar to the embodiments of the present disclosure.

[0045] The above explanations relate to a double-layer dielectric gate scheme. However, the concepts of the present disclosure may also apply to a three-layer gate dielectric. One embodiment of the three-layer gate dielectric is described in Fig. 15-16, which are also cross-sectional views of the IC device in the XZ plane and in the YZ plane. For the sake of consistency and clarity, similar components are shown in Fig. 2-14 and 15-16 are provided with the same reference numerals.

[0046] The stage of production as in Fig. 15-16 shows the same stage of production as in Fig. 12-13. In addition to the gate dielectric layers 350 and 390, the gate dielectric structure in this embodiment further comprises a gate dielectric layer 450 formed by a deposition process 440, for example, an ALD process. The gate dielectric layer 450 is formed directly on the gate dielectric layer 390 and directly below the gate electrode 430. The gate dielectric layer 450 includes a different material composition than the gate dielectric layers 350 and 390.In detail, while gate dielectric layer 350 is configured to form a good interface with interface layer 300 or to have good integration with the underlying channel, and gate dielectric layer 390 is configured to increase the overall dielectric constant of the gate structure and reduce noise, gate dielectric layer 450 is configured to assist gate electrode 430 in adjusting the threshold voltage. For example, the material composition of gate dielectric layer 450 is selected to assist the work function of the metal layers of gate electrode 430 in adjusting the threshold voltage.In some embodiments, the gate dielectric layer 350 includes a hafnium oxide material composition, the gate dielectric layer 390 includes a zirconium oxide material composition, and the gate dielectric layer 450 includes an aluminum oxide (Al2O3) material composition or a lanthanum oxide (La2O3) material composition.

[0047] The gate dielectric layer 450 is formed to have a thickness 460. The thickness 460 is less than the thickness 400 of the gate dielectric layer 390 and less than the thickness 360 of the gate dielectric layer 350. Again, the thickness 460 can be adjusted by adjusting the process parameters (e.g., deposition time) of the deposition process 440. In some embodiments, the thickness 460 is adjusted to be in a range between about 0.15 nm (1.5 angstroms) and about 0.25 nm (2.5 angstroms), a ratio of the thickness 360 to the thickness 460 is in a range between about 5:1 and about 10:1, and a ratio of the thickness 400 to the thickness 460 is in a range between about 1:1 and about 4:1.These ranges and ratios are not randomly chosen, but are specifically designed to ensure that gate dielectric layer 450 can adequately support threshold voltage adjustment without degrading the gate dielectric constant or noise level. Thus, each of gate dielectric layers 350, 390, and 450 can adequately and efficiently fulfill its respective role, for example, forming a good interface with interface layer 300, increasing the overall dielectric constant of the gate structure, reducing noise, and facilitating threshold voltage adjustment.

[0048] Fig. 17 shows a portion of the IC device 90 and a diagram 600 shown next to the portion of the IC device 90. While the diagram 500 in Fig. 14 of the embodiment with a two-layer gate dielectric as described above with reference to Fig. 2-13, the diagram 600 corresponds to the embodiment with a three-layer gate dielectric as described above with reference to Fig. 15-16. For simplicity, similar components are shown in Fig. 14 and Fig. 17 are provided with the same reference numerals.

[0049] As with diagram 500, diagram 600 includes curve 510 and curve 520, which represent the variations in the concentration levels of gate dielectric layer 350 and gate dielectric layer 390 along the vertical Z axis. Diagram 600 further includes curve 610, which represents the variation in the concentration levels of gate dielectric layer 450 along the vertical Z axis.

[0050] Curve 610 shows that the concentration level of the material of gate dielectric layer 450 (e.g., aluminum oxide or lanthanum oxide) also starts at a negligibly low level at fin structures 120 (again, fin structures 120 are not, or at least are not intended to contain, aluminum oxide or lanthanum oxide), remains relatively low in interface layer 300 and gate dielectric layers 350 and 390, and increases in gate dielectric layer 450 until a peak level 620 near the center of gate dielectric layer 450 is reached, after which it gradually decreases. Again, peak level 620 may be a function of the thickness of the gate dielectric layer. Peak level 620 is lower than peak levels 540 and 530. In some embodiments, a ratio of peak level 620 to peak level 530 ranges between about 1:19 and about 1:40.It should be understood that the ranges and ratios affecting peak levels 620 and 530 are not chosen randomly, but are specifically established to optimize the performance of IC device 90. These ranges and ratios allow, for example, gate dielectric layer 450 to be thick enough to adequately assist the work function metal in setting the threshold voltage, but not so thick that the dielectric constant of the overall gate dielectric structure decreases too much or introduces too much noise.

[0051] The multilayer gate dielectric structure of the present disclosure can be applied to various types of IC applications. For example, a multilayer gate dielectric structure can be implemented in an SRAM device. An SRAM device is a type of semiconductor memory that uses a bistable latch (e.g., a flip-flop) to store binary bits of information. A typical SRAM cell may include pull-up transistors (PU transistors), pull-down transistors (PD transistors), and pass-gate transistors (PG transistors). As semiconductor technology nodes evolve to smaller generations (e.g., smaller than the 10-nanometer node), SRAM write and read margins may become more important. An SRAM alpha ratio—defined as Id sat (saturation current) of the PU divided by Id satof the PG - can be adjusted to achieve the desired write and / or read range of the SRAM. Since Id sat an inverse function of a threshold voltage (V t ), the threshold voltage can be adjusted so that the desired Id sat is achieved.

[0052] Fig. 18 shows an exemplary circuit diagram for a single-port SRAM cell (e.g., 1-bit SRAM cell) 800. The single-port SRAM cell 800 includes pull-up transistors PU1 and PU2, pull-down transistors PD1 and PD2, and passgate transistors PG1 and PG2. As shown in the circuit diagram, transistors PU1 and PU2 are p-type transistors, and transistors PG1, PG2, PD1, and PD2 are n-type transistors. Since the SRAM cell 800 includes six transistors in the depicted embodiment, it may also be referred to as a 6T SRAM cell.

[0053] The drains of pull-up transistor PU1 and pull-down transistor PD1 are coupled together, and the drains of pull-up transistor PU2 and pull-down transistor PD2 are coupled together. Transistors PU1 and PD1 are cross-coupled with transistors PU2 and PD2 to form a first data latch. The gates of transistors PU2 and PD2 are coupled together and to the drains of transistors PU1 and PD1 to form a first storage node SN1, and the gates of transistors PU1 and PD1 are coupled together and to the drains of transistors PU2 and PD2 to form a complementary first storage node SNB1. The sources of the pull-up transistors PU1 and PU2 are coupled to the supply voltage Vcc (also referred to as Vdd) and the sources of the pull-down transistors PD1 and PD2 are coupled to a voltage Vss, which in some embodiments may be electrical ground.

[0054] The first storage node SN1 of the first data buffer is coupled to the bit line BLB via the passgate transistor PG1, and the complementary first storage node SNB1 is coupled to the complementary bit line BLB via the passgate transistor PG2. The first storage node N1 and the complementary first storage node SNB1 are complementary nodes that are often at opposite logic levels (logic high or logic low). The gates of the passgate transistors PG1 and PG2 are coupled to a word line WL.

[0055] Again, according to various aspects of the present disclosure, each of the transistors PU1, PU2, PD1, PD2, PG1, and PG2 can be implemented with a two-layer or three-layer gate dielectric structure as explained above. In this way, the problems of gate leakage and further the performance of the SRAM device are improved, for example, in terms of speed and power dissipation. It should be understood that although SRAM devices are used herein as a non-limiting example of IC applications that could implement the various aspects of the present disclosure, other types of IC applications could also implement the various aspects of the present disclosure.For example, the multilayer gate dielectric scheme described herein may be applied to peripheral logic circuits in an SRAM device (such as row decoders, column decoders, read / write circuits) or to other circuit devices such as ring oscillators, radio frequency (RF) devices, amplifiers, mixers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and the like.

[0056] Fig. 19 shows a system 900 for manufacturing integrated circuits according to embodiments of the present disclosure. The manufacturing system 900 includes multiple units 902, 904, 906, 908, 910, 912, 914, 916, ..., N interconnected by a communications network 918. The network 918 may be a single network or multiple different networks, such as an intranet and the Internet, and may include both wired and wireless communication channels.

[0057] In one embodiment, unit 902 represents a manufacturing collaboration service system; unit 904 represents a user, such as a product engineer, who monitors the products of interest; unit 906 represents an engineer, such as a processing engineer for controlling the process and relevant recipes or an equipment engineer for monitoring or adjusting conditions and setting processing tools; unit 908 represents a metrology tool for testing and measuring ICs; unit 910 represents a semiconductor processing tool, such as an EUV tool used to perform lithography processes; unit 912 represents a virtual metrology module connected to processing tool 910;Unit 914 represents an advanced processing control module connected to processing tool 910 and, in addition, other processing tools; and unit 916 represents a scanning module connected to processing tool 910.

[0058] Each unit may interact with other units and may provide integrated circuit fabrication, processing control, and / or computing capabilities and / or receive such capabilities from the other units. Each unit may also include one or more computer systems for performing computations and performing automation. For example, the advanced processing control module of unit 914 may include multiple pieces of computer hardware with software instructions encoded therein. The computer hardware may include hard drives, flash drives, CD-ROMs, RAM memory, display devices (e.g., monitors), and input / output devices (e.g., mouse and keyboard). The software instructions may be written in any suitable programming language and designed to perform specific tasks.

[0059] The integrated circuit manufacturing system 900 enables interaction between integrated circuit (IC) manufacturing units and advanced processing control of the IC manufacturing. In one embodiment, advanced processing control includes adjusting the processing conditions, configuration, and / or recipes of a processing tool applicable to the respective wafers according to the measurement results.

[0060] In another embodiment, the measurement results are measured on a subset of processed wafers according to an optimal sampling rate determined based on the process and / or product quality. In another embodiment, the measurement results are measured from selected fields and points of the subset of processed wafers according to an optimal sampling field / point determined based on various characteristics of the process and / or product quality.

[0061] One of the capabilities provided by the IC manufacturing system 900 can enable collaboration and information access in areas such as design, engineering, and processing, metrology, and advanced processing control. Another capability provided by the IC manufacturing system 900 can integrate systems between facilities, for example, between the metrology tool and the processing tool. Such integration allows the facilities to coordinate their activities. For example, integrating the metrology tool and the processing tool can enable manufacturing information to be more efficiently integrated into the manufacturing process or the APC module and enable wafer data to be obtained from online or on-site metrology with the processing tool integrated with the associated metrology tool.

[0062] Fig.20 is a flowchart illustrating a method 1000 for fabricating a semiconductor device according to another embodiment of the present disclosure. The method 1000 includes a step 1010 of forming an interface layer over a channel region of a substrate.

[0063] The method 1000 includes a step 1020 of depositing, using a first atomic layer deposition (ALD) process, a first type of dielectric material as a first portion of a gate dielectric over the interface layer. The first type of dielectric material has a first dielectric constant greater than the dielectric constant of silicon oxide.

[0064] The method 1000 includes a step 1030 of depositing, using a second ALD process, a second type of dielectric material as a second portion of the gate dielectric over the first type of dielectric material. The second type of dielectric material has a second dielectric constant greater than the first dielectric constant.

[0065] The method 1000 includes a step 1040 of forming a metal-containing gate electrode over the second type of dielectric material.

[0066] In some embodiments, the first ALD process and the second ALD process are performed in the same ALD chamber, and the first ALD process is performed with a longer process duration than the second ALD process. In some embodiments, the process durations of the first ALD process and the second ALD process are configured such that the first type of dielectric material is thicker than the second type of dielectric material by a factor of about 1.3 to about 5.6.

[0067] In some embodiments, forming the metal-containing gate electrode comprises depositing a work function metal component of a gate electrode directly on the second type of dielectric material, and depositing a fill metal component of the gate electrode over the work function metal component.

[0068] It should be understood that additional steps may be performed before, during, or after steps 1010-1040. For example, after the second ALD process has been performed and before the metal-containing gate electrode is formed, the method may include a step of depositing, by a third ALD process, a third type of dielectric material as a third portion of the gate dielectric over the second type of dielectric material. The third type of dielectric material is different from the first type of dielectric material and the second type of dielectric material. In some embodiments, depositing the first type of dielectric material includes depositing hafnium oxide directly on a top surface of the interface layer.In some embodiments, depositing the second type of dielectric material comprises depositing zirconium oxide directly onto a top surface of the first type of dielectric material. In some embodiments, depositing the third type of dielectric material comprises depositing lanthanum oxide or aluminum oxide directly onto a top surface of the second type of dielectric material. Additional steps may include forming additional interconnect features, packaging, or testing processes.

[0069] Overall, the present disclosure is concerned with forming a multi-layer gate dielectric structure rather than a single-layer gate dielectric structure. The multi-layer gate dielectric structure implements different types of materials for each of the gate dielectric layers, with each type of material (and respective thicknesses) selected to achieve a specific objective. For example, in the two-layer gate dielectric scheme, the bottom gate dielectric layer comprises a material and thickness configured to form a good interface and / or good integration with the interface layer and / or the underlying channel, and the top gate dielectric layer comprises a material and thickness configured to increase the overall dielectric constant and reduce the noise level.In the three-layer gate dielectric scheme, the lower gate dielectric layer has a material and a thickness configured to form a good interface and / or good integration with the interface layer and / or the underlying channel, the middle gate dielectric layer has a material and a thickness configured to increase the overall dielectric constant and reduce the noise level, and the upper gate dielectric layer has a material and a thickness configured to facilitate the adjustment of the threshold voltage.

[0070] Based on the foregoing explanations, it can be seen that the present disclosure offers advantages over conventional source / drain vias. However, it should be understood that not all advantages are explained herein, that different embodiments may achieve different advantages, and that no particular advantage is required for any embodiment. One of the advantages is that the present disclosure enables the further development of the miniaturization process. Conventional single-layer gate dielectric structures may no longer be feasible or suffer performance degradation when the device size reaches the 7 nm technology node or even below. For example, when the gate dielectric is implemented using a silicon oxide material, the gate dielectric should be very thin.Second, if the gate dielectric is implemented using a high-k material such as hafnium oxide, it may not achieve the high dielectric constant required to meet performance requirements such as speed. If the gate dielectric is implemented using a high-k material with an even higher dielectric constant than hafnium oxide, the narrower band gap associated with such high-k dielectric materials may lead to excessive gate leakage, increasing power consumption and compromising the reliability of the IC device.

[0071] In contrast, the multilayer gate dielectric scheme uses multiple gate dielectric layers to achieve different goals simultaneously. In some embodiments, a bottom layer of the gate dielectric structure is configured to form a good interface and / or have good integration with the underlying layers (e.g., the interface layer or the channel) to prevent the formation of defects at the bottom of the gate dielectric. The bottom layer also has a relatively high band gap among the high-k dielectric materials, which helps reduce gate leakage.Meanwhile, the top layer (in a two-layer gate dielectric scheme) or the middle layer (in a three-layer gate dielectric scheme) contains a different material composition than the bottom layer. For example, it may contain a material composition associated with a higher dielectric constant and / or fewer traps than the bottom layer. Thus, the top / middle layer can increase the overall dielectric constant of the gate dielectric structure, allowing the gate dielectric structure to achieve a thin thickness required for advanced technology nodes. The high-k dielectric constant contributes to increasing the speed of the IC device. The fewer traps in the middle layer also contributes to reducing the noise level, allowing the circuit design window to be increased and the chip area to be reduced.In the three-layer scheme, where a top layer is implemented, such a top layer further contains a material composition specifically configured to assist the gate electrode in adjusting the threshold voltage. On this basis, the multilayer gate dielectric structure can achieve a low equivalent oxide thickness while remaining thin, and it further reduces (or at least does not increase) gate leakage and improves device performance in terms of, for example, speed, power dissipation, noise, and reliability. Other advantages may include compatibility with existing manufacturing processes and simple and cost-effective implementation.

[0072] The advanced lithography process, method, and materials discussed above can be used in many applications, including fin field-effect transistors (FinFETs). For example, the fins can be patterned to create a relatively narrow spacing between features, for which the above disclosure is well-suited. Furthermore, spacers used in the formation of FinFET fins, also referred to as mandrels, can be processed according to the above disclosure.

[0073] It should be understood that the multilayer gate dielectric structures of the present disclosure discussed above can also be applied to multi-channel devices such as gate-all-around (GAA) devices. In this context, GAA devices include fin structures as discussed above and include multi-channel structures such as stacks of nanosheets, nanowires, or nanotubes formed over fin structures and wrapped by the gate. Gate dielectric structures (e.g., bilayer or trilayer structures) can surround each of the channels (e.g., in the form of a nanostructure such as a nanosheet or nanowire structure) 360 degrees circumferentially. Further details regarding the fabrication of GAA devices are described in U.S. Patent 10,164,012, entitled "Semiconductor Device and Manufacturing Method thereof," issued on June 25, 2001.December 2018, in U.S. Patent 10,361,278 entitled "Method of Manufacturing a Semiconductor Device and a Semiconductor Device," issued on July 23, 2019, and also in U.S. Patent 10,361,278 entitled "Multi-Gate Device and Method of Fabricating Thereof," issued on February 6, 2018, the disclosures of each of the foregoing being hereby incorporated by reference in their entirety. To the extent that the present disclosure relates to a fin structure or FinFET devices, these explanations may equally apply to GAA devices.

[0074] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims.

Claims

[1] Device comprising: a substrate (110); a first gate dielectric layer (350) disposed over the substrate (110), the first gate dielectric layer (350) containing a first material composition; and a second gate dielectric layer (390) disposed over the first gate dielectric layer (350) and in direct physical contact with the first gate dielectric layer (350), the second gate dielectric layer (390) containing a second material composition, wherein the first material composition is different from the second material composition, and wherein the first material composition and the second material composition each have a greater dielectric constant than a dielectric constant of silicon oxide, wherein the second material composition has a greater dielectric constant than the first material composition, and wherein the first gate dielectric layer (350) has a first thickness (360), the second gate dielectric layer (390) has a second thickness (400), and wherein the ratio of the first thickness (360) to the second thickness (400) is between about 1.3:1 and about 5.6:

1. [2] The device of claim 1, wherein the second material composition has fewer traps than the first material composition. [3] Device according to one of the preceding claims, wherein the first material composition contains hafnium oxide, and wherein the second material composition contains zirconium oxide, titanium oxide or lanthanum oxide. [4] The device of any one of claims 1 to 3, wherein the ratio of the first thickness (360) to the second thickness (400) is between about 2:1 and about 3.6:

1. [5] Device according to one of the preceding claims, further comprising: a third gate dielectric layer (450) disposed over the second gate dielectric layer (390), wherein the third gate dielectric layer (450) includes a third material composition different from the first material composition and the second material composition. [6] Device according to claim 5, wherein the first material composition contains hafnium oxide, wherein the second material composition contains zirconium oxide, and wherein the third material composition contains lanthanum oxide or aluminum oxide. [7] The device of any preceding claim, further comprising an interface layer (300) disposed between the substrate (110) and the first gate dielectric layer (350). [8] The device of claim 7, wherein the first gate dielectric layer (350) is disposed directly on the interface layer (300). [9] Apparatus according to claim 7 or 8, further comprising Gate spacers (230), wherein the interface layer (300) is arranged on side surfaces of the gate spacers (230); or Fin structures (120), wherein the interface layer (300) is arranged on side surfaces of the fin structures (120). [10] Device comprising: a source region (122) and a drain region (122) arranged in a substrate (110); a channel region disposed between the source region (122) and the drain region (122); and a gate structure (140) disposed over the channel region, the gate structure (140) comprising a gate dielectric component and a metal-containing gate electrode component; wherein the gate dielectric component comprises a plurality of different dielectric layers (350, 390), each having a greater dielectric constant than a dielectric constant of silicon oxide, and wherein the different dielectric layers (350, 390) have different dielectric constants from each other, wherein the plurality of different dielectric layers (350, 390) comprise a first dielectric layer (350) disposed over the channel region and a second dielectric layer (390) disposed directly on the first dielectric layer (350), wherein the first dielectric layer (350) has a first thickness (360), the second dielectric layer (390) has a second thickness (400), wherein the ratio of the first thickness (360) to the second thickness (400) is between about 1.3:1 and about 5.6:1, and wherein the second dielectric layer (390) has a greater dielectric constant than the first dielectric layer (350). [11] Device according to claim 10, wherein the plurality of different dielectric layers (350, 390) further comprise a third dielectric layer (450) disposed over the second dielectric layer (390), wherein the first dielectric layer contains hafnium oxide, wherein the second dielectric layer contains zirconium oxide, and wherein the third dielectric layer contains lanthanum oxide or aluminum oxide. [12] The device of claim 10 or 11, wherein the different dielectric layers (350, 390) have different levels of traps therein. [13] Method comprising: Forming an interface layer (300) over a channel region of a substrate (110); depositing, using a first ALD process, a first type of dielectric material as a first portion of a gate dielectric (350, 390) over the interface layer (300), wherein the first type of dielectric material has a first dielectric constant greater than a dielectric constant of silicon oxide; Depositing, using a second ALD process, a second type of dielectric material as a second portion of the gate dielectric (350, 390) directly on the first type of dielectric material, wherein the second type of dielectric material has a second dielectric constant greater than the first dielectric constant, and wherein the thickness (360) of the first dielectric material is greater than the thickness (400) of the second dielectric material, wherein a process duration of the first ALD process and the second ALD process is arranged such that the first type of dielectric material is thicker than the second type of dielectric material by a factor of between about 1.3 and about 5.6; and Forming a metal-containing gate electrode (430) over the second type of dielectric material. [14] Method according to claim 13, wherein the first ALD process and the second ALD process are carried out in a same ALD chamber, and where the first ALD process is performed with a longer process duration than the second ALD process. [15] The method of claim 13 or 14, further comprising: Depositing, by a third ALD process, a third type of dielectric material as a third portion of the gate dielectric (350, 390) over the second type of dielectric material, wherein the third type of dielectric material is different from the first type of dielectric material and the second type of dielectric material. [16] Method according to claim 15, wherein depositing the first type of dielectric material comprises depositing hafnium oxide directly on a top surface of the interface layer (300), wherein depositing the second type of dielectric material comprises depositing zirconium oxide directly on a top surface of the first type of dielectric material, and wherein depositing the third type of dielectric material comprises depositing lanthanum oxide or aluminum oxide directly on a top surface of the second type of dielectric material. [17] The method of any one of claims 13 to 16, wherein forming the metal-containing gate electrode (430) comprises: depositing a work function metal component of a gate electrode (430) directly on the second type of dielectric material; and Depositing a fill metal component of the gate electrode (430) over the work function metal component.

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