DUMMY FIN PROFILE CONTROL FOR ENLARGED GATE PROCESS WINDOW AND ASSOCIATED SEMICONDUCTOR DEVICE

Abstract

Procedure comprehensive: Forming isolation regions (22) extending into a semiconductor substrate (20), wherein semiconductor strips (24) are located between the isolation regions (22); Forming a dielectric dummy strip (25) between the insulation areas (22); Recessing the insulation regions (22) such that some sections of the semiconductor strips (24) protrude higher than the upper surfaces of the recessed insulation regions (22) to form protruding semiconductor fins (24'), and that a section of the dielectric dummy strip (25) protrudes higher than the upper surfaces of the recessed insulation regions (22) to form a dielectric dummy fin (25'); Etching the dielectric dummy fin (25') such that an upper width of the dielectric dummy fin (25') is smaller than a lower width of the dielectric dummy fin (25'); and Forming a gate stack (30) on the upper surfaces and side walls of the protruding semiconductor fins (24') and the dielectric dummy fin (25'), wherein the dielectric dummy fin (25') has multiple sublayers, wherein outer sublayers of the multiple sublayers have sections opposite to each other on opposite sides of respective inner sublayers of the multiple sublayers, and wherein upper surfaces of the outer sublayers are lower than upper surfaces of the respective inner sublayers.

Description

BACKGROUND

[0001] Metal-oxide-semiconductor devices (MOS devices) are fundamental devices in integrated circuits. A typical MOS device has a gate electrode made of polysilicon doped with p- or n-type impurities, using doping operations such as ion implantation or thermal diffusion. The work function of the gate electrode is adjusted to the silicon band edge. For an NMOS device (N-type metal-oxide-semiconductor device), the work function can be adjusted to be close to the silicon band edge. For a PMOS device (P-type metal-oxide-semiconductor device), the work function can be adjusted to be close to the silicon valence band. Adjusting the work function of the polysilicon gate electrode can be achieved by selecting appropriate impurities.

[0002] MOS devices with polysilicon gate electrodes exhibit a carrier depletion effect, also known as the polydepletion effect. This effect occurs when applied electric fields drive charge carriers from gate regions near the gate dielectric, forming depletion layers. In an N-doped polysilicon layer, the depletion layer contains ionized, non-mobile donor sites, while in a P-doped polysilicon layer, the depletion layer contains ionized, non-mobile acceptor sites. The depletion effect leads to an increase in the effective thickness of the gate dielectric, making it more difficult to create an inversion layer on the semiconductor surface.

[0003] The polydepletion problem can be solved by fabricating metal-gate electrodes or metal-silicide-gate electrodes, where the metallic gates used in NMOS and PMOS devices can also exhibit edge-to-edge exit work. Since NMOS and PMOS devices have different exit work requirements, dual-gate CMOS devices are used.

[0004] Prior art relating to the subject matter of the invention can be found, for example, in DE 10 2019 101555 A1, US 2020 / 0 135 723 A1 and US 2019 / 0 067 417 A1.

[0005] The invention is defined by the main claim and the dependent claims. Further examples of the invention are given by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figures 1-9, 10A, 10B, 11A, 11B, 12, 13A, 13B, 14 and 15 show the cross-sectional views and perspective views of intermediate stages in the formation of dielectric dummy fins, fin field-effect transistors (FinFETs) and gate isolation regions by cutting dummy gate stacks according to some examples. Fig. 16, Fig. 17, Fig. 18A and Fig. Figure 18B shows the cross-sectional views and perspective views of the formation of a gate isolation area by cutting replacement gate stacks according to some examples. Fig. 3A, Fig. 3B, Fig. 3C, Fig. 3D, Fig. 3E, Fig. 3F and Fig. Figure 3G shows cross-sectional views of dummy strips according to some examples. Fig. Figures 19A, 19B and 20-31 show the cross-sectional views of dielectric dummy fins according to some examples. Fig. Figure 32 shows a process flow for the production of dielectric dummy fins, gate insulation areas and FinFETs according to some examples. DETAILED DESCRIPTION

[0007] The following disclosure provides many different examples of the implementation of various features of the invention. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, only examples and are not intended to be limiting. For instance, the formation of a first feature over or on top of a second feature in the following description may include examples in which the first and second features are formed in direct contact, but may also include examples in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, reference numerals may be repeated in the various examples of the present disclosure.This repetition serves the purpose of simplicity and clarity and does not, in principle, prescribe any relationship between the various examples and / or configurations discussed herein.

[0008] Furthermore, for the sake of simplicity, spatially relative terms such as "below," "down," "downward," "above," "upward," and the like may be used here to describe the relationship of an element or feature to one or more other elements or features as shown in the drawings. These spatially relative terms are intended to encompass various orientations of the device during use or operation, in addition to the orientation shown in the drawings. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptors used here may be interpreted accordingly.

[0009] Fin-type field-effect transistors (FinFETs) with dummy fins and gate isolation regions for separating the gate stacks of the FinFETs, and the method for their fabrication, are provided according to various examples. The intermediate steps in the formation of dummy fins, gate isolation regions, and the corresponding FinFETs are illustrated according to some examples. Some modifications of certain examples are discussed. The examples explained herein are intended to provide examples to enable the fabrication or use of the subject matter of this disclosure, and the person skilled in the art will readily understand what modifications can be made while remaining within the scope of the various examples. Reference symbols are used throughout the various views and illustrated examples to denote similar / identical elements.Although examples of procedures can be explained for execution in a specific order, other examples of procedures can be executed in any logical order.

[0010] According to some examples in the present disclosure, the fabrication of a dummy fin involves etching the dummy fin to reduce its upper width, which may be smaller than its lower width. Reducing the upper width of the dummy fin reduces the difficulty of the structuring process for manufacturing dummy gate stacks and also reduces the difficulty of manufacturing replacement gate stacks. This increases the associated process windows.

[0011] Fig. Figures 1-9, 10A, 10B, 11A, 11B, 12, 13A, 13B, 14-17, 18A, and 18B show cross-sectional and perspective views of the intermediate stages in the formation of dummy fins, fin field-effect transistors (FinFETs), and gate isolation regions, according to some examples. The respective processes are also schematically reflected in the process flow as shown in Fig. 32 is shown.

[0012] Fig. Figure 1 shows a perspective view of an initial structure. The initial structure includes the wafer 10, which in turn includes the substrate 20. The substrate 20 can be a semiconductor substrate, which may be a silicon substrate, a silicon-germanium substrate, or a substrate formed from other semiconductor materials. The substrate 20 can be doped with a p-type or an n-type impurity. Isolation regions 22, such as shallow trench isolation regions (STI), are formed such that they extend from an upper surface of the substrate 20 into the substrate 20. The associated process is referred to as process 202 in process flow 200 in Fig. Figure 32 illustrates this. The sections of substrate 20 between adjacent STI regions 22 are referred to as semiconductor strips 24. According to some examples of the present disclosure, the semiconductor strips 24 are parts of the original substrate 20, and therefore the material of the semiconductor strips 24 is the same as that of the substrate 20. According to alternative examples of the present disclosure, the semiconductor strips 24 are substitute strips formed by etching the sections of substrate 20 between the STI regions 22 to form recesses and performing an epitaxial process to grow a different semiconductor material in the recesses. Thus, the semiconductor strips 24 are formed from a semiconductor material different from that of the substrate 20.According to some examples, the semiconductor strips 24 are formed from Si, SiP, SiC, SiPC, SiGe, SiGeB, Ge or a III-V compound semiconductor such as InP, GaAs, AlAs, InAs, InAlAs, InGaAs or the like.

[0013] The STI regions 22 can contain a lining oxide (not shown), which may be a thermal oxide formed by the thermal oxidation of a surface layer of the substrate 20. The lining oxide can also be a deposited silicon oxide layer formed, for example, by atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), or the like. The STI regions 22 can also contain a dielectric material over the lining oxide, the dielectric material being formed by flowable chemical vapor deposition (FCVD), spin deposition, or the like.

[0014] Fig. 2 and Fig. Figure 3 shows the fabrication of the dielectric dummy strip 25 according to some exemplary examples. It should be understood that the dielectric dummy strip 25 can be formed by different methods. With reference to Fig. 2. A semiconductor strip 24 is left exposed by an etching process, forming the trench 23. The formation of the trench 23 involves creating an etch mask (not shown), such as a photoresist, to cover some sections of the wafer 10, exposing the semiconductor strip 24 to be etched to the opening in the etch mask. The exposed semiconductor strip 24 is then etched to form the trench 23. The bottom of the trench 23 can be higher than or at the same level as the lower surface of the STI area 22.

[0015] Fig. Figure 3 shows the fabrication of the dielectric dummy strip 25, comprising filling the cavity with a dielectric material and performing a planarization process, such as a chemical-mechanical polishing (CMP) process or a mechanical grinding process. The associated process is designated as process 204 in process sequence 200 in Fig. Figure 32. According to some examples in the present disclosure, the dummy strip material 25 comprises a silicon-based material such as SiN, SiON, SiOCN, SiC, SiOC, SiO2, SiGe, or the like. According to alternative examples in the present disclosure, the dummy strip material 25 comprises a metal-based material, which may be an oxide or nitride of a metal, wherein the metal may comprise Ta, Hf, Cr, Al, Ni, Fe, Y, Cu, Sn, Co, or combinations thereof. The deposition process for forming a dielectric dummy strip 25 may include ALD, plasma-enhanced atomic layer deposition (PEALD), physical vapor deposition (PVD), CVD, plasma-enhanced chemical vapor deposition (PECVD), or the like. The dielectric dummy strip 25 may comprise a single or multiple sublayers. Each of the sublayers of the dielectric dummy strip 25 can have a thickness in a range between about 0.3 nm and about 50 nm.

[0016] The dielectric dummy strip 25 can be a single-layer strip or a multi-layer strip with several sublayers, e.g., up to about 20 layers. Each sublayer can have a thickness in the range between about 0.5 nm and about 50 nm. Fig. 3A, Fig. 3B, Fig. 3C, Fig. 3D, Fig. 3E, Fig. 3F and Fig. Figure 3G shows the multilayer dielectric dummy strip 25 according to some examples. The sublayers are shown as 25-1, 25-2, 25-3, etc. Fig. Figure 3A shows a dielectric dummy strip 25 with sublayers 25-1 and 25-2, wherein the upper surface of sublayer 25-1 is planar. Fig. Figure 3B shows a dielectric dummy strip 25 with sublayers 25-1 and 25-2, wherein the upper surface of sublayer 25-1 has an inverted pyramid shape with sloping and straight sidewalls (or bottom surfaces). The sloping and straight sidewalls throughout the description, including what is described in Fig. 1B, Fig. 24, Fig. 25 and Fig. 27 and Fig. Figure 30 shows that the layers are produced by etching materials with inclined lattice planes. The formation of layer 25-1 can involve depositing and planarizing layer 25-1 so that its upper surface is coplanar with the upper surface of the STI regions 22, and then back-etching layer 25-1. Fig. 3C shows a dielectric dummy strip 25 with sublayers 25-1 and 25-2, wherein sublayer 25-1 is conformal. Fig. 3D, Fig. 3E, Fig. 3F and Fig. Figure 3G shows three-layer dielectric dummy strips 25 according to some examples, comprising sublayers 25-1, 25-2, and 25-3. The details of the dielectric dummy strip 25, which may assume each of these examples, are not shown in the following drawings.

[0017] With reference to Fig. 4. The STI areas 22 are omitted. The upper sections of the semiconductor strips 24 and the dielectric dummy strip 25 protrude higher than the upper surfaces 22A of the remaining sections of the STI areas 22 to form protruding semiconductor fins 24' and dielectric dummy fins 25'. The associated process is designated as process 206 in process sequence 200 in Fig. Figure 32 illustrates that the etching can be carried out by a dry etching process using a mixture of NF3 (or HF) and NH3 as an etching gas. According to alternative examples in this disclosure, the sparing of the STI regions 22 is carried out by a wet etching process. The etching chemical may, for example, contain an HF solution. According to some examples, the dielectric dummy strip 25 has a top width Wtop1 and a bottom width Wbot1. The top width Wtop1 may be greater than, equal to, or less than the bottom width Wbot1 of the dielectric dummy strip 25, depending on the example. The dielectric dummy strip 25' also has a bottom width Wbot2, which may be greater than, equal to, or less than the bottom width Wbot1 of the widths Wtop1 and Wbot1.

[0018] In the examples shown above, the fins can be structured by any suitable process. For example, the fins can be structured by one or more photolithography processes, including dual or multiple structuring processes. Generally, dual or multiple structuring processes combine photolithography and self-aligning techniques, allowing the creation of structures with, for example, smaller spacing than those achievable by a single, direct photolithography process. In one example, a sacrificial layer is formed over a substrate and structured by a photolithography process. Alongside the structured sacrificial layer, spacers are formed by a self-aligning process. The sacrificial layer is then removed, and the remaining spacers or spikes can be used to structure the fins.

[0019] Fig. Figure 5 shows the etching process 28 for etching and reducing the upper width of the dielectric dummy fin 25'. The associated process is shown as process 208 in process sequence 200 in Fig. Figure 32 illustrates this. According to some exemplary examples, the etching process is a covering (area-based) etching process without the use of etching masks. Thus, the entire top surface of the wafer 10 is exposed to the etching chemical. According to alternative examples, the etching mask 27 is formed and structured to protect the sections of the wafer 10 that are not to be etched. For example, as in Fig. Figure 4 shows protruding semiconductor fins 24 covered by the etch mask 27. The etch mask 27 may be photoresist and may or may not be a hard mask, e.g., made of TiN, TaN, BN, or the like. The etch mask 27 is shown with a dashed line to indicate whether or not it may be formed. Using the etch mask 27 is more expensive but can protect the protruding fins 24'. The approach without the etch mask 27 is less expensive but presents the challenge of selecting a suitable etching chemical to prevent damage to the protruding fins 24'.

[0020] The etching process 28 can comprise a dry etching process or a wet etching process. According to some examples, the dry etching process is carried out by direct plasma etching, remote plasma etching, radical etching, or the like. The etching gas can contain a primary etching gas and a passivation gas to adjust the etch selectivity, so that a dielectric dummy fin 25' is etched while other exposed features, such as the fins 24' and the STI areas 22, are not etched. The primary etching gas can contain C12, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, H2, NF3, or the like, or combinations thereof. The passivation gas can contain N2, O2, CO2, SO2, CO, SiCl4, or the like, or combinations thereof. A dilute (carrier) gas such as Ar, He, Ne, or combinations thereof may also be added. The pressure of the etching gas can range between approximately 0.13 Pa and approximately 106.7 Pa.The etching gas flow rate can range from approximately 1 sccm to approximately 5000 sccm. The etching process can be performed with a plasma source power ranging from approximately 10 watts to approximately 3000 watts. A bias power may or may not be applied, and the bias power can be less than approximately 3000 watts. The bias power can be used to control the plasma etching direction. A higher bias power can be used to achieve more anisotropic etching and a greater reduction in the height of the 25' dummy fin, while a lower bias power (or no bias power) can be applied to achieve more isotropic etching, resulting in a greater reduction in the width (especially the top width) of the 25' dummy fin.

[0021] When wet etching is performed, the respective chemical solution for etching contains a primary etching chemical for etching the dummy fin 25' and an auxiliary etching chemical for adjusting the etch selectivity. The primary etching chemical may contain HF, F2, or the like, or combinations thereof. The auxiliary etching chemical may contain H3PO4, H2SO4, HCl, HBr, NH3, or combinations thereof. The solvent of the chemical solution may contain deionized (DI) water, alcohol, acetone, or the like, or combinations thereof. After the etching process, the etching mask 27, if present, is removed.

[0022] As a result of the etching process 28, the upper width of the dummy fin 25' is reduced. Since the aspect ratio of the trench between the fins 24' and 25' can be high, the widths of the upper sections of the dummy fin 25' can be reduced more than the widths of the respective lower sections. After the etching process 28, the dummy fin 25' can have an upper width Wtop1' and a lower width Wbot2'. The upper width Wtop1' is smaller than the lower width Wbot2'. Furthermore, the lower width Wbot2' can be equal to or smaller than the lower width Wbot2'. Fig. 4) and the top width Wtop1' is smaller than the top width Wtop1 ( Fig. 4) The upper surface of the dummy fin 25' can also be recessed. For example, the upper surface of the dummy fin 25' before the etching process 28 may be coplanar with the upper surfaces of the protruding fins 24', while the upper surface of the dummy fin 25' after the etching process 28 is lower than the upper surfaces of the protruding fins 24'. The height of the dummy fin 25' can be determined by the height difference ΔH ( Fig. 19B) are reduced, whereby this height difference may be greater than approximately 10 percent of the height of the dummy fin 25'. Further profiles of the protruding fin 25' are described with reference to Fig. 19A, Fig. 19B and Fig. Explained in sections 20 to 31.

[0023] With reference to Fig. 6. Dummy gate stacks 30 are formed on the upper surfaces and side walls of the (protruding) fins 24' and 25'. The associated process is designated as process 210 in process flow 200 in Fig. 32 shown. The dummy gate stacks 30 can be dummy gate dielectrics 32 (in Fig. (10B shown) and dummy gate electrodes 34 over the dummy gate dielectrics 32. The dummy gate dielectrics 32 can, for example, be made of silicon oxide. The dummy gate electrodes 34 can, for example, be made of or contain polysilicon or amorphous silicon, although other materials may also be used. Each of the dummy gate stacks 30 can also have one (or more) hard mask layer 36 over the dummy gate electrode 34. The hard mask layers 36 can be made of silicon nitride, silicon oxide, silicon carbonitride, or the like. The dummy gate stacks 30 further have longitudinal directions (directions along their respective lengths) that are perpendicular to the longitudinal directions of the projecting fins 24' and can intersect one or more projecting fins 24' and 25' and STI regions 22.

[0024] The fabrication of gate stacks 30 comprises forming one or more gate dielectric layers, forming a covering dummy gate electrode layer, planarizing the dummy gate electrode layer, depositing a hard mask layer, and subsequently structuring the deposited layers to form dummy gate stacks 30. During the structuring process, it becomes increasingly difficult to structure the sections of the deposited layers in the trenches 29 due to the progressively larger aspect ratios of the trenches 29 between the protruding fins 24' and 25'. Therefore, structuring the sections of the deposited layers in the trenches 29 is simplified by reducing the upper widths of the dummy fins 25' (and possibly reducing the height of the dummy fins 25').

[0025] Next, gate spacers 38 are formed on the side walls of dummy gate stacks 30. The associated process is also referred to as process 210 in process flow 200 in Fig. 32. According to some examples in the present disclosure, gate spacers 38 are formed from a dielectric material such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride or the like and can have a single-layer structure or a multi-layer structure with several dielectric layers.

[0026] In a subsequent process, the sections of the protruding fins 24' that are not covered by the dummy gate stack 30 and the gate spacers 38 are etched out, resulting in the structure as shown in Fig. Figure 7 shows the result. The corresponding process is designated as process 212 in process flow 200 in Fig. Figure 32 shows the recess. The recess can be anisotropic, and therefore the sections of the fins 24' that lie directly beneath the dummy gate stacks 30 and the gate spacers 38 are protected and not etched. The upper surfaces of the recessed semiconductor strips 24 can be lower than the upper surfaces 22A of the STI areas 22, according to some examples. The remaining spaces between the etched sections of the protruding fins 24' are referred to as recesses 40. In the etching process, the dielectric dummy fin 25' is not etched. For example, protruding fins 24' can be etched with C₂F₆, CF₄, SO₂, a mixture of HBr, Cl₂, and O₂, or a mixture of HBr, Cl₂, O₂, and CF₂, etc. If dry etching is used, KOH, tetramethylammonium hydroxide (TMAH), HF, or the like can be employed.

[0027] Next, epitaxial regions (source / drain regions) 42 are formed by selectively growing a semiconductor material from recesses 40, resulting in the structure as shown in Fig. Figure 8 shows the corresponding process. The associated process is designated as process 214 in process flow 200. Fig. Figure 32 illustrates this. According to some examples, the epitaxial regions contain silicon germanium, silicon, silicon carbon, or the like. Depending on whether the resulting FinFET is a P-type or an N-type FinFET, a P-type or an N-type impurity can be in situ doped as the epitaxial growth progresses. For example, if the resulting FinFET is a P-type FinFET, silicon germanium boron (SiGeB), GeB, or the like can be grown. Conversely, if the resulting FinFET is an N-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like can be grown. According to alternative examples in the present disclosure, the epitaxial regions 42 are formed from a III-V compound semiconductor such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof or multiple layers thereof.Once the epitaxial areas 42 have completely filled the recesses 40, the epitaxial areas 42 begin to expand horizontally, and facets can form.

[0028] Fig. Figure 9 shows a perspective view of the structure after the formation of a CESL (contact etch stop layer) 46 and an ILD (inter-layer dielectric) 48. The associated process is designated as process 216 in process flow 200 in Fig. Figure 32 shows the CESL 46 being formed from silicon nitride, silicon carbonitride, or the like. The CESL 46 can be formed by a conformal deposition process such as ALD or CVD. The ILD 48 can contain a dielectric material produced, for example, by FCVD, spin deposition, CVD, or another deposition process. The ILD 48 can also be formed from or contain an oxygen-containing dielectric material based on silicon oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. A planarization process, such as a CMP process or a mechanical grinding process, is performed to flatten the top surfaces of the ILD 48, the dummy gate stack 30, and the gate spacers 38. According to some examples in the present disclosure, the planarization process ends on the upper surface of the hard mask 36.According to alternative examples, the hard mask 36 is also removed during the planarization process, and the planarization process stops at the upper surface of the dummy gate electrode 34. Thus, the hard mask 36 is represented by a dashed line in some of the following drawings to indicate that it may or may not be present.

[0029] Fig. Figures 10A, 10B, 11A, and 11B show the fabrication of gate isolation areas by a dummy gate cutting process and a filling process according to some examples in the present disclosure. According to alternative examples, substitute gate stacks (made of metal) are cut instead of dummy gate stacks, and the associated processes are described in [reference to relevant section]. Fig. 16, Fig. 17, Fig. 18A and Fig. 18B shown.

[0030] According to Fig. In 10A, a dummy gate cutting process is performed by etching dummy gate stacks 30 to form openings 50. The associated process is designated as process 218 in process flow 200 in Fig. Figure 32 shows the process. The dummy gate stacks 30 are thus separated into discrete sections. To perform the dummy gate cutting process, an etch mask (not shown), which may contain a photoresist, can be formed and structured such that the sections of the dummy gate stacks 30 to be cut are exposed by the etch mask, while other sections are protected. The dummy gate stacks 30 are then etched by anisotropic processes until the underlying dielectric dummy fin 25' is exposed. An elongated dummy gate stack 30 is thus cut into two discrete sections 30A and 30B, which are separated from each other. Each discrete section of the dummy gate stack 30 can cross one, two, or more protruding fins 24' to form a single-fin or multi-fin FinFET. After etching the dummy gate stack 30, the etching mask is removed, e.g. by an ashing process.

[0031] Fig. Figure 10B shows a cross-sectional view from the reference cross-section 10B-10B in Fig. 10A. The opening 50 extends to the dummy fin 25', so that section 30A of the dummy gate stack 30 is completely separated from section 30B of the dummy gate stack 30. The opening 50 can be limited to the area directly above the dielectric dummy fin 25', and the corresponding side walls of the gate stack 30 facing the opening 50 are shown as 50SW. The opening 50 can also extend laterally beyond the side walls of the dielectric dummy fin 25', and the corresponding opening 50 can extend below the top surface of the dielectric dummy fin 25', as shown by dashed lines representing the side walls 50SW'.

[0032] Next, gate isolation areas 52 are formed to fill the openings 50. The associated process is designated as process 220 in process flow 200. Fig. 32. The resulting structure is shown in Fig. 11A and Fig. Figure 11B shows that each of the gate isolation regions 52 can be a single-layer structure with a dielectric layer of a homogeneous material or a multi-layer structure with several dielectric layers. The materials for forming the gate isolation regions 52 can be selected from SiN, SiON, SiOCN, SiC, SiOC, SiO2, or the like. The fabrication process can involve depositing one or more dielectric layers and then performing a planarization process, such as a CMP process or a mechanical grinding process, to remove excess sections of the dielectric material. The gate isolation regions 52 and the respective underlying dummy fin 25' separate the respective dummy gate stacks 30 into separate sections 30A and 30B.The gate isolation areas 52 and the dummy gate stacks 30A and 30B together form elongated strips in a top view and each of the elongated strips can be located between a pair of opposing gate spacers 38.

[0033] The dummy gate stacks 30A and 30B are then removed by etching, and the resulting structure is in Fig. Figure 12 shows the corresponding process. The associated process is designated as process 222 in process flow 200. Fig. Figure 32 shows that openings 54A and 54B are formed in the remaining space by the removed dummy gate stacks 30A and 30B. Fig. As shown in Figure 12, each of the openings 54A and 54B is defined by the gate isolation area 52 and the gate spacers 38, and the openings 54A and 54B are further separated from each other by the gate isolation area 52.

[0034] Fig. 13A and Fig. Figure 13B shows a perspective view and a cross-sectional view of the production of replacement gate stacks 62A and 62B. The associated process is designated as process 224 in process flow 200 in Fig. Figure 32 shows the FinFETs 64A and 64B. In this way, the FinFETs 64A and 64B are formed, with the gate stacks 62A and 62B being the replacement gate stacks of the FinFETs 64A and 64B. The replacement gates 62A and 62B can share common gate spacers 38A and 38B. Furthermore, the two replacement gates 62A and 62B are adjacent to the gate isolation area 52.

[0035] The replacement gate stacks 62A and 62B feature gate dielectrics 59 (including interface layers 56 and high-k dielectric layers 58, Fig. 13B) and gate electrodes 60. The interface layers 56 can be formed from silicon oxide or contain silicon oxide that can be formed by thermal or chemical oxidation. The high-k dielectric layers 58 are formed from one or more high-k dielectric materials such as hafnium oxide, zirconium oxide, lanthanum oxide, or the like. According to some examples in the present disclosure, the gate electrodes 60 are formed from metals, metal alloys, metal nitrides, or the like, combinations thereof, and / or composite layers thereof. For example, the gate electrodes 60 can have a composite structure with multiple layers of TiN, TiAl, TiAlC, TaN, Co, W, Al, and / or the like. The respective metals and the structure are selected such that the resulting replacement gate electrodes 60 exhibit suitable work functions. Fig. Figure 13B shows a cross-sectional view from the reference cross-section 13B-13B in Fig. 13A. The side walls of the gate isolation area 52 are shown as 52SW or 52SW'.

[0036] As in Fig. As shown in Figure 13B, the dielectric dummy strip 25' has side walls 25SW1, and the dielectric dummy strip 25 has side walls 25SW2. The side walls 25SW1 and 25SW2 can be straight or have straight sections having angles of inclination α1 and α2. The angle of inclination α1 is less than 90 degrees and can be in a range between approximately 75 degrees and approximately 85 degrees. The angle of inclination α2 can be greater than, equal to, or less than 90 degrees. According to some examples, the angle of inclination α1 is less than 90 degrees, and the angle of inclination α2 is greater than 90 degrees. Thus, the lower width Wbot2' of the dielectric dummy strip 25' can be greater than both the upper width Wtop1' and the lower width Wbot1 of the dielectric dummy strip 25.Furthermore, according to some exemplary embodiments, the widths can gradually and continuously increase from the upper surface to the lower surface of the dielectric dummy fin 25', while the widths can gradually and continuously decrease from the upper surface to the lower surface of the dielectric dummy strip 25.

[0037] As in Fig. As shown in Figure 14, in a subsequent process the replacement gate stacks 62A and 62B are etched back, creating recesses between the opposing gate spacers 38. Next, hard masks 65 are formed over the replacement gate stacks 62A and 62B. The associated process is designated as process 226 in process flow 200 in Figure 14. Fig. Figure 32 illustrates this. According to some examples in the present disclosure, the formation of hard masks 65 comprises a deposition process to form a covering dielectric material and a planarization process to remove the excess dielectric material over the gate spacers 38 and the ILD 48. The hard masks 65 can be formed, for example, from silicon nitride or other such dielectric materials.

[0038] Fig. Figure 15 shows some features, such as source / drain contact plug 66, source / drain silicide areas 68, and gate contact plug 70, which are formed in subsequent processes. The associated process is designated as process 228 in process flow 200. Fig. 23. The details of the processes are not discussed here.

[0039] Fig. 16, Fig. 17, Fig. 18A and Fig. Figure 18B shows the perspective and cross-sectional views of the intermediate stages in cutting replacement gate stacks and fabricating gate isolation areas according to alternative examples in this disclosure. Unless otherwise specified, the materials and fabrication processes of the components in these examples are substantially the same as those of the similar components in the preceding examples, as illustrated by reference to the above drawings and designated by the same reference numerals. Details regarding the fabrication process and materials of the components in the above are provided in the relevant section. Fig. 16, Fig. 17, Fig. 18A and Fig. The components shown in 18B can therefore be found in the discussion of the preceding examples.

[0040] The first steps in these examples are essentially the same as in Fig. Figures 1 to 9 are shown. Without cutting the dummy gate stack 30, the process then proceeds to Fig. 16, in which the replacement gate stack 62 is formed. The processes are essentially the same as in Fig. 12 and Fig. 13A is shown (with the exception that no gate isolation area is formed). With reference to Fig. Subsequently, replacement gate stacks 62 are cut in an etching process carried out by an anisotropic etching process. In this way, openings 50 are formed to separate replacement gate stacks 62 into replacement gate stacks 62A and 62B. The dummy fin 25' is exposed in the openings 50 above.

[0041] Next, as in Fig. 18A and Fig. Figure 18B shows the gate isolation areas 52 formed. The manufacturing process is essentially the same as in Fig. 10A, Fig. 10B, Fig. 11A and Fig. 11B is shown and will not be repeated here. The following are then shown in Fig. 14 and Fig. The 15 processes shown were carried out. The resulting structures are the same as in Fig. 14 and Fig. 15 shown.

[0042] Fig. Figures 19A, 19B, and 20-31 show some profiles of exemplary dummy fins 25' and gate isolation areas 52 according to some examples. It should be understood that the features (such as replacement gate stacks 62 and protruding fins 24') in the vicinity of dummy fins 25' and gate isolation areas 52 are shown schematically. The details of the adjacent features 62 and 24' can be found by reference to Fig. 13B and Fig. 18B will be implemented. The in Fig. The profiles shown in 19A, 19B and 20-31 can be achieved by adjusting the process conditions in etching process 28 ( Fig. 5) to change the surface profile of the dummy fins 25' and / or by adjusting the etching process recipes to create openings 50 ( Fig. 10A and Fig. 17) will be set.

[0043] Fig. 19A and Fig. 19B shows dummy fins 25' according to some examples. Fig. 19A is obtained from a cross-section in which no gate isolation area is formed, and Fig. 19B is obtained from a cross-section in which a gate isolation region is formed. For example, assuming that in Fig. 14. If a gate isolation area 52A is formed and the gate isolation area 52B is not formed, the one in Fig. 19A cross-section shown from the reference cross-section DD in Fig. 14A received and the one in Fig. The cross-section shown in 19B is taken from the reference cross-section CC in Fig. Received 14A. In Fig. 19A and Fig. 19B The dummy fin 25' can have a rounded top surface and straight sidewalls connected to the rounded top surface. The top width Wtop1' can be measured at the top of the straight sidewalls or as the width of a flat top surface, as in Fig. 20 is shown. The lower width Wbot2' is measured at the upper surface plane 22A of the STI areas 22 (in Fig. 19A and Fig. 19B not shown, see Fig. 5) The upper width Wtop1' is smaller than the lower width Wbot2'. According to some examples, both the upper width Wtop1' and the lower width Wbot2' lie in a range between approximately 0.5 nm and approximately 500 nm. Furthermore, the difference (Wbot2' - Wtop1') can be greater than approximately 2 nm and lie in a range between approximately 2 nm and approximately 100 nm. The ratio Wtop1' / Wbot2' can lie in a range between approximately 0.5 and approximately 0.95.

[0044] The height of the protruding fin 24' is HC1 in Fig. 19A and Fig. 19B, the height of the dummy fin 25' is HD1 in Fig. 19A and the height of the dummy fin 25' is HD2 in Fig. 19B. The height HC1 can be greater than or equal to the height HD1 and can be greater than or equal to the height HD2. According to some examples, the heights HC1, HD1, and HD2 are in a range between approximately 10 nm and approximately 300 nm. According to some examples, the height difference ΔH, which is equal to (HC1 - HD2), is greater than approximately 0.3 nm and can be in a range between approximately 0.3 nm and approximately 250 nm. The ratio ΔH / HC1 can be in a range between approximately 0.03 and approximately 0.8.

[0045] Fig. Figure 20 shows a dummy fin 25' having a flat top surface, vertical sidewalls, and curved top surfaces connecting the flat top surface to the vertical sidewalls. According to some examples, both the top width Wtop1' and the bottom width Wbot2' are in a range between approximately 2 nm and approximately 500 nm. The difference (Wbot2' - Wtop1') can be greater than approximately 2 nm and lies in a range between approximately 2 nm and approximately 100 nm. The angle of inclination θ, formed between the flat top surface and the tangent of the curved top surface, lies in a range between approximately 30 degrees and approximately 88 degrees.

[0046] Furthermore, some narrow dummy fins 25' (designated 25A') and wide dummy fins (designated 25B') may be present. According to some examples, the width of the wide fin 25B' can be 1.5 times or more than the width of the narrow fin 25A'. Due to the etching process, the wide dummy fin 25B' is etched faster than the narrow dummy fin 25A'. Thus, the height HD3 of the wide dummy fin 25B' is less than the height HD1 of the dummy fin 25B'.

[0047] Fig. 21 and Fig. Figure 22 shows the manufacture of the narrow dummy fins 25A' and 25C' and the wide dummy fin 25B' according to some examples. With reference to Fig. 21 The etching mask 27 is formed and structured such that the narrow dummy fin 25A' is exposed, while the narrow dummy fin 25C' and the wide dummy fin 25B' are protected. The etching process 28 (see Fig. Step 5) is performed to etch the narrow dummy fin 25A', while the narrow dummy fin 25C' and the wide dummy fin 25B' are not etched. The resulting dummy fins, which are the fins after completion of transistor formation, are in Fig. 22 shown. Fig. 22 The height HDo of the narrow dummy fins 25C' can be equal to the height HC1 of the protruding fin 24' and is greater than the height HD1 of the narrow dummy fins 25A'. It should be noted that the height HDo of the narrow dummy fins 25C' is greater than the height HD4 of the narrow dummy fins 25A' if the wide dummy fin 25B' is not etched. It should also be noted that the in Fig. 20 and Fig. The structures shown in Figure 22 can be present in the same chip. Since narrow dummy fins 25A' and wide dummy fins 25B' are not etched in the etching process 28, their upper widths can be equal to or greater than their respective lower widths, which differs from the etched dummy fin 25A'.

[0048] Fig. Figures 23 to 31 show enlarged views of area 74 in Fig. 11B or Fig. 13B according to some examples. Fig. 23 is Fig. 19A and Fig. 19B is similar, with the left part showing the features obtained from the cross-section in which no gate isolation area is formed (and thus the gate is not cut), while the right part shows the features obtained from the cross-section in which the gate isolation area 52 is formed. The upper surface of the dummy fin 25' is round. Fig. 24 shows a similar structure to that in Fig. 24, except that the dummy fin 25' has a flat upper surface and straight and inclined sidewalls. The gate isolation area 52 extends to contact the straight sidewalls of the dummy fins 25'. The gate isolation area 52 may have vertical sidewalls and inclined lower surfaces connected to the inclined sidewalls. According to some examples, the inclined lower surfaces are lower than the upper surface of the dummy fin 25'. Fig. 25 shows a similar structure to that in Fig. 24, except that the sloping side wall of the gate isolation area 52 extends from a plane higher than the upper surface of the dummy fin 25' to the plane lower than the upper surface of the dummy fin 25'.

[0049] Fig. Figures 26 to 32 show various multi-layered dummy fins 25', all of which have a smaller upper width than the respective lower width. Fig. Figure 26 shows that sublayer 25-2 has sloping side walls and a rounded top surface, while sublayer 25-1 has a flat top surface and straight and perpendicular side walls. Fig. Figure 27 shows that sublayer 25-1 has a concave (inverted pyramid shape) upper surface. Fig. Figure 28 shows that sublayer 25-1 has a conformal layer. Fig. 29, Fig. 30 and Fig. 31 show similar profiles to those in Fig. 26, Fig. 27 and Fig. 28, except that three sublayers 25-1, 25-2 and 25-3 are present.

[0050] The examples in the present disclosure exhibit several advantageous features. By performing an etching process in which the upper widths of the dummy fins are reduced to be smaller than their respective lower widths, it is easier to etch and fill trenches with a high aspect ratio between the protruding semiconductor fins and the dielectric dummy fins. Consequently, the process windows for the structuring process are increased both in the fabrication of dummy gate stacks and in the formation of replacement gate stacks.

Claims

[1] Procedure encompassing: Forming isolation regions (22) extending into a semiconductor substrate (20), wherein semiconductor strips (24) are located between the isolation regions (22); Forming a dielectric dummy strip (25) between the insulation areas (22); Recessing the insulation regions (22) such that some sections of the semiconductor strips (24) protrude higher than the upper surfaces of the recessed insulation regions (22) to form protruding semiconductor fins (24'), and that a section of the dielectric dummy strip (25) protrudes higher than the upper surfaces of the recessed insulation regions (22) to form a dielectric dummy fin (25'); Etching the dielectric dummy fin (25') such that an upper width of the dielectric dummy fin (25') is smaller than a lower width of the dielectric dummy fin (25'); and Forming a gate stack (30) on the upper surfaces and side walls of the protruding semiconductor fins (24') and the dielectric dummy fin (25'), wherein the dielectric dummy fin (25') has multiple sublayers, wherein outer sublayers of the multiple sublayers have sections opposite to each other on opposite sides of respective inner sublayers of the multiple sublayers, and wherein upper surfaces of the outer sublayers are lower than upper surfaces of the respective inner sublayers. [2] Method according to claim 1, wherein during the etching of the dielectric dummy strip (25) the protruding semiconductor fins (24') are exposed to an etching chemical used for etching. [3] Method according to claim 1, wherein during the etching of the dielectric dummy strip (25) the protruding semiconductor fins (24') are protected by an etching mask. [4] Method according to any of the foregoing claims, further comprising: Etching the gate stack (30) to form an opening, wherein the opening divides the gate stack (30) into two sections, and wherein the dielectric dummy fin (25') lies below the opening and is exposed through the opening; and Filling the opening with a dielectric material to form a gate insulation region (52). [5] The method of claim 4, further comprising: Removing the two sections of the gate stack (30) to form trenches; and Forming replacement gate stacks in the trenches. [6] Method according to any one of the preceding claims 1 to 4, further comprising: Replacing the gate stack (30) with a replacement gate stack; Etching the replacement gate stack to form an opening that separates the replacement gate stack into two sections, with the dielectric dummy fin (25') lying below and exposed through the opening; and Filling the opening with a dielectric material to form a gate insulation region (52). [7] Method according to any one of claims 1 to 6, wherein before etching the dielectric dummy fin (25') the upper width of the dielectric dummy fin (25') is greater than the lower width of the dielectric dummy fin (25'), and wherein the upper width is reduced more than the lower width by etching the dielectric dummy fin (25'). [8] Method according to any one of claims 1 to 6, wherein before etching the dielectric dummy fin (25') the upper width of the dielectric dummy fin (25') is equal to the lower width of the dielectric dummy fin (25'), and wherein the upper width is reduced more than the lower width by etching the dielectric dummy fin (25'). [9] Method according to any one of claims 1 to 8, wherein the etching of the dielectric dummy fin (25') is carried out by a dry etching process. [10] Method according to any one of claims 1 to 8, wherein the etching of the dielectric dummy fin (25') is carried out by a wet etching process. [11] Method according to any of the preceding claims, wherein the dielectric dummy fin (25') has a tapered profile after etching, with upper sections being narrower than the respective lower sections. [12] comprising a device: a semiconductor substrate (20); Isolation areas (22) above a bulk section of the semiconductor substrate (20); a semiconductor fin (24') that projects higher than the upper surfaces of the insulating regions (22), wherein the semiconductor fin (24') has a first longitudinal direction; and a dielectric dummy fin (25') projecting higher than the upper surfaces of the insulating regions (22), wherein the dielectric dummy fin (25') has a second longitudinal direction parallel to the first longitudinal direction, wherein the dielectric dummy fin (25') has an upper width and a lower width greater than the upper width, wherein the upper width and the lower width are defined in a lateral direction perpendicular to the first longitudinal direction, wherein the dielectric dummy fin (25') has multiple sublayers, wherein outer sublayers of the multiple sublayers have sections opposite to each other on opposite sides of respective inner sublayers of the multiple sublayers, and wherein upper surfaces of the outer sublayers are lower than upper surfaces of the respective inner sublayers. [13] Device according to claim 12, wherein the dielectric dummy fin (25') is tapered and the width of the dielectric dummy fin (25') decreases continuously from a lower end of the dielectric dummy fin (25') to an upper end of the dielectric dummy fin (25'). [14] Device according to claim 12, wherein the dielectric dummy fin (25') has a first upper surface which is lower than a second upper surface of the semiconductor fin (24'). [15] Device according to any one of claims 12 to 14, further comprising: a gate stack extending across an upper surface and side walls of the semiconductor fin (24'); and a gate isolation region (52) above and in contact with the dielectric dummy fin (25'), wherein a first side wall of the gate isolation region (52) contacts a second side wall of the gate stack. [16] Device according to claim 15, wherein the gate isolation area (52) comprises: a vertical and straight side wall and an inclined and straight lower surface connected to a lower end of the vertical and straight side wall, wherein the inclined and straight lower surface has at least one section lower than a bottom of the dielectric dummy fin (25') and wherein the gate insulation region (52) contacts an additional side wall of the dielectric dummy fin (25'). [17] comprising a device: a dielectric dummy fin (25'); a first protruding semiconductor fin (24') and a second protruding semiconductor fin (24') on opposite sides of the dielectric dummy fin (25'), wherein a first upper surface of the dielectric dummy fin (25') is lower than second upper surfaces of the first protruding semiconductor fin (24') and the second protruding semiconductor fin (24'); a first gate stack on the first protruding semiconductor fin (24'); a second gate stack on the second protruding semiconductor fin (24'); and a gate insulation region (52) between, and in contact with, the first gate stack and the second gate stack, wherein the gate insulation region (52) lies above, and in contact with, the dielectric dummy fin (25'), wherein the dielectric dummy fin (25') has multiple sublayers, wherein outer sublayers of the multiple sublayers have sections opposite to each other on opposite sides of respective inner sublayers of the multiple sublayers, and wherein upper surfaces of the outer sublayers are lower than upper surfaces of the respective inner sublayers. [18] Device according to claim 17, wherein the dielectric dummy fin (25') has a tapered profile, wherein upper widths of upper sections of the dielectric dummy fin (25') are progressively smaller than lower widths of the respective lower widths of the dielectric dummy fin (25'). [19] Device according to claim 18, further comprising: Isolation areas; and a semiconductor strip between the insulation area, wherein the semiconductor strip is overlapped by the first protruding semiconductor fin (24'), and wherein the semiconductor strip has an additional tapered profile, wherein upper widths of additional upper sections of the semiconductor strip are greater than lower widths of the respective lower sections of the semiconductor strip.

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