Display panel and display device

Abstract

A display device (100) comprising: a display panel (110) with an active area (AA) and a non-active area (NA) surrounding the active area (AA) on a substrate (400); a front cover arranged on an upper section of the display panel (110); a rear cover arranged on a lower section of the display panel (110); a dam (370) arranged to surround an outer edge of the active area (AA) in the non-active area (NA) of the display panel (110); a pad area (PAD) spaced apart from the dam (370) in the non-active area (NA), arranged at an edge of one side of the non-active area (NA) and comprising a plurality of pads (360) arranged in the pad area (PAD);at least one test lead (350), which is spaced apart from the dam (370) in the non-active area (NA), is arranged such that it surrounds part of an outer edge of the dam (370) and is connected to the plurality of pads (360), wherein the at least one test lead (350) is configured to detect damage in the non-active area (NA) by applying a current and detecting an output voltage;and at least one alignment mark (380, 781, 782, 783), wherein the at least one test line (350) has a first test line (351) arranged to surround the section of the outer edge of the dam (370), and a second test line (352) spaced apart from the first test line (351) and arranged to surround an outer edge of the first test line (351), wherein the second test line (352) has at least one groove (355), wherein the at least one alignment mark (380, 781, 782, 783) is integral with the second test line (352) and is arranged in the at least one groove (355), and wherein the at least one alignment mark (380, 781, 782, 783) has a U-shape.

Description

BACKGROUNDFIELD OF DISCLOSUREAspects of the present disclosure relate to a display panel and a display device, and more particularly provide a display panel and a display device capable of reducing an area of a surrounding area.Background DescriptionAs information society develops, display devices for displaying images in various forms are increasing in demand, and in recent years, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED) are used.Such a display device may include components disposed in upper and lower regions of a display panel to protect the display panel.An alignment mark for detecting the position of each component may be disposed in the display panel when the display panel and the components disposed in upper and lower parts of the display panel are bonded.The following publications are mentioned with respect to the prior art: U.S. Pat. No. 2018 / 0 136 508 A1, U.S. Pat. No. 2018 / 0 102 502 A1, U.S. Pat. No. 2019 / 0 157 607 A1.SUMMARYAn alignment mark may be disposed in a non-active area (or a border area) of a display panel, and the area occupied by the alignment mark in the non-active area may be enlarged due to a design condition or the like to improve the visibility of the alignment mark.Accordingly, the area of the non-active region is also increased. Recently, there is an increasing demand to reduce the size of the non-active area in order to secure the maximum area of the active area of the display panel. Accordingly, the inventors of the present disclosure have invented a new structure of a display panel and a display device capable of minimizing an increase in the area of a non-active area caused by an alignment mark.The present disclosure is to provide a display panel and a display device that have a low area enlargement rate of a non-active area even when an alignment mark is disposed in the non-active area of the display panel.The present disclosure is intended to provide a display panel and a display device having a simple method of manufacturing an alignment mark. Various embodiments of the present disclosure provide a display device according to claim 1 and a display panel according to claim 11. Further embodiments are described in the dependent claims.According to an aspect of the present disclosure, a display device having a non-active area with a small area is provided by an alignment mark. The display device according to an aspect of the present disclosure includes a display panel having an active area and a non-active area surrounding the active area; a front cover disposed at an upper portion of the display panel; a back cover disposed at a lower portion of the display panel; a bank disposed to surround an outer edge of the active area in the non-active area of the display panel; a pad area spaced apart from the bank in the non-active area and disposed at an edge of a side of the non-active area; at least one test line spaced apart from the bank in the non-active area and disposed to surround a part of an outer edge of the bank; and at least one alignment mark integral with the test line.According to another aspect of the present disclosure, a display panel having a non-active area with a small area is provided by an alignment mark. The display panel according to the aspect of the present disclosure includes a substrate having an active area and a non-active area surrounding the active area, a bank disposed to surround an outer edge of the active area in the non-active area of the substrate; a pad area spaced apart from the bank in the non-active area and disposed at an edge of a side of the non-active area; at least one test line spaced apart from the bank in the non-active area and disposed to surround a part of an outer edge of the bank; and at least one alignment mark integral with the test line.According to aspects of the present disclosure, at least one test line and an alignment mark disposed in a non-active area are integrally formed, thereby minimizing the area occupied by the alignment mark in the non-active area.According to aspects of the present disclosure, at least one test line and an alignment mark disposed in a non-active region are integrally formed, thereby simplifying the process of forming the alignment mark.BRIEF DESCRIPTION OF THE DRAWINGSThe above and other features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which: FIG. 1 is a diagram schematically showing a display device according to aspects of the present disclosure; FIG. 2 is a schematic configuration diagram of a display device according to aspects of the present disclosure; FIG. 3 is a plan view schematically showing a structure of a display panel of a display device according to aspects of the present disclosure; FIG. 4 is an enlarged view of the region X (part of an active region) of FIG. 3 ; FIG. 5 is an enlarged view of the region Y (part of a non-active region) of FIG. 3 ; FIG. 6 is a cross-sectional view taken along line A-B of FIG. 5 ; and FIG. 7 is an enlarged view of the region Z of FIG. 3.DETAILED DESCRIPTIONAdvantages and features of the present disclosure and methods for realizing them will become apparent from the aspects described in detail below with reference to the accompanying drawings. However, the present disclosure may be embodied in many different forms and should not be construed as being limited to the aspects set forth herein. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.Since the shapes, sizes, ratios, angles, and numbers indicated in the drawings for describing the aspects of the present disclosure are exemplary, the present disclosure is not limited to the illustrated subject matters. Like reference numerals refer to like elements throughout the specification. The terms such as "comprising", "with", "containing", "consisting of", "formed of", and "made of" used herein are generally intended to allow the addition of other components unless the terms are used with the term "only". The singular forms as used herein include the plural forms unless the context clearly indicates otherwise.In interpreting the elements, it is interpreted that an error region is included even if there is no explicit description.Spatially relative terms are to be understood with reference to the directions depicted in the drawings, including the different directions of components at the time of use or operation. For example, when an element illustrated in the drawings is turned over, an element described as "below" or "below" another element may be placed "above" another element.Terms such as "first" and "second" represent different constituent elements, regardless of the order and / or importance. A constituent element is used to be distinguished from other constituent elements, but does not limit corresponding constituent elements. Accordingly, the below-mentioned first constituent element may be the second constituent element in the technical sense of the present disclosure.Each of the features of the various aspects of the present disclosure may be partially or fully coupled or combined with each other, and various gear cutting and driving may be technically possible, and each of the aspects may be implemented independently or together in an associative relationship.Hereinafter, various configurations of a display device and a display panel having an alignment mark structure according to an aspect of the present disclosure will be described.A configuration of a display panel and a display device according to various embodiments of the present disclosure includes a display panel having an active area and a non-active area surrounding the active area; a front cover disposed at an upper portion of the display panel; a back cover disposed at a lower portion of the display panel; a bank disposed to surround an outer edge of the active area in the non-active area of the display panel; a pad area spaced apart from the bank in the non-active area and disposed at an edge of a side of the non-active area; at least one test line spaced apart from the bank in the non-active area and disposed to surround a part of an outer edge of the bank; and at least one alignment mark integral with the test line.According to one or more embodiments, in the configuration of the display panel and the display device of the present disclosure, a plurality of pads are disposed in the pad region, and the test line is electrically connected to the pad.According to one or more embodiments, in the configuration of the display panel and the display device of the present disclosure, the test line includes a first test line disposed to surround the portion of the outer edge of the bank and a second test line spaced apart from the first test line and disposed to surround an outer edge of the first test line.According to one or more embodiments, in the configuration of the display panel and the display device of the present disclosure, the at least one alignment mark is integral with the second inspection line.According to one or more embodiments, in the configuration of the display panel and the display device of the present disclosure, the non-active region includes at least one crack preventing line disposed in an external vicinity of the second inspection line.According to one or more embodiments, in the configuration of the display panel and the display device of the present disclosure, at least one thin film transistor is disposed on the active region substrate, the thin film transistor includes a gate electrode, an active layer, a source electrode, and a drain electrode disposed on the substrate, and the first test line and the second test line are disposed on the same layer as the gate electrode.According to one or more embodiments, in the configuration of the display panel and the display device of the present disclosure, the alignment mark is disposed on the same layer as the gate electrode of the thin film transistor. For example, the alignment mark may be formed of the same layer and / or may include or be made of the same material as the gate electrode.According to one or more embodiments, the second inspection line includes at least one groove in the configuration of the display panel and the display device of the present disclosure.According to one or more embodiments, in the configuration of the display panel and the display device of the present disclosure, the groove of the second inspection line includes a first portion extending in a first direction, a second portion extending in a second direction intersecting the first direction from the first portion, and a third portion extending in a direction corresponding to a direction in which the first portion extends from the second portion.According to one or more embodiments, in the configuration of the display panel and the display device of the present disclosure, the alignment mark is integral with at least one of the first to third portions of the second inspection line.According to one or more embodiments, in the configuration of the display panel and the display device of the present disclosure, a width of the alignment mark with respect to a direction in which a long short side of the display panel extends corresponds to a depth of the groove or is wider than the depth of the groove.According to one or more embodiments, in the configuration of the display panel and the display device of the present disclosure, a maximum width of the alignment mark with respect to a direction in which a short side of the display panel extends is larger than a maximum width of a signal line disposed in the non-active area.According to one or more embodiments, in the configuration of the display panel and the display device of the present disclosure, the alignment mark includes at least two portions having an angle of 90 degrees or more.Hereinafter, various aspects of the present disclosure will be described in detail with reference to the accompanying drawings.FIG. 1 is a diagram schematically showing a display device according to aspects of the present disclosure.A display device 100 according to aspects of the present disclosure may include a front cover 101, a rear cover 103, and a display panel 110.The front cover 101 may include a cover glass covering the display panel 110. The front cover 101 may cover a part of the upper surface of the display panel 110.On the upper surface of the display panel 110 exposed by the front cover 101, an image may be displayed.Meanwhile, when the display device 100 according to aspects of the present disclosure is a mobile terminal, a front camera and various sensors may be disposed in the front surface of the mobile terminal. Moreover, a rear camera and various sensors may be disposed in the rear surface of the rear cover 103. The sensors may be various sensors suitable for a mobile terminal, such as a proximity sensor, a gyro sensor, a geo-magnetic sensor, a motion sensor, an illumination sensor, an RGB sensor, a Hall sensor, a temperature / humidity sensor, a heart rate sensor, a fingerprint sensor, and the like.Although not illustrated in the drawing, the display device 100 according to aspects of the present disclosure may further have a configuration such as a center frame, a motherboard, and a battery.Here, the center frame may serve to support the display panel 110 at the rear of the display panel 110. In addition, the motherboard may be configured to be connected to a user input unit, a speaker, a microphone, a battery, and the like.Touch sensors may be disposed on the entire screen of the display panel 110. Moreover, aspects according to the present disclosure are not limited thereto, and a touch panel may be additionally disposed on the display panel 110.As described above, the display panel 110 according to aspects of the present disclosure may have a structure combined with at least two components. For example, the display panel 110 may be combined with the front cover 101, the rear cover 103, and the cover glass.In order to combine the display panel 110 with the front cover 101, the rear cover 103, and the cover glass, each component needs to be disposed at an appropriate position.To this end, the display panel 100 may include at least one alignment mark. The alignment mark may be used as an identification mark for alignment in the process of connecting the display panel 110 and other components.The display device 100 of the present disclosure may be a liquid crystal display (LCD), an organic light emitting display, or the like. The display device 100 may include the display panel 110 and a driving circuit for driving the display panel 110.FIG. 2 is a schematic configuration diagram of a display device according to aspects of the present disclosure.The display apparatus 100 according to aspects of the present disclosure may include a display panel 110, a data driving circuit 220, a gate driving circuit 230, a controller 240, and the like.On the display panel 110, K data lines DL and H gate lines GL are arranged. K is a natural number equal to or greater than 2, and H is a natural number equal to or greater than 2.In addition, a plurality of subpixels SP defined by the K data lines DL and the H gate lines GL may be disposed in the display panel 110. The plurality of subpixels SP may be arranged in a matrix manner, but aspects according to the present disclosure are not limited thereto.The display panel 110 may include an active area AA in which a representation (image) is displayed and a non-active area NA that is an edge area thereof and in which no image is displayed. Here, the non-active area NA is also referred to as a border area.In the active area (A / A), a plurality of sub-pixels (SP) for displaying an image are arranged. Each subpixel (SP) may include at least one emission region.In the non-active area NA, a pad area for electrically connecting the data driving circuit 220 is disposed, and a plurality of data connection lines (or signal lines) for connecting between the pad area and the plurality of data lines is disposed.The data driving circuit 220 is a circuit that drives the K data lines DL to display an image and outputs an image data voltage corresponding to an image signal to the K data lines DL.The gate drive circuit 230 is a circuit that sequentially drives the H gate lines GL to display an image, and that can sequentially supply a gate signal (scan signal) to the H gate lines GL to display an image.The controller 240 is a component for controlling the data driving circuit 220 and the gate driving circuit 230, and supplies various control signals (data driving control signal, gate driving control signal, etc.) to the data driving circuit 220 and the gate driving circuit 230.The controller 240 starts the sampling according to the timing implemented in each image, converts the image data input from the outside according to a data signal format used by the data driving circuit 220, then outputs the converted image data, and controls the data driving at an appropriate timing according to the sampling.Controller 240 may be a timing controller used in conventional display technology or a controller including a timing controller to perform other control functions.The data driving circuit 220 is provided only on one side (e.g., the top side or the bottom side) of the display panel 110 in FIG. 2, but may be provided on both sides (e.g., the top side and the bottom side) of the display panel 110, depending on a driving method, a panel design method, or the like.The data driver circuit 220 may be configured to include at least one source driver integrated circuit (SDIC).Each source driver integrated circuit (SDIC) may be connected to a bonding pad of the display panel 110 according to a tape automated bonding (TAB) method or a chip on glass (COG) method, or may be directly disposed in the display panel 110. In some cases, it may be integrated and disposed in the display panel 110. Moreover, each source driver integrated circuit (SDIC) may be implemented in a chip-on-film (COF) method mounted on a sheet connected to the display panel 110.Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital-to-analog converter (DAC), an output buffer, and the like.Each source driver integrated circuit (SDIC) may also include an analog-to-digital converter (ADC) in some cases.The gate driving circuit 230 is provided only on one side (e.g., the left or right side) of the display panel 110 in FIG. 2, but may be provided on both sides (e.g., the upper and lower sides) of the display panel 110, depending on a driving method, a panel design method, or the like.The gate driver circuit 230 may be configured to include at least one gate driver integrated circuit (GDIC).Each gate driver integrated circuit (GDIC) may be connected to a bonding pad of the display panel 110 according to a TAB method (TAB= Tape Automated Bonding) or a COG method (COG=Chip On Glass), or may be implemented in a GIP (Gate In Panel) type to be directly disposed in the display panel 110. In some cases, it may be integrated and disposed in the display panel 110. In addition, each gate driver integrated circuit (GDIC) may be implemented in a chip-on-film (COF) method mounted on a film connected to the display panel 110.Each gate driver integrated circuit (GDIC) may include a shift register, a level shifter, and the like.Each subpixel (SP) disposed in the display panel 110 may be configured to include a circuit element such as a transistor.The type and number of circuit elements constituting each pixel may be set differently depending on the intended function, design method, etc.FIG. 3 is a plan view schematically showing a structure of a display panel of a display device according to aspects of the present disclosure. FIG. 4 is an enlarged view of the region X (part of an active region) of FIG. 3, FIG. 5 is an enlarged view of the region Y (part of a non-active region) of FIG. 3.Referring to FIG. 3, the display panel 110 may include an active area AA that displays an image and a non-active area NA surrounding the outer periphery of the active area AA.A plurality of subpixels SP for displaying an image are arranged in the active area AA. Each subpixel (SP) may include at least one emission region. In addition, a non-emission region (NEA) surrounding the emission region (EA) may be disposed in the active region AA.Referring to FIG. 4, at least a thin film transistor (TFT) and an organic light emitting diode (OLED) may be disposed on a substrate 400. An encapsulation layer 490 for protecting the organic light emitting diode (OLED) from foreign substances (including moisture and oxygen) may be arranged on the organic light emitting diode (OLED).The thin film transistor (TFT) may include a gate electrode 410, an active layer 420, a source electrode 430, and a drain electrode 435.The organic light emitting diode (OLED) may include a first electrode 440, an organic layer 450, and a second electrode 460.In particular, at least one buffer layer 401 may be arranged on the substrate 400. In some cases, the buffer layer 401 may also be omitted. Alternatively, the buffer layer 401 may have a structure in which a plurality of thin layers are deposited. In this case, it may have a structure in which a plurality of inorganic layers are stacked, but the present disclosure is not limited thereto.The buffer layer 401 may be made of an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), but the present disclosure is not limited thereto.When the buffer layer 401 is a multilayer film, it may be a structure in which at least two layers of inorganic material including inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON) are alternately arranged. However, the present disclosure is not limited thereto.In the following description, the buffer layer 401 is described as a single-layer structure for convenience.A gate electrode 410 may be disposed on the buffer layer 401.The gate electrode 410 may include metal such as silver (Ag), aluminum (Al), magnesium (Mg), chromium (Cr), titanium (Ti), nickel (Ni), tungsten (W), gold (Au), tantalum (Ta), copper (Cu), cobalt (Co), iron (Fe), molybdenum (Mo), and platinum (Pt), or an alloy thereof, but the present disclosure is not limited thereto.Meanwhile, although the gate electrode 410 is illustrated as a single-layer structure in FIG. 4, the present disclosure is not limited thereto. For example, the gate electrode 410 may be formed of a multilayer structure of two or more layers. Examples of the multilayer structure are a double layer of a lower layer such as titanium (Ti), tantalum (Ta), molybdenum (Mo), ITO and an upper layer of copper (Cu), and a triple layer of molybdenum (Mo)-aluminum (Al)-molybdenum (Mo).A gate insulating layer 402 may be disposed on the gate electrode 410.The gate insulating film 402 may be made of an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), but the present disclosure is not limited thereto.On the gate insulating film 402, an active layer 420 may be disposed, which overlaps with the gate electrode 410.The active layer 420 may be made of various kinds of semiconductor layers.The active layer 420 may be, for example, any of an oxide semiconductor, an amorphous silicon semiconductor, and a polycrystalline silicon semiconductor, but the present disclosure is not limited thereto.On the active layer 420, a source electrode 430 and a drain electrode 435 may be disposed, which are spaced apart from each other.The source electrode 430 and the drain electrode 435 may include metals such as silver (Ag), aluminum (Al), magnesium (Mg), chromium (Cr), titanium (Ti), nickel (Ni), tungsten (W), gold (Au), tantalum (Ta), copper (Cu), cobalt (Co), iron (Fe), molybdenum (Mo), and platinum (Pt), or an alloy thereof, but the present disclosure is not limited thereto.A protective layer 403 may be disposed on the source electrode 430 and the drain electrode 435.The protection layer 403 may be made of an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), but the present disclosure is not limited thereto.A planarization layer 404 may be disposed on the protective layer 403. The planarization layer 404 may include a first planarization layer 404 adisposed on the protective layer 403 and a second planarization layer 404 bdisposed on the first planarization layer 404 a, but the present disclosure is not limited thereto, and the planarization layer 404 may be formed of a single layer or three or more layers.The planarization layer 404 may include an organic material capable of planarizing the substrate 400, but the present disclosure is not limited thereto.A first electrode 440 of the organic light emitting diode (OLED) may be disposed on the planarization layer 404. Here, the first electrode 440 may be an anode of the organic light emitting diode (OLED), but the present disclosure is not limited thereto.The first electrode 440 may be electrically connected to the drain electrode 435 of the thin film transistor (TFT) through a contact hole provided in the planarization layer 404 and the protection layer 403.FIG. 4 shows a configuration in which the first electrode 440 is in contact with the drain electrode 435, but the present disclosure is not limited thereto. For example, the first electrode 440 may be electrically connected to the source electrode 430 of the thin film transistor (TFT) instead of the drain electrode 435.The first electrode 440 may be an electrode including a transparent conductive material.For example, the first electrode 440 may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO), but the present disclosure is not limited thereto.The first electrode 440 may be a reflective electrode. For example, the first electrode 440 may be made of any one selected from a group including silver (Ag), aluminum (Al), magnesium (Mg), chromium (Cr), titanium (Ti), nickel (Ni), tungsten (W), gold (Au), tantalum (Ta), copper (Cu), cobalt (Co), iron (Fe), molybdenum (Mo), and platinum (Pt), or may be an alloy of two or more of the foregoing metals.Moreover, although the configuration in which the first electrode 440 is a single layer is illustrated in FIG. 4, the present disclosure is not limited thereto, and the first electrode 440 may be formed of multiple layers.Meanwhile, although not illustrated in the drawing, at least one auxiliary electrode may be disposed between the first planarization layer 404 aand the second planarization layer 404 bor on the same layer as the first electrode 440. For example, the at least one auxiliary electrode may be formed of the same layer and the same material as the first electrode.The auxiliary electrode is an electrode electrically connected to the second electrode 460 of the organic light emitting diode (OLED), and may serve to prevent a voltage drop by the second electrode 460.A bank 405 may be disposed on a portion of the top surface of the first electrode 440 and a portion of the top surface of the planarization layer 404.The bank 405 may serve to define a plurality of light emitting regions (EA) and non-light emitting regions (NEA) in the active region AA. Specifically, an area where the bank 405 is not disposed in the active area AA may be a light emitting area (EA), and an area where the bank 405 is disposed may be a non-light emitting area (NEA).At least one spacer 480 may be disposed on the bank 405. The spacer 480 may serve as a support portion that may support a mask in the process of forming the organic layer 450 of the organic light emitting diode (OLED).Meanwhile, FIG. 4 shows a structure in which at least one spacer 480 is disposed on the bank 405, but the structure according to the present aspect is not limited thereto, and it is possible that the spacer 408 is not disposed on the bank 405.On the top surface of the first electrode 440 that does not overlap with the bank 405, an organic layer 450 having at least one light emitting layer may be disposed.Meanwhile, although FIG. 4 shows a structure in which the organic layer 450 is disposed only on the upper surface of the first electrode 440 that does not overlap with the bank 405, the present disclosure is not limited thereto.For example, the organic layer 450 may be disposed on the first electrode 440 and the bank 405 in the active area (A / A).However, in the following description, for convenience of description, the structure in which the organic layer 450 is disposed on the upper surface of the first electrode 440 that does not overlap with the bank 405 will be mainly described.The second electrode 460 of the organic light emitting diode (OLED) may be disposed on the organic layer 450. Here, the second electrode 460 may be a cathode of the organic light emitting diode (OLED), but the present disclosure is not limited thereto.The second electrode 460 may be an electrode including a transparent conductive material. For example, the second electrode 460 may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO), but the present disclosure is not limited thereto.The second electrode 460 may be a semi-transmissive electrode or a reflective electrode. For example, the second electrode 460 may be made of any one selected from a group including silver (Ag), aluminum (Al), magnesium (Mg), chromium (Cr), titanium (Ti), nickel (Ni), tungsten (W), gold (Au), tantalum (Ta), copper (Cu), cobalt (Co), iron (Fe), molybdenum (Mo), and platinum (Pt), or may be an alloy of two or more of the foregoing metals.The second electrode 460 may be disposed on the entire surface of the active region (A / A), but the present disclosure is not limited thereto. For example, the second electrode 460 may be disposed only in a part of the active area (A / A).An encapsulation layer 490 for protecting the organic light emitting diode (OLED) from moisture and oxygen may be arranged on the second electrode 460.The encapsulation layer 490 may include a first encapsulation layer 491, a second encapsulation layer 492 and a third encapsulation layer 493 arranged on the second electrode 460. Although the encapsulation layer 490 is shown in FIG. 4 as having a multilayer structure, aspects of the present disclosure are not limited thereto. For example, the encapsulation layer 490 may be a single layer. However, in the following description, it is mainly described that the encapsulation layer 490 has a multilayer structure for convenience.The first encapsulation layer 491 and the third encapsulation layer 493 may include an inorganic insulating material, and the second encapsulation layer 492 may include an organic insulating material.Moreover, referring to FIG. 3, a pad area PAD, a bank 370, at least one test line 350, and at least one alignment mark 380 are disposed in the non-active area NA included in the display panel 110 of the display device 100 of the present disclosure.The pad area PAD may be disposed at an edge of the display panel. The pad region PAD may include a plurality of pads 360. The plurality of pads 360 may be electrically connected to the data driver circuit 220 via another film (e.g., an anisotropic conductive film, etc.).The dam 370 may include a first dam 371 and a second dam 372. The first bank 371 and the second bank 372 may be disposed so as to surround the active area AA, and at least one of the first bank 371 and the second bank 372 may block the flow of the second encapsulation layer 492 (see FIG. 4 ) disposed in the display panel 110. Specifically, the first bank 371 and the second bank 372 are disposed between the active region AA and the pad region (PAD) to prevent the second encapsulation layer 492 from entering the pad region (PAD).In addition, the test line 350 may be disposed to be spaced apart from the first and second dams 371 and 372 in the non-active area NA. For example, the first bank 371 may be disposed to surround the active area AA, and the second bank 372 may be disposed to surround the outer edge of the first bank 371.Moreover, the test line 350 may be disposed to surround a part of the outer edge of the second bank 372. For example, the test line 350 is disposed so as to surround the outer edge of the second bank 372, but is not disposed in a part of a side of the display panel 110 in which the pad region (PAD) is disposed.The test line 350 may include a first test line 351 surrounding a part of the outer edge of the second bank 372 and a second test line 352 surrounding the outer edge of the first test line 351.Meanwhile, FIG. 3 shows a structure in which two test lines 350 for detecting a crack are provided in the non-active area NA, but the structure of the display panel 110 according to aspects of the present disclosure is not limited thereto. The display panel 110 may include one or three or more than three test lines 350 disposed in the non-active area NA.A part of the non-active area NA of the display panel 110 may be provided with a bending area. When a large external force is applied to the display panel 110 when the display panel 110 is bent, a plurality of signal lines disposed in the non-active area NA may be damaged.The test line 350 is a structure that can determine whether a plurality of signal lines are damaged by an external force acting on the non-active area NA.The test line 350 may be electrically connected to the pads 360 disposed in the pad region (PAD). If damage, such as a crack, occurs in the non-active region NA, a crack can additionally be applied to the test line 350. As described above, when the test line 350 is damaged, the resistance of the test line 350 increases, thereby detecting the occurrence of a crack in the non-active region NA.Specifically, when a current corresponding to a reference voltage flows along the test line 350, an output voltage is detected, and it is possible to determine, by a detection result signal, whether the display panel 110 is damaged based on whether the detected output voltage is within a reference voltage range or not within the reference voltage range.At least one alignment mark 380 is disposed in the non-active area NA of the display panel 110.For example, the alignment mark 380 may be provided in at least one corner portion of the display panel 110 on one plane, and may also be disposed in at least one side according to the size of the display panel 110.The display panel 110, a front cover, a back cover, a cover glass, and the like can be aligned within a defect area by the alignment mark 380. When the components included in the display device 100 are misaligned, connecting the components included in the display device 100 may be difficult, and some components may have a failure, for example, covering the active area AA in which the image of the display panel 110 is displayed.Therefore, in order to prevent misalignment of the components included in the display device 100, the identifiability of the alignment mark 380 needs to be high.However, when the alignment mark 380 is disposed in the non-active area NA, the area of the non-active area NA may be increased with respect to the area occupied by the alignment mark 380. Therefore, there is a difficulty in reducing the area of the non-active region NA.In addition, identification of the alignment mark 380 may be difficult when the size of the alignment mark 380 is reduced to reduce the area of the non-active area NA.The display panel 110 according to the aspect of the present disclosure has a structure of the alignment mark 380 that has excellent identifiability and can minimize the area of the non-active area NA.The alignment mark 380 disposed in the non-active area NA may have a complicated shape or may have a width larger than the width of the signal lines to be different from other signal lines disposed in the non-active area NA. Here, the maximum width T of the alignment mark 380 and the maximum width of the signal lines in a direction parallel to a side of the display panel 110 may be measured with a small length on a plane, i.e., the shortest length of a straight line in the direction in which the short side of the display panel 110 extends.Referring to FIGS. 3 and 5, the alignment mark 380 disposed in the non-active area NA may be integral with at least one test line 350.For example, the alignment mark 380 may be integral with the second inspection line 352, which is the inspection line 350 disposed at the outermost side of the display panel 110. In other words, the test line 350 that is the farthest from the active area AA and the alignment mark 380 may be integrated.Thereby, the visibility of the alignment mark 380 can be increased, but the structure of the present disclosure is not limited thereto. For example, at least one alignment mark 380 may be integral with the first test line 351.The second inspection line 352 may include at least one groove 355 on a plane to ensure a space for the alignment mark 380 to be detected.Here, the entrance of the groove 355 of the second test line 352 may be disposed to face a crack prevention line 530 disposed in the non-active area NA.The groove 355 of the second inspection line 352 may be formed by a first portion 352 aextending in a second direction that is a direction intersecting a first direction from a region in which the second inspection line 352 extends in the first direction (e.g., a direction in which a long-length side of the display panel 110 extends), a second portion 352 bextending in the first direction from the first portion 352 a, and a third portion 352 cextending in the same direction as the direction in which the first portion 352 aextends from the second portion 352 b.In addition, at least one alignment mark 380 may be disposed in the groove 355 provided in the second test line 352. The alignment mark 380 may be integral with the second portion 352 bof the second test line 352.However, the structure in which the alignment mark 380 is integrally formed with the second portion 352 bof the second inspection line 352 is only an example, and the structure according to the aspect of the present disclosure is not limited thereto. The alignment mark 380 may have a structure integral with at least one of the first to third portions 352 a, 352 b, and 352 cof the second inspection line 352.As an example of the shape of the alignment mark 380, the alignment mark 380 may include a first region 380 a, a second region 380 band a third region 380 c.The first to third regions 380 a, 380 b, and 380 cextend in the first direction and may be formed integrally with each other. In this case, the second region 380 bmay be arranged between the first region 380 aand the third region 380 c. Moreover, each of the first to third regions 380 a, 380 b, and 380 cmay have a rectangular shape in a plane.The heights of the first and third regions 380 a, 380 ccorresponds to each other, and the height of the second region 380 bmay be lower than the heights of the first and third regions 380 a, 380 c. Here, each of the heights of the first to third regions 380 a, 380 b, and 380 cmay mean the minimum length based on a direction corresponding to the direction in which the first and third portions 352 a, 352 cof the second test line 352 are extended.In other words, the shape of the alignment mark 380 may be a shape corresponding to. As described above, the alignment mark 380 may have a shape in which a plurality of portions having an angle of 90 degrees or more are present on one plane. The visibility of the alignment mark 380 can be improved when a portion having an angle of 90 degrees or more is present, compared to a case where a portion having a curve such as a circular or elliptical shape is present. The visibility of the alignment mark 380 according to the present aspect can be improved when a large number of portions having an angle of 90 degrees or more are present.Meanwhile, FIGS. 3 and 5 show that the alignment mark 380 has a shape of but the shape of the alignment mark 380 according to the present disclosure is not limited thereto. For example, the alignment mark 380 may have a polygonal shape such as a square, pentagonal, or hexagon. In the aspect of the present disclosure, a shape having at least two parts with an angle of 90 degrees or more is sufficient to improve the visibility of the alignment mark 380.A depth H 1 of the groove 355 of the second test line 352 relative to the second direction may be equal to or less than the first width H 2 of the alignment mark 380. When a first width H 2 of the alignment mark 380 is less than the depth H 1 of the groove 355 of the second inspection line 352, the visibility of the alignment mark 380 may be difficult.Here, the depth H 1 of the groove 355 of the second test line 352 may be a minimum length from a side of the first portion 352 amost from the active area AA of the second test line 352 to a side of the second portion 352 bmost from the active area AA. In addition, the first width H 2 of the alignment mark 380 may be a minimum length from a side of the alignment mark 380 that is farthest from the active area AA to a side of the alignment mark 380 that is closest to the active area AA (here, the width of the area corresponding to the second portion 352 bis excluded).Moreover, the second width W 1 of the alignment mark 380 may be equal to or greater than half of the width W 2 of the groove 355 of the second test line 352. Here, both the second width W 1 of the alignment mark 380 and the width W 2 of the groove 355 of the second inspection line 352 may be a minimum length in a direction corresponding to the direction in which the second portion 352 bof the second inspection line 352 extends.Meanwhile, as shown in FIG. 5, the alignment mark 380 is disposed in the groove 355 of the second inspection line 352, and may have a structure in which the alignment mark 380 and the first and third portions 352 a, 352 cof the second inspection line 352 are disposed separately from each other in the groove 355.At this time, the sum of the width W 3 of the area between the alignment mark 380 and the first portion 352 aand the width W 4 of the area between the alignment mark 380 and the third portion 352 cmay be smaller than the second width W 1 of the alignment mark 380. The width W 3 of the region between the alignment mark 380 and the first portion 352 aand the width W 4 of the region between the alignment mark 380 and the third portion 352 cmay correspond to each other, but the present aspect is not limited thereto.Thus, the area where the alignment mark 380 is disposed in the groove 355 of the second test line 352 may be larger than the area where the alignment mark 380 is not disposed. Thereby, the visibility of the alignment mark 380 can be improved.Meanwhile, as shown in FIG. 5, at least one crack preventing line 530 may be provided outside the second test line 352. Here, the crack preventing line 530 may be disposed farther from the active area AA than the second test line 352.The crack prevention line 530 may be disposed on the same layer as the first and second inspection lines 351 and 352, but the present disclosure is not limited thereto.A part of the non-active area NA of the display panel 110 may be provided with a bending area. When a large external force is applied to the display panel 110 during bending of the display panel 110, a crack may be generated in the display panel 110. The crack generated in the non-active area NA may spread to the active area AA, which may result in difficulties in displaying an image.The crack preventing line 530 may serve to prevent the crack from propagating into the active area AA even when a crack occurs in the non-active area NA of the display panel 110.In addition, the display panel 110 according to the aspect of the present disclosure may include at least one test line 520 disposed between the first and second test lines 351 and 352 disposed in the non-active area NA.Next, the structure of the non-active area according to the aspect of the present disclosure will be described in detail with reference to FIG. 6.FIG. 6 is a cross-sectional view taken along line A-B of FIG. 5.In describing the present aspect, the description of the same or corresponding components as those in the previous aspect is omitted. Next, a partial structure of the non-active area of the display panel according to the present aspect will be described with reference thereto.Referring to FIG. 6, in the non-active area NA of the display panel according to the aspect of the present disclosure, the test line 350, a plurality of signal lines 630, 635, and 640, the first and second dams 371 and 372, and the crack prevention line 530 may be disposed.In particular, a buffer layer 401 may be disposed on the substrate 400.A gate insulating layer 402 may be disposed on the buffer layer 401.The gate insulating film 402 may include the first test line 351 and the second test line 352. Here, the second test line 352 may be integral with the alignment mark 380. The first test line 351 and the second test line 352 (or alignment mark) may be disposed on the same layer as the gate electrode 410 (see FIG. 4 ) disposed in the active area of the display panel 110. Moreover, the first test line 351 and the second test line 352 (or the alignment mark) may include the same material as the gate electrode 410, but the present aspect is not limited thereto.When the first test line 351, the second test line 352, and the alignment mark 380 are disposed on the same layer as the gate electrode 410 and include the same material, the first test line 351, the second test line 352, the alignment mark 380, and the gate electrode 410 may be formed by the same process. Therefore, the process of forming the alignment mark 380 is simplified.On the substrate 400 on which the first test line 351 and the second test line 352 (or alignment mark) are disposed, a protection layer 403 may be disposed.Here, the protective layer 403 may be in a transparent or translucent state, so that the alignment mark 380 is easily seen.A first signal line 630 may be disposed on the protective layer 403.A first planarization layer 404 adisposed so as to expose a part of the upper surface of the first signal line 630 may be disposed on the first signal line 630.A second signal line 635 in contact with the first signal line 630 may be disposed on a part of the upper surface of the first planarization layer 404 aand on the first signal line 630.On the substrate 400 on which the second signal line 635 is disposed, the second planarization layer 404 b, a first pattern 604 aof the first bank 371, a first pattern 604 bof the second bank 372, and a first pattern 604 cof the crack prevention line 530 may be disposed.The second planarization layer 404 b, the first pattern 604 aof the first bank 371, the first pattern 604 bof the second bank 372, and the first pattern 604 cof the crack prevention line 530 may be disposed on the same layer with each other and include the same material.The second planarization layer 404 b, the first pattern 604 aof the first bank 371, and the first pattern 604 bof the second bank 372 may be respectively disposed to overlap with a part of the upper surface of the second signal line 635. In addition, a hole may be provided between the second planarization layer 404 band the first pattern 604 aof the first bank 371, and between the first pattern 604 aof the first bank 371 and the first pattern 604 bof the second bank 372.A part of the upper surface of the second signal line 635 may be exposed through the hole provided between the second planarization layer 404 band the first pattern 604 aof the first bank 371 and between the first pattern 604 aof the first bank 371 and the first pattern 604 bof the second bank 372.In addition, a hole may be provided between the first structure 604 bof the second bank 372 and the first structure 604 cof the crack prevention line 530. In addition, the first inspection line 351 and the second inspection line 352 (or an alignment mark) may be disposed in a region corresponding to a region between the first pattern 604 bof the second bank 372 and the first pattern 604 cof the crack prevention line 530.Here, since the second test line 352 is integrally formed with the alignment mark 380, a first width H 2 of the second test line 352 (or alignment mark) may be larger than a width H 3 of the first test line 351.A third signal line 640 may be disposed on the second planarization layer 404 b, the second signal line 635, and the first pattern 604 aof the first bank 371. The third signal line 640 may be in contact with the second signal line 635 in the region corresponding to the region where the hole provided between the second planarization layer 404 band the first pattern 604 aof the first bank 371 is located.Moreover, the third signal line 640 may be disposed so as to surround the upper surface and the side surface of the first pattern 604 aof the first bank 371, but the structure of the present aspect is not limited thereto. The third signal line 640 may be disposed to overlap a part of the surface of the second signal line 635, or may be disposed in a part of the upper surface of the second signal line 635.In other words, in the present aspect, a structure in which the third signal line 640 is in contact with the second signal line 635 in a region corresponding to a region in which the hole provided between the second planarization layer 404 band the first pattern 604 aof the first bank 371 is located is sufficient.The first to third signal lines 630, 635, and 640 may be lines that electrically connect the pad region PAD disposed in the non-active region NA and the sub-pixel SP of the active region AA.The first signal line 630 may be, for example, a signal line to which a supply voltage is applied from the pads 360 of the pad region PAD.The second signal line 635 may be configured to be disposed on the same layer as the auxiliary electrode disposed in the active area AA, and is a signal line electrically connected to the first signal line 630. Moreover, the third signal line 640 may be configured to be disposed on the same layer as the first electrode 440 of the organic light emitting diode (OLED), and is a signal line electrically connected to the first and second signal lines 630 and 635.On the third signal line 640 disposed on the second planarization layer 404 b, a bank 405 may be disposed. In addition, the second pattern 605 aof the first bank 371 may be disposed on the third signal line 640 disposed on the first pattern 604 aof the first bank 371. In addition, the second structure 605 bof the second bank 372 is disposed on the first structure 604 bof the second bank 372, and the second structure 605 cof the crack prevention line 530 may be disposed on the first structure 604 cof the crack prevention line 530.The bank 405, the second structure 605 aof the first bank 371, the second structure 605 bof the second bank 372, and the second structure 605 cof the crack prevention line 530 may be disposed on the same layer and may include the same material, but the present aspect is not limited thereto.In addition, the third pattern 606 aof the first bank 371 is disposed on the second pattern 605 aof the first bank 371, and the third pattern 606 bof the second bank 372 may be disposed on the second pattern 605 bof the second bank 372.The third pattern 606 aof the first bank 371 and the third pattern 606 bof the second bank 372 may be disposed on the same layer as the spacer 480 disposed in the active region AA and include the same material, but the present aspect is not limited thereto.The first and second dams 371 and 372 having the above-described structure may serve to prevent the material of the second encapsulation layer 492 from flowing into the pad region PAD.Meanwhile, in FIG. 5, the shape of the alignment mark 380 is mainly described based on a structure having a shape such as but the shape of the alignment mark 380 of the present disclosure is not limited thereto.FIG. 7 is an enlarged view of the region Z of FIG. 3.In describing the present aspect, the description of the same or corresponding components as in the previous aspect is omitted. Next, a partial structure of the non-active area of the display panel according to the present aspect will be described with reference thereto.The alignment mark 380 for aligning the display panel 110 and other components disposed in the upper and lower regions of the display panel 110 has a shape in which a region having an angle of 90 degrees or more is present.The second test line 352 disposed in the non-active area NA may include first to third portions 352 a, 352 b, and 352 c, as described with reference to FIG. 5. Moreover, the second test line 352 may include a fourth portion 752 dextending in the first direction from the first portion 352 aand a fifth portion 752 eextending in the first direction from the third portion 352 c.The second inspection line 352 having such a shape may be integrally formed with an alignment mark in a plurality of regions.For example, the second test line 352 may be integral with a first alignment mark 781. Here, the first alignment mark 781 may have a structure including the alignment mark 380 of FIG. 5 integral with a part of the second portion 352 bof the second test line 352.Moreover, the second test line 352 may be integral with a second alignment mark 782. Here, the second alignment mark 782 may include the first portion 352 aof the second test line 352, a portion of the fourth portion 752 d, a portion (including a portion connected to the first portion 352 a) of the second portion 352 b, and a portion of the alignment mark 380 of FIG. 5 integral with a portion of the second portion 352 b.Moreover, the second test line 352 may be integral with a third alignment mark 783. Here, the third alignment mark 783 may include the third portion 352 cof the second test line 352, a portion of the fifth portion 752 e, a portion (including a portion connected to the third portion 352 c) of the second portion 352 b, and the alignment mark 380 of FIG. 5 integral with a portion of the second portion 352 b.In other words, the shape of the alignment mark of the present disclosure may be differently shaped, and the first to third alignment marks 781, 782, and 783 may have a shape in which a large number of portions having an angle of 90 degrees or more exist on one plane. Accordingly, the display panel 110 according to aspects of the present disclosure may include an alignment mark having high visibility.According to the aspects of the present disclosure described above, at least one test line and an alignment mark disposed in the non-active region are integrally formed, thereby minimizing the area occupied by the alignment mark in the non-active region.Moreover, according to the above-described aspects of the present disclosure, at least one test line and an alignment mark disposed in the non-active region are integrally formed, thereby simplifying the process of forming the alignment mark.The above description has been presented to enable any person skilled in the art to make and use the technical idea of the present disclosure, and has been provided in connection with a particular application and its requirements. Various modifications, additions and substitutions to the described aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects and applications without departing from the scope of the present disclosure. The above description and the accompanying drawings illustrate an example of the technical idea of the present disclosure for illustration purposes only. That is, the disclosed aspects are intended to illustrate the scope of the technical idea of the present disclosure. Therefore, the scope of the present disclosure is not limited to the aspects shown, but has the broadest scope consistent with the claims. The scope of the present disclosure should be construed based on the following claims.

Claims

A display device (100) comprising: a display panel (110) having an active area (AA) and a non-active area (NA) surrounding the active area (AA) on a substrate (400); a front cover disposed at an upper portion of the display panel (110); a back cover disposed at a lower portion of the display panel (110); a bank (370) disposed to surround an outer edge of the active area (AA) in the non-active area (NA) of the display panel (110); a pad region (PAD) spaced apart from the bank (370) in the non-active region (NA), disposed at an edge of a side of the non-active region (NA), and having a plurality of pads (360) disposed in the pad region (PAD); at least one test line (350) spaced apart from the bank (370) in the non-active region (NA) is disposed to surround a part of an outer edge of the bank (370) and connected to the plurality of pads (360), the at least one test line (350) being configured to detect damage in the non-active region (NA) by applying a current and detecting an output voltage; and at least one alignment mark (380, 781, 782, 783), wherein the at least one test line (350) comprises a first test line (351) arranged to surround the portion of the outer edge of the dam (370) and a second test line (352) spaced apart from the first test line (351) and arranged to surround an outer edge of the first test line (351), wherein the second test line (352) comprises at least one groove (355), wherein the at least one alignment mark (380, 781, 782, 783) is integral with the second test line (352) and is arranged in the at least one groove (355), and wherein the at least one alignment mark (380, 781, 782, 783) has a U-shape.The display device (100) according to claim 1, wherein the non-active region (NA) includes at least one crack preventing line (530) disposed in an outer periphery of the second test line (352).The display device (100) according to any one of claims 1 to 2, further comprising at least one thin film transistor (TFT) disposed on the substrate (400) of the active region (AA).The display device (100) of claim 3, wherein the at least one thin film transistor (TFT) includes a gate electrode (410), an active layer (420), a source electrode (430), and a drain electrode (435) disposed on the substrate (400), and the first test line (351) and the second test line (352) are disposed on the same layer as the gate electrode (410).The display device (100) of claim 4, wherein the at least one alignment mark (380, 781, 782, 783) is disposed on the same layer as the gate electrode (410) of the thin film transistor (TFT).The display device (100) of any one of claims 1 to 5, wherein the at least one groove (355) of the second test line (352) includes a first portion (352a) extending in a first direction, a second portion (352b) extending in a second direction intersecting the first direction from the first portion (352a), and a third portion (352c) extending in a direction corresponding to a direction in which the first portion (352a) extends from the second portion (352b).The display device (100) of claim 6, wherein the at least one alignment mark (380, 781, 782, 783) is integral with at least one of the first to third portions (352a, 352b, 352c) of the second test line (352).The display device (100) according to any one of claims 1 to 7, wherein a width (H2) of the at least one alignment mark (380, 781, 782, 783) with respect to a direction in which a short side of the display panel (110) extends corresponds to a depth (H1) of the at least one groove (355) or is wider than the depth (H1) of the at least one groove (355).The display device (100) according to any one of claims 1 to 8, wherein a maximum width (T) of the at least one alignment mark (380, 781, 782, 783) with respect to a direction in which a short side of the display panel (110) extends is greater than a maximum width of a signal line disposed in the non-active area (NA).The display device (100) according to any one of claims 1 to 9, wherein the at least one alignment mark (380, 781, 782, 783) includes at least two portions having an angle of 90 degrees or more.A display panel (110) comprising: a substrate (400) having an active area (AA) and a non-active area (NA) surrounding the active area (AA); a bank (370) arranged to surround an outer edge of the active area (AA) in the non-active area (NA) of the substrate (400); a pad area (PAD) spaced apart from the bank (370) in the non-active area (NA), arranged at an edge of a side of the non-active area (NA), and comprising a plurality of pads (360) arranged in the pad area (PAD); at least one test line (350) spaced apart from the bank (370) in the non-active area (NA) is arranged to surround a portion of an outer edge of the bank (370) and connected to the plurality of pads (360), the at least one test line (350) being configured to detect damage in the non-active area (NA) by applying a current and detecting an output voltage; and at least one alignment mark (380, 781, 782, 783), wherein the at least one test line (350) comprises a first test line (351) arranged to surround the portion of the outer edge of the dam (370) and a second test line (352) spaced apart from the first test line (351) and arranged to surround an outer edge of the first test line (351), wherein the second test line (352) comprises at least one groove (355), wherein the at least one alignment mark (380, 781, 782, 783) is integral with the second test line (352) and is arranged in the groove (355), and wherein the at least one alignment mark (380, 781, 782, 783) has a U-shape.The display panel (110) of claim 11, wherein the at least one groove (355) of the second test line (352) includes a first portion (352a) extending in a first direction, a second portion (3 52b) extending in a second direction intersecting the first direction from the first portion (352a), and a third portion (352c) extending in a direction corresponding to a direction in which the first portion (352a) extends from the second portion (352b).The display panel (110) of any one of claims 11 to 12, wherein a width (H2) of the at least one alignment mark (380, 781, 782, 783) with respect to a direction in which a short side of the display panel (110) extends corresponds to a depth (H1) of the at least one groove (355) or is wider than the depth (H1) of the at least one groove (355).

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