METHOD FOR MANUFACTURING A THREE-DIMENSIONAL STORAGE DEVICE

Abstract

Method comprising: forming a word line (62, 62B, 62T, 112) between a pair of dielectric layers (72, 106); robbing side walls of the dielectric layers (72, 106) of a side wall of the word line (62, 62B, 62T, 112) to expose an upper surface and a lower surface of the word line (62, 62B, 62T, 112); forming a data storage layer (84, 122) on the side walls of the dielectric layers (72, 106) and the upper surface, lower surface, and side wall of the word line (62, 62B, 62T, 112); forming a semiconductor strip (82, 124) on the data storage layer (84, 122); forming a bit line (64B, 144B) and a source line (64S, 144S) that contact the semiconductor strip (82, 124);Forming a trench (110) in a multilayer stack (104), wherein the multilayer stack (104) has the dielectric layers (72, 106), wherein the recessing of the sidewalls of the dielectric layers (72, 106) widens the trench (110) to form sidewall recesses (114), wherein the data storage layer (84, 122) and the semiconductor strip (82, 124) each extend into the sidewall recesses (114); and separating a first insulation region (126) in the trench (110) and the sidewall recesses (114), comprising forming the bit line (64B, 144B) and the source line (64S, 144S): replacing a first section of the first insulation region (126) outside the sidewall recesses (114) with a conductive line (132), with a second section of the first insulation region (126) remaining in the sidewall recesses (114);and forming a second isolation region (142) that divides the conductive line (132) into the bit line (64B, 144B) and the source line (64S, 144S).

Description

GENERAL STATE OF THE ARTSemiconductor memories are used in integrated circuits for electronic devices including radios, televisions, mobile phones, and personal computing devices as examples. Semiconductor memories have two main categories. One is volatile memory; the other is nonvolatile memory. Volatile memories include random access memory (RAM) which can be further divided into two sub-categories, static random access memory (SRAM) and dynamic random access memory (DRAM). Both the SRAM and DRAM are volatile because they will lose the information they store when not energized.On the other hand, nonvolatile memories may retain data stored thereon. One type of nonvolatile semiconductor memory is a ferroelectric random access memory (FeRAM). Advantages of the FeRAM include its fast read / write speed and its small size.WO 2019 / 152 226 A1 discloses a memory structure comprising active columns of polysilicon. US 2016 / 0 071 871 A1 discloses a semiconductor memory device having a stacked body including a plurality of electrode layers and a plurality of insulating intermediate layers.The invention is defined by claim 1.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be appreciated that, in accordance with practice in the industry, various features are not drawn to scale. Indeed, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. FIG. 1 is a block diagram of a random access memory. FIGS. 2A and 2B are various views of a memory array. FIGS. 3-11D are various views of intermediate stages in the fabrication of a memory array, in accordance with some embodiments. FIGS. 14-17C are various views of intermediate stages in the fabrication of a memory array 52, in accordance with some other embodiments. FIGS. 18A-18C are various views of a memory array, in accordance with some other embodiments. FIG. 19 is a cross-sectional view of a semiconductor device according to some embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, reference numerals may be repeated in the various examples of the present disclosure. This repetition is for convenience and clarity and does not fundamentally dictate a relationship between the various embodiments and / or configurations discussed.Further, spatially relative terms such as "below," "below," "lower," "above," "upper," and the like may be used herein for convenience in description to describe the relationship of an element or feature to (another) element(s) or feature(s) as illustrated in the drawings. The spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the drawings. The device may be otherwise (rotated 90 degrees or oriented with other orientations) and the spatially relative descriptors used herein may accordingly be interpreted equally.According to various embodiments, three-dimensional memory arrays are formed of thin film transistors (TFTs) having three-dimensional channel regions. Such channel regions may be formed by forming word lines between dielectric layers and recessing the sidewalls of the dielectric layers from the sidewalls of the word lines. Film stacks for the TFTs are then deposited along the sidewalls of the word lines and along the top and bottom surfaces of the word lines exposed by the recess. Bit and source lines are formed in contact with the film stacks for the TFTs, thereby completing the formation of the TFTs. Forming the TFTs with three-dimensional channel regions may allow the performance of the TFTs to be improved.FIG. 1 is a block diagram of a random access memory 50. the random access memory 50 includes a memory array 52, a row decoder 54, and a column decoder 56. The memory array 52, the row decoder 54, and the column decoder 56 may each be part of a same semiconductor die or may be parts of different semiconductor dies. For example, the memory array 52 may be part of a first semiconductor die, while the row decoder 54 and the column decoder 56 may be parts of a second semiconductor die.The memory array 52 includes memory cells 58, word lines 62, bit lines 64B, and source lines 64S. The memory cells 58 are arranged in rows and columns. The word lines 62, the bit lines 64B, and the source lines 64S are electrically connected to the memory cells 58. The word lines 62 are conductive lines extending along the rows of the memory cells 58. The bit lines 64B and the source lines 64S are conductive lines extending along the columns of the memory cells 58.Row decoder 54 may be, for example, a static CMOS decoder, a pseudo-NMOS decoder, or the like. During operation, row decoder 54 selects desired memory cells 58 in a row of memory array 52 by activating word line 62 for the row. Column decoder 56 may be, for example, a static CMOS decoder, a pseudo-NMOS decoder, or the like, and may include write drivers, sense amplifiers, combinations thereof, or the like. During operation, column decoder 56 selects desired memory cells 58 from columns of memory array 52 in the selected row and reads data from or writes data to selected memory cells 58 with bit lines 64B and source lines 64S.FIGS. 2A and 2B are various views of a memory array 52. FIG. 2A is a circuit diagram of the memory array 52. FIG. 2B is a three-dimensional view of a portion of the memory array 52, and is described in conjunction with FIG. 2A. Each memory cell 58 of the memory array 52 is a flash memory cell comprising a programmable TFT.FIGS. 2A and 2B illustrate three perpendicular directions D 1, D 2, and D 3 to which the subsequent FIGS. refer for the sake of clear illustration. The first direction D 1 is parallel to a main surface of an underlying substrate. The second direction D 2 is perpendicular to the first direction D, and is parallel to the main surface of the underlying substrate. The third direction D 3 is perpendicular to the first direction D 1, the second direction D 2, and the main surface of the underlying substrate.In some embodiments, the memory array 52 is a flash memory array, such as a NOR flash memory array. In some embodiments, the memory array 52 is another type of non-volatile memory array, such as a magneto-resistive random access memory (MRAM) array, a resistive random access memory (RRAM) array, or the like. Each of the memory cells 58 is a flash memory cell having a TFT 68. The gate of each TFT 68 is electrically connected to a respective word line 62, a first source / drain region of each TFT 68 is electrically connected to a respective bit line 64B, and a second source / drain region of each TFT 68 is electrically connected to a respective source line 64S (each electrically connected to ground). The memory cells 58 in a same row of the memory array 52 share a common word line 62, while the memory cells in a same column of the memory array 52 share a common bit line 64B and a common source line 64S.The memory array 52 includes a plurality of horizontally disposed conductive lines (e.g., the word lines 62), each of the word lines 62 being disposed between dielectric layers 72. The word lines 62 extend in the first direction D 1. The wordlines 62 may have a staircase configuration such that the lower wordlines 62 are longer than and extend past endpoints of the upper wordlines 62. For example, in FIG. 2B, multiple stacked layers of the word lines 62 are illustrated, with the top word lines 62T being the shortest lines and the bottom word lines 62B being the longest lines. Respective lengths of the word lines 62 increase in a direction extending toward the underlying substrate. This allows a portion of each wordline 62 to be accessed from above the memory array 52, such that conductive contacts may be formed at an exposed portion of each wordline 62.The bit lines 64B and the source lines 64S are vertically arranged conductive lines. The bit lines 64B and the source lines 64S extend in the third direction D 3. An isolation region 74 is disposed between and isolates adjacent ones of the bit lines 64B and the source lines 64S. The boundaries of each memory cell 58 are defined by pairs of the bit lines 64B and the source lines 64S along with an intersecting word line 62. An isolation region 76 is disposed between and isolates adjacent TFTs 68 (e.g., adjacent pairs of the bit lines 64B and the source lines 64S). Although FIGS. 2A and 2B illustrate a particular placement of the bit lines 64B with respect to the source lines 64S, it should be appreciated that the placement of the bit lines 64B and the source lines 64S may be reversed in other embodiments.The memory array 52 further includes semiconductor strips 82 and tunnel strips 84. The tunnel strips 84 contact the word lines 62, and the semiconductor strips 82 are disposed between the tunnel strips 84 and the bit lines 64B, the source lines 64S, and the isolation regions 74.The semiconductor strips 82 provide channel regions for the TFTs 68 of the memory cells 58 and may also be referred to as channel layers. For example, when an appropriate voltage (e.g., higher than a respective threshold voltage of a corresponding TFT 68) is applied by a corresponding word line 62, a portion of a semiconductor strip 82 intersecting the word line 62 may allow current to flow from a bit line 64B to a corresponding source line 64S (e.g., in the first direction D 1). In FIG. 2B, each semiconductor strip 82 contacts a surface of each corresponding word line 62, thereby providing planar channel regions for the TFTs 68. As will be explained in more detail below, according to various embodiments, the semiconductor strips 82 are formed to contact multiple surfaces of the respective word lines 62, thereby providing three-dimensional channel regions for the TFTs 68.The tunnel strips 84 may be polarized in one of two different directions by applying an appropriate voltage across the tunnel strip 84, and may also be referred to as data storage layers. Depending on a polarization direction of a specific portion of a tunnel strip 84, a threshold voltage of a corresponding TFT 68 varies and a digital value (e.g., o or 1) may be stored. For example, if a portion of tunnel strip 84 has a first electrical polarization direction, the corresponding TFT 68 may have a relatively low threshold voltage, and if the portion of tunnel strip 84 has a second electrical polarization direction, the corresponding TFT 68 may have a relatively high threshold voltage. The difference between the two threshold voltages may be referred to as the threshold voltage offset. A larger threshold voltage offset makes it easier (e.g., less prone to errors) to read the digital value stored in the corresponding memory cell 58. In some embodiments, the tunnel strips 84 are formed of a high-k ferroelectric material, and thus the memory array 52 may also be referred to as a ferroelectric random access memory (FeRAM) array.In order to perform a write operation on a specific memory cell 58, a write voltage is applied across a portion of the tunnel stripe 84 corresponding to the memory cell 58. The write voltage may be applied, for example, by applying appropriate voltages to the word line 62, the bit line 64B, and the source line 64S corresponding to the memory cell 58. By applying the write voltage across the portion of the tunnel stripe 84, a polarization direction of the portion of the tunnel stripe 84 can be changed. As a result, the corresponding threshold voltage of the corresponding TFT 68 may be switched from a low threshold voltage to a high threshold voltage (or vice versa), such that a digital value may be stored in the memory cell 58. Because the word lines 62 and the bit lines 64B intersect in the memory array 52, individual memory cells 58 may be selected and written to.In order to perform a read operation on a specific memory cell 58, a read voltage (a voltage between the low and high threshold voltages) is applied to the word line 62 corresponding to the memory cell 58. Depending on the polarization direction of the corresponding portion of the tunnel strip 84, the TFT 68 of the memory cell 58 may or may not be turned on. Thus, the bit line 64B may or may not be discharged through the source line 64S (e.g., to ground) so that the digital value stored in the memory cell 58 may be determined. Because the word lines 62 and the bit lines 64B intersect in the memory array 52, individual memory cells 58 may be selected and read therefrom.FIGS. 3-11D are various views of intermediate stages in the fabrication of a memory array 52, in accordance with some embodiments. FIGS. 3, 4, 5, 6, 7A, 8A, 9A, 10 and 11A are three-dimensional views. FIGS. 7B, 8B, and 9B are cross-sectional views respectively shown along the reference cross-sections B-B in FIGS. 7A, 8A, and 9A. FIGS. 11B, 11C, and 11D are cross-sectional views shown along reference cross-sections B-B, C-C, and D-D in FIG. 11A, respectively. A portion of the memory array 52 is illustrated. Some features, such as the staircase arrangement of the word lines (see FIG. 2B ), are not shown for clarity of illustration.In FIG. 3, a substrate 102 is provided. The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or an n-dopant) or undoped. The substrate 102 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates such as a multilayer substrate or a gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate 102 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, Aluminiumgalliumarsenid gallium indium arsenide, gallium indium phosphide, and / or Galliumindiumarsenidphosphid; or combinations thereof. The substrate 102 may include a dielectric material. For example, the substrate 102 may be a dielectric substrate or may include a dielectric layer on a semiconductor substrate. Acceptable dielectric materials for the substrate 102 include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or the like. In some embodiments, the substrate 102 is formed of silicon carbide.A multilayer stack 104 is formed over the substrate 102. The multilayer stack 104 comprises alternating dielectric layers 106 and sacrificial layers 108. The dielectric layers 106 are formed of a first dielectric material and the sacrificial layers 108 are formed of a second dielectric material. The dielectric materials may be selected from the candidate dielectric materials of the substrate 102, respectively.The multilayer stack 104 will be patterned in the subsequent processing. As such, the dielectric materials of the dielectric layers 106 and the sacrificial layers 108 both have a high etch selectivity with respect to the etching of the material of the substrate 102. The patterned dielectric layers 106 will be used to isolate subsequently formed TFTs. The patterned sacrificial layers 108 may also be referred to as dummy layers and will be replaced with word lines for the TFTs in the subsequent processing. As such, the second dielectric material of the sacrificial layers 108 also has a high etch selectivity with respect to the etching of the first dielectric material of the dielectric layers 106. In embodiments where the substrate 102 is formed of silicon carbide, the dielectric layers 106 may be formed of silicon oxide and the sacrificial layers 108 may be formed of silicon nitride. Other combinations of dielectric materials that have acceptable etch selectivity with respect to each other may also be used.Each layer of the multilayer stack 104 may be formed by an acceptable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. A thickness of each of the layers may range from about 40 nm to about 50 nm. In some embodiments, the dielectric layers 106 are formed with a different thickness than the sacrificial layers 108. For example, the dielectric layers 106 may be formed with a greater thickness than the sacrificial layers 108. In the illustrated embodiment, multilayer stack 104 includes three layers of dielectric layers 106 and two layers of sacrificial layers 108. It should be appreciated that the multilayer stack 104 may include other amounts of the dielectric layers 106 and the sacrificial layers 108. The multilayer stack 104 may have a total height in the range of about 1000 nm to about 10000 nm.In FIG. 4, trenches 110 are patterned in the multilayer stack 104. In the illustrated embodiment, the trenches 110 extend through the multilayer stack 104 and expose the substrate 102. In another embodiment, the trenches 110 extend through some, but not all, layers of the multilayer stack 104. The trenches 110 may be patterned using acceptable photolithography and etching techniques, such as an etching process that is selective with respect to the multilayer stack 104 (e.g., selectively removing the dielectric materials of the dielectric layers 106 and the sacrificial layers 108 at a faster rate than the material of the substrate 102). The etching may be any acceptable etching process, such as a reactive ion etch (RIE), a neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. In embodiments where the substrate 102 is formed of silicon carbide, the dielectric layers 106 are formed of silicon oxide, and the sacrificial layers 108 are formed of silicon nitride, the trenches 110 may be formed by dry etching using a fluorine-based gas (e.g., C 4 F 6), mixed with hydrogen gas (H 2- gas) or oxygen gas (O 2- gas). After the patterning, respective portions of the multilayer stack 104 are disposed between respective ones of the trenches 110. Each portion of the multilayer stack 104 has a width W 1 in the second direction D 2 which may range from about 100 nm to about 120 nm. Further, each portion of the multilayer stack 104 is spaced apart by a separation distance S 1 in the second direction D 2 which may range from about 75 nm to about 85 nm.In FIG. 5, sacrificial layers 108 are replaced by wordlines 112. The word lines 112 each have a main layer and may include one or more additional layers such as adhesive layers, barrier layers, diffusion layers, and the like. In some embodiments, the word lines 112 each include a main layer and one or more adhesive layers. For example, the adhesive layers may extend along the top and bottom surfaces of the main layers. The adhesive layers may be formed of a first conductive material having good adhesion to the material of the dielectric layers 106, such as a metal nitride such as titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, hafnium nitride, or the like. The main layers may be formed of a second conductive material having good adhesion to the material of the adhesive layers, such as a metal such as tungsten, ruthenium, molybdenum, cobalt, aluminum, nickel, copper, silver, gold, alloys thereof, or the like. The material(s) of the wordlines 112 may / may each be formed by an acceptable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like.The word lines 112 may include a plurality of conductive features formed in different processes. For example, first conductive features 112A may be formed to replace some portions of sacrificial layers 108, and subsequently second conductive features 112B may be formed to replace remaining portions of sacrificial layers 108. In such embodiments, a lateral etch is performed to expand a first subset of the trenches 110 while masking a second subset of the trenches 110. In particular, portions of the sidewalls of the sacrificial layers 108 exposed by the trenches 110 are recessed to form sidewall recesses. The sidewall recesses may be formed by an acceptable etching process, such as one that is selective with respect to the material of the sacrificial layers 108 (e.g., selectively removes the material of the sacrificial layers 108 at a faster rate than the material(s) of the dielectric layers 106 and the substrate 102). The etching may be isotropic. In embodiments where the substrate 102 is formed of silicon carbide, the dielectric layers 106 are formed of silicon oxide, and the sacrificial layers 108 are formed of silicon nitride, the trenches 110 may be extended by wet etching using phosphoric acid (H 3 PO 4). In another embodiment, dry etching that is selective to the material of sacrificial layers 108 may be used. The material(s) of the word lines 112 are then conformally deposited in the sidewall recesses to form the first conductive features 112A. An acceptable etching process, such as a dry etch (e.g., a reactive ion etch (RIE), a neutral beam etch (NBE), the like), a wet etch, the like, or a combination thereof, may be performed to remove excess material(s) of the word lines 112 from the sidewalls of the dielectric layers 106 and the top surface of the substrate 102. The etching may be anisotropic. The above process may then be repeated to form the second conductive features 112B. The first conductive features 112A and the second conductive features 112B are collectively referred to as word lines 112 of the memory array 52.It should be appreciated that the dielectric layers 106 and the word lines 112 may be formed in other ways. For example, instead of forming the multilayer stack 104 of FIG. 3 and replacing the sacrificial layers 108 with wordlines 112, a multilayer stack of alternating dielectric layers and conductive layers may be formed. The multilayer stack may be patterned with trenches to form the word lines 112 from remaining portions of the conductive layers.In FIG. 6, the trenches 110 are extended to form sidewall recesses 114. In particular, portions of the sidewalls of the dielectric layers 106 exposed by the trenches 110 are recessed to form the sidewall recesses 114. Although the sidewalls of the dielectric layers 106 are just illustrated, the sidewalls may be concave or convex. The sidewall recesses 114 may be formed by an acceptable etching process, such as one that is selective with respect to the material of the dielectric layers 106 (e.g., selectively removes the material of the dielectric layers 106 at a faster rate than the materials of the word lines 112 and the substrate 102). The etching may be isotropic. In embodiments where the substrate 102 is formed of silicon carbide, the dielectric layers 106 are formed of silicon oxide, and the word lines 112 are formed of tungsten, the trenches 110 may be extended by wet etching using dilute hydrofluoric acid (dHF). In another embodiment, the trenches 110 may be extended by dry etching using carbon tetrafluoride (CF 4).After forming, the sidewall recesses 114 have a depth D 4 that extends past the sidewalls of the dielectric layers 106. A timed etching process may be used to stop etching the sidewall recesses 114 after the sidewall recesses 114 reach a desired depth D 4 in the second direction D 2. For example, the sidewall recesses 114 may be formed with a depth D 4 in the range of about 30 nm to about 40 nm. Forming the sidewall recesses 114 exposes the top and bottom surfaces of the word lines 112. As will be explained in more detail below, one or more layers provide channel regions and data storage for the subsequently formed TFTs is formed in the sidewall recesses 114, thereby allowing the layers to contact the top surfaces and the bottom surfaces of the word lines 112. After the sidewall recesses 114 are formed, the remaining portions of the dielectric layers 106 have a width W 2 in the second direction D 2 which may range from about 20 nm to about 40 nm, and the word lines 112 have a width W 3 in the second direction D 2 which may range from about 100 nm to about 120 nm. Forming the sidewalls 114 may reduce the widths of the dielectric layers 106 by about 60% to about 80%. Forming the sidewall recess 114 with dimensions in the ranges discussed herein allows the TFTs to be formed with channel regions of a desired length. Forming the sidewall recess 114 with dimensions outside the ranges discussed herein may not allow the TFTs to be formed with channel regions of a desired length.In FIGS. 7A and 7B, TFT film stacks are formed in the trenches 110 and the sidewall recesses 114. In particular, two tunnel strips 122, two semiconductor strips 124, and an isolation region 126 are formed in each of the trenches 110 (and their corresponding sidewall recesses 114). In this embodiment, no other layers are formed in the trenches 110. In another embodiment (discussed in more detail below), additional layers are formed in the trenches 110.The tunnel strips 122 are data storage strips formed of an acceptable material for storing digital values. In some embodiments, the tunnel strips 122 are formed of a high-k ferroelectric material, such as hafnium zirconium oxide (HfZrO); zirconium oxide (ZrO), hafnium oxide (HfO) doped with lanthanum (La), silicon (Si), aluminum (Al), or the like; undoped hafnium oxide (HfO); or the like. In another embodiment (discussed below), the tunnel strips 122 comprise a low-k dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like. The material of the tunnel strips 122 may be formed by an acceptable deposition process, such as ALD, CVD, physical vapor deposition (PVD), or the like. The tunnel strips 122 may have a thickness in the range of about 9 nm to about 11 nm.The semiconductor strips 124 are channel strips formed of an acceptable material for providing channel regions for the TFTs, such as indium gallium zinc lead oxide (IGZTO), indium gallium zinc oxide (IGZO), indium tin oxide (ITO), zinc oxide (ZnO), polysilicon, amorphous silicon, or the like. The material of the semiconductor strips 124 may be formed by an acceptable deposition process, such as ALD, CVD, PVD, or the like. The semiconductor strips 124 may have a thickness in the range of about 9 nm to about 11 nm.The isolation regions 126 are formed of an acceptable material for protecting and electrically isolating the underlying semiconductor strips 124 and tunnel strips 122. Acceptable dielectric materials include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or the like. The material of the isolation regions 126 may be formed by an acceptable deposition process, such as ALD, CVD, flowable CVD (FCVD), or the like. The isolation regions 126 may have a thickness in the range of about 8 nm to about 14 nm.The tunnel strips 122, the semiconductor strips 124, and the isolation regions 126 may be formed by a combination of deposition, etching, and planarization. For example, a tunnel layer is conformally deposited in the trenches 110 and the sidewall recesses 114. More specifically, the tunnel layer extends along the sidewalls of the word lines 112, the recessed sidewalls of the dielectric layers 106, and the top and bottom surfaces of the word lines 112 exposed by the sidewall recesses 114. In some embodiments, the tunnel layer is HfZrO deposited by ALD. The tunnel layer may optionally be anisotropically etched to remove portions of the tunnel layer on the undersides of the trenches 110, exposing the substrate 102 and separating the tunnel strips from horizontally adjacent TFTs. A semiconductor layer is then conformally deposited on the tunnel layer and in the trenches 110 and the sidewall recesses 114. In some embodiments, the semiconductor layer is IGZTO deposited by ALD. The semiconductor layer may then be anisotropically etched to remove portions of the semiconductor layer on the bottom surfaces of the trenches 110, exposing the substrate 102 and separating the semiconductor strips from horizontally adjacent TFTs. A dielectric layer is then conformally deposited on the semiconductor layer and in the remaining portions of the trenches 110 and the sidewall recesses 114. In some embodiments, the dielectric layer is an oxide, such as silicon oxide, deposited by FCVD. A removal process is then applied to the various layers to remove excess materials over the top dielectric layer 106 / wordline 112. The removal process may be a planarization process such as chemical mechanical polishing (CMP), etch back, combinations thereof, or the like. The portions of the tunnel layer, the semiconductor layer, and the dielectric layer remaining in the trenches 110 form the tunnel strips 122, the semiconductor strips 124, and the isolation regions 126, respectively. The planarization process exposes the top dielectric layer 106 / wordline 112 such that the top surfaces of the top dielectric layer 106 / wordline 112, the tunnel strips 122, the semiconductor strips 124, and the isolation regions 126 are coplanar (within process variations) after the planarization process.At least the tunnel strips 122 and the semiconductor strips 124 have portions in the sidewall recesses 114. The isolation regions 126 may also include portions in the sidewall recesses 114. The tunnel strips 122 and the semiconductor strips 124 thus extend along the top and bottom surfaces of the word lines 112 exposed by the sidewall recesses 114, thereby providing three-dimensional channel regions 124C (see FIG. 8B ) for the TFTs. Thus, by increasing the touched area of the word lines 112, the lengths of the channel regions 124C for the TFTs may be increased, thereby improving the performance and efficiency of the TFT compared to TFTs having planar channel regions. For example, three-dimensional channel regions may produce a larger electric field with lower gate voltages than planar channel regions. Increasing the electric field in the channel regions may help improve the writing speed of the memory array 52.In FIGS. 8A and 8B, conductive lines 132 are formed in the isolation regions 126. The conductive lines 132 may contact the substrate 102. As will be explained in more detail below, the conductive lines 132 are columns that are divided into bit lines and source lines for the TFTs. The bit lines and the source lines also act as source / drain regions of the TFTs. As such, the conductive lines 132 are formed in contact with the semiconductor strips 124, such that the bit lines and the source lines will be adjacent to the channel regions 124C.As an example of forming the conductive lines 132, openings for the conductive lines 132 are formed through the isolation regions 126. The openings may be formed with an etching process that is selective with respect to the isolation regions 126 (e.g., selectively removes the material of the isolation regions 126 at a faster rate than the materials of the tunnel strips 122 and the semiconductor strips 124). For example, the openings through the isolation regions 126 may be formed by dry etching using ammonia (NH 3- gas) gas and hydrogen fluoride (HF) gas performed using an etch mask 134 having a pattern of the conductive lines 132. The etch mask 134 may include a photoresist, a hard mask, spacers, combinations thereof, or the like, which may be patterned using acceptable photolithography and etching techniques. A liner such as a diffusion barrier layer, an adhesion layer or the like and a main layer are formed in the openings. The liner may be formed of a conductive material such as titanium, titanium nitride, tantalum, tantalum nitride, or the like, which may be deposited by a conformal deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the liner may include an adhesion layer and at least a portion of the adhesion layer may be treated to form a diffusion barrier layer. The main layer may be formed of a conductive material such as tungsten, cobalt, ruthenium, aluminum, nickel, copper, a copper alloy, silver, gold, or the like, which may be deposited by ALD, CVD, PVD, or the like. In some embodiments, the conductive lines 132 include a liner formed of titanium nitride and a main layer formed of tungsten. A removal process is then applied to the various layers to remove excess material(s) of the conductive lines 132 over the isolation regions 126, the semiconductor strip 124, the tunnel strip 122, and the top dielectric layer 106 / wordline 112. The removal process may be a planarization process such as chemical mechanical polishing (CMP), etch back, combinations thereof, or the like. The remaining material(s) form / form the conductive lines 132 in the openings. The etch mask 134 may be removed during the process of forming the conductive lines 132 (e.g., by the etch process, the removal process, or the like) or may be removed after the conductive lines 132 are formed, such as by (an) acceptable etch and / or etch process(s).After the conductive lines 132 are formed, some of the portions of the isolation regions 126 outside the sidewall recesses 114 (see FIG. 7A ) are replaced, but the portions of the isolation regions 126 remain in the sidewall recesses 114. Thus, portions 126P of the isolation regions 126 are disposed between the conductive lines 132 and the corresponding semiconductor strips 124. The semiconductor strips 124 have first portions (e.g., portions outside the sidewall recesses 114) that contact the conductive lines 132 and have second portions (e.g., those in the sidewall recesses 114) that are spaced apart from the conductive lines 132 by the portions 126P of the isolation regions 126.In FIGS. 9A and 9B, isolation regions 142 are formed by the semiconductor stripes 124, the isolation regions 126, and the conductive lines 132. The isolation regions 142 subdivide the semiconductor strips 124 and the conductive lines 132 to form the TFTs 68 (see FIG. 9B ). Specifically, the conductive lines 132 are divided to form bit lines 144B and source lines 144S. As mentioned previously, the bit lines 144B and the source lines 144S act as source / drain regions of the TFTs 68. After the isolation regions 142 are formed, each TFT 68 includes a portion of a tunnel strip 122, a portion of a semiconductor strip 124, a bit line 144B, and a source line 144S. The isolation regions 142 also extend into portions of the word lines 112 and the tunnel strips 122, but do not subdivide the word lines 112 or the tunnel strips 122.As an example of forming the isolation regions 142, openings for the isolation regions 142 are formed through the semiconductor strips 124, the isolation regions 126, and the conductive lines 132. The openings also extend into portions of the tunnel strips 122 (such as those portions that extend along the top, bottom, and side surfaces of the word lines 112) and portions of the word lines 112 (such as those portions that are below the removed portions of the tunnel strips 122). Each opening divides a conductive line 132 into a bit line 144B and a source line 144S, and also divides two semiconductor strips 124 into four semiconductor strips 124. The openings may be formed with an etching process that removes the conductive and dielectric materials of the layers of the memory cell 52. For example, the openings may be formed by dry etching using a fluorine-based gas (e.g., C 4 F 6) and hydrogen gas (H 2- gas) or oxygen gas (O 2- gas) performed using an etch mask 148 having a structure of the isolation regions 142. The etch mask 148 may include a photoresist, a hard mask, spacers, combinations thereof, or the like, which may be patterned using acceptable photolithography and etching techniques. The openings may be formed using acceptable photolithography and etching techniques. A dielectric material is then formed in the openings. The dielectric material may be formed of oxides such as silicon oxide, nitrides such as silicon nitride, carbides such as silicon carbide, combinations thereof, or the like, which may be deposited by CVD, ALD, or the like. In some embodiments, the isolation regions 142 are formed of silicon nitride. A removal process is then applied to the various layers to remove excess dielectric material of the isolation regions 142 over the bitlines 144B, the source lines 144S, the isolation regions 142, the isolation regions 126, the semiconductor strip 124, the tunnel strip 122, and the top dielectric layer 106 / wordline 112. The removal process may be a planarization process such as chemical mechanical polishing (CMP), etch back, combinations thereof, or the like. The remaining dielectric material forms the isolation regions 142 in the openings. The etch mask 148 may be removed during the process of forming the isolation regions 142 (e.g., by the etch process, the removal process, or the like) or may be removed after the isolation regions 142 are formed, such as by (an) acceptable etch and / or etch process(s).The isolation regions 142 each have a width W 4 in the first direction D 1 which may range from about 38 nm to about 41 nm. The isolation regions 142 may subdivide the conductive lines 132 into bit lines 144B and source lines 144S having equal or different widths. The bit lines 144B each have a width W 5 in the first direction D 1 which may be in the range of about 38 nm to about 42 nm, and the source lines 144S each have a width W 6 in the first direction D 1 which may be in the range of about 38 nm to about 42 nm. The width W 4 may be greater than, less than, or equal to the width W 6. The portions of the isolation regions 126 between the bit lines 144B and the source lines 144S have a width W 7 in the first direction D 1 which may range from about 90 nm to about 110 nm. The bit lines 144B, the source lines 144S, and the portions of the isolation regions 126 between the bit lines 144B and the source lines 144S each have a width W 8 in the second direction D 2 which may range from about 35 nm to about 45 nm.In FIG. 10, an inter-layer dielectric (ILD) 152 is deposited over the bitlines 144B, the source lines 144S, the isolation regions 142, the isolation regions 126, the semiconductor strip 124, the tunnel strip 122, and the top dielectric layer 106 / wordline 112. The ILD 152 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, or the like. Dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, an etch stop layer is formed between the ILD 152 and the bitlines 144B, the source lines 144S, the isolation regions 142, the isolation regions 126, the semiconductor strip 124, the tunnel strip 122, and the top dielectric layer 106 / wordline 112. The etch stop layer may be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having high etch selectivity with respect to the etching of the ILD 152. The etch stop layer may be formed by any suitable method, such as CVD, ALD, or the like.Bit line contacts 154 and source line contacts 156 are then formed extending through the ILD 152. Contact openings are formed through the ILD 152. The contact openings may be formed using acceptable photolithography and etching techniques. A liner such as a diffusion barrier layer, an adhesion layer, or the like and a conductive material are then formed in the contact holes. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The liner may be deposited by a conformal deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the liner may include an adhesion layer and at least a portion of the adhesion layer may be treated to form a diffusion barrier layer. The conductive material may be tungsten, cobalt, ruthenium, aluminum, nickel, copper, a copper alloy, silver, gold, or the like. The conductive material may be deposited by ALD, CVD, PVD, or the like. A removal process may be performed to remove excess material from the top surface of the ILD 152. The removal process may be a planarization process such as chemical mechanical polishing (CMP), etch back, combinations thereof, or the like. The remaining liner and conductive material in the contact openings form the bit line contacts 154 and the source line contacts 156. The bit line contacts 154 are physically and electrically coupled to the bit lines 144B. The source line contacts 156 are physically and electrically coupled to the source lines 144S.In FIGS. 11A, 11B, 11C, and 11D, an interconnect structure 160 is formed over the intermediate structure. The interconnect structure 160 may include, for example, metallization structures 162 in a dielectric material 164 (not shown in FIG. 11A, see FIGS. 11B, 11C, and 11D ). The dielectric material 164 may include one or more dielectric layers, such as one or more layers of a low-k (LK) dielectric material or an ultra-low-k (ELK) dielectric material. The metallization structures 162 may be metal interconnects (e.g., conductive lines, conductive vias, etc.) formed in the one or more dielectric layers. The interconnect structure 160 may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. Metallization patterns 162 of interconnect structure 160 are electrically connected to bit lines 144B (through bit line contacts 154) and source lines 144S (through source line contacts 156) and interconnect TFTs 68 to form functional memories.As shown in FIGS. 11C and 11D, the bit lines 144B and the source lines 144S are formed in an alternating structure. Forming the bit lines 144B and the source lines 144S in an alternating structure helps prevent adjacent bit lines 144B / source lines 144S in the cross-section of FIG. 11C from being shorted when a word line 112 is activated.FIGS. 12A, 12B, and 12C are cross-sectional views of the memory arrays 52 according to various embodiments. FIGS. 12A, 12B, and 12C are shown along reference cross section C-C in FIG. 11A. Wordlines 112 having different profile shapes are shown. The profile shapes of the word lines 112 may be determined by the etch selectivity between the material of the dielectric layers 106 and the material of the word lines 112 during the etch process used to form the sidewall recesses 114 (see FIG. 6 ).In FIG. 12A, the word lines 112 have quadrangular profile shapes. The sidewall of each wordline 112 forms a right angle θ 1 with the top and bottom surfaces of the wordline 112. The word lines 112 may be formed with quadrangular profile shapes by recessing the sidewalls of the dielectric layers with an etching process having a high etching selectivity between the dielectric layers 106 and the word lines 112, such as an etching process that selectively removes the material of the dielectric layers 106 about 5 to about 8 times faster than the materials of the word lines 112.In FIG. 12B, the word lines 112 have tapered profile shapes. The sidewall of each wordline 112 forms an obtuse angle θ 2 with the top and bottom surfaces of the wordline 112. The angle θ 2 is greater than 90 degrees, such as in the range of about 92 degrees to about 98 degrees. The word lines 112 may be formed with tapered profile shapes by recessing the sidewalls of the dielectric layers with an etching process having high etch selectivity between the dielectric layers 106 and the word lines 112, such as an etching process that selectively removes the material of the dielectric layers 106 about 5 to about 8 times faster than the materials of the word lines 112.In FIG. 12C, the word lines 112 have expanded profile shapes. The sidewall of each wordline 112 forms an acute angle θ 3 with the top and bottom surfaces of the wordline 112. The angle θ 3 is less than 90 degrees, such as in the range of about 85 degrees to about 89 degrees. The word lines 112 may be formed with expanded profile shapes by recessing the sidewalls of the dielectric layers with an etching process having a high etch selectivity between the dielectric layers 106 and the word lines 112, such as an etching process that selectively removes the material of the dielectric layers 106 about 5 to about 8 times faster than the materials of the word lines 112.The word lines 112 of FIGS. 12A, 12B, and 12C have shapes with sharp corners. Sharp corner shapes are those formed by an arc having a length less than about 3% of the thickness of the word lines 112, such as an arc length in the range of about 1.2 nm to about 1.5 nm. The corner shapes of the word lines 112 may be determined by the rate of the lateral etching of the etching process used to form the sidewall recesses 114 (see FIG. 6 ). The word lines 112 may be formed with sharp corner shapes by recessing the dielectric layers 106 with an etching process having a lateral etching rate in the range of about 2 μm / min to about 2.5 μm / min.FIGS. 13A, 13B, and 13C are cross-sectional views of the memory arrays 52 according to various embodiments. FIGS. 13A, 13B, and 13C are shown along the reference cross section C-C in FIG. 11A. The embodiments shown in FIGS. 13A, 13B, and 13C are each similar to the embodiments shown in FIGS. 12A, 12B, and 12C, except that the word lines 112 have shapes with rounded corners. Rounded corner shapes are those formed by an arc having a length greater than about 3% of the thickness of the word lines 112, such as a length in the range of about 1.2 nm to about 1.5 nm. The word lines 112 may be formed with rounded corner shapes by recessing the dielectric layers 106 with an etching process having a lateral etching rate in the range of about 2 μm / min to about 2.5 μm / min.FIGS. 14-17C are various views of intermediate stages in the fabrication of a memory array 52, in accordance with some other embodiments. FIGS. 14, 15, 16A, and 17A are three-dimensional views. FIG. 16B is a cross-sectional view showing a similar cross-section to FIG. 9B. FIGS. 17B and 17C are cross-sectional views showing a similar cross-section to FIGS. 11B and 11C. Some features, such as the staircase arrangement of the word lines (see FIG. 2B ), are not shown for clarity of illustration. In this embodiment, isolation strips are formed between the tunnel strips 122 and the word lines 112, which may help reduce the parasitic capacitance of the TFTs.In FIG. 14, a structure similar to that described with reference to FIG. 6 is formed or obtained. An isolation layer 172 is then conformally deposited in the trenches 110 and the sidewall recesses 114. More specifically, the isolation layer 172 extends along the sidewalls of the word lines 112, the recessed sidewalls of the dielectric layers 106, and the top and bottom surfaces of the word lines 112 exposed by the sidewall recesses 114. The isolation layer 172 may be formed of a dielectric material. The dielectric material may be formed of oxides such as silicon oxide, nitrides such as silicon nitride, carbides such as silicon carbide, combinations thereof, or the like, which may be deposited by CVD, ALD, or the like. In some embodiments, the isolation layer 172 is silicon oxide or aluminum oxide deposited by ALD. The insulation layer 172 may have a thickness in the range of about 9 nm to about 10 nm.In FIG. 15, the isolation layer 172 is patterned to form isolation strips 174. The isolation layer 172 may be patterned with an etching process that is selective with respect to the isolation layer 172 (e.g., selectively removes the material of the isolation layer 172 at a faster rate than the materials of the dielectric layers 106 and the word lines 112). For example, the openings through the insulation layer 172 may be formed by dry etching using ammonia gas (NH 3- gas) and hydrogen fluoride gas (HF gas) performed using an etch mask 176 having a structure of the insulation strips 174. The etch mask 176 may include a photoresist, a hard mask, spacers, combinations thereof, or the like, which may be patterned using acceptable photolithography and etching techniques. The etch mask 176 may be removed during the process of forming the isolation strips 174 (e.g., by the etch process) or may be removed after the isolation strips 174 are formed, such as by (an) acceptable etch and / or etch process(s).In FIGS. 16A and 16B, the tunnel stripes 122, the semiconductor stripes 124, the isolation regions 126, the isolation regions 142, the bit lines 144B, and the source lines 144S are formed using processes similar to those described with reference to FIGS. 7A to 9B. After forming, the tunnel strips 122 contact some portions of the word lines 112 and the isolation strips 174 contact other portions of the word lines 112. In other words, tunnel strips 122 are formed on isolation strips 174 and portions of word lines 112. The bit lines 144B and the source lines 144S are formed directly adjacent to the isolation strips 174. In other words, each isolation strip 174 is disposed between a column of word lines 112 and a respective one of a bit line 144B or a source line 144S. The isolation strips 174 increase the amount of electrical isolation between the word lines 112 and the bit lines 144B / source lines 144S, thereby reducing parasitic capacitance on the channel regions 124C of the TFTs 68. Reducing the parasitic capacitance of the TFTs 68 may help improve the read speed of the memory array 52.In FIGS. 17A and 17B, an interconnect structure 160 is formed over the intermediate structure. The interconnect structure 160 may be formed using a similar process to that described with reference to FIGS. 11A, 11B, 11C, and 11D.FIGS. 18A-18C are various views of a memory array 52, in accordance with some other embodiments. FIG. 18A is a cross-sectional view showing a similar cross-section to FIG. 9B. FIGS. 18B and 18C are cross-sectional views showing a similar cross-section to FIGS. 11B and 11C. Some features, such as the staircase arrangement of the word lines (see FIG. 2B ), are not shown for clarity of illustration. In this embodiment, the tunnel strips 122 comprise a low-k dielectric material. In particular, tunnel strips 122 include a plurality of low-k dielectric layers 122A, 122B, 122C instead of a high-k ferroelectric layer.The first dielectric layers 122A are formed on the substrate 102 and in contact with the sidewalls of the dielectric layers 106 and the word lines 112. The second dielectric layers 122B are formed on the first dielectric layers 122A. The third dielectric layers 122C are formed on the second dielectric layers 122B. In some embodiments, the first dielectric layers 122A and the third dielectric layers 122C are formed of a first dielectric material (e.g., an oxide such as silicon oxide) and the second dielectric layers 122B are formed of another second dielectric material (e.g., a nitride such as silicon nitride). The first dielectric layers 122A, the second dielectric layers 122B, and the third dielectric layers 122C may be formed by a combination of deposition, etching, and planarization in a manner similar to that discussed above with reference to the high-k tunnel strips 122. In some embodiments, dielectric layers 122A, 122B, 122C are layers for floating gate transistors. For example, dielectric layers 122A may be barrier layers, dielectric layers 122B may be trapping layers, and dielectric layers 122C may be tunnel layers.The embodiments of Figures 14-18C are shown with word lines 112 having quadrangular profile shapes and sharp corner shapes (similar to those described with reference to Figure 12A). It should be noted that the embodiments of Figs. 14-18C may be formed with word lines 112 having tapered profile shapes or flared profile shapes, and with word lines 112 having shapes with rounded corners.In the embodiments described with reference to FIGS. 3-18C, the memory array 52 is formed over a substrate 102, such as a dielectric substrate. In some embodiments, the memory array 52 is formed as part of a stand-alone device (e.g., a memory die) that is integrated with other devices (e.g., a logic die) by device packaging. In some embodiments, the memory array 52 is embedded in another device, such as a logic die. In such embodiments, the substrate 102 may be omitted or may be an underlying layer, such as an underlying dielectric layer, an underlying semiconductor substrate, or the like.FIG. 19 is a cross-sectional view of a semiconductor device 200 according to some embodiments. FIG. 19 is a simplified view and some features are omitted for clarity of illustration. The semiconductor device 200 includes a logic region 200L and a memory region 200M. Memory devices (e.g., flash memory) are formed in the memory region 200M, and logic devices (e.g., logic circuits) are formed in the logic region 200L. For example, a memory array 52 (see FIG. 1 ) may be formed in the memory region 200M, and the row decoder 54 and the column decoder 56 (see FIG. 1 ) may be formed in the logic region 200L. The memory region 200M may be disposed at an edge of the logic region 200L or the logic region 200L may surround the memory region 200M.The logic region 200L and the memory region 200M are formed over a same semiconductor substrate 202. The semiconductor substrate 202 may be silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. The semiconductor substrate 202 may include other semiconductor materials such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer substrates or gradient substrates, may also be used.Devices 204 are formed on the active surface of the semiconductor substrate 202. The devices 204 may be active devices or passive devices. For example, the electrical components may be transistors, diodes, capacitors, resistors, or the like, formed by any suitable formation method. The devices 204 are interconnected to form the memory devices and logic devices of the semiconductor device 200.One or more interlayer dielectric layer(s) (ILD) layers 206 are formed on the semiconductor substrate 202, and electrically conductive features, such as contact plugs 208, are electrically connected to the devices 204. The ILD layer(s) 206 may / may be formed of any suitable dielectric material, for example, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), or the like; nitride such as silicon nitride; or the like. The ILD layer(s) may / may be formed by any acceptable deposition process, such as spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), the like, or a combination thereof. The electrically conductive features in the ILD layer(s) may be formed by any suitable process, such as deposition, damascene (e.g., single damascene, dual damascene, etc.), the like, or combinations thereof.An interconnect structure 210 is formed over the semiconductor substrate 202. The interconnect structure 210 interconnects the devices 204 to form integrated circuits in each of the logic region 200L and the memory region 200M. The interconnect structure 210 includes a plurality of metallization layers M 1-M 5. Although five metallization layers are illustrated, it should be appreciated that more or fewer metallization layers may be included. Each of the metallization layers M 1-M 5 includes metallization structures in the dielectric layers. The metallization structures are connected to the devices 204 of the semiconductor substrate 202 and each include the metal lines L 1-L 5 and the metal vias V 1-V 5 formed in one or more inter-metal dielectric (IMD) layers. The interconnect structure 210 may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. In some embodiments, the contact plugs 208 are also part of the metallization structures, such as part of the lowermost layer of the metal vias V 1.In this embodiment, the memory array 52 is formed in the interconnect structure 210. The memory array 52 may be formed in any of the metallization layers M 1-M 5 and is illustrated as formed in an intermediate metallization layer M 4, although it may also be formed in lower metallization layers M 1-M 3 or an upper metallization layer M 5. The memory array 52 is electrically connected to the devices 204. In this embodiment, a metallization layer overlying the memory array 52 (e.g., metallization layer M 5) includes interconnects with the bit lines 144B and the source lines 144S. In another embodiment, a metallization layer underlying the memory array 52 (e.g., metallization layer M 3) includes interconnects with the bit lines 144B and the source lines 144S.In some embodiments, the interconnect structure 210 may be formed by first forming the layers underlying the memory array 52, e.g., metallization layers M 1-M 3. The memory array 52 may then be formed on the metallization layer M 3, wherein the substrate 102 is an etch stop layer on the IMD of the metallization layer M 3. After forming the memory array 52, the remainder of the metallization layer M 4 may be formed, such as by depositing and planarizing the IMD for the metallization layer M 4 and then forming the metal lines M 4 and the metal vias M 4. The layers (if present) overlying the memory array 52, e.g., metallization layer M 5, may then be formed.Embodiments may achieve advantages. Each wordline 112 may be formed with a fin-like structure by laterally recessing the dielectric layers 106 prior to forming the film stacks for the TFTs 68. The wordlines 112 having fin-like structures include three-dimensional channel regions 124C. Forming the TFTs 68 with three-dimensional channel regions may allow the performance of the TFTs 68 to be improved. For example, three-dimensional channel regions may produce larger electric fields with lower gate voltages than planar channel regions. Flash memory arrays can thus be formed that are suitable for applications that require high performance memories (e.g., artificial intelligence, high performance computing, etc.). Further, forming memory arrays with three-dimensional channel regions may allow the average size of devices (e.g., TFTs) in the memory arrays to be reduced while the channel regions maintain sufficient performance. The density of flash memories can thus be improved.In an embodiment, a method includes: forming a wordline between a pair of dielectric layers; recessing sidewalls of the dielectric layers from a sidewall of the wordline to expose a top surface and a bottom surface of the wordline; forming a tunnel strip on the sidewalls of the dielectric layers and the top surface, the bottom surface, and the sidewall of the wordline; forming a semiconductor strip on the tunnel strip; and forming a bitline and a source line contacting the semiconductor strip.In some embodiments, the method further comprises: forming a trench in a multilayer stack, the multilayer stack including the dielectric layers, wherein recessing the sidewalls of the dielectric layers expands the trench to form sidewall recesses, wherein the tunnel strip and the semiconductor strip extend into the sidewall recesses, respectively; and depositing a first isolation region in the trench and the sidewall recesses. In some embodiments of the method, forming the bit line and the source line includes: replacing a first portion of the first isolation region outside the sidewall recesses with a conductive line, a second portion of the first isolation region remaining in the sidewall recesses; and forming a second isolation region that divides the conductive line into the bit line and the source line. In some embodiments of the method, the multilayer stack further includes a sacrificial layer between the dielectric layers, and forming the wordline includes: replacing the sacrificial layer with the wordline. In some embodiments of the method, recessing the sidewalls of the dielectric layers includes: etching the dielectric layers with an etching process, the etching process removing a dielectric material of the dielectric layers at a faster rate than a conductive material of the wordline. In some embodiments of the method, the etching process reduces widths of the dielectric layers by 60% to 80%. In some embodiments of the method, the etching process includes wet etching performed with dilute hydrofluoric acid, the wet etching forming sidewall recesses, the sidewall recesses each having a depth in a range of 30 nm to 40 nm. In some embodiments of the method, the tunnel strip contacts the sidewalls of the dielectric layers and the top surface, the bottom surface, and the sidewall of the wordline. In some embodiments, the method further comprises: forming an isolation strip contacting the sidewalls of the dielectric layers and the top surface, the bottom surface, and the sidewall of the wordline, the isolation strip disposed between the tunnel strip and the wordline.In an embodiment, a device includes: a pair of dielectric layers; a word line between the dielectric layers, sidewalls of the dielectric layers being recessed from a sidewall of the word line; a tunnel strip on an upper surface of the word line, the sidewall of the word line, a lower surface of the word line, and the sidewalls of the dielectric layers; a semiconductor strip on the tunnel strip; a bit line contacting a sidewall of the semiconductor strip; and a source line contacting the sidewall of the semiconductor strip.In some embodiments, the apparatus further comprises: an isolation region on the semiconductor strip, wherein the bit line and the source line each extend through the isolation region, wherein a first portion of the isolation region is disposed between the semiconductor strip and each of the bit line and the source line. In some embodiments of the device, the sidewall of the wordline forms acute angles with each of the top surface and the bottom surface of the wordline. In some embodiments of the device, the sidewall of the wordline forms obtuse angles with each of the top surface and the bottom surface of the wordline. In some embodiments of the device, the sidewall of the wordline forms right angles with each of the top surface and the bottom surface of the wordline. In some embodiments of the device, the word line has sharp corner shapes. In some embodiments of the device, the word line has shapes with rounded corners.In an embodiment, a device includes: a first wordline; a dielectric layer on the first wordline; a second wordline on the dielectric layer; a semiconductor strip including a first portion along a sidewall of the first wordline, a second portion along a sidewall of the dielectric layer, and a third portion along a sidewall of the second wordline; a bitline contacting the first portion and the third portion of the semiconductor strip; and an isolation region between the bitline and the second portion of the semiconductor strip.In some embodiments, the device further comprises: a tunnel strip between the semiconductor strip and each of the first word line and the second word line, the tunnel strip comprising a high-k ferroelectric material. In some embodiments, the device further comprises: a tunnel strip between the semiconductor strip and each of the first word line and the second word line, the tunnel strip comprising a low-k dielectric material. In some embodiments, the device further includes: an isolation strip between the bit line and each of the first word line and the second word line; and a tunnel strip between the isolation strip and the semiconductor strip.

Claims

A method comprising: forming a word line (62, 62B, 62T, 112) between a pair of dielectric layers (72, 106); recessing sidewalls of the dielectric layers (72, 106) from a sidewall of the word line (62, 62B, 62T, 112) to expose a top surface and a bottom surface of the word line (62, 62B, 62T, 112); forming a data storage layer (84, 122) on the sidewalls of the dielectric layers (72, 106) and the top surface, bottom surface and sidewall of the word line (62, 62B, 62T, 112); forming a semiconductor stripe (82, 124) on the data storage layer (84, 122); forming a bit line (64B, 144B) and a source line (64S, 144S) contacting the semiconductor strip (82, 124); forming a trench (110) in a multilayer stack (104), the multilayer stack (104) including the dielectric layers (72, 106), recessing the sidewalls of the dielectric layers (72, 106) expanding the trench (110) to form sidewall recesses (114), the data storage layer (84, 122) and the semiconductor strip (82, 124) respectively extending into the sidewall recesses (114); Depositing a first isolation region (126) in the trench (110) and the sidewall recesses (114), wherein forming the bit line (64B, 144B) and the source line (64S, 144S) comprises: replacing a first portion of the first isolation region (126) outside the sidewall recesses (114) with a conductive line (132), wherein a second portion of the first isolation region (126) remains in the sidewall recesses (114); and forming a second isolation region (142) dividing the conductive line (132) into the bit line (64B, 144B) and the source line (64S, 144S).The method of claim 1, wherein the multilayer stack (104) further comprises a sacrificial layer (108) between the dielectric layers (72, 106), wherein forming the wordline (62, 62B, 62T, 112) comprises: replacing the sacrificial layer (108) with the wordline (62, 62B, 62T, 112).The method of any preceding claim, wherein recessing the sidewalls of the dielectric layers (72, 106) comprises: etching the dielectric layers (72, 106) by an etching process, the etching process removing a dielectric material of the dielectric layers (72, 106) at a faster rate than a conductive material of the wordline (62, 62B, 62T, 112).The method of claim 3, wherein the etching process reduces widths of the dielectric layers (72, 106) by 60% to 80%.The method of claim 3 or 4, wherein the etching process comprises a wet etch performed with dilute hydrofluoric acid, the wet etch forming sidewall recesses, the sidewall recesses (114) each having a depth of 30 nm to 40 nm.The method of any preceding claim, wherein the data storage layer (84, 122) contacts the sidewalls of the dielectric layers (72, 106) and the top surface, bottom surface, and sidewall of the wordline (62, 62B, 62T, 112).The method of any preceding claim, further comprising: forming an isolation strip (174) contacting the sidewalls of the dielectric layers (72, 106) and the top surface, bottom surface, and sidewall of the wordline (62, 62B, 62T, 112), wherein the isolation strip (174) is disposed between the data storage layer (84, 122) and the wordline (62, 62B, 62T, 112).

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