Semiconductor devices and manufacturing processes for a semiconductor device

Abstract

Semiconductor device, exhibiting: - a semiconductor substrate (51) of a first conductivity type in which a cell region (1), an interface region (2) surrounding the cell region (1), and a termination region (3) surrounding the interface region (2) are defined; and - an insulating film (10) arranged on a surface of the semiconductor substrate (51), where: - the insulating film (10) contains a first opening part area (10a1, 10a2) in at least one of the cell area (1) and the closure area (3) and a second opening part area (10b) in the interface area (2), wherein the second opening part area has an opening ratio that is less than an opening ratio of the first opening part area (10a1, 10a2), - the semiconductor device further features: - a first defect layer (7, 8) of a second conductivity type, which is arranged on the surface of the semiconductor substrate (51) below the first opening part region (10a1, 10a2); and - a second defect layer (9) of the second conductivity type, which has a defect concentration that is lower than a defect concentration of the first defect layer (7, 8), and is arranged on the surface of the semiconductor substrate (51) below the second opening part region (10b), and - the second defect layer (9) is arranged continuously across sub-areas under each of a plurality of second opening sub-areas (10b).

Description

BACKGROUND OF THE INVENTION Area of ​​the invention

[0001] The present invention relates to semiconductor devices and manufacturing methods for a semiconductor device. Description of the background technology

[0002] Regarding a semiconductor device, a configuration has been proposed that includes an impurity layer between a cell region and a termination region, exhibiting a lower impurity concentration than that of a subregion of the cell region on the termination region side (for example, published Japanese patent applications JP 2000-150 859 A and published Japanese patent application JP 2013-125 928 A). According to such a configuration containing the impurity layer, a positive voltage is less readily applied to a subregion between an anode and a cathode in the semiconductor device during recovery. Therefore, current concentration and heat generation induced during recovery in the subregion of the cell region on the termination region side can be reduced.

[0003] However, if the defect layer is added as above, there are problems such as the need for an additional mask and process, and increased manufacturing costs.

[0004] German patent application DE 10 2009 041 192 A1 discloses a semiconductor device comprising a semiconductor body with a front surface. Within the semiconductor body, an active cell region with a semiconductor device structure and a border region surrounding the active cell region are arranged. The front surface of the semiconductor body has a passivation layer over the border region and over the cell region. The passivation layer comprises a semiconducting insulating layer of a semiconducting material whose band gap is larger than that of the semiconductor body material.

[0005] German patent application DE 10 2011 083 230 A1 discloses a semiconductor device in which the storage of a carrier in a guard ring region is prevented. The semiconductor device comprises an IGBT cell with a base region and an emitter region, which are located in a - The IGBT cell consists of a drift layer and a p-collector layer located beneath the drift layer, with a buffer layer in between. A guard ring region surrounds the IGBT cell. The lower surface of the guard ring region has a mesa structure, which is provided by removing the collector layer.

[0006] Document US 2018 / 0233554A1 describes a semiconductor device comprising a semiconductor substrate with an active region and an edge termination region, a top electrode, an insulating layer with a contact hole arranged between the semiconductor substrate and the top electrode, a first-type conductivity drift region, a second-type conductivity base region, a second-type well region, and a second-type conductivity extension region extending from the base region toward the well region and separated from the top electrode by the insulating layer.where the sum of a first distance from an end section of the contact hole closer to the trough area to an end section of the extension area closer to the trough area and a second distance from the end section of the extension area closer to the trough area to the trough area is less than the thickness of the semiconductor substrate in the active region. SUMMARY

[0007] The present invention was made with regard to the problems described above and has the objective of providing a technology that can reduce the manufacturing costs of a semiconductor device.

[0008] The problem underlying the invention is solved according to the invention in a semiconductor device by the features of claim 1, in a semiconductor device by the features of claim 4, in a manufacturing method for a semiconductor device by the features of claim 7, and in a manufacturing method for a semiconductor device by the features of claim 8. Advantageous embodiments are the subject of the respective dependent claims.

[0009] The present invention relates to a semiconductor device. The semiconductor device comprises a semiconductor substrate of a first conductivity type and an insulating film. A cell region, an interface region surrounding the cell region, and a termination region surrounding the interface region are defined in the semiconductor substrate. The insulating film is arranged on a surface of the semiconductor substrate. The insulating film includes a first open-aperture region in at least one of the cell region and the termination region, and a second open-aperture region in the interface region. The second open-aperture region has an open-aperture ratio that is lower than the open-aperture ratio of the first open-aperture region. Furthermore, the semiconductor device comprises a first impurity layer of a second conductivity type and a second impurity layer of the second conductivity type.The first defect layer is located on the surface of the semiconductor substrate beneath the first opening region. The second defect layer has a defect concentration lower than that of the first defect layer and is also located on the surface of the semiconductor substrate beneath the second opening region.

[0010] According to one aspect of the present invention, the second defect layer is arranged continuously over sub-areas beneath each of a plurality of second opening sub-areas.

[0011] According to another aspect of the present invention, the concentration of the second defect layer on the surface of the semiconductor substrate is higher than 0.001 times and lower than 0.5 times the concentration of the first defect layer on the surface of the semiconductor substrate.

[0012] The manufacturing costs of the semiconductor device can be reduced.

[0013] These and other tasks, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when it is carried out in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a top view illustrating a configuration of a related semiconductor device. Fig. Figure 2 is a cross-sectional diagram illustrating a configuration of the related semiconductor device. Fig. Figure 3 is a circuit diagram illustrating an equivalent circuit of the related semiconductor device during a recovery operation. Fig. Figure 4 is a graphical representation showing different waveforms of the related semiconductor device during a recovery operation. Fig. Figure 5 is a cross-sectional diagram illustrating a manufacturing process for the related semiconductor device. Fig. Figure 6 is a cross-sectional diagram illustrating a manufacturing process for the related semiconductor device. Fig. Figure 7 is a cross-sectional diagram illustrating a manufacturing process for the related semiconductor device. Fig. Figure 8 is a cross-sectional diagram illustrating a manufacturing process for the related semiconductor device. Fig. Figure 9 is a cross-sectional diagram illustrating a manufacturing process for the related semiconductor device. Fig. Figure 10 is a cross-sectional diagram illustrating a manufacturing process for the related semiconductor device. Fig. Figure 11 is a cross-sectional diagram illustrating a manufacturing process for the related semiconductor device. Fig. Figure 12 is a cross-sectional diagram illustrating a manufacturing process for the related semiconductor device. Fig. Figure 13 is a cross-sectional diagram illustrating a manufacturing process for the related semiconductor device. Fig. Figure 14 is a cross-sectional diagram illustrating a manufacturing process for the related semiconductor device. Fig. Figure 15 is a cross-sectional diagram illustrating a manufacturing process for the related semiconductor device. Fig. Figure 16 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a first embodiment. Fig. Figure 17 is a top view illustrating a configuration of a first opening part area and second opening part areas according to the first embodiment. Fig. Figure 18 is a cross-sectional diagram illustrating a manufacturing process for the semiconductor device according to the first embodiment. Fig. Figure 19 is a cross-sectional diagram illustrating a manufacturing process for the semiconductor device according to the first embodiment. Fig. Figure 20 is a cross-sectional diagram illustrating a manufacturing process for the semiconductor device according to the first embodiment. Fig. Figure 21 is a cross-sectional diagram illustrating a manufacturing process for the semiconductor device according to the first embodiment. Fig. Figure 22 is a cross-sectional diagram illustrating a manufacturing process for the semiconductor device according to the first embodiment. Fig. Figure 23 is a top view illustrating a configuration of a first opening part area and second opening part areas according to a first modification. Fig. Figure 24 is a top view illustrating a configuration of first opening part areas and second opening part areas according to the first modification. Fig. Figure 25 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a second modification. Fig. Figure 26 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a second embodiment. Fig. Figure 27 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a third embodiment. DESCRIPTION OF PREFERRED EXECUTION FORMS<Verwandte Halbleitervorrichtung>

[0014] Before describing a semiconductor device according to embodiments of the present invention, a related semiconductor device (hereinafter referred to as the "related semiconductor device") will first be described. The following description is given by taking an example of a configuration in which a first conductivity type is an N-type and a second conductivity type is a P-type. However, this is not limiting, and the first conductivity type may be a P-type and the second conductivity type may be an N-type.

[0015] Fig. Figure 1 is a top view illustrating a configuration of a related semiconductor device. As shown in Fig. As illustrated in Figure 1, the related semiconductor device comprises an N-type semiconductor substrate 51. The semiconductor substrate 51 can consist of a general semiconductor wafer or of an epitaxial growth layer.

[0016] In the semiconductor substrate 51, a cell subregion 1, an interface subregion 2, and a termination subregion 3 are defined. In a top view, interface subregion 2 is adjacent to and surrounds cell subregion 1, and termination subregion 3 is adjacent to and surrounds interface subregion 2. For example, a semiconductor switching element with an embedded diode (not shown) and / or a diode are arranged in cell subregion 1. The following description uses an example configuration in which a semiconductor switching element with an embedded diode is arranged in cell subregion 1.In such a configuration, cell part 1 conducts electricity when the semiconductor switching element is switched on, and termination part 3 holds a breakdown voltage when the semiconductor switching element is switched off.

[0017] Fig. 2 is along line AA' of Fig. 1 Cross-sectional diagram taken. The related semiconductor device comprises a drift layer 6, an anode layer 7, guide ring layers 8, a load resistance layer 9, an insulating film 10, a front surface electrode 11, a conductive termination film 12, a semi-insulating film 13, a buffer layer 14, an (N+) layer 15 and a rear surface electrode 16.

[0018] In the example of Fig. 2 The drift layer 6, apart from the anode layer 7, the guide ring layers 8, the load resistance layer 9, the buffer layer 14 and the (N+) layer 15, is a sub-area of ​​the semiconductor substrate 51 of the N type.

[0019] The insulating film 10 is, for example, an oxide film and is arranged on a surface of the semiconductor substrate 51. The insulating film 10 contains a first opening region in at least one of the cell region 1 and the termination region 3, and a first defect layer of the (P+) type is arranged in a surface of the semiconductor substrate 51 below the first opening region.

[0020] The following describes an example in which the first opening part regions are arranged in both the cell part region 1 and the closure part region 3. Also described is an example in which the first impurity layer of the (P+) type is each of the anode layer 7 arranged under a first opening part region 10a1 of the cell part region 1 and of the guide ring layers 8 arranged under first opening part regions 10a2 of the closure part region 3, and wherein a plurality of guide ring layers 8 is arranged under a plurality of the first opening part regions 10a2 of the closure part region 3.

[0021] The front surface electrode 11, which is a conductive film, is arranged on the insulating film 10 and is connected to the anode layer 7 via the first opening section 10a1. The conductive termination film 12, which is a conductive film, is arranged on the insulating film 10 and is connected to the guide ring layers 8 via the first opening sections 10a2.

[0022] The semi-insulating film 13 is arranged on a portion of the front surface electrode 11 on the side of the termination portion 3, the conductive termination film 12, and the insulating film 10. For example, the semi-insulating film 13 is a composite film containing a compound of elements of the semiconductor substrate 51 and an insulator, or an organic semiconductor film.

[0023] The buffer layer 14 is an N-type impurity layer with an impurity concentration higher than that of the drift layer 6 (semiconductor substrate 51) and is located on one side of a back surface on the semiconductor substrate 51. The (N+) layer 15 is an (N+)-type impurity layer with an impurity concentration higher than that of the drift layer 6 and the buffer layer 14 and is further located on the back surface of the semiconductor substrate 51 on the buffer layer 14. The back surface electrode 16 is located on a back surface of the (N+) layer 15.

[0024] Fig. Figure 3 is a circuit diagram illustrating an equivalent circuit of the related semiconductor device during a recovery operation. A semiconductor switching element 61 is located in cell subregion 1, and a diode 62 is located in cell subregion 1. An anode of the diode 62 corresponds to the front surface electrode 11, and a cathode of the diode 62 corresponds to the rear surface electrode 16. A parasitic inductance L s The circuit is connected between the diode 62 and the semiconductor switching element 61, and a load inductance L. m is connected in parallel to diode 62. A gate resistor R g is connected between the semiconductor switching element 61 and an AC power supply 63. Vcc is, for example, 1800 V. The temperature is, for example, 423 K. A gate voltage ranges, for example, from -15 V to 15 V. The parasitic inductance L sThe voltage of the circuit is, for example, 2.47 µH.

[0025] When the semiconductor switching element 61 of cell section 1 is switched on, carriers are stored in cell section 1 and termination section 3. When the semiconductor switching element 61 is in a recovery state, a positive voltage is also applied between the front surface electrode 11, which serves as the anode, and the rear surface electrode 16, which serves as the cathode.

[0026] Fig. Figure 4 is a graphical representation showing a current waveform (Jf: solid line) and a voltage waveform (Vka: dashed line) of the related semiconductor device during a recovery operation. During a recovery operation (T1 to T2), diode 62 is in a state of high reverse current, high voltage, and high dl / dt. Consequently, currents flow as indicated by the arrows of Fig. As indicated in 2, internal currents flow towards the anode side. In particular, internal currents from the termination section 3 concentrate on a contact section of the cell section 1 on the termination side (a section indicated by the dashed circle of Fig. 2 is indicated), and thus heat is generated in this sub-area.

[0027] In the related semiconductor device, the load-resistance layer 9 is arranged to reduce this heat generation. The load-resistance layer 9 is a P-type defect layer exhibiting a defect concentration lower than that of the anode layer 7 and the guide ring layers 8, and is located in the interface subregion 2. Note that, as in Fig. As illustrated in Figure 2, in the related semiconductor device, the entire upper surface of the load-resistance layer 9 is covered by the insulating film 10. Furthermore, the load-resistance layer 9 is connected to and located between the anode layer 7 and the guide ring layer 8, and a lower end of the load-resistance layer 9 is located above the lower ends of the anode layer 7 and the guide ring layer 8.

[0028] The load resistance layer 9, configured as described above, acts as a resistor (load resistance) for internal currents during recovery. Therefore, internal currents and heat generation can be reduced. The lower the concentration of load resistance layer 9, the higher its load resistance value. Consequently, the ability to interrupt a recovery process to reduce internal currents can be enhanced without increasing the chip size. <herstellungsverfahren>

[0029] Next, a manufacturing process for the related semiconductor device will be described. Fig. 5 to Fig. Figure 15 each represents a cross-sectional diagram illustrating a manufacturing process for the related semiconductor device.

[0030] First, as in Fig. Figure 5 illustrates the preparation of the semiconductor substrate 51. As shown in Figure 5. Fig. As illustrated in Figure 6, an insulating film 21 is then formed on a surface of the semiconductor substrate 51. Formation methods for the insulating film 21 include, for example, heating the semiconductor substrate 51, deposition or coating on the semiconductor substrate 51, or the like.

[0031] As in Fig. As illustrated in Figure 7, photolithography and etching are then performed on the insulating film 21, thereby creating a structure. In this way, the first opening regions 10a1 and 10a2 are formed in the insulating film 21 of cell section 1 and closure region 3, exposing the semiconductor substrate 51. As shown in Fig. As illustrated in Figure 8, defects 22 of the P-type are then injected into the semiconductor substrate 51 through the first opening part regions 10a1 and 10a2 at a relatively high concentration.

[0032] As in Fig. As illustrated in Figure 9, the injected defects 22 are activated next. In this way, the anode layer 7 is formed under the first opening section 10a1, and the guide ring layers 8 are formed under the first opening section 10a2. Note that due to the temperature during this activation, bottom sections of the first opening sections 10a1 and 10a2 are oxidized, and an insulating film 23 is formed on these bottom sections.

[0033] Then, as in Fig. As illustrated in Figure 10, photolithography and etching are performed on the insulating film 21, thereby forming an opening portion 24 in the insulating film 21 of the interface portion 2, exposing the semiconductor substrate 51. As shown in Fig. As illustrated in Figure 11, the opening section 24 then contains defects 25 of the P-type with a lower concentration than the injection concentration of Fig. 8 injected into the semiconductor substrate 51.

[0034] As in Fig. As illustrated in Figure 12, the injected defects 25 are then activated. In this way, the load-resistant layer 9 is formed under the opening section 24. Note that due to the temperature during this activation, the bottom section of the opening section 24 is oxidized and an insulating film 26 is formed on the bottom section.

[0035] As in Fig. As illustrated in 13, the insulating film 23 is then removed from the bottom part areas of the first opening part areas 10a1 and 10a2 by a process of Fig. The mask used is number 7. In this way, the insulation film is 10 of Fig. 2 trained. As in Fig. As illustrated in Figure 14, the front surface electrode 11 and the conductive finishing film 12 are then selectively formed on the anode layer 7 and the guide ring layers 8, respectively, and, as shown in Fig. As illustrated in Figure 15, the semi-insulating film 13 is selectively formed. The buffer layer 14, the (N+) layer 15, and the back surface electrode 16 are then formed on the back surface of the semiconductor substrate 51. Thus, the related semiconductor device of Fig. 2 completed.

[0036] Furthermore, in order to form the load-resistance layer 9 in the manufacturing process of the related semiconductor device, a Fig. 10 used dedicated masks and dedicated processes in the injection process of the defects 25 of Fig. 11 and the activation process of Fig. 12 are required. Consequently, there is a problem that this causes an increase in manufacturing costs. In light of this, this problem can be solved in the embodiments of the present invention described below. <Erste Ausführungsform>

[0037] Fig. Figure 16 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a first embodiment of the present invention. The cross-sectional diagram of Fig. 16 corresponds to the cross-sectional diagram of Fig. 2. In the following, components according to the first embodiment that are identical or similar to the components described above will be designated by the same or similar reference numerals, and different components will be described predominantly.

[0038] As in Fig. As illustrated in Figure 16, the insulating film 10 according to the first embodiment not only contains the first opening part regions 10a1 and 10a2, but also contains a plurality of second opening part regions 10b in the interface part region 2, each of which has an opening ratio that is less than that of each of the first opening part regions 10a1 and 10a2. Here, the opening ratio refers to a ratio of an opening part region (of the first opening part region or of the second opening part region) per unit area and is a value obtained by dividing the total area of ​​an opening part region by the total area of ​​the insulating film 10 and the opening part region.

[0039] Fig. Figure 17 is a top view illustrating the first opening section 10a1 and the second opening sections 10b. Note that the first opening section 10a2 is essentially the same as the first opening section 10a1, and the same applies in the following. In the example of Fig. 17. In particular, the first opening part area 10a1 has no pattern, whereas the second opening part areas 10b have a striped pattern. Consequently, each of the plurality of second opening part areas 10b has a lower opening ratio than each of the first opening part areas 10a1 and 10a2.

[0040] The load-resistance layer 9 according to the first embodiment is a second impurity layer of the P-type with an impurity concentration that, as in the load-resistance layer 9 of the related semiconductor device, is lower than that of the anode layer 7 and the guide ring layers 8. In the first embodiment, the concentration of the anode layer 7 on a surface of the semiconductor substrate 51 is 10 16 up to 10 18 per cm -3 , and a concentration of the load-resistance layer 9 on a surface of the semiconductor substrate 51 is 10 14 up to 10 16 per cm -3 Note that it is preferred that the concentration of the load-resisting layer 9 on a surface of the semiconductor substrate 51 is higher than 0.001 times and lower than 0.5 times the concentration of the anode layer 7 on a surface of the semiconductor substrate 51.

[0041] As in Fig. As illustrated in Figure 16, the load-resistance layer 9 according to the first embodiment is furthermore arranged in a surface of the semiconductor substrate 51 across positions under each of the plurality of second opening part regions 10b. The semi-insulating film 13 is further connected to the front surface electrode 11 and the conductive termination film 12 and is connected to the load-resistance layer 9 through the second opening part regions 10b. <herstellungsverfahren>

[0042] Next, a manufacturing process for the semiconductor device according to the first embodiment is described. Fig. 18 to Fig. Figures 22 are each a cross-sectional diagram illustrating a manufacturing process for the semiconductor device according to the first embodiment.

[0043] As in the case of the related semiconductor device, the semiconductor substrate 51 is prepared first ( Fig. 5) and the insulating film 21 is formed on a surface of the semiconductor substrate 51 ( Fig. 6). As in Fig. As illustrated in Figure 18, photolithography and etching are then performed, forming the first opening part regions 10a1 and 10a2, which expose the semiconductor substrate 51 in the insulating film 21 of cell part region 1 and the end part region 3, and forming the second opening part regions 10b, which expose the semiconductor substrate 51 in the insulating film 21 of the interface part region 2. In this way, the insulating film 10 of Fig. 16 essentially formed.

[0044] Next, as in Fig. As illustrated in Figure 19, P-type defects 32 are injected into the semiconductor substrate 51 through the first opening regions 10a1 and 10a2 at a relatively high concentration. Note that, since the second opening regions 10b have an opening ratio that is lower than that of the first opening regions 10a1 and 10a2, the defects 32 reach the semiconductor substrate less readily under the second opening regions 10b. Therefore, when an injection device applies the P-type defects 32 uniformly, the P-type defects 32 are injected into the semiconductor substrate 51 under the first opening regions 10a1 and 10a2 at a relatively high concentration, whereas the P-type defects 32 are injected into the semiconductor substrate 51 under the second opening regions 10b at a lower concentration than the concentration shown above.

[0045] As in Fig. As illustrated in Figure 20, the injected defects 32 are then activated. In this way, the anode layer 7 is formed under the first opening part region 10a1, the guide ring layers 8 are formed under the first opening part regions 10a2, and the load resistance layer 9 is formed under the second opening part regions 10b. Note that an insulating film (not shown) that forms on the bottom part regions of the first opening part regions 10a1 and 10a2 and the second opening part regions 10b due to the temperature during activation is removed by a process of Fig. 18 masks are used.

[0046] As in Fig. As illustrated in Figure 21, the front surface electrode 11 and the conductive finishing film 12 are next selectively formed on the anode layer 7 and the guide ring layers 8, respectively, and, as shown in Fig. As illustrated in Figure 22, the semi-insulating film 13 is selectively formed. The buffer layer 14, the (N+) layer 15, and the back surface electrode 16 are then formed on the back surface of the semiconductor substrate 51. Thus, the semiconductor device of Fig. 16 completed. <Overview of the first embodiment>

[0047] According to the semiconductor device of the first embodiment as described above, a dedicated mask and dedicated processes for forming the load-resistance layer 9, which are required in the fabrication of the related semiconductor device, are not necessary. Therefore, the manufacturing costs of the semiconductor device can be reduced.

[0048] Note that in the configuration where the semiconductor substrate 51 (load resistance layer 9) is exposed in the second opening part regions 10b, impurities can penetrate the semiconductor substrate 51 and degrade the device's characteristics. Furthermore, due to the influence of an external electrical charge in an application environment, the surface of the semiconductor substrate 51 can become charged by an oxide film, and the long-term reliability of the semiconductor device can be impaired.

[0049] In light of this, in the first embodiment, the second opening portions 10b are covered by the semi-insulating film 13. Therefore, a deterioration of the device's characteristics due to impurities is less likely to occur. Furthermore, the semi-insulating film 13 exhibits transient conduction characteristics of an electric charge, and thus an electric charge induced by an external influence flows due to this transient conduction. As a result, a local anomaly in the potential distribution due to an external influence is less likely to occur, and thus long-term reliability can be increased. <Erste Modifikation>

[0050] In the first embodiment, an example of the first opening part area 10a1 and the second opening part areas 10b is shown in Fig. 17 illustrates. However, the shapes of the second opening sub-areas 10b and the first opening sub-areas 10a1 and 10a2 are not limited to those shown in Fig. 17 are illustrated, as long as the opening ratio of the second opening part areas 10b is less than the opening ratio of each of the first opening part areas 10a1 and 10a2. For example, as in Fig. As illustrated in Figure 23, the first opening sub-area 10a1 may, in particular, have no structure, whereas the second opening sub-areas 10b may have a dotted structure. Furthermore, for example, as shown in Figure 23, the first opening sub-areas 10a1 may have no structure. Fig. Figure 24 illustrates that the first opening sections 10a1 may have a striped structure and the second opening sections 10b may have a dotted structure.

[0051] Although an illustration has been omitted, the first opening sections 10a1 can also have a striped structure, and the second opening sections 10b can have a striped structure of a different size compared to the striped structure of the first opening sections 10a1. Alternatively, the first opening sections 10a1 can have a honeycomb structure, and the second opening sections 10b can have a honeycomb structure of a different size and density compared to the honeycomb structure of the first opening sections 10a1. Note that in the examples of the Fig. 17, Fig. 23 and Fig. 24 each of the first opening part areas 10a1 and the second opening part areas 10b in the insulating film 10 are uniformly arranged, but may be locally uneven.

[0052] As described above, by controlling the opening ratio of the second opening part regions 10b, the impurity concentration of the load resistance layer 9 can be controlled, and thus the ability to interrupt recovery can be controlled. In this way, a semiconductor device with a suitable ability to interrupt recovery can be realized. Note that the above first modification can also be used similarly for various other configurations than the first embodiment. <Zweite Modifikation>

[0053] The semiconductor device according to the first embodiment contains the conductive termination film 12 ( Fig. 16). As in Fig. As illustrated in Figure 25, the semiconductor device may not include the conductive termination film 12. In this case, the semi-insulating film 13 is connected to the front surface electrode 11 and is connected to each of the guide ring layers 8 and the load-resisting layer 9 via the first opening part regions 10a2 and the second opening part regions 10b. Effects similar to those of the first embodiment can also be obtained with such a configuration. Note that the second modification described above can be used similarly for various other configurations besides the first embodiment. <Zweite Ausführungsform>

[0054] Fig. Figure 26 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a second embodiment of the present invention. The cross-sectional diagram of Fig. 26 corresponds to the cross-sectional diagram of Fig. 16. In the following, components of the second embodiment that are the same as or similar to the components described above are designated by the same or similar reference numerals, and different components are predominantly described.

[0055] As in Fig. As illustrated in 26, the semiconductor device according to the second embodiment has a configuration in which the configuration ( Fig. 16) a (P+) layer 17 is added to the semiconductor device according to the first embodiment.

[0056] The (N+) layer 15 is a third defect layer of the (N+) type with a defect concentration higher than that of the semiconductor substrate 51. In the second embodiment, the (N+) layer 15 is arranged on the back surface of the semiconductor substrate 51 at the interface sub-region 2, the cell sub-region 1, and a corresponding sub-region which is a sub-region of the termination region 3, corresponding to a guide ring layer 8a that is closest to the interface sub-region 2.

[0057] The (P+) layer 17 is a fourth defect layer of the (P+) type. The (P+) layer 17 is located on the back surface of the semiconductor substrate 51 at a position of the termination region 3, with the exception of the corresponding subregion mentioned above.

[0058] According to the semiconductor device of the second embodiment, which is configured as described above, a reduction of currents flowing towards the anode side during a recovery from the termination part region 3, i.e., a capability to interrupt a recovery, can be further increased. <Dritte Ausführungsform>

[0059] Fig. Figure 27 is a cross-sectional diagram illustrating a configuration of a semiconductor device according to a third embodiment of the present invention. The cross-sectional diagram of Fig. 27 corresponds to the cross-sectional diagram of Fig. 16. In the following, components according to the third embodiment that are the same as or similar to the components described above will be referred to by the same or similar reference numerals, and different components will be described predominantly.

[0060] As in Fig. As illustrated in 27, the semiconductor device according to the third embodiment has a configuration in which the configuration ( Fig. 16) a lifetime killer level 18 is added to the semiconductor device according to the first embodiment. Specifically, the semiconductor substrate 51 contains the lifetime killer level 18 in the termination region 3. Note that, for example, the lifetime killer level 18 is formed by irradiation with electron beams, proton irradiation, diffusion of heavy metals, or the like.

[0061] According to the semiconductor device of the third embodiment, configured as described above, the carrier concentration of the termination region 3 can be reduced due to the lifetime killer layer 18. Therefore, the reduction of currents flowing towards the anode side during recovery from the termination region 3, i.e., the ability to interrupt recovery, can be further increased.< / herstellungsverfahren> < / herstellungsverfahren>

Claims

[1] Semiconductor device, exhibiting: - a semiconductor substrate (51) of a first conductivity type in which a cell region (1), an interface region (2) surrounding the cell region (1), and a termination region (3) surrounding the interface region (2) are defined; and - an insulating film (10) arranged on a surface of the semiconductor substrate (51), where: - the insulating film (10) contains a first opening part area (10a1, 10a2) in at least one of the cell area (1) and the closure area (3) and a second opening part area (10b) in the interface area (2), wherein the second opening part area has an opening ratio that is less than an opening ratio of the first opening part area (10a1, 10a2), - the semiconductor device further features: - a first defect layer (7, 8) of a second conductivity type, which is arranged on the surface of the semiconductor substrate (51) below the first opening part region (10a1, 10a2); and - a second defect layer (9) of the second conductivity type, which has a defect concentration that is lower than a defect concentration of the first defect layer (7, 8), and is arranged on the surface of the semiconductor substrate (51) below the second opening part region (10b), and - the second defect layer (9) is arranged continuously across sub-areas under each of a plurality of second opening sub-areas (10b). [2] Semiconductor device according to claim 1, wherein: - the first defect layer (7, 8) comprises an anode layer (7) arranged below the first opening part region (10a1) of the cell region (1), and a guide ring layer (8) arranged below the first opening part region (10a2) of the termination region (3), and - the second defect layer (9) comprises a load resistance layer (9). [3] Semiconductor device according to claim 1 or 2, further comprising: - a conductive film (11, 12) arranged on the insulating film (10) and connected to the first defect layer (7, 8) through the first opening part region (10a1, 10a2); and - a semi-insulating film (13) connected to the conductive film (11, 12) and connected to the second defect layer (9) through the second opening part area (10b). [4] Semiconductor device, exhibiting: - a semiconductor substrate (51) of a first conductivity type in which a cell region (1), an interface region (2) surrounding the cell region (1), and a termination region (3) surrounding the interface region (2) are defined; and - an insulating film (10) arranged on a surface of the semiconductor substrate (51), where: - the insulating film (10) contains a first opening part area (10a1, 10a2) in at least one of the cell area (1) and the closure area (3) and a second opening part area (10b) in the interface area (2), wherein the second opening part area has an opening ratio that is less than an opening ratio of the first opening part area (10a1, 10a2), - the semiconductor device further features: - a first defect layer (7, 8) of a second conductivity type, which is arranged on the surface of the semiconductor substrate (51) below the first opening part region (10a1, 10a2); and - a second defect layer (9) of the second conductivity type, which has a defect concentration that is lower than a defect concentration of the first defect layer (7, 8), and is arranged on the surface of the semiconductor substrate (51) below the second opening part region (10b), and - a concentration of the second impurity layer (9) on the surface of the semiconductor substrate (51) is higher than 0.001 times and lower than 0.5 times a concentration of the first impurity layer (7) on the surface of the semiconductor substrate (51). [5] Semiconductor device according to claim 2, wherein: - a plurality of the guide ring layers (8) is arranged under a plurality of the first opening part areas (10a2) of the closing area (3), and - the semiconductor device further features: - a third defect layer (15) of the first conductivity type, having a defect concentration higher than the defect concentration of the semiconductor substrate (51), and arranged on a rear surface of the semiconductor substrate (51) at the interface region (2), the cell region (1) and a corresponding subregion, which is a subregion of the termination region (3) corresponding to one of the plurality of guide ring layers (8) closest to the interface region (2); and - a fourth defect layer (17) of the second conductivity type, which is arranged on the rear surface of the semiconductor substrate (51) at a position of the termination region (3) except for the corresponding subregion. [6] Semiconductor device according to one of the preceding claims, wherein the semiconductor substrate (51) contains a lifetime killer layer (18) in the termination region (3). [7] Manufacturing process for a semiconductor device, showing the steps: - Preparing a semiconductor substrate (51) of a first conductivity type in which a cell region (1), an interface region (2) surrounding the cell region (1) and a termination region (3) surrounding the interface region (2) are defined; - Forming an insulating film (10) on a surface of the semiconductor substrate (51), wherein the insulating film (10) comprises a first opening part region (10a1, 10a2) in at least one of the cell region (1) and the termination region (3) and a second opening part region (10b) in the interface region (2), wherein the second opening part region (10b) has an opening ratio that is less than an opening ratio of the first opening part region (10a1, 10a2); - Injecting defects of a second conductivity type through the first opening part region (10a1, 10a2) and the second opening part region (10b) into the semiconductor substrate (51); and - Activation of the injected impurities, thereby forming a first impurity layer (7, 8) of the second conductivity type, which is arranged on the surface of the semiconductor substrate (51) below the first opening part region (10a1, 10a2), and a second impurity layer (9) of the second conductivity type, which has an impurity concentration that is lower than an impurity concentration of the first impurity layer (7, 8), and is formed on the surface of the semiconductor substrate (51) below the second opening part region (10b), wherein the second defect layer (9) is arranged continuously over sub-areas under each of a plurality of second opening sub-areas (10b). [8] Manufacturing process for a semiconductor device, showing the steps: - Preparing a semiconductor substrate (51) of a first conductivity type in which a cell region (1), an interface region (2) surrounding the cell region (1) and a termination region (3) surrounding the interface region (2) are defined; - Forming an insulating film (10) on a surface of the semiconductor substrate (51), wherein the insulating film (10) comprises a first opening part region (10a1, 10a2) in at least one of the cell region (1) and the termination region (3) and a second opening part region (10b) in the interface region (2), wherein the second opening part region (10b) has an opening ratio that is less than an opening ratio of the first opening part region (10a1, 10a2); - Injecting defects of a second conductivity type through the first opening part region (10a1, 10a2) and the second opening part region (10b) into the semiconductor substrate (51); and - Activation of the injected impurities, thereby forming a first impurity layer (7, 8) of the second conductivity type, which is arranged on the surface of the semiconductor substrate (51) below the first opening part region (10a1, 10a2), and a second impurity layer (9) of the second conductivity type, which has an impurity concentration that is lower than an impurity concentration of the first impurity layer (7, 8), and is formed on the surface of the semiconductor substrate (51) below the second opening part region (10b), wherein a concentration of the second impurity layer (9) on the surface of the semiconductor substrate (51) is higher than 0.001 times and lower than 0.5 times a concentration of the first impurity layer (7) on the surface of the semiconductor substrate (51).

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