CIRCUIT STRUCTURE AND METHOD FOR STORAGE IN MEMORY WITH MEMORY CELL AND MRAM STACK

Abstract

Circuit structure (100) comprising: a latch (102) having a first inverter (104) configured to store a digital bit, wherein the latch (102) comprises a static random-access memory (SRAM) circuit with the first inverter (104) and a second inverter (106); a first diode (108) coupled to the first inverter (104) of the latch (102); a first magnetic random-access memory (MRAM) stack coupled to the first inverter (104) of the latch (102) via the first diode (108), wherein the first MRAM stack (110) comprises: a first layer (112) and a second layer (114), each having a corresponding magnetic moment, wherein the magnetic moment of the second layer (114) is adjustable between a parallel orientation and an antiparallel orientation with respect to the magnetic moment of the first layer (112). is;and a spin Hall electrode (120) directly coupled to the first MRAM stack (110); a second diode (138) coupled to the second inverter (106); a second MRAM stack (140) coupled via the second diode (138) to the second inverter (106) of the latch (102), wherein the second MRAM stack (140) comprises: a third layer (142), and a fourth layer (144) between the third layer (142) and the spin Hall electrode (120), wherein the third layer (142) and the fourth layer (144) each have a corresponding magnetic moment and the magnetic moment of the fourth layer (144) is adjustable between a parallel orientation and an antiparallel orientation with respect to the magnetic moment of the third layer (142); a first access transistor coupled to the first inverter (104) of the latch (102) and is coupled via the first diode (108) to the first layer (112) of the first MRAM stack (110);a second access transistor coupled to the second inverter (106) of the latch (102) and, via the second diode (138), to the third layer (142) of the second MRAM stack (140); and a word line (150) coupled to a gate terminal of the first access transistor and a gate terminal of the second access transistor.

Description

Technical FieldEmbodiments of the invention generally relate to integrated circuit (IC) memory devices. More specifically, embodiments of the invention provide a circuit structure and method for storing in a memory using a memory cell in combination with a magnetic random access memory (MRAM) stack.BackgroundRandom access memory (RAM) structures are important for the operation of integrated circuits (ICs). RAM refers to a collection of electrically powered memory cells that can be read and / or written in any order and that can provide storage of working data or machine code for a device. RAM is considered a "volatile" form of memory because power is needed to obtain the stored information. The two most common types of volatile RAM structures are a static random access memory (SRAM) and a dynamic random access memory (DRAM). Other types of RAM may include magnetic random access memory (MRAM), resistive random access memory (RRAM), and other memory elements having different operating principles and memory characteristics.When RAM is used in an intermittently operated device (i.e., a device that quickly switches between "off" and "on"), the RAM may be used in conjunction with various forms of non-volatile memory (NVM). However, the use of NVM may entail additional technical challenges. In an IC structure that includes both NVM and SRAM, a relatively high amount of energy may be required to implement a checkpoint operation for copying SRAM data to the NVM elements. In alternative schemes that use NVM instead of SRAM for intermittent power devices, NVM has lower access speeds than SRAM. Conventional approaches to de-sharpening these schemes, e.g. combining multiple types of RAM in a hybrid circuit, have proven unsatisfactory because sensitivity is poor and the power requirement remains well above that of pure SRAM configurations. Moreover, these solutions typically require a significant area on an IC chip.In this case, Zhou, Haochang et al., Design of an erasable spintronics memory based on current-path-dependent field-free spin orbit torque, AIP Advances, 2020, 10th Jg., No. 1 discloses a design for an erasable spintronic memory, Zhao, Weisheng et al., High speed, high stability and low power sensing amplifier for MTJ / CMOS hybrid logic circuits, IEEE Transactions on Magnetics, 2009, 45th Jg., No. 10, pp. 3784-3787, discloses a fast, stable and energy-efficient amplifier for MTJ / CMOS hybrid logic circuits, from Kang, Germany, Wang et al., Low store power high-speed high-density nonvolatile SRAM design with spin Hall effect-driven magnetic tunnel junctions, IEEE Transactions on Nanotechnology, 2016, 16th Jg., No. 1, pp. 148-154, disclose a design of a power saving, fast, and high density nonvolatile SRAM that utilizes the spin Hall effect. Furthermore, DE 600 25 152 T2 shows an MRAM memory that uses differential sense amplifiers to increase read accuracy and speed and CN106251896A shows a nonvolatile memory unit based on magnetic tunnel junctions (MTJs) and using the spin Hall effect.SummaryExamples provide a circuit structure, comprising: a latch having a first inverter configured to store a digital bit; a first diode coupled to the first inverter of the latch; a first magnetic random access memory (MRAM) stack coupled to the first inverter of the latch via the first diode, the first MRAM stack comprising: a first layer and a second layer each having a corresponding magnetic moment, the magnetic moment of the second layer being adjustable between a parallel orientation and an anti-parallel orientation with respect to the magnetic moment of the first layer; and a spin hall electrode directly connected to the first MRAM stack.Further examples provide a circuit structure comprising: a static random access memory (SRAM) cell having a first inverter configured to store a first logic voltage and a second inverter configured to store a second logic voltage; a first magnetic random access memory (MRAM) stack coupled to the first inverter of the SRAM cell via a first access transistor; a second MRAM stack coupled to the second inverter of the SRAM cell via a second access transistor, each of the first MRAM stack and the second MRAM stack comprising: a first layer and a second layer each having a corresponding magnetic moment, the magnetic moment of the second layer adjustable between a parallel orientation and an anti-parallel orientation with respect to the magnetic moment of the first layer in response to an applied voltage; and a spin hall electrode directly coupled to the first MRAM stack and the second MRAM stack.Further examples provide a method for recording data in an integrated circuit (IC) structure, the method comprising: providing a circuit structure comprising: a latch electrically coupled to another component of the IC structure and having a first inverter configured to store a digital bit, a first diode coupled to the first inverter, a first magnetic random access memory (MRAM) stack coupled to the first inverter of the latch via the first diode, the first MRAM stack comprising: a first layer having a first magnetic moment in a first orientation, and a second layer on the first layer having a second magnetic moment, that is adjustable between the first orientation and a second orientation opposite the first orientation in response to an applied voltage, and a spin hall electrode directly coupled to the first MRAM stack; transferring a read current via the first diode from the first inverter of the memory cell to the first MRAM stack; and transferring a write current via the spin hall electrode, wherein transferring the write current records the digital bit of the memory cell in the first MRAM stack.According to the invention, there is a structure according to claim 1 or 6 and a method according to claim 10.Brief Description of the DrawingsThese and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings which illustrate various embodiments of the invention, in which: FIG. 1 shows a schematic view of a circuit structure according to embodiments of the invention. FIG. 2 shows a schematic view of a circuit structure according to further embodiments of the invention. FIG. 3 shows a schematic view of a circuit structure according to still further embodiments of the invention. FIG. 4 shows a schematic view of a circuit structure having multiple memory cells and magnetic random access memory (MRAM) stacks, according to embodiments of the invention.It should be understood that the drawings of the invention are not necessarily to scale. The drawings are intended to represent only typical aspects of the invention and should therefore not be considered as limiting the scope of the invention. In the drawings, like reference numerals represent like elements.Detailed DescriptionIn the following description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific exemplary embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it is to be understood that other embodiments may be utilized and changes may be made without departing from the scope of the present teachings. The following description is, therefore, for illustrative purposes only.It will be understood that when an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it may be directly on the other element or intervening elements may also be present. In contrast, an element referred to as being "directly on" or "directly over" another element may not have intervening elements. When an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element or intervening elements may be present. In contrast, there are no intervening elements when an element is referred to as being "directly connected" or "directly coupled" to another element.Reference throughout the specification to "one embodiment" of the present invention and other variations thereof, it is intended that a particular feature, structure, characteristic, etc. described in connection with the embodiment be provided in at least one embodiment of the present invention. Therefore, the terms "in one embodiment," as well as any other variations that occur at various places in the specification, do not necessarily all refer to the same embodiment. It is to be understood that the use of " / ", "and / or" and "at least one of", e.g., in the cases of "A / B", "A and / or B" and "at least one of A and B", is intended to include the selection of only the first listed option (A) or the selection of only the second listed option (B) or the selection of both options (A and B). In another example, a corresponding formulation in the cases "A, B, and / or C" and "at least one of A, B, and C" is intended to include only the first listed option (A) or only the selection of the second listed option (B), or only the selection of the third listed option (C), or the selection of the first and second listed options (A and B), or the selection of the first and third listed options (A and C), or the selection of the second and third listed options (B and C), or the selection of all three options (A and B and C). This can easily be extended to any number of listed options.Embodiments of the invention relate to a circuit structure and a method thereof for recording data in an integrated circuit (IC) structure. Embodiments of the invention integrate multiple types of random access memory (RAM) to provide memory "checkpointing", i.e., the ability to store digital bits in a redundant, non-volatile memory element. Embodiments of the invention provide this capability while also maintaining lower operating energy and surface area than conventional memory structures. RAM refers to any type of memory cell that serves to temporarily store data. RAM may take a variety of forms, including static RAM ("SRAM") or dynamic RAM ("DRAM"). RAM may be implemented using a variety of circuit structures, electronic elements, and / or device architectures. The components of the RAM provide a memory cell capable of electronically storing data in the form of a binary digit, i.e., a recorded high or low voltage, to implement various types of logic. During operation, the memory cells in RAM must be configured so that writing information (i.e., storing high and low voltages) and reading information (i.e., identifying the stored voltage in a particular cell) is easily possible.Embodiments of the invention provide a circuit structure comprising a memory cell (e.g., a portion of the RAM) having a latch for storing a digital bit. A first diode may couple the first latch to a magnetic random access memory (MRAM) stack. The MRAM stack may be located outside the memory cell structure. The MRAM stack may include a first layer (sometimes referred to as a "solid layer") and a second layer (sometimes referred to as a "free layer"). The material composition of each layer may generate a magnetic field in a particular orientation, referred to as a "magnetic moment.". The magnetic moment of the first layer may be fixed in an orientation. The magnetic moment of the second layer may be adjusted between a parallel orientation and an anti-parallel orientation with respect to the magnetic orientation of the first layer. By transmitting a "write current" through a spin Hall electrode, a threshold voltage difference may form across the MRAM stack. The voltage difference across the MRAM stack may shift the magnetic orientation of the second layer between its parallel and anti-parallel states.Further, the use of an MRAM element having voltage controlled magnetic anisotropy (VCMA) may be employed to assist or prevent the spin Hall electrode's ability to change the magnetic orientation of the first layer. By using a voltage difference applied across the top and bottom electrodes of the MRAM element, the barrier to changing the orientation of the free layer can be increased (which makes switching / writing difficult) or decreased (which increases the ability to write / switch states).The structure may also include a spin Hall electrode directly coupled to the first MRAM stack. A "spin Hall electrode" refers to a conductive material capable of exhibiting the "spin Hall effect", i.e., the accumulation of "spin" (i.e., a torque shown by particles) on the side surfaces of a material when an electric current is passed through the material. Such materials may comprise metals having a density of at least about five grams per cubic centimeter (g / cm 3). Such metals are colloquially known as "heavy metals" and may include, without limitation, materials such as tantalum (Ta), osmium (Os), gold (Au), silver (Ag), cobalt (Co), etc. The spin Hall electrode material may be coupled to the first MRAM stack at one of its side surfaces, thereby generating a spin along the MRAM stack when currents flow through the spin Hall electrode. The accumulated spin may introduce energy into the second layer of the MRAM stack. Electrical currents transferred from the diode to the MRAM stack may form a magnetic tunnel junction when a current flows through the spin Hall electrode. The magnetic tunnel junction and the accumulated spin together selectively change the orientation of their magnetic moment between parallel and anti-parallel states during operation of the circuit. When the MRAM stack is in a parallel orientation, this may indicate a first digital bit (which may be represented as a "high" or "low" logic voltage). The MRAM stack in anti-parallel orientation may indicate a second, opposite digital bit and / or a logic voltage.Referring to FIG. 1, a circuit structure (hereinafter simply "structure") 100 according to various embodiments of the invention is illustrated. The structure 100 may include a latch 102, which may be embodied as an SRAM cell and / or any other memory structure now known or later developed. The latch 102 can be provided in particular in the form of a volatile memory cell. The latch 102 of the structure 100 may include a first inverter 104 and optionally a second inverter 106, which together store a digital bit in the form of a first logic voltage and a second logic voltage, respectively. A "latch" refers to an electrical data storage element formed of two cross-coupled inverting elements (e.g., a set of two transistors as shown in FIG. 1 ) and switchable between two stable states. The two stable states of each inverter 104, 106 may correspond to two logic voltages, each representing a "one" or "zero". The logic voltage of one or both inverters 104, 106 may correspond to a digital bit of "one" or "zero". Each inverter 104, 106 may be electrically coupled to ground GND. In this case, the digital bit stored in the latch 102 is cleared when electrically isolated from a power source.The structure 100 may include at least a first diode 108 electrically coupled to the first inverter 104. The first diode 108 may provide an electrical connection between the first inverter 104 and a first magnetic random access memory (MRAM) stack 110 via their opposing terminals. The first diode 108 may allow electrical current flow from the first inverter 104 to the first MRAM stack 110, but not in the opposite direction. In operation, the first MRAM stack 110 of the structure 100 may be used as a storage medium to replicate a digital bit previously stored in the first inverter 104. Such an operation may be referred to as checkpointing, and the MRAM stack 110 may function as a "backup" storage element for digital bits stored in the latch 102 of the fabric 100.For example, the first MRAM stack 110 may include a first layer 112 and a second layer 114 separated from each other by an insulator layer 116 therebetween. The first layer 112 may be referred to as a "solid layer" and the second layer 114 may be referred to as a "free layer.". The insulator layer 116 may be extremely thin (e.g., about ten angstroms), which may form a magnetic tunnel junction between the layers 112, 114, as described herein. Further, the size, shape, and composition of the layer 114 may be selected such that the second layer 114 exhibits a VCMA effect during operation. Each of the layers 112, 114 of the first MRAM stack 110 may be formed of one or more ferromagnetic metals, or more generally may comprise any material having a magnetic moment in a detectable orientation. At the time of manufacture, the first plate 112 may be formed as a permanent magnet set to a certain polarity, while the second plate 114 may have a different magnetization level. The degree of magnetization of the second plate 114 may be selected such that application of at least one threshold voltage to the first MRAM stack 110 re-aligns the magnetic field of the second plate 114. The realignment of the magnetic field of the second plate 114 may result from a magnetic tunnel junction forming along the insulator layer 116 when the threshold voltage is applied to the first MRAM stack 110. The two orientations of the magnetic moment of the second plate 114 may include a first orientation that is parallel to the first plate 112 (i.e., a "parallel orientation") and a second orientation that is oppositely oriented with respect to the first plate 112 (i.e., an "anti-parallel orientation"). During operation, each of the two magnetic orientations of the second plate 114 may correspond to a predetermined digital value (i.e., a "one" or "zero").The structure 100 may include additional components for writing data to and / or erasing data from the first MRAM stack 110. As shown, the first MRAM stack 110 may be directly coupled to a spin Hall electrode 120, e.g., by being formed directly thereon. The spin Hall electrode 120 described above may include metals having a density of at least about five grams per cubic centimeter (g / cm 3) e.g., one or more "heavy metals.". Regardless of the configuration, the composition of the spin Hall electrode 120 may accumulate a spin at its lateral edges when a write current I W is transmitted along the spin Hall electrode 120. The spin Hall electrode 120 may be electrically coupled to ground GND via a restore transistor 122. A gate terminal RG of the restore transistor 122 may control whether the spin hall electrode 120 is electrically coupled to ground GND, which in turn allows the first MRAM stack 110 to undergo a "checkpointing" or "restore" operation as described herein.The structure 100 comprises a set of memory access transistors MT1, MT2 for controlling read and write operations to enable the functions of a random access memory. A first memory access transistor MT 1 may be coupled to the first inverter 104, while a second memory access transistor MT 2 may be coupled to the second inverter 106. The first memory access transistor MT 1 may be coupled to a bit line 130 configured to have an adjustable voltage level, and the second memory access transistor MT 2 may be coupled to a bit line rail (bit line bar) 132, which may also be adjusted to an adjustable voltage. The bit line 130 and the bit line rail 132 may each be coupled to another component (hereinafter simply "component") 134, which represents one or more electrical circuits connected to the structure 100. The component 134 may represent any functional device including and / or connected to, for example, a power supply coupling, one or more digital logic circuits, one or more metallic wiring layers, and / or any other device configured to interact with the latch 102 of the structure 100.The bit line 130 and the bit line rail 132 may be electrically connected to other structures 100 and other latches 102, respectively, but such connections are omitted in FIG. 1 for clarity.To read the memory from the structure 100, the bit line 130 and the bit line rail 132 are precharged and brought to a high voltage. Then, the gates of the individual memory access transistors MT1, MT2 are turned on. The page with an internal node set to a "low" bit of data discharges faster. An amplifier circuit (not shown) coupled to structure 100 evaluates the voltage difference between 130 and 132 and the bottom side is considered zero if the difference exceeds a threshold. To store (checkpoint) data in the memory cell, a diode 108 is connected to the latch 102 as shown in FIG. 1. During checkpointing operation, access transistors MT1 and MT2 are turned off by setting a first word line 150 coupled to first memory access transistor MT1 and a second word line 152 coupled to second memory access transistor MT2 to a logic "low" voltage.In this phase, checkpoint operation may be implemented in two phases. First, the terminal RG is set to a low voltage, the line 124 to the voltage V 1 is set to a low voltage, and the line 126 to the voltage V 2 is set to a high voltage. In alternative embodiments, the same checkpointing operation can be implemented without a transistor coupled at its gate to the terminal RG, simply by setting the two voltages V 1, V 2 to ground and setting the voltage of the terminal SG to a high voltage. When the terminal SG is set to the high voltage, a high negative Iw is transmitted to the Hall electrode 120. By applying this current, the second layer 114 in the MRAM cell 110 is placed in its antiparallel state (e.g., representing a logic "1"). The second step of checkpoint includes setting the terminal SG to a low voltage, thereby reversing the voltage difference between V1 and V2 and setting it to a value that allows a smaller positive current Iw to flow through the spin Hall electrode 120. SG is again set to a high voltage and Iw is passed through the spin Hall electrode 120. At this stage, the MRAM stack 110 has a voltage difference between the first layer 112 and the second layer 114 (due to the insulating layer 116). The magnitude of this voltage difference (between 112 and 114) depends on the state of an internal node 160 between two transistors of the first inverter 104 in the latch 102. When node 160 is set to a low voltage, the resulting voltage difference causes the VCMA effect of MRAM stack 110 to lower the energy barrier for second layer 114 to change state. Current through the spin Hall electrode 120 induces spin Hall transfer to the second layer 114, thereby switching the magnetic state to its parallel state (e.g., corresponding to logic level "0") and storing the corresponding logic level. When the internal node 160 is set to a high voltage, the VCMA effect is not triggered and the second layer 114 would resist switching during application of the current Iw and remain in the anti-parallel state (e.g., logic "1" in this example). At this point, the terminal SG remains set to a low voltage.With continued reference to FIG. 1, structure 100 may also provide a restore operation in which data previously recorded in MRAM stacks 110 is restored in inverters 104, 106 of latch 102. Here, the bit line rail 132 is brought to a voltage level corresponding to the midpoint of the electrical resistance of the MRAM cells 110. The bit line 130 is accordingly set to a supply voltage (indicated by "Vdd"). At this point, memory access transistors MT1 and MT2 may be turned on via a high voltage applied across word lines 150, 152. The terminal SG is set to a low voltage, thereby disconnecting the leads 124 and 126 from the spin Hall electrode 120. The terminal RG is set high, thereby connecting the spin Hall electrode 120 to ground. At this point, current in bit line 130 flows through memory access transistor MT1, through diode 108, and through MRAM stack 110 to spin Hall electrode 120, and to ground. Depending on the electrical resistance of the MRAM stack 110, the voltage at the internal node 160 will be higher or lower than the voltage of the bit line rail 132. When the MRAM stack 110 is in the low-ohmic state (logic 0), the internal node 160 is pulled to a lower level than an internal node 162 for the second inverter 106. In this case, inverters 104, 106 interpret internal node 160 as "low" and node 162 for second latch 152 as "high". Conversely, if internal node 160 has a higher voltage than node 162, inverters 104, 106 interpret internal node 160 as "high" and node 162 as "low.". At this point, memory access transistors MT1, MT2 are turned off (setting word lines 150 and 152 to a low voltage) and line 120 is set to "floating" (i.e., turning off V1, V2).Referring to FIG. 2, further embodiments of the structure 100 may include multiple MRAM elements for selectively recording digital bits from both sides of the latch 102 by connecting to the first inverter 104 and the second inverter 106. Here, a second diode 138 may electrically couple the second inverter 106 to a second MRAM stack 140. The second MRAM stack 140, in turn, may be directly electrically coupled to another part of the spin Hall electrode 120. The second MRAM stack 140 may include a third layer 142, a fourth layer 144, and an intermediate insulator layer 146 in a similar arrangement to the first MRAM stack 110. Thus, the second MRAM stack 140 may store a digital bit therein based on the parallel or anti-parallel magnetic moment of the fourth layer 144. In this configuration, the second MRAM stack 140 may be electrically coupled to and capable of storing the logic voltage recorded in the second inverter 106.The second MRAM stack 140 may operate independently of the first MRAM stack 110 to store a logic voltage from the second inverter 106, respectively. Substantially the same process as described above with reference to FIG. 1 may be used to implement checkpointing operation in such a configuration. Due to the complementary nature of internal nodes 160 and 162, MRAM stacks 110 and 140 will store the logic values on each side of latch 102 and complement each other when checkpointing is complete, essentially as described above. In this manner, the logic levels in inverters 104, 106 in MRAM stacks 110, 140 are replicated instead of each MRAM stack 110, 140 being specific to the digital bit stored in latch 102.With continued reference to FIG. 2, a user may perform a restore operation or restore operation without the need for a reference voltage. An operator may pre-charge both the bit line 130 and the bit line rail 132 to a high voltage state to implement restore operation. Then, the word line 150 may also be set to a high voltage to allow access to the latch 102. In addition, the restore transistor 122 may be turned on (i.e., RG is set to a high voltage), thereby grounding the spin Hall electrode 120. At this point, current flows through bit line 130, through diode 108, and through MRAM stack 110, into spin Hall electrode 120, and to ground GND. Similarly, current also flows through bit line 132, through diode 138, through MRAM stack 140, into spin Hall electrode 120, and to ground GND. After these operations are completed, the MRAM stack 110 is in an opposite (i.e., higher or lower) ohmic state to the MRAM stack 140. This, in turn, results in internal node 160 being at the voltage level opposite node 162. This slope in the voltage between 160 and 162 is enhanced by the current flow in latch 102, which simulates the logic levels stored in MRAM cells 110 and 140.Referring to FIG. 3, further embodiments of the invention may structurally integrate the first diode 108 and / or the second diode 138 into other components, e.g., a first access transistor AT 1 and a second access transistor AT 2. In an electrical circuit, the channel region connecting the source of a transistor to the drain may operate as a diode when at least one threshold voltage is applied to the gate of the transistor. The first access transistor AT 1 may include a first diode 108 between its source and drain terminals such that the first diode 108 electrically couples the first inverter 104 to the first MRAM stack 110. The second access transistor AT2 may similarly include a second diode 138 between its source and drain terminals. Thus, the second diode of the second access transistor 138 may electrically couple the second inverter 106 to the second MRAM stack 140. Each access transistor AT 1, AT 2 may be coupled at its gate to a word line 150. The word line 150 may have a word line voltage V W which may be set between a high and a low value to enable or disable the current flow via the access transistor(s) AT 1, AT 2. When the current flow through the access transistors AT 1, AT 2 is activated, an operator of the structure 100 may selectively transmit a write current I W through the spin Hall electrode 120 to replicate data from the latch 102 into the MRAM stack / stacks 110, 140 (as described above with reference to FIG. 2 ). When the current flow through the access transistors AT 1, AT 2 is disabled, the MRAM stack / stacks 110, 140 may be electrically isolated from the latch 102 when data is written to or read from the first latch and / or the second inverter 104, 106.Referring to FIG. 4, embodiments of the invention may provide MRAM stacks 110, 140 to store data from multiple latches 102 using a spin Hall electrode 120. In such a configuration, the structure 100 may include a first latch 102A, a second latch 102B, and a third latch 102C. The first latch 102A may be coupled to the spin Hall electrode 120 via a first set of MRAM stacks 110A, 140A. Latches 102B, 102C may similarly be coupled to the spin Hall electrode 120 via respective sets of MRAM stacks (110B and 140B, 110C and 140C). The structure 100 may optionally include more or less than three latches 102, and three are shown only as an example in FIG. 4.Each latch 102A, 102B, 102C may be coupled to a corresponding component 134 (or alternatively, to the same component) to control the operation of latch(s) 102 in the same manner as described herein in FIGS. 1-3. By transferring the write current I W through the spin Hall electrode 120 while simultaneously applying a voltage to the word line 150, data in each latch 102A, 102B, 102C may be simultaneously replicated in each MRAM stack 110A, 140A, 110B, 140B, 110C, 140C. In further embodiments, the structure 100 may include multiple spin Hall electrodes 120 and word lines 150 each communicating with a single set of latches 102 and MRAM stacks 110, 140. In this case, an operator of the structure 100 may only select a set of latches 102 to store digital bits in the corresponding MRAM stack(s) 110, 140 by applying a voltage V W to the word line 150 and the write current I W to the spin Hall electrode 120.Embodiments of the invention provide various technical and commercial advantages, some of which are described herein as examples. As described herein, embodiments of structure 100 combine multiple forms of RAM (i.e., electrical and magnetic RAM) to replicate previously stored data with minimal prints at the surface and operating power of a device. The use of the spin hall electrode 120 also allows for the use of the same combination of elements for checkpointing data from the latch 102 into the MRAM stack / stacks 110, 140 and for recovering the checkpointed data in the latch 102 after a power cycle of a device. Embodiments of the invention may be readily incorporated into current circuit diagrams, e.g., by inserting MRAM stack(s) 110, 140 and spin Hall electrode 120 at the electrical connections to word line 150 where applicable, or otherwise near the location of an existing latch 102. The use of bistable MRAM stacks 110, 140 enables, in particular, an electrically recorded "zero" or "one" in the latch(s) 102 to be replaced as a parallel or antiparallel magnetic moment of the second layer 114 or the fourth layer 144 with little or no risk of error during checkpoint and restore operations.The above-described method is used in the manufacture of integrated circuit chips. The resulting integrated circuit chips may be sold by the manufacturer in the form of unprocessed wafers (i.e., as a single wafer with multiple bare chips), as a die, or in packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier with leads attached to a motherboard or other parent carrier) or in a multichip package (e.g., a ceramic carrier with surface interconnections and / or buried interconnections). In either case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, keyboard, or other input device, and a central processor.

Claims

A circuit structure (100) comprising: a latch (102) having a first inverter (104) and configured to store a digital bit, the latch (102) comprising a static random access memory (SRAM) circuit including the first inverter (104) and a second inverter (106); a first diode (108) coupled to the first inverter (104) of the latch (102); a first magnetic random access memory (MRAM) stack coupled to the first inverter (104) of the latch (102) via the first diode (108), the first MRAM stack (110) comprising: a first layer (112) and a second layer (114) each having a corresponding magnetic moment, the magnetic moment of the second layer (114) being adjustable between a parallel orientation and an anti-parallel orientation with respect to the magnetic moment of the first layer (112); and a spin hall electrode (120) directly coupled to the first MRAM stack (110); a second diode (138) coupled to the second inverter (106); a second MRAM stack (140) coupled to the second inverter (106) of the latch (102) via the second diode (138), the second MRAM stack (140) comprising: a third layer (142); and a fourth layer (144) between the third layer (142) and the spin hall electrode (120), wherein the third layer (142) and the fourth layer (144) each have a corresponding magnetic moment, and the magnetic moment of the fourth layer (144) is adjustable between a parallel orientation and an anti-parallel orientation with respect to the magnetic moment of the third layer (142); a first access transistor coupled to the first inverter (104) of the latch (102) and to the first layer (112) of the first MRAM stack (110) via the first diode (108); a second access transistor coupled to the second inverter (106) of the latch (102) and to the third layer (142) of the second MRAM stack (140) via the second diode (138); and a word line (150) coupled to a gate terminal of the first access transistor and a gate terminal of the second access transistor.The circuit structure (100) of claim 1, wherein a material composition of the second layer (114) is structured to adjust the magnetic moment in response to an applied voltage.The circuit structure (100) of claim 1, wherein the second layer (114) of the first MRAM stack (110) contacts and overlies the spin Hall electrode (120).The circuit structure (100) of claim 1, wherein the spin Hall electrode (120) comprises at least one metal having a density of at least about five grams per cubic centimeter (g / cm 3).The circuit structure (100) of claim 1, further comprising a restore transistor (122) electrically coupled between the spin hall electrode (120) and ground.A circuit structure (100) comprising a static random access memory (SRAM) cell having a first inverter configured to store a first logic voltage and a second inverter configured to store a second logic voltage; a first magnetic random access memory (MRAM) stack (110) coupled to the first inverter of the SRAM cell via a first access transistor; a second MRAM stack (140) coupled to the second inverter of the SRAM cell via a second access transistor, each of the first MRAM stack (110) and the second MRAM stack (140) comprising: a first layer (112) and a second layer (114) each having a corresponding magnetic moment, the magnetic moment of the second layer (114) being adjustable between a parallel orientation and an anti-parallel orientation with respect to the magnetic moment of the first layer (112) in response to an applied voltage; a spin hall electrode (120) directly coupled to the first MRAM stack (110) and the second MRAM stack (140); a word line (150) coupled to a gate terminal of the first access transistor and a gate terminal of the second access transistor, wherein the word line (150) selectively allows a current flow via the first access transistor and the second access transistor.The circuit structure (100) of claim 6, wherein both the first MRAM stack (110) and the second MRAM stack (140) contact and overlie the spin Hall electrode (120).The circuit structure (100) of claim 6, wherein the spin hall electrode (120) comprises at least one metal having a density of at least about five grams per cubic centimeter (g / cm 3).The circuit structure (100) of claim 6, further comprising a restore transistor (122) electrically coupled between the spin hall electrode (120) and ground.A method for recording data within an integrated circuit (IC) (100) (IC) structure, the method comprising: providing a circuit structure (100) comprising: a latch (102) electrically coupled to another component (134) of the IC structure (100) and having a first inverter (104) configured to store a digital bit, a first diode (108) coupled to the first inverter (104), a first magnetic random access memory (MRAM) stack coupled to the first inverter (104) of the latch via the first diode (108), the first MRAM stack (110) comprising: a first layer (112) having a first magnetic moment in a first orientation, and a second layer (114) on the first layer (112) having a second magnetic moment adjustable between the first orientation and a second orientation opposite the first orientation, and a spin hall electrode (120) directly coupled to the first MRAM stack (110); transferring a read current via the first diode (108) from the first inverter (104) of the memory cell to the first MRAM stack (110), wherein transferring the read current via the first diode (108) comprises applying a voltage to an access transistor coupled between the first inverter (104) of the memory cell and the first MRAM stack (110); transmitting a write current across the spin hall electrode (120), wherein transmitting the write current records the digital bit of the memory cell within the first MRAM stack (110).The method of claim 10, further comprising: electrically isolating the memory cell from the other component of the IC structure (100); and electrically coupling the spin Hall electrode (120) to ground, wherein electrically coupling the spin Hall electrode (120) to ground records the digital bit of the MRAM stack within the latch (102).The method of claim 10, further comprising transmitting a data stream to the first inverter (104) of the memory cell after transmitting the read current via the first diode (108).The method of claim 12, further comprising transmitting a reference current to a portion of the latch (102) while the read current is transmitted across the first diode (108).The method of claim 10, wherein the first MRAM stack (110) of the provided circuit is one of a plurality of MRAM stacks each coupled to the spin hall electrode (120) and a corresponding latch (102) of the memory cell, and wherein transmitting the write current records a plurality of digital bits from the plurality of latches (102) within the plurality of MRAM stacks.

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