Stacked multigate structure and its manufacturing process

Abstract

comprising a semiconductor device (200): a stack (204b) of first channel layers (208); a first S / D epitaxy feature (228S) and a second S / D epitaxy feature (228D) adjacent to respective opposite sides of at least a part of the first canal layers (208), wherein the first and the second S / D epitaxy feature (228S, 228D) have a first conductivity type; a stack (204a) of second channel layers (208) stacked over the first channel layers (208); a third S / D epitaxy feature (248S) and a fourth S / D epitaxy feature (248D) adjacent to respective opposite sides of at least a part of the second canal layers (208), wherein the third and fourth S / D epitaxy features (248S, 248D) exhibit a second conductivity type; and a dielectric insulating layer (242) arranged between the first channel layers (208) and the second channel layers (208), wherein the dielectric insulating layer (242) isolates both the third and the fourth S / D epitaxy feature (248S, 248D) from a bottommost channel layer of the second channel layers (208); wherein the total number of active channel layers (208) of the first channel layers (208) differs from that of the second channel layers (208).

Description

BACKGROUND

[0001] The integrated semiconductor circuit (semiconductor IC) industry has experienced exponential growth. Technological advances in IC materials and design have spawned generations of ICs, with each generation becoming smaller and more complex. Throughout IC evolution, functional density (i.e., the number of interconnected components per unit area) has generally increased, while geometric size (i.e., the smallest component (or trace) that can be manufactured) has decreased. This miniaturization process generally offers advantages by increasing production efficiency and the associated cost reduction. However, miniaturization has also increased the complexity of processing and manufacturing ICs.

[0002] As IC technologies evolve toward ever smaller technology nodes, multigate devices, for example, have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effects (SCEs). A multigate device generally refers to a device with a gate structure, or part thereof, that extends over more than one side of a channel region. Gate-all-around (GAA) transistors are examples of multigate devices that have become popular and promising candidates for high-power, low-leakage applications. The name GAA transistor derives from the gate structure, which can extend around the channel region, providing access to the stacked semiconductor channel layers on four sides.Compared to planar transistors, this configuration offers better channel control and drastically reduces SCEs (particularly by reducing leakage below the threshold). The channel area of ​​a GAA transistor is formed from stacked semiconductor channel layers, such as nanowires, nanosheets, other nanostructures, and / or other conceivable variations. The number of stacked semiconductor channel layers is selected based on the device performance, especially the current control capability of the transistors.

[0003] As the semiconductor industry continues to advance into sub-10-nanometer technology process nodes in the pursuit of higher device density, higher performance, and lower costs, challenges in both fabrication and design have led to stacked device structure configurations, such as complementary field-effect transistors (FETs). In a complementary FET, the semiconductor channel layers of an n-type FET (nFET) and a p-type FET (pFET) are stacked on top of each other, and the number of semiconductor channel layers is often the same in each nFET and pFET. However, nFETs and pFETs typically have different current-controlling capabilities. Thus, it is necessary for the number of stacked semiconductor channel layers in nFETs and pFETs to differ in order to obtain balanced drive currents from a pair of stacked transistors.Therefore, the existing manufacturing process for GAA transistors is generally suitable for the intended purposes, but not satisfactory in all aspects.

[0004] Publication US 2020 / 0219979A1 describes an integrated CMOS circuit structure formed over a substrate, comprising a lower PMOS region and an upper NMOS region. The lower PMOS region includes stacked nanoribbons over a raised substrate section and adjacent P-type S / D structures. The upper NMOS region includes stacked nanoribbons over an insulating structure and adjacent N-type S / D structures. The insulating structure is not adjacent to the stacked nanoribbons wrapped by gate structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present disclosure is best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, the various features are not shown to scale and are for illustrative purposes only. In fact, the dimensions of the various features may be enlarged or reduced as desired for the sake of clarity. Fig. Figure 1 shows a flowchart of a process for manufacturing a semiconductor device with stacked GAA transistors according to one or more aspects of the present disclosure. Fig. 2A, Fig. 2B, Fig. 2C, Fig. 3A, Fig. 3B, Fig. 3C, Fig. 4A, Fig. 4B, Fig. 4C, Fig. 5A, Fig. 5B, Fig. 5C, Fig. 6A, Fig. 6B, Fig. 6C, Fig. 7A, Fig. 7B, Fig. 7C, Fig. 8A, Fig. 8B, Fig. 8C, Fig. 9A, Fig. 9B, Fig. 9C, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 11A, Fig. 11B, Fig. 11C, Fig. 12A, Fig. 12B, Fig. 12C, Fig. 13A, Fig. 13B, Fig. 13C, Fig. 14A, Fig. 14B, Fig. 14C, Fig. 15A, Fig. 15B, Fig. 15C, Fig. 16A, Fig. 16B and Fig. Figure 16C illustrates fragmentary cross-sectional views of a workpiece during a manufacturing process according to the method of Fig. 1 according to one or more aspects of the present revelation. Fig. Figure 17 shows a flowchart of a process for manufacturing a semiconductor device with stacked GAA transistors according to one or more aspects of the present disclosure. Fig. 18A, Fig. 18B, Fig. 18C, Fig. 19A, Fig. 19B, Fig. 19C, Fig. 20A, Fig. 20B, Fig. 20C, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 22A, Fig. 22B, Fig. 22C, Fig. 23A, Fig. 23B, Fig. 23C, Fig. 24A, Fig. 24B, Fig. 24C, Fig. 25A, Fig. 25B, Fig. 25°C, Fig. 26A, Fig. 26B, Fig. 26C, Fig. 27A, Fig. 27B, Fig. 27C, Fig. 28A, Fig. 28B, Fig. 28°C, Fig. 29A, Fig. 29B, Fig. 29C, Fig. 30A, Fig. 30B, Fig. 30°C Fig. 31A, Fig. 31B, Fig. 31C, Fig. 32A, Fig. 32B, Fig. 32C, Fig. 33A, Fig. 33B and Fig. Figure 33C illustrates fragmentary cross-sectional views of a workpiece during a manufacturing process according to the method of Fig. 17 according to one or more aspects of the present revelation. Fig. Figure 34 shows a flowchart of a method for manufacturing a semiconductor device with a rear-side busbar according to one or more aspects of the present disclosure. Fig. 35A, Fig. 35B, Fig. 35°C Fig. 36A, Fig. 36B, Fig. 36C, Fig. 37A, Fig. 37B, Fig. 37C, Fig. 38A, Fig. 38B, Fig. 38C, Fig. 39A, Fig. 39B, Fig. 39C, Fig. 40A, Fig. 40B, Fig. 40°C, Fig. 41A, Fig. 41B, Fig. 41C, Fig. 42A, Fig. 42B, Fig. 42C, Fig. 43A, Fig. 43B, Fig. 43C, Fig. 44A, Fig. 44B, Fig. 44C, Fig. 45A, Fig. 45B, Fig. 45°C, Fig. 46A, Fig. 46B, Fig. 46C, Fig. 47A, Fig. 47B, Fig. 47C, Fig. 48A, Fig. 48B, Fig. 48C, Fig. 49A, Fig. 49B, Fig. 49C, Fig. 50A, Fig. 50B and Fig. Figure 50C illustrates fragmentary cross-sectional views of a workpiece during a manufacturing process according to the method of Fig. 34 according to one or more aspects of the present revelation. Fig. Figure 51 shows a flowchart of a method for manufacturing a semiconductor device with a rear-side busbar according to one or more aspects of the present disclosure. Fig. 52A, Fig. 52B, Fig. 52C, Fig. 53A, Fig. 53B, Fig. 53C, Fig. 54A, Fig. 54B, Fig. 54C, Fig. 55A, Fig. 55B, Fig. 55C, Fig. 56A, Fig. 56B, Fig. 56C, Fig. 57A, Fig. 57B, Fig. 57C, Fig. 58A, Fig. 58B, Fig. 58C, Fig. 59A, Fig. 59B, Fig. 59C, Fig. 60A, Fig. 60B, Fig. 60°C Fig. 61A, Fig. 61B, Fig. 61C, Fig. 62A, Fig. 62B, Fig. 62C, Fig. 63A, Fig. 63B, Fig. 63C, Fig. 64A, Fig. 64B, Fig. 64C, Fig. 65A, Fig. 65B, Fig. 65C, Fig. 66A, Fig. 66B, Fig. 66C, Fig. 67A, Fig. 67B and Fig. Figure 67C illustrates fragmentary cross-sectional views of a workpiece during a manufacturing process according to the method of Fig. 51 according to one or more aspects of the present revelation. Fig. Figure 68 shows a flowchart of a method for manufacturing a semiconductor device with a rear-side busbar according to one or more aspects of the present disclosure. Fig. 69A, Fig. 69B, Fig. 69C, Fig. 70A, Fig. 70B, Fig. 70°C, Fig. 71A, Fig. 71B, Fig. 71C, Fig. 72A, Fig. 72B, Fig. 72C, Fig. 73A, Fig. 73B, Fig. 73C, Fig. 74A, Fig. 74B, Fig. 74C, Fig. 75A, Fig. 75B, Fig. 75C, Fig. 76A, Fig. 76B, Fig. 76C, Fig. 77A, Fig. 77B, Fig. 77C, Fig. 78A, Fig. 78B, Fig. 78C, Fig. 79A, Fig. 79B, Fig. 79C, Fig. 80A, Fig. 80B, Fig. 80°C, Fig. 81A, Fig. 81B, Fig. 81C, Fig. 82A, Fig. 82B, Fig. 82C, Fig. 83A, Fig. 83B, Fig. 83C, Fig. 84A, Fig. 84B and Fig. Figure 84C illustrates fragmentary cross-sectional views of a workpiece during a manufacturing process according to the method of Fig. 68 according to one or more aspects of the present revelation. Fig. Figure 85 shows a flowchart of a method for manufacturing a semiconductor device with a rear-side busbar according to one or more aspects of the present disclosure. Fig. 86A, Fig. 86B, Fig. 86C, Fig. 87A, Fig. 87B, Fig. 87C, Fig. 88A, Fig. 88B, Fig. 88C, Fig. 89A, Fig. 89B, Fig. 89C, Fig. 90A, Fig. 90B, Fig. 90C, Fig. 91A, Fig. 91B, Fig. 91C, Fig. 92A, Fig. 92B, Fig. 92C, Fig. 93A, Fig. 93B, Fig. 93C, Fig. 94A, Fig. 94B, Fig. 94C, Fig. 95A, Fig. 95B, Fig. 95C, Fig. 96A, Fig. 96B, Fig. 96C, Fig. 97A, Fig. 97B, Fig. 97C, Fig. 98A, Fig. 98B and Fig. Figure 98C illustrates fragmentary cross-sectional views of a workpiece during a manufacturing process according to the method of Fig. 85 according to one or more aspects of the present revelation. Fig. 99 and Fig. Figure 100 shows fragmentary cross-sectional views of a workpiece according to various aspects of the present disclosure. Fig. Figure 101 shows a fragmentary cross-sectional view of a semiconductor device with two areas having different configurations according to one or more aspects of the present disclosure. Fig. 102A, Fig. 102B, Fig. 102C, Fig. 102D, Fig. 102E, Fig. 103A, Fig. 103B, Fig. 103C and Fig. Figure 103D shows fragmentary cross-sectional views of various embodiments of source / drain epitaxy features according to one or more aspects of the present disclosure. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments and examples of the implementation of various features of the provided subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, only examples and are not intended to be limiting. For instance, the formation of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, reference numerals may be repeated in the various examples of the present disclosure.This repetition serves for simplicity and clarity and does not fundamentally prescribe a relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, to simplify the description, spatially relative terms such as "under," "below," "below," "above," "on," "above," "below," and the like can be used to describe the relationship of one element or feature to another, as shown in the drawings. These spatially relative terms should encompass not only the orientation shown in the drawings but also other orientations of the device during use or operation. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative terms used here can be interpreted accordingly.When a number or range of numbers is described with "approximately", "about", or the like, the term includes numbers that lie within certain deviations (for example, + / - 10% or other deviations) from the described number, in accordance with the knowledge of a person skilled in the art with regard to the specific technology disclosed herein, unless otherwise specified. For example, the term "about 5 nm" may include the dimensional range from 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.

[0008] This application relates generally to semiconductor structures and fabrication methods, in particular integrated circuits (ICs) with stacked transistors having different numbers of active channel layers. In various embodiments, at least two gate-all-around (GAA) transistors with different (or varying) numbers of active channel layers are stacked one above the other. The different number of active channel layers helps to obtain balanced drive currents from the GAA transistor above and the GAA transistor below. The two stacked GAA transistors may have the same number of semiconductor channel layers (or referred to as channel layers), but at least one or more are floating, which, according to various aspects of the present disclosure, leads to a different number of active channel layers.The pair of stacked GAA transistors can be of opposite conductivity types, such as an nFET stacked on top of a pFET, or vice versa, or of the same conductivity type, such as two stacked nFETs or two stacked pFETs. Furthermore, an IC chip can contain two regions, one of which has stacked GAA transistors with the same number of active channel layers, and another of which has stacked GAA transistors with a different number of active channel layers, to suit different application requirements on a single chip.

[0009] The details of the structure and fabrication methods of the present disclosure are described below in conjunction with the accompanying drawings, which illustrate a method for fabricating stacked GAA transistors according to some embodiments. A GAA transistor relates to a transistor with vertically stacked, horizontally oriented channel layers, such as nanowires, nanosheets, other nanostructures, and / or other conceivable variations. Stacked GAA devices are promising candidates for advancing CMOS to the next stage of development because they offer high device density, improved gate controllability, lower leakage current, and full compatibility with FinFET device layouts. Stacked GAA transistors relate to two or more GAA transistors stacked vertically on top of each other.The stacked GAA transistors can be of the same conductivity type (n-type or p-type) or of different conductivity types (n-type and p-type). The channel layers of the GAA transistors can have the same gate structure, for example, a common gate structure. Alternatively, each GAA transistor can have its own individual gate structure.

[0010] The various aspects of this revelation will now be described in more detail with reference to the drawings. In this context, Fig. 1, Fig. 17, Fig. 34, Fig. 51, Fig. 68 and Fig. 85 flowcharts illustrating processes 100, 300, 500, 700, 900, and 1100 for manufacturing a semiconductor device from a workpiece according to the embodiments of this disclosure. Processes 100, 300, 500, 700, 900, and 1100 are merely examples, and this disclosure is not intended to be limited to what is expressly described in processes 100, 300, 500, 700, 900, and 1100. Additional steps may be provided before, during, and after processes 100, 300, 500, 700, 900, and 1100, and some of the described steps may be substituted, eliminated, or rearranged for additional embodiments of the processes. For the sake of simplicity, not all steps are described in detail herein. Procedures 100, 300, 500, 700, 900 and 1100 are described below in conjunction with Fig. 2A-16C, 18A-33C, 35A-50C, 52A-67C, 69A-84C, 86A-98C described, which represent fragmentary cross-sectional views of the workpiece at various stages of manufacture according to embodiments of methods 100, 300, 500, 700, 900 and 1100. Fig. Figures 99-100 present fragmentary cross-sectional views along a channel region, providing a summary and further illustrating alternative embodiments according to various aspects of the present disclosure. To better illustrate various aspects of the present disclosure, each of the drawings ending with the capital letter A shows a fragmentary cross-sectional view along a channel region (i.e., a section along a longitudinal direction of a channel layer), each of the drawings ending with the capital letter B shows a fragmentary cross-sectional view of a source region (i.e., a section into a source region perpendicular to the longitudinal direction of a channel layer), and each of the drawings ending with the capital letter C shows a fragmentary cross-sectional view of a drain region (i.e., a section into a drain region perpendicular to the longitudinal direction of a channel layer).

[0011] With reference to Fig. In Figures 1 and 2A-C, the method 100 comprises a block 102 in which a workpiece 200 is provided. It should be noted that, since the workpiece 200 is processed into a semiconductor device, it may also be referred to as a semiconductor device (or device) 200, depending on the context. The workpiece 200 may have a substrate section 202 and a stack section 204 arranged above the substrate section 202. The substrate section 202 may also be referred to as a substrate 202. Although not explicitly shown in the drawings, the substrate 202 may include an n-well region and a p-well region for fabricating transistors of different conductivity types. In one embodiment, the substrate 202 may be a Si substrate (silicon). In some other embodiments, the substrate 202 may contain other semiconductors such as germanium (Ge), silicon-germanium (SiGe), or a III-V semiconductor material.Exemplary III-V semiconductor materials can include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 can also incorporate an insulating layer, such as a silicon oxide layer, to obtain a silicon-on-insulator (SOI) structure. If present, each of the n-wells and p-wells in the substrate 202 is formed and exhibits a doping profile. An n-well can have a doping profile of an n-type dopant such as phosphorus (P) or arsenic (As). A p-well can contain a doping profile of a p-doping agent such as boron (B). The doping in the n-well and the p-well can be formed by ion implantation or thermal diffusion and can be considered part of substrate 202.To avoid ambiguity, the X direction, the Y direction and the Z direction are perpendicular to each other.

[0012] As in Fig. As shown in Figure 2A-C, the stacking section 204 has multiple channel layers 208 nested with multiple sacrificial layers 206. The channel layers 208 and the sacrificial layers 206 can have different semiconductor compositions. In some implementations, the channel layers 208 are formed from silicon (Si) and the sacrificial layers 206 are formed from silicon-germanium (SiGe). In these implementations, the additional germanium content in the sacrificial layers 206 allows for selective removal or omission of the sacrificial layers 206 without causing significant damage to the channel layers 208. In some embodiments, the sacrificial layers 206 and the channel layers 208 are epitaxial layers and can be deposited by an epitaxial process. Suitable epitaxial methods include vapor deposition (VDE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable methods.The sacrificial layers 206 and the channel layers 208 are deposited alternately and sequentially to form the stack section 204. As explained in more detail below, the channel layers 208 in the lower section of the stack section 204 provide channel elements of a lower GAA transistor, and the channel layers 208 in the upper section of the stack section 204 provide channel elements of an upper GAA transistor. The term "channel element(s)" as used herein refers to any section of material for channel(s) in a transistor at the nanoscale or microscale that has an elongated shape, irrespective of the cross-sectional shape of that section. Thus, this term refers to both circular and substantially circular elongated sections of material, as well as beam- or rod-shaped sections of material that, for example, have a cylindrical shape or a substantially rectangular cross-section.Thus, the channel layers 208 in the lower section of the stack section 204 and the associated nested sacrificial layers 206 together define a first stack 204a, and the channel layer 208 in the upper section of the stack section 204 and the associated nested sacrificial layers 206 together define a second stack 204b. The one sacrificial layer 206 that lies between the first stack 204a and the second stack 204b is specifically referred to as the middle sacrificial layer 206M. In other words, the first stack 204a has channel layers 206 and sacrificial layers 208 below the middle sacrificial layer 206M, and the second stack 204b has channel layers 206 and sacrificial layers 208 above the middle sacrificial layer 206M.

[0013] It should be noted that in Fig. Figures 2A-C show three (3) layers of channel layers 208 in the first stack 204a and an equal number of channel layers 208 in the second stack 204b, which is for illustrative purposes only and does not intend to limit the scope of the claims. It is apparent that any number of channel layers 208 can be formed independently in the first stack 204a and in the second stack 204b. The number of layers depends on the desired number of channel elements for the device 200. In some embodiments, the number of channel layers 208 in each stack is between 2 and 10.

[0014] In some embodiments, each sacrificial layer 206 has a thickness of about 2 nm to about 6 nm. The sacrificial layers 206 can be of substantially uniform thickness. In the illustrated embodiment, however, the middle epitaxial layer 206M is thicker than (for example, twice as thick or three times as thick as) the other epitaxial layers 206. In some embodiments, each channel layer 208 has a thickness of about 6 nm to about 12 nm. In some embodiments, the channel layers 208 of the stack are of substantially uniform thickness. The thickness of each sacrificial layer 206 and channel layer 208 is selected with regard to the device performance.

[0015] With reference to Fig. In Figures 1 and 3A-C, the method 100 comprises a block 104 in which a fin-shaped structure 209 is formed from the stacked section 204. In some embodiments, the stacked section 204 and an upper section of the substrate 202 are structured to form the fin-shaped structure 209. For structuring purposes, a hard mask layer can be deposited over the stacked section 204. The hard mask layer can be a single layer or a multilayer. In one example, the hard mask layer comprises a silicon oxide layer and a silicon nitride layer over the silicon oxide layer. As in Fig. As shown in Figures 3A-C, the fin-shaped structure 209 extends vertically along the Z-direction from the substrate 202 and longitudinally along the X-direction. The fin-shaped structure 209 comprises a base section 209B formed from the substrate 202 and a stack section 209S formed from the stack of channel layers 208 and nested sacrificial layers 206. The fin-shaped structure 209 can be structured by suitable methods, including dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, smaller spacings than those achievable by a single, direct photolithography process.In one embodiment, for example, a material layer is formed over a substrate and structured by a photolithography process. Spacers are formed along the structured material layer by a self-aligning process. The material layer is then removed, and the remaining spacers or mandrels can then be used to structure the fin-shaped structure 209 by etching the stack section 204 and the substrate 202. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable methods. In some of the embodiments described in [reference], the following methods are used: Fig. In the implementations shown in Figures 3A-C, after the fin-shaped structure 209 has been formed, a first lining 210 can be conformally deposited over the workpiece 200. The first lining 210 can contain silicon nitride and can be deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0016] As in Fig. As shown in Figures 1 and 3A-C, the method 100 comprises a block 106 in which buried busbars (or referred to as bottom busbars) 211 are formed. In some embodiments, prior to back-etching the first lining 210, a metal layer for the buried busbars 211 is deposited onto the workpiece 200 by metal-organic CVD or PVD. The deposited metal layer is recessed to form the buried busbars 211. The metal layer for the buried busbars 211 may contain tungsten (W), ruthenium (Ru), copper (Cu), aluminum (Al), silver (Ag), molybdenum (Mo), rhenium (Re), iridium (Ir), cobalt (Co), or nickel (Ni). In the embodiment shown, each of the buried busbars 211 comprises a width W of about 40 nm to 80 nm and a height H of about 30 nm to about 50 nm. As shown in Fig. As shown in 3A-C, the buried busbars 211 comprise a first buried busbar 211-1 and a second buried busbar 211-2.

[0017] With reference to Fig. In embodiments 1 and 4A-C, method 100 comprises a block 108 in which an insulating feature 214 is formed. In some embodiments, a second lining 213 is applied to the buried busbars 211 to protect them from oxidation. The second lining 213 may be similar to the first lining 210 in composition and formation. As in Fig. As shown in Figure 4A-C, the buried busbars 211 lie laterally between the first lining 210 and the second lining 213. The insulation feature 214 is then formed above the second lining 213. The insulation feature 214 can also be referred to as a shallow trench insulation (STI) feature 214. In an exemplary process, a dielectric material for the insulation feature 214 is deposited onto the first layer 210 by CVD, subatmospheric CVD (SACVD), flowable CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), spin coating, and / or another suitable process. Subsequently, the deposited dielectric material is planarized and recessed until the fin-shaped structure 209 rises above the insulation feature 214. That is, after the recess of the insulation feature 214, the base section 209B of the fin-shaped structure 209 is surrounded by the insulation feature 214.The dielectric material for the insulating feature 214 can include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials. After the formation of the insulating feature 214, the first lining 210 and the second lining 213 are selectively recessed until the stacking section 204 of the fin-shaped structure 209 is exposed.

[0018] With reference to Fig. In Figures 1 and 5A-C, the process 100 comprises a block 110 in which a dummy gate stack 222 is formed over the stack section 204. In some embodiments, a gate replacement process (or gate-load process) is used, in which the dummy gate stack 222 serves as a placeholder for a functional gate structure. Other processes and configurations are possible. To form the dummy gate stack 222, a dummy dielectric layer 216, a dummy gate electrode layer 218, and a gate-top hard mask layer 220 are deposited over the workpiece 200. The deposition of these layers can be carried out by low-pressure CVD (LPCVD), CVD, plasma-enhanced CVD (PECVD), PVD, ALD, thermal oxidation, E-beam evaporation, or other suitable deposition techniques or combinations thereof.The dummy dielectric layer 216 may contain silicon oxide, the dummy gate electrode layer 218 may contain polysilicon, and the gate-top hard mask layer 220 may be a multilayer containing silicon oxide and silicon nitride. The gate-top hard mask layer 220 is patterned by photolithography and etching processes. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist winding, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. The etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods.The dummy dielectric layer 216 and the dummy gate electrode layer 218 are then etched using the structured gate-top hard mask 220 as an etching mask to form the dummy gate stack 222. The dummy gate stack 222 extends longitudinally along the Y-direction to wrap around the fin-shaped structure 209 and terminates on the insulating feature 214. The portion of the fin-shaped structure 209 that lies beneath the dummy gate stack 222 is a channel region. The channel region and the dummy gate stack 222 also define source / drain regions that are not vertically overlapped by the dummy gate stack 222. The channel region is positioned between two source / drain regions along the X-direction.

[0019] With reference to Fig. In Figures 1 and 6A-C, the process 100 comprises a block 112 in which source / drain sections of the fin-shaped structure 209 are recessed to form source / drain recesses 224. The operations in block 112 may include forming a gate spacer layer 223 over the sidewalls of the dummy gate stack 222 before the source / drain sections of the fin-shaped structure 209 are recessed. In some embodiments, forming the gate spacer layer 223 includes depositing one or more dielectric layers over the workpiece 200. In one example process, the one or more dielectric layers are deposited by CVD, SACVD, or ALD. The one or more dielectric layers may comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, and / or combinations thereof.In an example process, the workpiece 200 is etched after the deposition of the gate spacer layer 223 by an etching process that selectively omits the source / drain regions of the fin-shaped structure 209. The selective omission of the source / drain regions results in source / drain grooves 224 between adjacent dummy gate stacks 222. The etching process in block 112 can be a dry etching process or a suitable etching process. An exemplary dry etching process can use an oxygen-containing gas, hydrogen, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof. As in . Fig. As shown in Figure 6A, the side walls of the sacrificial layers 206 and the channel layers 208 are exposed in the channel area in the source / drain trenches 224.

[0020] With reference to Fig. In Figures 1 and 7A-C, the method 100 comprises a block 114 in which internal spacer features 226 are formed. In block 114, the sacrificial layers 206, including the middle sacrificial layer 206M, exposed in the source / drain channels 224, are selectively and partially recessed to form internal spacer recesses, while the exposed channel layers 208 remain substantially unetched. In an embodiment in which the channel layers 208 contain substantially silicon (Si) and the sacrificial layers 206 contain substantially silicon germanium (SiGe), the selective and partial recession of the sacrificial layers 206 may include a SiGe oxidation process followed by removal of the SiGe oxide. In these embodiments, the SiGe oxidation process may include the use of ozone (O3).In some other embodiments, the selective recession can be a selective isotropic etching process (for example, a selective dry etching process or a selective wet etching process), and the extent to which the sacrificial layers 206 are recessed is controlled by the duration of the etching process. The selective dry etching process can involve the use of one or more fluorine-based etchants, such as fluorine gas or fluorocarbons. The selective wet etching process can include a hydrogen fluoride (HF) or NH4OH etchant. After the formation of the inner spacer recesses, an inner spacer material layer is deposited over the workpiece 200, including within the inner spacer recesses. The inner spacer material layer can comprise silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material.The deposited inner spacer material layer is then back-etched to remove excess inner spacer material layer above the gate spacer layer and the sidewalls of the channel layers 208, forming the inner spacer features 226 as shown in . Fig. 7A shown. In some embodiments, the re-etching process in block 114 may be a dry etching process comprising the use of an oxygen-containing gas, hydrogen, nitrogen, a fluorine-containing gas (for example, CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (for example, Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (for example, HBr and / or CHBR3), an iodine-containing gas (for example, CF3I), other suitable gases and / or plasmas and / or combinations thereof.

[0021] With reference to Fig. In sections 1 and 8A-C, process 100 comprises a block 118 in which a dielectric sacrificial layer 215 is deposited in the source / drain channels 224. The dielectric sacrificial layer 215 may contain silicon oxide, silicon oxycarbide, or a dielectric material that allows selective etching of the dielectric sacrificial layer 215 while the internal spacer features 226 remain substantially intact. The dielectric sacrificial layer 215 may be deposited by CVD. The dielectric sacrificial layer 215 is then back-etched to expose the second stack 204b, while the sidewalls of the first stack 204a remain covered. That is, after back-etching the dielectric sacrificial layer 215, the sidewalls of the channel layers 208 of the second stack 204b and the respective internal spacer features nested therein are exposed in the source / drain channels 224.The etching process can be a dry etching process, a wet etching process, or a suitable etching process. The extent to which the dielectric sacrificial layer 215 is recessed is controlled by the duration of the etching process. The operations in block 118 further include conformal deposition of a third lining 225 onto the workpiece 200. The sidewalls of the first stack 204b are covered by the third lining 225. The third lining 225 can contain silicon nitride, silicon carbonitride, or another suitable dielectric material that provides an etching difference to the dielectric sacrificial layer 215. The third lining 225 can be deposited by CVD, ALD, or another suitable deposition method.

[0022] With reference to Fig. In sections 1 and 9A-C, process 100 comprises a block 120 in which the lateral portion of the third lining 225 is removed. Using an anisotropic etching process, such as RIE or another suitable dry etching process, the vertical portion of the third lining 225 covering the side walls of the second stack 204b remains, while the lateral portion of the third lining 225 is removed from the source / drain trenches 224, thereby exposing the dielectric sacrificial layer 215. The operations in block 120 further include the removal of the dielectric sacrificial layer 215 by a selective etching process to expose the first stack 204a.In an example where the dielectric sacrificial layer 215 is formed from an oxide and the inner spacer features 226 and the third lining 225 are formed from nitrides, the dielectric sacrificial layer 215 can be selectively removed using diluted hydrofluoric acid (DHF) or buffered hydrofluoric acid (BHF). The BHF comprises hydrofluoric acid and ammonium fluoride. After completion of the operations in Block 120, the sidewalls of the channel layers 208 of the first stack 204a in the source / drain trenches 224 are exposed, while the sidewalls of the channel layers 208 of the second stack 204b and an upper portion of the middle sacrificial layer 206M remain covered by the third lining 225.

[0023] With reference to Fig. In embodiments 1 and 10A-C, method 100 comprises a block 122 in which a first source feature 228S and a first drain feature 228D are formed in the source / drain trenches 224. In some embodiments, the first source feature 228S and the first drain feature 228D can be formed using an epitaxial growth process such as VPE, UHV-CVD, MBE, and / or other suitable processes. The epitaxial growth process can utilize gaseous and / or liquid precursors that interact with the composition of the substrate 202 and the channel layers 208. The exposed sidewalls of the channel layers 208 of the first stack 204a functionally serve as semiconductor seed layers. Thus, the epitaxial growth of the first source feature 228S and the first drain feature 228D can occur both from the upper surface of the substrate 202 and from the exposed sidewalls of the channel layers 208 of the first stack 204a. As shown in Fig. As shown in Figure 10A, the first source feature 228S and the first drain feature 228D are in physical contact with (or adjacent to) the channel layers 208 or the released channel of the first stack 204a. Since the channel layers 208 in the second stack 204b are covered by the third lining 225, epitaxial growth does not occur from its side walls. The duration of epitaxial growth is controlled such that the first source feature 228S and the first drain feature 228D do not extend upwards beyond the middle sacrificial layer 206M. Depending on the conductivity type of the lower GAA transistor to be formed, the first source feature 228S and the first drain feature 228D can be n-source / drain or p-source / drain features.Exemplary n-type source / drain features can contain Si, GaAs, GaAsP, SiP, or another suitable material and can be doped in situ during the epitaxy process by introducing an n-type dopant such as phosphorus (P) or arsenic (As), or ex situ by an implantation process (i.e., a junction implant process). Exemplary p-type source / drain features can contain Si, Ge, AlGaAs, SiGe, boron-doped SiGe, or another suitable material and can be doped in situ during the epitaxy process by introducing a p-type dopant such as boron (B), or ex situ by an implantation process (i.e., a junction implant process).

[0024] With reference to Fig. In sections 1 and 11A-C, process 100 comprises a block 126 in which a first contact etch stop layer (CESL) 230 and a first interlayer dielectric layer (ILD) 232 are deposited on the first source feature 228S and the first drain feature 228D. The operations in block 126 include removing the third lining 225 to expose the second stack 204b in an etching process. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The first CESL 230 may contain silicon nitride, silicon oxynitride, and / or other materials known in the art and may be formed by ALD, plasma-enhanced chemical vapor deposition (PECVD), and / or other suitable deposition or oxidation processes.In some embodiments, the first CESL 230 is conformally deposited onto the workpiece 200, and the first ILD layer 232 is deposited over the first CESL 230 by a PECVD process or another suitable deposition technique. Subsequently, the first CESL 230 and the first ILD layer 232 are back-etched by a selective etching process. Both the first CESL 230 and the first ILD layer 232 are back-embedded beneath the bottom channel layer 208 of the second stack 204b. After completion of the operations in block 126, the first CESL 230 is conformally deposited onto the surfaces of the first source feature 228S, the first drain features 228D, and partially onto the sidewalls of the middle sacrificial layer 206M.The first ILD layer 232 can contain materials such as TEOS oxide (tetraethyl orthosilicate), undoped silicate glass, or doped silicon oxide such as boron phosphosilicate glass (BPSG), fused silica (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. In some embodiments, the workpiece 200 can be annealed after the formation of the first ILD layer 232 to improve the integrity of the first ILD layer 232.

[0025] With reference to Fig. In 1 and 12A-C, Method 100 comprises a block 128 in which interconnect features, such as a first drain contact 234, a first source contact 236, and a first source contact via 238, are formed. Considering interconnect features in the source area as an illustrative example, lithography processes are used to form a contact opening that exposes the first source feature 228S. Further lithography processes can be used to form a via opening for the first source contact via 238, and the via opening extends at least through the CESL 230 and the insulation feature 214, exposing the first buried busbar 211-1.To reduce contact resistance, a silicide layer 240 can be formed on the first source feature 228S by depositing a metal layer over the first source feature 228S and performing an annealing process to induce silicide formation between the metal layer and the first source feature 228S. A suitable metal layer can contain titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), or tungsten (W). The silicide layer 240 can contain titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi), or nickel silicide (NiSi). After the formation of the silicide layer 240, a metal filler layer can be deposited in the contact orifice and the contact through-holes. The metal filler layer can contain titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta) or tantalum nitride (TaN).Similar to the first source contact 236, a contact opening is first formed to expose the first drain feature 228D. A silicide layer 240 is formed on the first drain feature 228D, and a metal filler layer is deposited to fill the remainder of the contact opening and form the first drain contact 234. A contact etching process can follow to remove excess material, leaving an upper surface of the first drain contact 234 and the first source contact 236 below the bottom channel layer 208 of the second stack 204b. In particular, a source and a drain can be used interchangeably in various other embodiments, such as interconnect features, which in one embodiment electrically couple the first drain feature 228D to the first buried busbar 211-1.

[0026] With further reference to Fig. In Figures 1 and 12A-C, the process 100 comprises a block 130 in which a dielectric insulating layer 242 is deposited over the first ILD layer 232 and covers the interconnect features formed in previous operations in block 128. The dielectric insulating layer 242 may contain silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, or another suitable insulating material. In one embodiment, the dielectric insulating layer 242 can be formed by filling the source / drain grooves 224 with dielectric insulating material (for example, by a CVD process or a spin-on-glass process) and back-etching the dielectric insulating material by a selective etching process. As described in Figures 1 and 12A-C, the process 100 comprises a block 130 in which a dielectric insulating layer 242 is deposited over the first ILD layer 232 and covers the interconnect features formed in previous operations in block 128. The dielectric insulating layer 242 may contain silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, or another suitable insulating material. Fig. As shown in Figure 12A, the dielectric insulating layer 242 covers opposite side walls of at least the lowest channel layer 208 of the second stack 204b. In some embodiments, the dielectric insulating layer 242 borders more than one lower channel layer 208 in the second stack 204b.

[0027] With reference to Fig. In sections 1 and 13A-C, the process 100 comprises a block 132 in which a second source feature 248S and a second drain feature 248D are formed in the source / drain trenches 224. Similar to the first source feature 228S and the first drain feature 228D, the second source feature 248S and the second drain feature 248D can be formed using an epitaxial process, such as VPE, UHV-CVD, MBE, and / or other suitable processes. The epitaxial growth process can utilize gaseous and / or liquid precursors that interact with the channel layers 208. The exposed sidewalls of the channel layers 208 of the second stack 204b functionally serve as semiconductor seed layers. Thus, the epitaxial growth of the second source feature 248S and the second drain feature 248D can occur from the exposed sidewalls of the channel layers 208 of the second stack 204b, but not from those adjacent to the dielectric insulating layer 242. As in Fig. As shown in Figure 13A, the second source feature 248S and the second drain feature 248D are thus in physical contact with (or adjacent to) the upper channel layers 208 of the second stack 204b and form active channel layers. The term "active channel layer" refers to a channel layer whose two ends are bordered by source / drain features, allowing charge carriers to pass through. Since the bottommost channel layer 208 in the second stack 204b is covered by the dielectric insulating layer 242, no epitaxial growth occurs from its side walls. Because the bottommost channel layer 208 of the second stack 204b is isolated from the second source feature 248S and the second drain feature 248D by the dielectric insulating layer 242, it becomes a "floating" (or inactive) channel layer.The term "floating channel layer" refers to a channel layer that is isolated from the contacting source / drain features at one or both ends, preventing charge carriers from passing through. Depending on the conductivity type of the upper GAA transistor being formed, the second source feature 248S and the second drain feature 248D can be n-type or p-type source / drain features. Exemplary n-type source / drain features can contain Si, GaAs, GaAsP, SiP, or another suitable material and can be doped in situ during the epitaxy process by introducing an n-type dopant such as phosphorus (P) or arsenic (As), or ex situ by an implantation process (i.e., a junction implant process).Exemplary p-source / drain features can contain Si, Ge, AlGaAs, SiGe, boron-doped SiGe, or another suitable material and can be doped in situ during the epitaxy process by introducing a p-type dopant such as boron (B) or ex situ by an implantation process (i.e., a junction implant process). In some embodiments, the upper and lower GAA transistors to be formed are of opposite types, for example, an nFET over a pFET, or vice versa. Thus, in some embodiments, the second source / drain features and the first source / drain features have opposite conductivity types. In some other embodiments, the upper and lower GAA transistors to be formed are of the same conductivity type, for example, an nFET over an nFET or a pFET over a pFET.Thus, in some other embodiments, the second source / drain features and the first source / drain features exhibit the same conductivity type.

[0028] In particular, the second source feature 248S and the second drain feature 248D are stacked directly above the first source feature 228S and the first drain feature 228D and have a smaller height and volume, which is due to the smaller total number of active channel layers of the second stack for the epitaxial growth of source / drain features. Even though the first and second source / drain features in Fig. 13A-C with crystalline facets (for example, in hexagonal form) in the YZ plane are shown (as in Fig. 102A), other shapes are also possible, such as a rod-shaped shape as in Fig. 102B shown. While the first and second source / drain features in Fig. 13A-C are shown to fill the source / drain trenches 224 in the XZ plane (as in Fig. 102C), since the source / drain features in the same source / drain trench 224 grew from the opposite sidewalls of the active channel layers, the source / drain features cannot have merged laterally, as in Fig. 102D, which corresponds to the source / drain features with crystalline facets, and as in Fig. 102E, which corresponds to rod-shaped source / drain features. Since the first and second source / drain features grew epitaxially from the sidewalls of the active channel layers, air gaps may also be trapped when adjacent source / drain features merge, as in Fig. 103A-B is shown. Fig. 103A includes air gaps 249 next to the inner spacers 226 and between the dielectric insulating layer 242 and the fused source / drain features. Fig. 103B include air gaps 249 between the dielectric insulating layer 242 and the fused source / drain features. Fig. Figures 103C-D show fragmentary cross-sectional views in the YZ plane with air gaps 249 enclosed between the dielectric insulating layer 242 and the fused source / drain features with crystalline facets or rod-shaped forms. To avoid ambiguity, both the first source / drain features 228S / D and the second source / drain features 248S / D can be identified as having different source / drain feature profiles as shown in Fig. 102A-103D are shown.

[0029] With reference to Fig. In embodiments 1 and 14A-C, the process 100 comprises a block 136 in which a second CESL 250 and a second ILD layer 252 are deposited on the second source feature 248S and the second drain feature 248D. The second CESL 250 may contain silicon nitride, silicon oxynitride, and / or other materials known in the art and may be formed by ALD, plasma-enhanced chemical vapor deposition (PECVD), and / or other suitable deposition or oxidation processes. In some embodiments, the second CESL 250 is first conformally deposited on the workpiece 200, and the second ILD layer 252 is deposited over the second CESL 250 by a PECVD process or another suitable deposition technique.The second ILD layer 252 can contain materials such as TEOS oxide, undoped silicate glass, or doped silicon oxide such as boron phosphosilicate glass (BPSG), fused silica (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. In some embodiments, the workpiece 200 can be annealed after the formation of the second ILD layer 252 to improve its integrity. After completion of the operations in block 136, the second CESL 250 is conformally deposited on the surfaces of the second source feature 248S, the second drain features 248D, and on the sidewalls of the gate spacer layer 223. A planarization process, such as a chemical-mechanical polishing (CMP) process, can be performed to remove excess material and expose the top surfaces of the dummy gate stacks 222.In some embodiments, the gate-top hard mask layer 220 is removed by the CMP process and the dummy gate electrode layer 218 is exposed.

[0030] With reference to Fig. In blocks 1 and 15A-C, with the dummy gate stack 222 exposed, process 100 proceeds to block 138, where the dummy gate stack 222 is removed and replaced by a gate structure 254. The removal of the dummy gate stack 222 can involve one or more etching processes that selectively act on the material within the dummy gate stack 222. For example, the removal of the dummy gate stack 222 can be performed by selective wet etching, selective dry etching, or a combination thereof. After the removal of the dummy gate stack 222, the sidewalls of the channel layers 208 and the sacrificial layers 206 of both the first and second stacks 204a / b in the channel region located between the source region and the drain region are exposed. Afterwards, the sacrificial layers 206 in the channel area are selectively removed to expose the channel layers 208 as the channel elements.Since the dimensions of the channel elements are in the nanometer range, the channel elements can also be referred to as nanostructures. The selective removal of the sacrificial layers 206 can be achieved by selective dry etching, selective wet etching, or other selective etching methods. In some embodiments, selective wet etching includes APM etching (for example, an ammonia hydroxide-hydrogen peroxide-water mixture). In some embodiments, selective removal includes SiGe oxidation followed by silicon germanium oxide removal. For example, the oxidation can be carried out by ozone purification, and subsequently, the silicon germanium oxide can be removed with an etchant such as NH4OH.

[0031] Since the channel elements are exposed, the gate structure 254 is deposited to wrap each of the channel layers (including the active or floating layers) of both the first and second stacks 204a / b in the channel region, forming a lower GAA transistor 260a and an upper GAA transistor 260b stacked on top of the lower GAA transistor 260a. Because the gate structure 254 engages channel layers in both the upper and lower GAA transistors, it is also referred to as a common gate structure 254. The common gate structure 254 comprises a common gate dielectric layer 256 and a common gate electrode layer 258 above the gate dielectric layer 256. The common gate dielectric layer 256 includes an interface layer (not explicitly shown) and a high-k dielectric layer surrounding and in contact with the channel elements.In some embodiments, the interface layer contains silicon oxide and can be formed by a pre-cleaning process. An exemplary pre-cleaning process may involve the use of RCA SC-1 (ammonia, hydrogen peroxide, and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). The high-k dielectric layer is then deposited over the interface layer by ALD, CVD, and / or other suitable methods. The high-k dielectric layer is formed from high-k dielectric materials. As used and described here, high-k dielectric materials include dielectric materials with a high dielectric constant, for example, greater than that of thermal silicon oxide (~3.9). The high-k dielectric layer may contain hafnium oxide.Alternatively, the high-k dielectric layer can be made of other high-k dielectric materials such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), Contains silicon oxynitride (SiON), combinations thereof, or other suitable materials.

[0032] The common gate electrode layer 258 is then deposited 408 over the common gate dielectric layer by ALD, PVD, CVD, electron beam evaporation, or other suitable methods. The common gate electrode layer 258 can comprise a single layer or, alternatively, a multilayer structure, such as various combinations of a metal layer with a selected work function to improve device performance (work function metal layer), a lining layer, a wetting layer, an adhesive layer, a metal alloy, or a metal silicide.For example, the common gate electrode layer 258 can contain titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other resistant metals, or other suitable metal materials, or a combination thereof. Furthermore, if the semiconductor device 200 contains n-transistors and p-transistors, different common gate electrode layers can be formed separately for n-transistors and p-transistors, which may contain different metal layers (for example, to provide different n- and p-work-function metal layers).

[0033] The operations in block 138 may further include the formation of a self-aligned capping layer (SAC) 253 over the common gate structure 254. In some embodiments, the SAC 253 comprises La₂O₃, Al₂O₃, SiOCN, SiOC, SiCN, SiO₂, SiC, ZnO, ZrN, Zr₂Al₃O₄, TiO₂, TaO₂, ZrO₂, HfO₂, Si₃N₄, Y₂O₃, AlON, TaCN, ZrSi, or other suitable materials. The SAC 253 protects the common gate structure 254 from etching and CMP processes used to etch the S / D contact holes. The SAC 253 can be formed by recessing the gate structure, depositing one or more dielectric materials over the recessed gate structure, and performing a CMP process on the one or more dielectric materials.

[0034] With reference to Fig. In sections 1 and 16A-C, process 100 comprises a block 140 in which interconnect features, such as a second source contact 262, a second drain contact 264, a second source contact via 266, a second drain contact via 268, and a first drain contact via 270, are formed. The second drain contact 264 is formed above and in contact with the second drain feature 248D. Similar to the formation of the first drain contact 234 in block 128, a contact opening is first formed to expose the second drain feature 248D, a silicide layer 269 is formed on the second drain feature 248D, and a metal filler layer is deposited to fill the remainder of the contact opening.Additional lithography processes can be used to form a via opening for the second source contact via 266, and the via opening extends through at least the second CESL 250, the dielectric insulating layer 242, the first ILD layer 232, the first CESL 230, and the insulating feature 214, exposing the second buried busbar 211-2. The metal filler layer can contain titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta), or tantalum nitride (TaN). In some embodiments, each of the contact feedthroughs can have a lining between the metal filler layer and the adjacent dielectric material to improve electrical integrity. Such a lining can contain titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt nitride (CoN), nickel nitride (NiN) or tantalum nitride (TaN).The second source contact via 266 serves to couple the second source contact 262 and the second buried busbar 211-2.

[0035] The operations in Block 140 further include forming an upper interconnect layer 272 above the second ILD layer 252. The upper interconnect layer 272 has a dielectric layer and a second busbar in the dielectric layer. The second busbar includes conductive lines (not explicitly shown) and vias that couple the underlying contacts to the conductive lines in the second busbar, such as the second drain contact via 268 and the first drain contact via 270. Lithography processes can be used to form a via opening for the first drain contact via 270, extending through at least the dielectric insulating layer 242, the second CESL 250, and the second ILD layer 252, and a metal filler layer is deposited to fill the via opening.Similarly, the second drain contact via 268 is formed above the second drain contact 264 and couples it to the second busbar in the upper interconnect layer 272. Since the formation of the second drain contact via 268 and the first drain contact via 270 requires the creation of a via opening that extends into the upper interconnect layer 272, these via openings cannot be formed simultaneously with via openings for the first and second source contact features. In some other embodiments, the via openings for the first and second drain contact features are formed separately and etched in multiple etching steps.

[0036] It will now be on Fig. Reference is made to 16A-C. After completion of the operations in Procedure 100, a lower GAA transistor 260a and an upper GAA transistor 260b are formed, stacked on top of the lower GAA transistor 260a. The lower GAA transistor 260a has channel layers (or is referred to as channel elements) located between the first source feature 228S and the first drain feature 228D. The upper GAA transistor 260b has the same number of channel layers as the lower GAA transistor 260a. One difference is that not all channel layers of the upper GAA transistor 260b are located between the second source feature 248S and the second drain feature 248D and serve as active channel layers for the passage of charge carriers. At least one lowest channel layer is bounded by the dielectric insulating layer 242 and becomes a “floating” (inactive) channel layer.Thus, the upper GAA transistor 260b has one fewer active channel layer than the lower GAA transistor 260a. In various embodiments, two or more lower channel layers of the upper GAA transistor 260b can be adjacent to the dielectric insulating layer 242, and therefore the upper GAA transistor 260b can have two or more fewer active channel layers than the lower GAA transistor 260a. A smaller number of active channel layers reduces the current control capability of the upper GAA transistor 260b, but this can be compensated for by the current output of the stacked GAA transistor pair. For example, if the upper GAA transistor is an nFET and the lower GAA transistor is a pFET, an nFET often offers stronger current control capability due to its higher charge carrier mobility. By reducing the total number of active channel layers of the nFET, a balanced current output can be achieved from the nFET and pFET pair.

[0037] A common gate structure 254 wraps each channel layer of the upper GAA transistor and the lower GAA transistor 260a and 260b, with the dielectric insulating layer 242 located between the first source 228S and the second source 248S, and also between the first drain 228D and the second drain 248D. The first source feature 228S is coupled to a lower power rail via the first source contact 236 and the first source contact via 238. The second source feature 248S is coupled to the lower power rail via the second source contact 262 and the second source contact via 266. The first source contact via 238 and the second source contact via 266 are located on opposite sides of the first contact 228S. The first drain feature 228D is coupled to an upper busbar via the first drain contact 234 and via the first drain contact via 270.The second drain feature 248D is coupled to the upper busbar via the second drain contact 264 and the second drain contact via 268. The upper busbar is located in the upper interconnect layer 272.

[0038] Reference is now made to procedure 300. Fig. Figure 17 shows a flowchart of Process 300 according to various aspects of the present disclosure. Throughout the present disclosure, similar reference symbols denote the same / similar features regarding composition and formation. Some details of the processes in Process 300 may be simplified or even omitted if similar details have already been described above in connection with Process 100.

[0039] With reference to Fig. In sections 17 and 18A-C, the method 300 comprises a block 302 in which a workpiece 200 is provided. The workpiece 200 comprises a substrate section 202 (also referred to as the substrate) and a stacking section 204 above the substrate 202. The stacking section 204 comprises a first stack 204a and a second stack 204b above the first stack 204a. The substrate 202 and the stacking section 204 have already been explained above, and a detailed description is omitted here.

[0040] With reference to Fig. In sections 17 and 19A-C, process 300 comprises a block 304 in which a fin-shaped structure 209 is formed from the stacked section 204. The processes in block 304 are similar to those in block 104, and a detailed description is omitted here for the sake of brevity.

[0041] With further reference to Fig. In sections 17 and 19A-C, procedure 300 comprises a block 306 in which buried busbars 211 are formed. The processes in block 306 are similar to those in block 106, and a detailed description is omitted for the sake of brevity.

[0042] With reference to Fig. In sections 17 and 20A-C, process 300 comprises a block 308 in which an insulation feature 214 is formed. The processes in block 308 are similar to those in block 108, and a detailed description is omitted for the sake of brevity.

[0043] With reference to Fig. In sections 17 and 21A-C, procedure 300 comprises a block 310 in which a dummy gate stack 222 is formed above the stack section 204. The operations in block 310 are similar to those in block 110, and a detailed description is omitted for the sake of brevity.

[0044] With reference to Fig. In sections 17 and 22A-C, process 300 comprises a block 312 in which source / drain sections of the fin-shaped structure 209 are omitted to form source / drain recesses 224. The processes in block 312 are similar to those in block 112, and a detailed description is omitted for the sake of brevity.

[0045] With reference to Fig. In sections 17 and 23A-C, process 300 comprises a block 314 in which the internal spacer features 226 are formed. The processes in block 314 are similar to those in block 114, and a detailed description is omitted for the sake of brevity.

[0046] With reference to Fig. In Figures 17 and 24A-C, the method 300 comprises a block 316 in which a first dielectric insulating layer 241 is deposited in the source / drain recesses 224. The first dielectric insulating layer 241 can contain silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, or another suitable insulating material. In one embodiment, the dielectric insulating layer 242 can be formed by filling the source / drain recesses 224 with dielectric insulating material (for example, by a CVD process or a spin-on-glass process) and back-etching the dielectric insulating material by a selective etching process. As described in Figures 17 and 24A-C, the method 300 comprises a block 316 in which a first dielectric insulating layer 241 is deposited in the source / drain recesses 224. Fig. As shown in Figure 24A, the first dielectric insulating layer 241 covers opposite side walls of at least the lowest channel layer 208 of the first stack 204a. In some embodiments, the first dielectric insulating layer 241 borders more than one lower channel layer 208 in the first stack 204a.

[0047] With reference to Fig. In sections 17 and 25A-C, process 300 comprises a block 318 in which a dielectric sacrificial layer 215 is deposited in the source / drain trenches 224 and covers the first dielectric insulating layer 241. The dielectric sacrificial layer 215 may contain silicon oxide, silicon oxycarbide, or a dielectric material that allows selective etching of the dielectric sacrificial layer 215 while leaving the internal spacer features 226 substantially intact. The dielectric sacrificial layer 215 may be deposited by CVD. The dielectric sacrificial layer 215 is then back-etched to expose the second stack 204b while the sidewalls of the first stack 204a remain covered. This means that after etching back the dielectric sacrificial layer 215, the side walls of the channel layers 208 of the second stack 204b and the respective internal spacer features located between them are exposed in the source / drain trenches 224.The etching process can be a dry etching process, a wet etching process, or a suitable etching process. The extent to which the dielectric sacrificial layer 215 is recessed is controlled by the duration of the etching process. The operations in block 118 further include conformal deposition of a third cover layer 225 on the workpiece 200. The sidewalls of the first stack 204b are covered by the third lining 225. The third lining 225 can contain silicon nitride, silicon carbonitride, or another suitable dielectric material that provides an etching difference to the dielectric sacrificial layer 215. The third lining 225 can be deposited by CVD, ALD, or another suitable deposition method.

[0048] With reference to Fig. In references 17 and 26A-C, process 300 comprises a block 320 in which the lateral portion of the third lining 225 is removed. By using anisotropic etching, such as RIE or another suitable dry etching process, the vertical portion of the third lining 225 covering the side walls of the second stack 204b remains, while the lateral portion of the third lining 225 is removed from the source / drain trenches 224, thereby exposing the dielectric sacrificial layer 215. The operations in block 320 further include the removal of the dielectric sacrificial layer 215 by a selective etching process to expose upper portions of the first stack 204a, with the bottommost channel layer 208 remaining covered by the first dielectric insulating layer 241.In an example where the dielectric sacrificial layer 215 is formed from an oxide and the internal spacer features 226, the third lining 225, and the first dielectric insulating layer 241 are formed from nitrides, the dielectric sacrificial layer 215 can be selectively etched using dilute hydrofluoric acid (DHF) or buffered hydrofluoric acid (BHF). The BHF contains hydrofluoric acid and ammonium fluoride. After completion of the operations in block 120, the sidewalls of the upper channel layers 208 of the first stack 204a in the source / drain trenches 224 are exposed, while the sidewalls of the channel layers 208 of the second stack 204b and an upper portion of the middle sacrificial layer 206M remain covered by the third lining 225.

[0049] With reference to Fig. In sections 17 and 27A-C, the process 300 comprises a block 322 in which a first source feature 228S and a first drain feature 228D are formed in the source / drain trenches 224. The first source feature 228S and the first drain feature 228D can be formed by an epitaxial process such as VPE, UHV-CVD, MBE, and / or other suitable processes. The epitaxial growth process can utilize gaseous and / or liquid precursors that interact with the channel layers 208. The exposed sidewalls of the channel layers 208 of the first stack 204a functionally serve as semiconductor seed layers. Thus, the epitaxial growth of the first source feature 228S and the first drain feature 228D can occur from the exposed sidewalls of the channel layers 208 of the first stack 204a, but not from those (for example, the lowest one in the drawing) adjacent to the first dielectric insulating layer 241. As in Fig. As shown in Figure 27A, the first source feature 228S and the first drain feature 228D are thus in physical contact with (or adjacent to) the upper channel layers 208 of the first stack 204a and form active channel layers. Since the bottommost channel layer 208 in the first stack 204a is covered by the first dielectric insulating layer 241, no epitaxial growth occurs from its sidewalls. Because the bottommost channel layer 208 of the first stack 204a is isolated from the first source feature 228S and the first drain feature 228D by the first dielectric insulating layer 241, it becomes a "floating" (or inactive) channel layer. Since the channel layers 208 in the second stack 204b are covered by the third lining 225, no epitaxial growth occurs from its sidewalls.The duration of epitaxial growth is controlled such that the first source feature 228S and the first drain feature 228D do not extend above the middle sacrificial layer 206M. The material compositions of the first source feature 228S and the first drain feature 228D have already been explained above, and their detailed description is omitted here.

[0050] With reference to Fig. In sections 17 and 28A-C, process 300 comprises a block 326 in which a first contact etch stop layer (CESL) 230 and a first ILD layer 232 are deposited on the first source feature 228S and the first drain feature 228D. The processes in block 326 are similar to those in block 126, and a detailed description is omitted for the sake of brevity.

[0051] With reference to Fig. In sections 17 and 29A-C, method 300 comprises a block 328 in which interconnect features such as a first drain contact 234, a first source contact 236, and a first source contact via 238 are formed. The processes in block 328 are similar to those in block 128, and a detailed description is omitted for the sake of brevity.

[0052] With further reference to Fig. In Figures 17 and 29A-C, the method 300 comprises a block 330 in which a second dielectric insulating layer 242 is deposited over the first ILD layer 232 and covers the interconnect features formed in previous operations in block 328. The second dielectric insulating layer 242 may contain silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, or another suitable insulating material. In one embodiment, the dielectric insulating layer 242 can be formed by filling the source / drain grooves 224 with dielectric insulating material (for example, by a CVD process or a spin-on-glass process) and back-etching the dielectric insulating material by a selective etching process. As described in Figures 17 and 29A-C, the method 300 comprises a block 330 in which a second dielectric insulating layer 242 is deposited over the first ILD layer 232 and covers the interconnect features formed in previous operations in block 328. Fig. As shown in Figure 29A, the dielectric insulating layer 242 covers the internal spacer features 226, which are present on the side walls of the middle sacrificial layer 206M, but not on the side walls of the lower channel layer 208 of the second stack 204b. In other words, the side walls of the lower channel layers 208 of the second stack 204 remain exposed in the source / drain trenches 224.

[0053] With reference to Fig. In sections 17 and 30A-C, the process 300 comprises a block 332 in which a second source feature 248S and a second drain feature 248D are formed in the source / drain trenches 224. The second source feature 248S and the second drain feature 248D can be formed by an epitaxial process such as VPE, UHV-CVD, MBE, and / or other suitable processes. The epitaxial growth process can utilize gaseous and / or liquid precursors that interact with the channel layers 208. The exposed sidewalls of the channel layers 208 of the second stack 204b functionally serve as semiconductor seed layers. Since no channel layers 208 adjoin the second dielectric insulating layer 242, the epitaxial growth of the second source feature 248S and the second drain feature 248D can occur from the exposed sidewalls of all channel layers 208 of the second stack 204b. As shown in Fig. As shown in Figure 30A, the second source feature 248S and the second drain feature 248D are thus in physical contact with (or adjacent to) each channel layer 208 of the second stack 204b, making all channel layers 208 of the second stack 204b active channel layers. The material compositions of the second source feature 248S and the second drain feature 248D have already been explained above, and a detailed description is omitted here.

[0054] With reference to Fig. In sections 17 and 31A-C, process 300 comprises a block 336 in which a second CESL layer 250 and a second ILD layer 252 are deposited on the second source feature 248S and the second drain feature 248D. The processes in block 336 are similar to those in block 136, and a detailed description is omitted for the sake of brevity.

[0055] With reference to Fig. In sections 17 and 32A-C, procedure 300 includes a block 338 in which the dummy gate stack 222 is removed and replaced by a common gate structure 254. The operations in block 338 are similar to those in block 138, and a detailed description is omitted for the sake of brevity.

[0056] With reference to Fig. In sections 17 and 33A-C, method 300 comprises a block 340 in which interconnect features, such as a second source contact 262, a second drain contact 264, a second source contact via 266, a second drain contact via 268, a first drain contact via 270, and an upper interconnect layer 272, are formed. The operations in block 340 are similar to those in block 140, and a detailed description is omitted for the sake of brevity.

[0057] It will now be on Fig. Reference is made to 33A-C. After completion of the operations in procedure 300, a lower GAA transistor 260a and an upper GAA transistor 260b are formed, the latter stacked on top of the lower GAA transistor 260a. The upper GAA transistor 260b has channel layers (or is referred to as channel elements) located between the second source feature 248S and the second drain feature 248D. The lower GAA transistor 260a comprises the same number of channel layers as the upper GAA transistor 260b. One difference is that not all channel layers of the lower GAA transistor 260a are located between the first source feature 248S and the first drain feature 248D and serve as active channel layers, allowing charge carriers to move through them. At least one lowest channel layer borders the first dielectric insulating layer 241 and becomes a “floating” (inactive) channel layer.Thus, the lower GAA transistor 260a has one fewer active channel layer than the upper GAA transistor 260b. In various embodiments, two or more lower channel layers of the lower GAA transistor 260a can be connected to the first dielectric insulating layer 241, and thus the lower GAA transistor 260a can have two or more fewer active channel layers than the upper GAA transistor 260b. A smaller number of active channel layers reduces the current control capability of the lower GAA transistor 260a, but this can compensate for the current output in the pair of stacked GAA transistors. For example, if the upper GAA transistor is a pFET and the lower GAA transistor is an nFET, an nFET often provides stronger current control capability due to its higher charge carrier mobility. Due to the reduction in the total number of active channel layers of the nFET, a balanced current output of the nFET and pFET pair can be achieved.

[0058] A common gate structure 254 wraps each channel layer of the upper GAA transistor and the lower GAA transistor 260a and 260b, with the second dielectric insulating layer 242 located between the first source 228S and the second source 248S, as well as between the first drain 228D and the second drain 248D. The first source feature 228S is coupled to a lower power rail via the first source contact 236 and the first source contact via 238. The second source feature 248S is coupled to the lower power rail via the second source contact 262 and the second source contact via 266. The first source contact via 238 and the second source contact via 266 are located on opposite sides of the first contact 228S. The first drain feature 228D is coupled to an upper busbar via the first drain contact 234 and the first drain contact via 270.The second drain feature 248D is coupled to the upper busbar via the second drain contact 264 and the second drain contact via 268. The upper busbar is located in the upper interconnect layer 272.

[0059] Reference is now made to procedure 500. Fig. Figure 34 shows a flowchart of Process 500 according to various aspects of the present disclosure. Throughout the present disclosure, similar reference symbols denote the same / similar features with respect to composition and formation. Some details of the operations in Process 500 may be simplified or omitted, provided that similar details are described above in connection with Process 100.

[0060] With reference to Fig. In sections 34 and 35A-C, the method 500 comprises a block 502 in which a workpiece 200 is provided. The workpiece 200 comprises a substrate section 202 (also referred to as the substrate) and a stacking section 204 above the substrate 202. The stacking section 204 comprises a first stack 204a and a second stack 204b above the first stack 204a. The substrate 202 and the stacking section 204 have already been explained above, and a detailed description is therefore omitted.

[0061] With reference to Fig. In sections 34 and 36A-C, process 500 comprises a block 504 in which a fin-shaped structure 209 is formed from the stacked section 204. The processes in block 504 are similar to those in block 104, and a detailed description is omitted for the sake of brevity.

[0062] As in Fig. As shown in Figures 34 and 36A-C, the process 500 comprises a block 506 in which the buried busbars 211 are formed. The processes in block 506 are similar to those in block 106, and a detailed description is omitted for the sake of brevity.

[0063] With reference to Fig. In sections 34 and 37A-C, process 500 comprises a block 508 in which an insulation feature 214 is formed. The processes in block 508 are similar to those in block 108, and a detailed description is omitted for the sake of brevity.

[0064] With reference to Fig. In sections 34 and 38A-C, procedure 500 comprises a block 510 in which a dummy gate stack 222 is formed above the stack section 204. The operations in block 510 are similar to those in block 110, and a detailed description is omitted for the sake of brevity.

[0065] With reference to Fig. In sections 34 and 39A-C, process 500 comprises a block 512 in which source / drain sections of the fin-shaped structure 209 are omitted to form source / drain recesses 224. The processes in block 512 are similar to those in block 112, and a detailed description is omitted for the sake of brevity.

[0066] With reference to Fig. In sections 34 and 40A-C, process 500 comprises a block 514 in which the internal spacer features 226 are formed. The processes in block 514 are similar to those in block 114, and a detailed description is omitted for the sake of brevity.

[0067] With reference to Fig. In sections 34 and 41A-C, process 500 comprises a block 518 in which a dielectric sacrificial layer 215 is deposited in the source / drain trenches 224 to cover the sidewalls of the channel layer 208 of the first stack 204a, and a third lining 225 is conformally deposited over the workpiece 200 to cover the sidewalls of the channel layer 208 of the second stack 204b. The operations in block 518 are similar to those in block 118, and a detailed description is omitted for the sake of brevity.

[0068] With reference to Fig. In sections 34 and 42A-C, process 500 comprises a block 520 in which a lateral section of the third lining 225 is removed to expose the dielectric sacrificial layer 215, and the dielectric sacrificial layer 215 is subsequently removed in a selective etching process to expose the first stack 204a. The operations in block 520 are similar to those in block 120, and a detailed description is omitted for the sake of brevity.

[0069] With reference to Fig. In sections 34 and 43A-C, the process 500 comprises a block 522 in which a first source feature 228S and a first drain feature 228D are formed in the source / drain trenches 224 adjacent to the channel layers 208 of the first stack 204a. Since the channel layers 208 in the second stack 204b are covered by the third lining 225, no epitaxial growth occurs from their sidewalls. The processes in block 522 are similar to those in block 122, and a detailed description is omitted for the sake of brevity.

[0070] With reference to Fig. In sections 34 and 44A-C, process 500 comprises a block 526 in which the third lining 225 is removed to expose the second stack 204b, and a first CESL layer 230 and a first ILD layer 232 are deposited on the first source feature 228S and the first drain feature 228D. The operations in block 526 are similar to those in block 126, and a detailed description is omitted for the sake of brevity.

[0071] With reference to Fig. In sections 34 and 45A-C, method 500 comprises a block 528 in which interconnect features such as a first drain contact 234, a first source contact 236, and a first source contact via 238 are formed. The processes in block 528 are similar to those in block 128, and a detailed description is omitted for the sake of brevity.

[0072] With further reference to Fig. In Figures 34 and 45A-C, the method 500 comprises a block 530 in which a dielectric insulating layer 242 is deposited over the first ILD layer 232 and covers the interconnect features formed in previous operations in block 528. The dielectric insulating layer 242 may contain silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, or another suitable insulating material. In one embodiment, the dielectric insulating layer 242 can be formed by filling the source / drain grooves 224 with dielectric insulating material (for example, by a CVD process or a spin-on-glass process) and back-etching the dielectric insulating material in a selective etching process. As described in Figures 34 and 45A-C, the method 500 comprises a block 530 in which a dielectric insulating layer 242 is deposited over the first ILD layer 232 and covers the interconnect features formed in previous operations in block 528. The dielectric insulating layer 242 may contain silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, or another suitable insulating material. Fig. As shown in Figure 45A, the dielectric insulating layer 242 covers the internal spacer features 226, which are located on the side walls of the middle sacrificial layer 206M, but not on the side walls of the lower channel layer 208 of the second stack 204b. In other words, the side walls of the lower channel layers 208 of the second stack 204b remain exposed in the source / drain trenches 224.

[0073] With reference to Fig. In sections 34 and 46A-C, the process 500 comprises a block 532 in which a second source feature 248S and a second drain feature 248D are formed in the source / drain trenches 224. The second source feature 248S and the second drain feature 248D can be formed by an epitaxial process, such as VPE, UHV-CVD, MBE, and / or other suitable processes. The epitaxial growth process can utilize gaseous and / or liquid precursors that interact with the channel layers 208. The exposed sidewalls of the channel layers 208 of the second stack 204b functionally serve as semiconductor seed layers. Since no channel layers 208 border the dielectric insulating layer 242, the epitaxial growth of the second source feature 248S and the second drain feature 248D can occur from the exposed sidewalls of all channel layers 208 of the second stack 204b. As shown in Fig. As shown in Figure 46A, the second source feature 228S and the second drain feature 228D are thus in physical contact with (or adjacent to) each channel layer 208 of the second stack 204a. The material compositions of the second source feature 228S and the second drain feature 228D are explained above, and a detailed description is omitted for the sake of brevity.

[0074] With reference to Fig. In sections 34 and 47A-C, the process 500 comprises a block 534 in which the second source feature 248S and the second drain feature 248D are back-etched to expose at least the topmost channel layer 208 in the second stack 204b, thereby exposing its sidewalls. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. As in Fig. As shown in Figure 47A, the upper surfaces of the second source feature 248S and the second drain feature 248D are recessed beneath the topmost channel layer 208, but continue to cover other channel layers 208 below. In some embodiments, the upper surfaces of the second source feature 248S and the second drain feature 248D are recessed beneath two or more topmost channel layers 208 in the second stack 204b.

[0075] With reference to Fig. In Figures 34 and 48A-C, the method 500 comprises a block 536 in which a second CESL 250 and a second ILD layer 252 are deposited on the second source feature 248S and the second drain feature 248D. In some embodiments, the second CESL 250 is first conformally deposited on the workpiece 200 by ALD, plasma-enhanced chemical vapor deposition (PECVD), and / or other suitable deposition or oxidation processes. The conformal second CESL 250 covers the recessed upper surfaces of the second source feature 248S and the second drain feature 248D and further covers the exposed sidewalls of the top channel layer 208 in the second stack 204b. Isolated by the second CESL 250 from the second source feature 248S and the second drain feature 248D, the top channel layer 208 in the second stack 204b becomes a “floating” (or inactive) channel layer.The second ILD layer 252 is deposited over the second CESL 250 by a PECVD process or another suitable deposition technique. The material compositions of the second CESL 250 and the second ILD layer 252 are explained above, and a detailed description is omitted for the sake of brevity. A planarization process, for example, a chemical-mechanical polishing (CMP) process, can be performed to remove excess material and expose the top surfaces of the dummy gate stacks 222. In some embodiments, the gate-top hard mask layer 220 is removed by the CMP process, and the dummy gate electrode layer 218 is exposed.

[0076] With reference to Fig. In sections 34 and 49A-C, procedure 500 includes a block 538 in which the dummy gate stack 222 is removed and replaced by a common gate structure 254. The operations in block 538 are similar to those in block 138, and a detailed description is omitted for the sake of brevity.

[0077] With reference to Fig. In sections 34 and 50A-C, method 500 comprises a block 540 in which interconnect features such as a second source contact 262, a second drain contact 264, a second source contact via 266, a second drain contact via 268, a first drain contact via 270, and an upper interconnect layer 272 are formed. The operations in block 540 are similar to those in block 140, and a detailed description is omitted for the sake of brevity.

[0078] It will now be on Fig. Reference is made to 50A-C. After completion of the operations in Procedure 100, a lower GAA transistor 260a and an upper GAA transistor 260b are formed, the latter stacked on top of the lower GAA transistor 260a. The lower GAA transistor 260a has channel layers (or is referred to as channel elements) located between the first source feature 228S and the first drain feature 228D. The upper GAA transistor 260b has the same number of channel layers as the lower GAA transistor 260a. One difference is that not all channel layers of the upper GAA transistor 260b are located between the second source feature 248S and the second drain feature 248D and serve as active channel layers, allowing charge carriers to move through them. At least one uppermost channel layer borders the second CESL 250 and becomes a “floating” (inactive) channel layer.Thus, the upper GAA transistor 260b has one fewer active channel layer than the lower GAA transistor 260a. In various embodiments, two or more upper channel layers of the upper GAA transistor 260b can be adjacent to the second CESL 250, and therefore the upper GAA transistor 260b can have two or more fewer active channel layers than the lower GAA transistor 260a. A smaller number of active channel layers reduces the current control capability of the upper GAA transistor 260b, but this can compensate for the current output in the pair of stacked GAA transistors. For example, if the upper GAA transistor is an nFET and the lower GAA transistor is a pFET, an nFET often provides stronger current control capability due to its higher charge carrier mobility. Due to the reduction in the total number of active channel layers of the nFET, a balanced current output can be achieved from the pair of nFET and pFET.

[0079] A common gate structure 254 wraps each channel layer of the upper GAA transistor and the lower GAA transistors 260a and 260b, while the dielectric isolation layer 242 lies between the first source 228S and the second source 248S, as well as between the first drain 228D and the second drain 248D. The first source feature 228S is coupled to a lower power rail via the first source contact 236 and the first source contact via 238. The second source feature 248S is coupled to the lower power rail via the second source contact 262 and the second source contact via 266. The first source contact via 238 and the second source contact via 266 are located on opposite sides of the first contact 228S. The first drain feature 228D is coupled to an upper busbar via the first drain contact 234 and the first drain contact via 270.The second drain feature 248D is coupled to the upper busbar via the second drain contact 264 and the second drain contact via 268. The upper busbar is located in the upper interconnect layer 272.

[0080] Reference is now made to procedure 700. Fig. Figure 51 shows a flowchart of Process 500 according to various aspects of the present disclosure. Throughout the present disclosure, similar reference symbols denote the same / similar features with respect to composition and formation. Some details of the operations in Process 700 may be simplified or omitted, provided that similar details are explained above in connection with Process 100.

[0081] With reference to Fig. In sections 51 and 52A-C, the method 700 comprises a block 702 in which a workpiece 200 is provided. The workpiece 200 comprises a substrate section 202 (also referred to as the substrate) and a stacking section 204 above the substrate 202. The stacking section 204 comprises a first stack 204a and a second stack 204b above the first stack 204a. The substrate 202 and the stacking section 204 have already been explained above, and a detailed description is omitted for the sake of brevity.

[0082] With reference to Fig. In sections 51 and 53A-C, process 700 comprises a block 704 in which a fin-shaped structure 209 is formed from the stacked section 204. The processes in block 704 are similar to those in block 104, and a detailed description is omitted for the sake of brevity.

[0083] As in Fig. As shown in Figures 51 and 53A-C, the procedure 700 comprises a block 706 in which the buried busbars 211 are formed. The processes in block 706 are similar to those in block 106, and a detailed description is omitted for the sake of brevity.

[0084] With reference to Fig. In sections 51 and 54A-C, process 700 comprises a block 708 in which an insulation feature 214 is formed. The processes in block 708 are similar to those in block 108, and a detailed description is omitted for the sake of brevity.

[0085] With reference to Fig. In sections 51 and 55A-C, procedure 700 comprises a block 710 in which a dummy gate stack 222 is formed above the stack section 204. The operations in block 710 are similar to those in block 110, and a detailed description is omitted for the sake of brevity.

[0086] With reference to Fig. In sections 51 and 56A-C, process 700 comprises a block 712 in which source / drain sections of the fin-shaped structure 209 are omitted to form source / drain recesses 224. The processes in block 712 are similar to those in block 112, and a detailed description is omitted for the sake of brevity.

[0087] With reference to Fig. In sections 51 and 57A-C, process 700 comprises a block 714 in which the internal spacer features 226 are formed. The processes in block 714 are similar to those in block 114, and a detailed description is omitted for the sake of brevity.

[0088] With reference to Fig. In references 51 and 58A-C, process 700 comprises a block 718 in which a dielectric sacrificial layer 215 is deposited in the source / drain trenches 224 to cover the sidewalls of the channel layer 208 of the first stack 204a, and a third lining 225 is conformally deposited over the workpiece 200 to cover the sidewalls of the channel layer 208 of the second stack 204b. The operations in block 718 are similar to those in block 118, and a detailed description is omitted for the sake of brevity.

[0089] With reference to Fig. In sections 51 and 59A-C, process 700 comprises a block 720 in which a lateral section of the third lining 225 is removed to expose the dielectric sacrificial layer 215, and the dielectric sacrificial layer 215 is subsequently removed by a selective etching process to expose the first stack 204a. The operations in block 520 are similar to those in block 120, and a detailed description is omitted for the sake of brevity.

[0090] With reference to Fig. In sections 51 and 60A-C, process 700 comprises a block 722 in which a first source feature 228S and a first drain feature 228D are formed in the source / drain trenches 224 adjacent to the channel layers 208 of the first stack 204a. Since the channel layers 208 in the second stack 204b are covered by the third lining 225, no epitaxial growth occurs from their sidewalls. The processes in block 722 are similar to those in block 122, and a detailed description is omitted for the sake of brevity.

[0091] With reference to Fig. In sections 51 and 61A-C, process 700 comprises a block 724 in which the first source feature 228S and the first drain feature 228D are back-etched to expose at least the topmost channel layer 208 in the first stack 204a, thereby exposing its sidewalls. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. As in Fig. As shown in Figure 61A, the upper surfaces of the first source feature 228S and the first drain feature 228D are recessed beneath the topmost channel layer 208 in the first stack 204a, but continue to cover other channel layers 208 below. In some embodiments, the upper surfaces of the first source feature 228S and the first drain feature 228D are recessed beneath two or more topmost channel layers 208 in the first stack 204a.

[0092] With reference to Fig. In references 51 and 62A-C, the method 700 comprises a block 726 in which the third lining 225 is removed to expose the second stack 204b, and a first CESL 230 and a first ILD layer 232 are deposited on the first source feature 228S and the first drain feature 228D. In some embodiments, the first CESL 230 is first conformally deposited on the workpiece 200 by ALD, plasma-enhanced chemical vapor deposition (PECVD), and / or other suitable deposition or oxidation processes. The first ILD layer 232 is deposited over the first CESL 230 by a PECVD process or another suitable deposition method. Subsequently, the first CESL 230 and the first ILD layer 232 are back-etched to expose the second stack 204b.The conformal first CESL 230 further covers the recessed upper surfaces of the first source feature 228S and the first drain feature 228D and also covers the exposed sidewalls of the top channel layer 208 in the first stack 204a. Isolated from the first source feature 228S and the first drain feature 228D by the first CESL 230, the top channel layer 208 in the first stack 204a becomes a "floating" (or inactive) channel layer. The material compositions of the first CESL 230 and the first ILD layer 232 have already been explained above, and a detailed description is omitted for the sake of brevity.

[0093] With reference to Fig. In sections 51 and 63A-C, method 700 comprises a block 728 in which interconnect features such as a first drain contact 234, a first source contact 236, and a first source contact via 238 are formed. The processes in block 528 are similar to those in block 128, and a detailed description is omitted for the sake of brevity.

[0094] With further reference to Fig. In Figures 51 and 63A-C, the method 700 comprises a block 730 in which a dielectric insulating layer 242 is deposited over the first ILD layer 232, covering the interconnect features formed in previous operations in block 528. The dielectric insulating layer 242 may contain silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, or another suitable insulating material. In one embodiment, the dielectric insulating layer 242 can be formed by filling the source / drain grooves 224 with dielectric insulating material (for example, by a CVD process or a spin-on-glass process) and back-etching the dielectric insulating material by a selective etching process. As described in Figures 51 and 63A-C, the method 700 comprises a block 730 in which a dielectric insulating layer 242 is deposited over the first ILD layer 232 and the interconnect features are covered in previous operations in block 528. The dielectric insulating layer 242 may contain silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, or another suitable insulating material. Fig. As shown in Figure 63A, the dielectric insulating layer 242 covers the internal spacer features 226, which are located on the side walls of the middle sacrificial layer 206M, but not on the side walls of the lower channel layer 208 of the second stack 204b. In other words, the side walls of the lower channel layers 208 in the second stack 204b remain exposed in the source / drain trenches 224.

[0095] With reference to Fig. In sections 51 and 64A-C, the process 700 comprises a block 732 in which a second source feature 248S and a second drain feature 248D are formed in the source / drain trenches 224. The second source feature 248S and the second drain feature 248D can be formed by an epitaxial process such as VPE, UHV-CVD, MBE, and / or other suitable processes. The epitaxial growth process can utilize gaseous and / or liquid precursors that interact with the channel layers 208. The exposed sidewalls of the channel layers 208 of the second stack 204b functionally serve as semiconductor seed layers. Since no channel layers 208 border the dielectric insulating layer 242, the epitaxial growth of the second source feature 248S and the second drain feature 248D can occur from the exposed sidewalls of all channel layers 208 of the second stack 204b. As shown in Fig. As shown in Figure 46A, the second source feature 248S and the second drain feature 248D are thus in physical contact with (or adjacent to) each channel layer 208 of the second stack 204b. The material compositions of the second source feature 248S and the second drain feature 248D have been explained above, and a detailed description is omitted for the sake of brevity.

[0096] With reference to Fig. In sections 51 and 65A-C, process 700 comprises a block 736 in which a second CESL layer 250 and a second ILD layer 252 are deposited on the second source feature 248S and the second drain feature 248D. The processes in block 736 are similar to those in block 136, and a detailed description is omitted for the sake of brevity.

[0097] With reference to Fig. In sections 51 and 66A-C, procedure 700 includes a block 738 in which the dummy gate stack 222 is removed and replaced by a common gate structure 254. The operations in block 738 are similar to those in block 138, and a detailed description is omitted for the sake of brevity.

[0098] With reference to Fig. In sections 51 and 67A-C, method 700 comprises a block 740 in which interconnect features, such as a second source contact 262, a second drain contact 264, a second source contact via 266, a second drain contact via 268, a first drain contact via 270, and an upper interconnect layer 272, are formed. The operations in block 540 are similar to those in block 140, and a detailed description is omitted for the sake of brevity.

[0099] It will now be on Fig. Reference is made to 67A-C. After completion of the operations in Procedure 700, a lower GAA transistor 260a and an upper GAA transistor 260b are formed, the latter stacked on top of the lower GAA transistor 260a. The upper GAA transistor 260b has channel layers (or is referred to as channel elements) located between the second source feature 248S and the second drain feature 248D. The lower GAA transistor 260a comprises the same number of channel layers as the upper GAA transistor 260b. One difference is that not all of the channel layers of the lower GAA transistor 260a are located between the first source feature 248S and the first drain feature 248D and serve as active channel layers, allowing charge carriers to move through them. At least one uppermost channel layer borders the first CESL 230 and becomes a "floating" (inactive) channel layer.Thus, the lower GAA transistor 260a has one fewer active channel layer than the upper GAA transistor 260b. In various embodiments, two or more upper channel layers of the lower GAA transistor 260a can be adjacent to the first CESL 230, and therefore the lower GAA transistor 260a can have two or more fewer active channel layers than the upper GAA transistor 260b. A smaller number of active channel layers reduces the current control capability of the lower GAA transistor 260a, which, however, can compensate for the current output in the pair of stacked GAA transistors. For example, if the upper GAA transistor is a pFET and the lower GAA transistor is an nFET, an nFET often provides stronger current control capability due to its higher charge carrier mobility. Due to the reduction in the total number of active channel layers of the nFET, a balanced current output can be achieved from the pair of nFET and pFET.

[0100] A common gate structure 254 wraps each channel layer of the upper GAA transistor and the lower GAA transistors 260a and 260b, while the dielectric insulating layer 242 lies between the first source 228S and the second source 248S, as well as between the first drain 228D and the second drain 248D. The first source feature 228S is coupled to a lower power rail via the first source contact 236 and the first source contact via 238. The second source feature 248S is coupled to the lower power rail via the second source contact 262 and the second source contact via 266. The first source contact via 238 and the second source contact via 266 are located on opposite sides of the first contact 228S. The first drain feature 228D is coupled to an upper busbar via the first drain contact 234 and the first drain contact via 270.The second drain feature 248D is coupled to the upper busbar via the second drain contact 264 and the second drain contact via 268. The upper busbar is located in the upper interconnect layer 272.

[0101] Reference is now made to procedure 900. Fig. Figure 68 shows a flowchart of Process 900 according to various aspects of the present disclosure. Throughout the present disclosure, similar reference symbols denote the same / similar characteristics with respect to composition and formation. Some details of the processes in Process 900 may be simplified or omitted if similar details have already been described above in connection with Process 100.

[0102] With reference to Fig. In references 68 and 69A-C, the method 900 comprises a block 902 in which a workpiece 200 is provided. The workpiece 200 comprises a substrate section 202 (also referred to as the substrate) and a stack section 204 above the substrate 202. The stack section 204 comprises a first stack 204a and a second stack 204b above the first stack 204a, the first stack 204a having one or more channel layers 208 than the second stack 204b. The material compositions of the substrate 202 and the stack section 204 are explained above, and a detailed description is omitted for the sake of brevity.

[0103] With reference to Fig. In sections 68 and 70A-C, process 900 comprises a block 904 in which a fin-shaped structure 209 is formed from the stacked section 204. The processes in block 904 are similar to those in block 104, and a detailed description is omitted for the sake of brevity.

[0104] As in the Fig. As shown, procedure 900 comprises a block 906 in which the buried busbars 211 are formed. The processes in block 906 are similar to those in block 106, and a detailed description is omitted for the sake of brevity.

[0105] With reference to Fig. In sections 68 and 71A-C, process 900 comprises a block 908 in which an insulation feature 214 is formed. The processes in block 908 are similar to those in block 108, and a detailed description is omitted for the sake of brevity.

[0106] With reference to Fig. In sections 68 and 72A-C, procedure 900 comprises a block 910 in which a dummy gate stack 222 is formed above the stack section 204. The operations in block 310 are similar to those in block 110, and a detailed description is omitted for the sake of brevity.

[0107] With reference to Fig. In sections 68 and 73A-C, process 900 comprises a block 912 in which source / drain sections of the fin-shaped structure 209 are omitted to form source / drain recesses 224. The processes in block 912 are similar to those in block 112, and a detailed description is omitted for the sake of brevity.

[0108] With reference to Fig. In sections 68 and 74A-C, process 900 comprises a block 914 in which the internal spacer features 226 are formed. The processes in block 914 are similar to those in block 114, and a detailed description is omitted for the sake of brevity.

[0109] With reference to Fig. In references 68 and 75A-C, process 900 comprises a block 918 in which a dielectric sacrificial layer 215 is deposited in the source / drain trenches 224 to cover the sidewalls of the channel layer 208 in the first stack 204a, and a third lining 225 is conformally deposited over the workpiece 200 to cover the sidewalls of the channel layer 208 in the second stack 204b. The operations in block 918 are similar to those in block 118, and a detailed description is omitted for the sake of brevity.

[0110] With reference to Fig. In references 68 and 76A-C, process 900 comprises a block 920 in which a lateral section of the third lining 225 is removed to expose the dielectric sacrificial layer 215, and the dielectric sacrificial layer 215 is subsequently removed by a selective etching process to expose the first stack 204a. The operations in block 920 are similar to those in block 120, and a detailed description is omitted for the sake of brevity.

[0111] With reference to Fig. In sections 68 and 77A-C, process 900 comprises a block 922 in which a first source feature 228S and a first drain feature 228D are formed in the source / drain trenches 224 adjacent to the channel layers 208 of the first stack 204a. Since the channel layers 208 in the second stack 204b are covered by the third lining 225, no epitaxial growth occurs from their sidewalls. The processes in block 922 are similar to those in block 122, and a detailed description is omitted for the sake of brevity.

[0112] With reference to Fig. In sections 68 and 78A-C, process 900 comprises a block 926 in which the third lining 225 is removed to expose the second stack 204b, and a first CESL layer 230 and a first ILD layer 232 are deposited on the first source feature 228S and the first drain feature 228D. The operations in block 926 are similar to those in block 126, and a detailed description is omitted for the sake of brevity.

[0113] With reference to Fig. Procedure 900, as described in sections 68 and 79A-C, includes a block 928 in which interconnect features, such as a first drain contact 234, a first source contact 236, and a first source contact via 238, are formed. The processes in block 928 are similar to those in block 128, and a detailed description is omitted for the sake of brevity.

[0114] With further reference to Fig. In Figures 68 and 79A-C, the process 900 comprises a block 930 in which a dielectric insulating layer 242 is deposited over the first ILD layer 232 and covers the interconnect features formed in previous operations in block 528. The dielectric insulating layer 242 may contain silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, or another suitable insulating material. In one embodiment, the dielectric insulating layer 242 can be formed by filling the source / drain grooves 224 with dielectric insulating material (for example, by a CVD process or a spin-on-glass process) and back-etching the dielectric insulating material by a selective etching process. As described in Figures 68 and 79A-C, the process 900 comprises a block 930 in which a dielectric insulating layer 242 is deposited over the first ILD layer 232 and covers the interconnect features formed in previous operations in block 528. The dielectric insulating layer 242 may contain silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, or another suitable insulating material. Fig. As shown in Figure 79A, the dielectric insulating layer 242 covers the internal spacer features 226, which are located on the side walls of the middle sacrificial layer 206M, but not on the side walls of the lower channel layer 208 of the second stack 204b. In other words, the side walls of the lower channel layers 208 of the second stack 204b remain exposed in the source / drain trenches 224.

[0115] With reference to Fig. In sections 68 and 80A-C, the process 900 comprises a block 932 in which a second source feature 248S and a second drain feature 248D are formed in the source / drain trenches 224. The second source feature 248S and the second drain feature 248D can be formed using an epitaxial process, such as VPE, UHV-CVD, MBE, and / or other suitable processes. The epitaxial growth process can utilize gaseous and / or liquid precursors that interact with the channel layers 208. The exposed sidewalls of the channel layers 208 of the second stack 204b functionally serve as semiconductor seed layers. Since no channel layers 208 border the dielectric insulating layer 242, the epitaxial growth of the second source feature 248S and the second drain feature 248D can occur from the exposed sidewalls of all channel layers 208 of the second stack 204b. As shown in Fig. As shown in Figure 80A, the second source feature 248S and the second drain feature 248D are thus in physical contact with (or adjacent to) each channel layer 208 in the second stack 204b. The material compositions of the second source feature 248S and the second drain feature 248D are explained above, and a detailed description is omitted for the sake of brevity.

[0116] With reference to Fig. In sections 68 and 81A-C, process 900 comprises a block 936 in which a second CESL 250 and a second ILD layer 252 are deposited on the second source feature 248S and the second drain feature 248D. The processes in block 936 are similar to those in block 136, and a detailed description is omitted for the sake of brevity.

[0117] With reference to Fig. In sections 68 and 82A-C, procedure 900 includes a block 938 in which the dummy gate stack 222 is removed and replaced by a common gate structure 254. The operations in block 938 are similar to those in block 138, and a detailed description is omitted for the sake of brevity.

[0118] With reference to Fig. In sections 68 and 83A-C, method 900 comprises a block 940 in which interconnect features such as a second source contact 262, a second drain contact 264, a second source contact via 266, a second drain contact via 268, a first drain contact via 270, and an upper interconnect layer 272 are formed. The operations in block 940 are similar to those in block 140, and a detailed description is omitted for the sake of brevity.

[0119] It will now be on Fig. Reference is made to 83A-C. After completion of the operations in Procedure 900, a lower GAA transistor 260a and an upper GAA transistor 260b are formed, stacked above the lower GAA transistor 260a. The upper GAA transistor 260b contains channel layers (or is referred to as channel elements) located between the second source feature 248S and the second drain feature 248D. The lower GAA transistor 260a contains channel layers located between the first source feature 228S and the first drain feature 228D. Each channel layer 208 in the first stack 204a and the second stack 204b is an active channel layer. One difference is that the lower GAA transistor 260a has at least one more channel layer 208 than the upper GAA transistor 260b, since the first stack 204a has at least one more channel layer 208 than the second stack 204b.Thus, the lower GAA transistor 260a has at least one more active channel layer than the upper GAA transistor 260b. In various embodiments, the lower GAA transistor 260a can have two or more active channel layers than the upper GAA transistor 260b. Alternatively, if the process 900 begins in block 902 with a second stack 204b having at least one more channel layer 208 than the first stack 204b, the upper GAA transistor 260b would, after completion of the operations in process 900, thus have at least one more active channel layer than the lower GAA transistor 260a. Such an alternative embodiment of process 900 is described in [reference]. Fig. Figure 84A-C is shown. According to the alternative embodiment, the upper GAA transistor 260b can have two or more active channel layers than the lower GAA transistor 260a.

[0120] In both in Fig. In embodiments 83A-C and 84A-C, a common gate structure 254 surrounds each channel layer of the upper GAA transistor and the lower GAA transistor 260a and 260b, wherein the second dielectric insulating layer 242 is located between the first source 228S and the second source 248S, and also between the first drain 228D and the second drain 248D. The first source feature 228S is coupled to a lower bus via the first source contact 236 and the first source contact via 238. The second source feature 248S is coupled to the lower bus via the second source contact 262 and the second source contact via 266. The first source contact via 238 and the second source contact via 266 are arranged on opposite sides of the first contact 228S.The first drain feature 228D is coupled to an upper busbar via the first drain contact 234 and the first drain contact via 270. The second drain feature 248D is coupled to the upper busbar via the second drain contact 264 and the second drain contact via 268. The upper busbar is located in the upper interconnect layer 272.

[0121] Reference is now made to procedure 1100. Fig. Figure 85 shows a flowchart of process 1100 according to various aspects of the present disclosure. Throughout the present disclosure, similar reference numerals denote the same / similar features with respect to composition and design. Some details of the processes in process 1100 may be simplified or omitted, provided that similar details are described above in connection with process 100.

[0122] With reference to Fig. In sections 85 and 86A-C, method 1100 comprises a block 1102 in which a workpiece 200 is provided. The workpiece 200 contains a substrate 202 and a first stack 204 above the substrate 202. The first stack 204 comprises several channel layers 208, which are nested with several sacrificial layers 206. It should be noted that in Fig. Figure 86A-C shows three (3) layers of the channel layers 208 in the first stack 204a, which serves only for illustration and is not intended as a limitation of the subject matter of the claims. It is conceivable that any number of channel layers 208 can be formed in the first stack 204a. The number of layers depends on the desired number of channel elements for the device 200. In some embodiments, the number of channel layers 208 in the first stack 204a is between 2 and 10. The material compositions of the substrate 202 and the first stack 204a are explained above, and a detailed description is omitted for the sake of brevity.

[0123] With reference to Fig. In sections 85 and 87A-C, process 1100 comprises a block 1104 in which a fin-shaped structure 209 is formed from the first stack 204a. The processes in block 1104 are similar to those in block 104, and a detailed description is omitted for the sake of brevity.

[0124] With further reference to Fig. In sections 85 and 87A-C, procedure 1100 comprises a block 1106 in which buried busbars 211 are formed. The processes in block 1106 are similar to those in block 106, and a detailed description is omitted for the sake of brevity.

[0125] With reference to Fig. In sections 85 and 88A-C, process 1100 comprises a block 1108 in which an insulation feature 214 is formed. The processes in block 1108 are similar to those in block 108, and a detailed description is omitted for the sake of brevity.

[0126] With reference to Fig. In sections 85 and 89A-C, procedure 1100 comprises a block 1110 in which a dummy gate stack 222 is formed above the stack section 204. The operations in block 310 are similar to those in block 110, and a detailed description is omitted for the sake of brevity.

[0127] With reference to Fig. In sections 85 and 90A-C, process 1100 comprises a block 1112 in which source / drain sections of the fin-shaped structure 209 are omitted to form source / drain recesses 224. The processes in block 1112 are similar to those in block 112, and a detailed description is omitted for the sake of brevity.

[0128] With reference to Fig. In sections 85 and 91A-C, process 1100 comprises a block 1114 in which the internal spacer features 226 are formed. The processes in block 1114 are similar to those in block 114, and a detailed description is omitted for the sake of brevity.

[0129] With reference to Fig. In sections 85 and 92A-C, process 1100 comprises a block 1116 in which a first source feature 228S and a first drain feature 228D are formed in the source / drain trenches 224, which adjoin the channel layers 208 of the first stack 204a. The processes in block 1116 are similar to those in block 122, and a detailed description is omitted for the sake of brevity.

[0130] With reference to Fig. In sections 85 and 93A-C, process 1100 comprises a block 1118 in which a first CESL layer 230 and a first ILD layer 232 are deposited on the first source feature 228S and the first drain feature 228D. The operations in block 1118 are similar to those in block 126, and a detailed description is omitted for the sake of brevity. A planarization process, such as a chemical-mechanical polishing (CMP) process, can be performed to remove excess material and expose the top surfaces of the dummy gate stacks 222. In some embodiments, the gate-top hard mask layer 220 is removed in the CMP process, and the dummy gate electrode layer 218 is exposed.

[0131] With reference to Fig. In sections 85 and 94A-C, procedure 1100 includes a block 1120 in which the dummy gate stack 222 is removed and replaced by a first gate structure 254a. The operations in block 1120 are similar to those in block 138, and a detailed description is omitted for the sake of brevity.

[0132] With reference to Fig. In sections 85 and 95A-C, method 1100 comprises a block 1122 in which interconnect features, such as a first drain contact 234, a first source contact 236, and a first source contact via 238, are formed. The processes in block 1122 are similar to those in block 128, and a detailed description is omitted for the sake of brevity.

[0133] With reference to Fig. In accordance with documents 85 and 96A-C, method 1100 comprises a block 1124 in which a dielectric insulating layer 242 is deposited over the first ILD layer 232 and covers the interconnect features formed in previous operations in block 1122. The dielectric insulating layer 242 may contain silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, or another suitable insulating material. In one embodiment, the dielectric insulating layer 242 may be formed by CVD, PECVD, or another suitable method.

[0134] With further reference to Fig. In sections 85 and 96A-C, the process 1100 comprises a block 1126 in which a second stack 204b is bonded to the top of the workpiece 200. Like the first stack 204a, the second stack 204b also contains several channel layers 208 nested with several sacrificial layers 206. In the Fig. In the embodiments shown in Figure 96A, the first stack 204a and the second stack 204b have different numbers of channel layers 208. In the illustrated embodiment, the first stack 204a has, in particular, more channel layers 208 than the second stack 204b. However, the present disclosure is not limited to the first stack 204a having fewer channel layers 208 than the second stack 204b or having different configurations, such as different layer thicknesses. To facilitate bonding, an adhesive layer (not explicitly shown) may be formed on a lower surface of the second stack 204b. The second stack 204b and the adhesive layer can be considered a separate substrate, as opposed to the substrate 202. In some embodiments, the adhesive layer comprises silicon oxide and may also be referred to as an adhesive oxide layer.In some embodiments, the second stack 204b can be bonded directly to the workpiece 200 by utilizing the interface between the dielectric insulating layer 242 and the adhesive layer. In an exemplary direct bonding process, both the dielectric insulating layer 242 and the adhesive layer are cleaned using RCA SC-1 (ammonia, hydrogen peroxide, and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). The cleaned dielectric insulating layer 242 and the adhesive layer are then joined and pressed together. The direct bond can be strengthened by a tempering process. In some alternative embodiments, the sacrificial layers 206 and channel layers 208 in the second stack 204b are epitaxial layers and can be deposited onto the workpiece 200 by an epitaxial process.Suitable epitaxy processes include gas phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE) and / or other suitable processes.

[0135] With reference to Fig. In sections 85 and 97A-C, procedure 1100 includes a block 1128 in which the operations in blocks 1104, 1110-1120 are performed for the second stack 204b. Due to the similarity of the process steps, the operations in block 1128 are summarized below for simplicity. In block 1104, the second stack 204b is structured to form a second fin-shaped structure. In block 1110, a second dummy gate stack is formed over the channel area of ​​the second fin-shaped structure to serve as a placeholder for a functional second gate structure. In block 1112, the source / drain section of the second fin-shaped structure is recessed to form source / drain recesses, similar to the source / drain trenches 224.In block 1114, the sacrificial layers 206 in the channel region are selectively and partially etched to form internal spacer recesses, and internal spacer features are formed in such internal spacer recesses. In block 1116, a second source feature 248S and a second drain feature 248D are formed in the source / drain recesses. In block 1118, a second CESL 250 and a second ILD layer 252 are deposited on the second source feature 248S and the second drain feature 248D. In block 1120, the dummy gate stack above the second fin-shaped structure is replaced by a second gate structure 254b. The sacrificial layers 206 in the channel region are selectively removed to expose the channel layers 208 as channel elements, and the second gate structure 254b wraps around each of the channel elements in the second stack 204b.

[0136] With reference to Fig. In sections 85 and 98A-C, method 1100 comprises a block 1130 in which interconnect features, such as a second source contact 262, a second drain contact 264, a second source contact via 266, a second drain contact via 268, a first drain contact via 270, and an upper interconnect layer 272, are formed. The operations in block 1130 are similar to those in block 140, and a detailed description is omitted for the sake of brevity.

[0137] It will now be on Fig. Reference is made to 98A-C. After completion of the operations in procedure 1100, a lower GAA transistor 260a and an upper GAA transistor 260b are formed, the latter stacked above the lower GAA transistor 260a. The upper GAA transistor and the lower GAA transistor are separated from each other by a dielectric insulating layer 242. The upper GAA transistor 260b has channel layers (or is referred to as channel elements) located between the second source feature 248S and the second drain feature 248D. The lower GAA transistor 260a has channel layers located between the first source feature 228S and the first drain feature 228D. Each channel layer 208 in the first stack 204a and the second stack 204b is an active channel layer.One difference is that the lower GAA transistor 260a has at least one more channel layer 208 than the upper GAA transistor 260b, since the first stack 204a has at least one more channel layer 208 than the second stack 204b. Thus, the lower GAA transistor 260a has at least one more active channel layer than the upper GAA transistor 260b. In various embodiments, the lower GAA transistor 260a can have two or more active channel layers than the upper GAA transistor 260b. Alternatively, if the process 900 in block 902 begins with a second stack 204b that has at least one more channel layer 208 than the first stack 204b, then after completion of the operations in process 900, the upper GAA transistor 260b would have at least one more active channel layer than the lower GAA transistor 260a.According to another alternative embodiment, the upper GAA transistor 260b can have two or more active channel layers than the lower GAA transistor 260a.

[0138] A first gate structure 254a wraps each channel layer of the lower GAA transistor 260a. A second gate structure 254b wraps each channel layer of the upper GAA transistor 260b. The dielectric insulating layer 242 lies between the first gate structure 254a and the second gate structure 254b, between the first source 228S and the second source 248S, and also between the first drain 228D and the second drain 248D. The first source feature 228S is coupled to a lower power rail via the first source contact 236 and the first source contact via 238. The second source feature 248S is coupled to the lower power rail via the second source contact 262 and the second source contact via 266. The first source contact via 238 and the second source contact via 266 are arranged on two sides of the first contact 228S.The first drain feature 228D is coupled to an upper busbar via the first drain contact 234 and the first drain contact via 270. The second drain feature 248D is coupled to the upper busbar via the second drain contact 264 and the second drain contact via 268. The upper busbar is located in the upper interconnect layer 272.

[0139] Fig. 99 and Fig. Figure 100 illustrates some embodiments of a workpiece with a lower GAA transistor 260a and an upper GAA transistor 260b stacked above the lower GAA transistor 260a, using methods 100, 300, 500, 700, 900, 1100, or combinations thereof. Examples I-XV in Fig. 99 and Fig. The number 100 is for illustrative purposes only and is not limiting. For example, the difference in the number of active channel layers between stacked GAA transistors formed by the illustrated methods could be two, three, or even more.

[0140] Example I illustrates an embodiment in which a workpiece is formed by method 100. The lower GAA transistor 260a has channel layers located between the first source / drain features. The upper GAA transistor 260b has the same number of channel layers as the lower GAA transistor 260a. One difference is that not all channel layers of the upper GAA transistor 260b are located between the second source / drain features and can serve as active channel layers. At least one bottommost channel layer borders a dielectric insulating layer 242 and becomes a "floating" (inactive) channel layer. Thus, the upper GAA transistor 260b has one fewer active channel layer than the lower GAA transistor 260a.In an alternative embodiment, two or more lower channel layers of the upper GAA transistor 260b can be adjacent to the dielectric insulating layer 242, and thus the upper GAA transistor 260b can have two or more fewer active channel layers than the lower GAA transistor 260a. A common gate structure wraps each channel layer of the upper GAA transistor and the lower GAA transistor. Due to the smaller total number of active channel layers of the second stack for epitaxial growth of the source / drain feature, the second source / drain features of the upper GAA transistor 260b are smaller in height and volume than the first source / drain features of the lower GAA transistor 260a. To avoid ambiguity, the first source / drain features and the second source / drain features in Example I, as well as in subsequent Examples II-XV or other alternative embodiments, can have the different source / drain feature profiles as shown in [reference missing]. Fig. 102A-103D are shown.

[0141] Example II illustrates an embodiment in which a workpiece is formed by method 300. The upper GAA transistor 260b has channel layers located between the first source / drain features. The lower GAA transistor 260a has the same number of channel layers as the upper GAA transistor 260b. One difference is that not all channel layers of the lower GAA transistor 260a are located between the first source / drain features and can serve as active channel layers. At least one bottommost channel layer borders a dielectric insulating layer 241 and becomes a "floating" channel layer. Thus, the lower GAA transistor 260a has one fewer active channel layer than the upper GAA transistor 260b.In an alternative embodiment, two or more lower channel layers of the lower GAA transistor 260a can be adjacent to the dielectric insulating layer 241, and thus the lower GAA transistor 260a can have two or more fewer active channel layers than the upper GAA transistor 260b. A common gate structure wraps each channel layer of both the upper and lower GAA transistors. Due to the smaller total number of active channel layers of the first stack for epitaxial growth of source / drain features, the first source / drain features of the lower GAA transistor 260a are smaller in height and volume than the second source / drain features of the upper GAA transistor 260b.

[0142] Example III illustrates an embodiment in which a workpiece is formed by method 500. The lower GAA transistor 260a has channel layers located between the first source / drain features. The upper GAA transistor 260b has the same number of channel layers as the lower GAA transistor 260a. One difference is that not all channel layers of the upper GAA transistor 260b are located between the second source / drain features and can serve as active channel layers. At least one uppermost channel layer borders a CESL 250 and becomes a "floating" channel layer. Thus, the upper GAA transistor 260b has one fewer active channel layer than the lower GAA transistor 260a.In an alternative embodiment, two or more upper channel layers of the upper GAA transistor 260b can be connected to the CESL 250, and thus the upper GAA transistor 260b can have two or more fewer active channel layers than the lower GAA transistor 260a. A common gate structure wraps each channel layer of both the upper and lower GAA transistors. Due to the recessed upper surfaces, the second source / drain features of the upper GAA transistor 260b are smaller in height and volume than the first source / drain features of the lower GAA transistor 260a.

[0143] Example IV illustrates an embodiment in which a workpiece is formed by method 700. The upper GAA transistor 260b has channel layers located between the second source / drain features. The lower GAA transistor 260a has the same number of channel layers as the upper GAA transistor 260b. One difference is that not all channel layers of the lower GAA transistor 260a are located between the first source / drain features and can serve as active channel layers. At least one uppermost channel layer borders a CESL 230 and becomes a "floating" channel layer. Thus, the lower GAA transistor 260a has one fewer active channel layer than the upper GAA transistor 260b.In an alternative embodiment, two or more upper channel layers of the lower GAA transistor 260a can be connected to the CESL 230, and thus the lower GAA transistor 260a can have two or more fewer active channel layers than the upper GAA transistor 260b. A common gate structure wraps each channel layer of both the upper and lower GAA transistors. Due to the recessed upper surfaces, the first source / drain features of the lower GAA transistor 260a are smaller in height and volume than the second source / drain features of the upper GAA transistor 260b.

[0144] Example V illustrates an embodiment in which a workpiece is formed by method 900. The lower GAA transistor 260a has channel layers located between the first source / drain features. The upper GAA transistor 260b has channel layers located between the second source / drain features. Each channel layer is an active channel layer. One difference is that the lower GAA transistor 260a has at least one more channel layer 208 than the upper GAA transistor 260b. Thus, the lower GAA transistor 260a has at least one more active channel layer than the upper GAA transistor 260b. In various embodiments, the lower GAA transistor 260a can have two or more active channel layers than the upper GAA transistor 260b. A common gate structure wraps each channel layer of the upper GAA transistor and the lower GAA transistor.Due to the smaller number of channel layers for the epitaxial growth of source / drain features, the second source / drain features of the upper GAA transistor 260b are smaller in height and volume than the first source / drain features of the lower GAA transistor 260a. Example VI shows an alternative embodiment of Method 900 in which the upper GAA transistor 260b has at least one more channel layer, and thus one more active channel layer, than the lower GAA transistor 260a. Due to fewer channel layers for the epitaxial growth of source / drain features, the first source / drain features of the lower GAA transistor 260a are smaller in height and volume than the second source / drain features of the upper GAA transistor 260b. Other features of the alternative embodiment of Example VI are structurally similar to Example V.

[0145] Example VII illustrates an embodiment in which structures formed by Method 100 and structures formed by Method 500 are combined. The lower GAA transistor 260a has channel layers located between the first source / drain features. The upper GAA transistor 260b has the same number of channel layers as the lower GAA transistor 260a. One difference is that not all channel layers of the upper GAA transistor 260b are located between the second source / drain features and can serve as active channel layers. At least one lowest channel layer is adjacent to a dielectric insulating layer 242 and becomes a "floating" channel layer. Furthermore, at least one uppermost channel layer is adjacent to a CESL 250 and becomes a "floating" channel layer. Thus, the upper GAA transistor 260b has at least two fewer active channel layers than the lower GAA transistor 260a.In an alternative embodiment, the upper GAA transistor 260b may have three or more fewer active channel layers than the lower GAA transistor 260a. A common gate structure wraps each channel layer of both the upper and lower GAA transistors. Due to the smaller total number of active channel layers of the second stack for the epitaxial growth of source / drain features and the recessed top surfaces, the second source / drain features of the upper GAA transistor 260b are smaller in height and volume than the first source / drain features of the lower GAA transistor 260a.

[0146] Example VIII illustrates an embodiment in which the structures formed by Method 300 and those formed by Method 700 are combined. The lower GAA transistor 260a has channel layers located between the first source / drain features. The upper GAA transistor 260b has the same number of channel layers as the lower GAA transistor 260a. One difference is that not all channel layers of the lower GAA transistor 260a are located between the first source / drain features and can serve as active channel layers. At least one lowest channel layer borders a dielectric insulating layer 241 and becomes a "floating" channel layer. Furthermore, at least one uppermost channel layer borders a CESL 230 and becomes a "floating" channel layer. Thus, the lower GAA transistor 260a has at least two fewer active channel layers than the upper GAA transistor 260b.In an alternative embodiment, the lower GAA transistor 260a may have three or more fewer active channel layers than the upper GAA transistor 260b. A common gate structure wraps each channel layer of both the upper and lower GAA transistors. Due to the smaller total number of active channel layers in the first stack for the epitaxial growth of source / drain features and the recessed top surfaces, the first source / drain features of the lower GAA transistor 260a are smaller in height and volume than the second source / drain features of the upper GAA transistor 260b.

[0147] Example IX illustrates an embodiment in which the structures formed by Method 100, the structures formed by Method 500, and the structures formed by Method 900 are combined. The lower GAA transistor 260a has channel layers located between the first source / drain features. The upper GAA transistor 260b has a smaller number of channel layers than the lower GAA transistor 260a. Furthermore, not all channel layers of the upper GAA transistor 260b are located between the second source / drain features and can serve as active channel layers. At least one lowest channel layer borders a dielectric insulating layer 242 and becomes a "floating" channel layer. Furthermore, at least one uppermost channel layer borders a CESL 250 and becomes a "floating" channel layer. Thus, in the illustrated embodiment, the upper GAA transistor 260b has only a single active channel layer.In other words, the upper GAA transistor 260b has at least three fewer active channel layers than the lower GAA transistor 260a. In an alternative embodiment, the upper GAA transistor 260b can have four or more fewer active channel layers than the lower GAA transistor 260a. A common gate structure wraps each channel layer of both the upper and lower GAA transistors. Due to the smaller total number of active channel layers of the second stack for the epitaxial growth of source / drain features and the recessed top surfaces, the second source / drain features of the upper GAA transistor 260b are smaller in height and volume than the first source / drain features of the lower GAA transistor 260a.

[0148] Example X illustrates an embodiment in which the structures formed by method 300, the structures formed by method 700, and the structures formed by method 900 are combined. The upper GAA transistor 260b has channel layers located between the second source / drain features. The lower GAA transistor 260a has a smaller number of channel layers than the upper GAA transistor 260b. Furthermore, not all channel layers of the lower GAA transistor 260a are located between the first source / drain features and can serve as active channel layers. At least one lowest channel layer borders a dielectric insulating layer 241 and becomes a "floating" channel layer. Furthermore, at least one uppermost channel layer borders a CESL 230 and becomes a "floating" channel layer. Thus, in the illustrated embodiment, the lower GAA transistor 260a has only a single active channel layer.In other words, the lower GAA transistor 260a has at least three fewer active channel layers than the upper GAA transistor 260b. In an alternative embodiment, the lower GAA transistor 260a can have four or more fewer active channel layers than the upper GAA transistor 260b. A common gate structure wraps each channel layer of both the upper and lower GAA transistors. Due to the smaller total number of active channel layers in the first stack for epitaxial source / drain feature growth and the recessed top surfaces, the first source / drain features of the lower GAA transistor 260a are smaller in height and volume than the second source / drain features of the upper GAA transistor 260b.

[0149] Example XI illustrates an embodiment in which structures formed by Method 100 and structures formed by Method 900 are combined. The lower GAA transistor 260a has channel layers located between the first source / drain features. The upper GAA transistor 260b has fewer channel layers than the lower GAA transistor 260a. Furthermore, not all channel layers of the upper GAA transistor 260b are located between the second source / drain features and can serve as active channel layers. At least one lowest channel layer borders a dielectric insulating layer 242 and becomes a "floating" channel layer. Thus, the upper GAA transistor 260b has at least two fewer active channel layers than the lower GAA transistor 260a. In an alternative embodiment, the upper GAA transistor 260b may have three or more fewer active channel layers than the lower GAA transistor 260a.A common gate structure wraps each channel layer of the upper GAA transistor and the lower GAA transistor. Due to the smaller total number of active channel layers of the second stack for the epitaxial growth of source / drain features, the second source / drain features of the upper GAA transistor 260b are smaller in height and volume than the first source / drain features of the lower GAA transistor 260a.

[0150] Example XII illustrates an embodiment in which structures formed by method 300 and structures formed by method 900 are combined. The upper GAA transistor 260b has channel layers located between the second source / drain features. The lower GAA transistor 260a has a smaller number of channel layers than the upper GAA transistor 260b. Furthermore, not all channel layers of the lower GAA transistor 260a are located between the first source / drain features and can serve as active channel layers. At least one bottommost channel layer borders a dielectric insulating layer 241 and becomes a "floating" channel layer. Thus, the lower GAA transistor 260a has at least two fewer active channel layers than the upper GAA transistor 260b. In an alternative embodiment, the lower GAA transistor 260a can have three or more fewer active channel layers than the upper GAA transistor 260b.A common gate structure wraps each channel layer of the upper GAA transistor and the lower GAA transistor. Due to the smaller total number of active channel layers of the first stack for the epitaxial growth of source / drain features, the first source / drain features of the lower GAA transistor 260a are smaller in height and volume than the second source / drain features of the upper GAA transistor 260b.

[0151] Example XIII illustrates an embodiment in which structures formed by Method 500 and structures formed by Method 900 are combined. The lower GAA transistor 260a has channel layers located between the first source / drain features. The upper GAA transistor 260b has a smaller number of channel layers than the lower GAA transistor 260a. Furthermore, not all channel layers of the upper GAA transistor 260b are located between the second source / drain features and can serve as active channel layers. At least one bottommost channel layer borders a CESL 250 and becomes a "floating" channel layer. Thus, the upper GAA transistor 260b has at least two fewer active channel layers than the lower GAA transistor 260a. In an alternative embodiment, the upper GAA transistor 260b can have three or more fewer active channel layers than the lower GAA transistor 260a.A common gate structure wraps each channel layer of the upper GAA transistor and the lower GAA transistor. Due to the smaller total number of active channel layers of the second stack for the epitaxial growth of source / drain features and the recessed upper surfaces, the second source / drain features of the upper GAA transistor 260b are smaller in height and volume than the first source / drain features of the lower GAA transistor 260a.

[0152] Example XIV illustrates an embodiment in which structures formed by Method 700 and structures formed by Method 900 are combined. The upper GAA transistor 260b has channel layers located between the second source / drain features. The lower GAA transistor 260a has a smaller number of channel layers than the upper GAA transistor 260b. Furthermore, not all channel layers of the lower GAA transistor 260a are located between the first source / drain features and can serve as active channel layers. At least one uppermost channel layer borders a CESL 230 and becomes a "floating" channel layer. Thus, the lower GAA transistor 260a has at least two fewer active channel layers than the upper GAA transistor 260b. In an alternative embodiment, the lower GAA transistor 260a can have three or more fewer active channel layers than the upper GAA transistor 260b.A common gate structure wraps each channel layer of the upper GAA transistor and the lower GAA transistor. Due to the smaller total number of active channel layers of the first stack for the epitaxial growth of source / drain features and the recessed upper surfaces, the first source / drain features of the lower GAA transistor 260a are smaller in height and volume than the second source / drain features of the upper GAA transistor 260b.

[0153] Example XV illustrates an embodiment in which a workpiece is formed by method 1100. The upper GAA transistor and the lower GAA transistor are separated from each other by a dielectric insulating layer 242. Each of the upper GAA transistors and the lower GAA transistor has its own gate structure. The lower GAA transistor 260a has channel layers located between the first source / drain features. The upper GAA transistor 260b has channel layers located between the second source / drain features. Each channel layer is an active channel layer. One difference is that the lower GAA transistor 260a has at least one more channel layer 208 than the upper GAA transistor 260b. Thus, the lower GAA transistor 260a has at least one more active channel layer than the upper GAA transistor 260b.In various embodiments, the lower GAA transistor 260a can have two or more active channel layers than the upper GAA transistor 260b. Due to the smaller number of channel layers available for the epitaxial growth of source / drain features, the second source / drain features of the upper GAA transistor 260b are smaller in height and volume than the first source / drain features of the lower GAA transistor 260a. Alternatively, in some other embodiments, the upper GAA transistor 260b can have at least one more active channel layer than the lower GAA transistor 260a.

[0154] Now, the focus will shift to... Fig. Reference is made to 101. Depending on the performance requirements of a device, the workpiece can have 200 different regions with the same or different active channel elements in the pair of stacked GAA transistors. In the embodiment shown, region I has a pair of stacked GAA transistors, each having the same number of active channel elements, while region II has a pair of stacked GAA transistors, each having a different number of active channel elements. Structures similar to Example I are shown in Region II, which is only an example and is not limiting. For example, Examples II-XV in Fig. 99 and Fig. 100 in area II are formed by applying the processes described in procedures 100, 300, 500, 700, 900, 1100 or combinations thereof to area II.

[0155] Embodiments of the present disclosure offer advantages. The present disclosure provides a different number of active channel layers for transistors in a stacked configuration in various embodiments. Due to the different number of active channel layers in the stacked configuration, the output currents from the pair of stacked transistors can be balanced. Furthermore, an IC chip can have two regions, one of which has stacked GAA transistors with the same number of active channel layers and another of which has stacked GAA transistors with a different number of active channel layers, thus providing flexibility for different application requirements on a single chip and improving the device's performance. Furthermore, the method for fabricating stacked transistors can be easily integrated into existing semiconductor manufacturing processes.

[0156] According to one exemplary aspect, the present disclosure relates to a semiconductor device. The semiconductor device comprises: a stack of first channel layers; a first and a second source / drain (S / D) epitaxy feature adjacent to opposite sides of at least a portion of the first channel layers, wherein the first and the second S / D epitaxy feature exhibit a first conductivity type; a stack of second channel layers stacked above the first channel layers; and a third and a fourth S / D epitaxy feature adjacent to opposite sides of at least a portion of the second channel layers, wherein the third and the fourth S / D epitaxy feature exhibit a second conductivity type, the total number of active channel layers of the first channel layers being different from the number of second channel layers.In some embodiments, the difference between the total number of active channel layers of the first channel layers and the second channel layers is equal to or greater than two. In some non-inventional examples, the semiconductor device further comprises a dielectric insulating layer that isolates at least one of the first, second, third, and fourth S / D epitaxic features from an adjacent one of the first and second channel layers. According to the invention, the dielectric insulating layer is arranged between the first channel layers and the second channel layers, wherein the dielectric insulating layer isolates both the third and the fourth S / D epitaxic features from a bottommost channel layer of the second channel layers.In some non-inventional examples, the dielectric insulating layer is arranged below an uppermost channel layer of the first channel layers, wherein the dielectric insulating layer isolates both the first and second S / D epitaxic features from a lowermost channel layer of the first channel layers. In some embodiments, at least one of the first and second S / D epitaxic features has an upper surface below an uppermost channel layer of the first channel layers. In some embodiments, at least one of the third and fourth S / D epitaxic features has an upper surface below an uppermost channel layer of the second channel layers.In some embodiments, the semiconductor device further comprises a first busbar below the first channel layers and a second busbar above the second channel layers, wherein the first and third S / D epitaxy features are electrically coupled to the first busbar and the second and fourth S / D epitaxy features are electrically coupled to the second busbar. In some embodiments, the third S / D epitaxy feature is located directly above the first S / D epitaxy feature and the fourth S / D epitaxy feature is located directly above the second S / D epitaxy feature. In some embodiments, the semiconductor device further comprises a gate structure that wraps around each of the first and second channel layers. In some embodiments, the first and second conductivity types are opposite.

[0157] According to another exemplary aspect, the present disclosure relates to a semiconductor device. The semiconductor device comprises: a substrate; a first transistor above the substrate, wherein the first transistor has first channel layers and a first S / D feature adjacent to active elements of the first channel layers; a second transistor above the first transistor, wherein the second transistor has second channel layers and a second S / D feature adjacent to active elements of the second channel layers; and a dielectric insulating layer arranged between the first channel layers and the second channel layers, wherein the dielectric insulating layer isolates the second S / D feature from a bottommost channel layer of the second channel layers, and wherein the number of active elements of the first channel layers differs from the number of active elements of the second channel layers.In some embodiments, the number of first channel layers differs from the number of second channel layers. In some embodiments, the number of first channel layers is equal to the number of second channel layers. In some embodiments, the semiconductor device further comprises a gate structure that wraps around each of the first and second channel layers. In some embodiments, the semiconductor device further comprises a first gate structure that wraps around each of the first channel layers; a second gate structure that wraps around each of the second channel layers; and an insulating layer arranged between the first and second gate structures. In some embodiments, the semiconductor device further comprises a busbar below the first channel layers, wherein both the first and second S / D features are electrically coupled to the busbar.

[0158] In another exemplary aspect, the present disclosure relates to a method. The method comprises: obtaining a workpiece having a substrate section and a stack section above the substrate section, the stack section having a first stack of first channel layers nested with first sacrificial layers, and a second stack of second channel layers nested with second sacrificial layers, the second stack being above the first stack; forming a fin-shaped structure from the stack section and the substrate section, the fin-shaped structure having a source region and a drain region; forming a first source feature in the source region and a first drain feature in the drain region; depositing an insulating layer over the first source feature and the first drain feature, the insulating layer being adjacent to a bottommost of the second channel layers;and forming a second source feature in the source region and above the insulating layer, and a second drain feature in the drain region and above the insulating layer, wherein the dielectric insulating layer isolates both the second source feature and the second drain feature from the lowest of the second channel layers. In some embodiments, the method further comprises recessing the second source feature and the second drain feature below an uppermost of the second channel layers; and depositing a dielectric layer over the second source feature and the second drain feature, wherein the dielectric layer is adjacent to the uppermost of the second channel layers. In some embodiments, the method further comprises forming a first busbar below the first stack; forming a second busbar above the second stack;Forming first interconnect features that electrically couple the first source feature and the second source feature to the first busbar; and forming second interconnect features that electrically couple the first drain feature and the second drain feature to the second busbar.

Claims

[1] comprising a semiconductor device (200): a stack (204b) of first channel layers (208); a first S / D epitaxy feature (228S) and a second S / D epitaxy feature (228D) adjacent to respective opposite sides of at least a part of the first canal layers (208), wherein the first and the second S / D epitaxy feature (228S, 228D) have a first conductivity type; a stack (204a) of second channel layers (208) stacked over the first channel layers (208); a third S / D epitaxy feature (248S) and a fourth S / D epitaxy feature (248D) adjacent to respective opposite sides of at least a part of the second canal layers (208), wherein the third and fourth S / D epitaxy features (248S, 248D) exhibit a second conductivity type; and a dielectric insulating layer (242) arranged between the first channel layers (208) and the second channel layers (208), wherein the dielectric insulating layer (242) isolates both the third and the fourth S / D epitaxy feature (248S, 248D) from a bottommost channel layer of the second channel layers (208); wherein the total number of active channel layers (208) of the first channel layers (208) differs from that of the second channel layers (208). [2] Semiconductor device (200) according to claim 1, wherein the difference between the total number of active channel layers (208) of the first channel layers (208) and the second channel layers (208) is equal to or greater than two. [3] Semiconductor device (200) according to one of the preceding claims, wherein at least one of the first and the second S / D epitaxy feature (228S, 228D) has an upper surface below a topmost channel layer of the first channel layers (208). [4] Semiconductor device (200) according to one of the preceding claims, wherein at least one of the third and fourth S / D epitaxy feature (248S, 248D) has an upper surface below a topmost channel layer of the second channel layers (208). [5] Semiconductor device (200) according to any one of the preceding claims, further comprising: a first busbar (211) below the first channel layers (208); and a second busbar above the second channel layers (208), wherein the first and third S / D epitaxy features (228S, 248S) are electrically coupled to the first busbar (211), and the second and fourth S / D epitaxy features (228D, 248D) are electrically coupled to the second busbar. [6] Semiconductor device (200) according to claim 5, wherein the third S / D epitaxy feature (248S) is located directly above the first S / D epitaxy feature (228S) and the fourth S / D epitaxy feature (248D) is located directly above the second S / D epitaxy feature (228D). [7] Semiconductor device (200) according to one of the preceding claims, further comprising: a gate structure (254) that wraps around each of the first channel layer (208) and the second channel layer (208). [8] Semiconductor device (200) according to one of the preceding claims, wherein the first conductivity type and the second conductivity type are opposite. [9] comprising a semiconductor device (200): a substrate (202); a first transistor (260a) above the substrate (202), wherein the first transistor (260a) has first channel layers (208) and a first S / D feature (228S, 228D) adjacent to active elements of the first channel layers (208); a second transistor (260b) above the first transistor, wherein the second transistor (260b) has second channel layers (208) and a second S / D feature (248S, 248D) adjacent to active elements of the second channel layers (208); and a dielectric insulating layer (242) arranged between the first channel layers (208) and the second channel layers (208), wherein the dielectric insulating layer (242) insulates the second S / D feature (248S, 248D) from a bottommost channel layer of the second channel layers (208); wherein the number of active elements of the first channel layers (208) differs from the number of active elements of the second channel layers (208). [10] Semiconductor device (200) according to claim 9, wherein a number of the first channel layers (208) differs from that of the second channel layers (208). [11] Semiconductor device (200) according to claim 9, wherein a number of the first channel layers (208) is equal to that of the second channel layers (208). [12] Semiconductor device (200) according to any one of claims 9 to 11, further comprising: a gate structure (254) that wraps around each of the first channel layers (208) and the second channel layers (208). [13] Semiconductor device (200) according to any one of claims 9 to 11, further comprising: a first gate structure (254a) that wraps around each of the first channel layers (208); a second gate structure (254b) that wraps around each of the second channel layers (208); and an insulating layer (242) that is arranged between the first gate structure (254a) and the second gate structure (254b). [14] Semiconductor device (200) according to any one of claims 9 to 13, further comprising: a busbar (211, 211-1, 211-2) under the first channel layers (208), wherein the first S / D feature (228S, 228D) and the second S / D feature (248S, 248D) are electrically coupled to the busbar (211, 211-1, 211-2). [15] Procedure (100, 300, 500, 700, 900, 1100) comprising: Retained (102, 302, 502, 702, 902, 1102) of a workpiece (200) comprising a substrate section (202) and a stacking section (204) above the substrate section (202), wherein the stacking section (204) comprises a first stack (204b) of first channel layers (208) nested with first sacrificial layers (206) and a second stack (204a) of second channel layers (208) nested with second sacrificial layers (206), wherein the second stack (204a) is above the first stack (204b); Forming (104, 304, 504, 704, 904, 1104) a fin-shaped structure (209) from the stacking section (204) and the substrate section (202), wherein the fin-shaped structure (209) has a source region and a drain region; Forming (122, 322, 522, 722, 922, 1116) a first source feature (228S) in the source region and a first drain feature (228D) in the drain region; Deposition (130, 330, 530, 730, 930, 1124) of an insulating layer (242) over the first source feature (228S) and the first drain feature (228D), wherein the insulating layer (242) adjoins a lowermost of the second channel layers (208); and Forming (132, 332, 532, 732, 932, 1128) a second source feature (248S) in the source region and above the insulating layer (242) and a second drain feature (248D) in the drain region and above the insulating layer (242), wherein the dielectric insulating layer (242) insulates both the second source feature (248S) and the second drain feature (248D) from the lowest of the second channel layers (208). [16] Method (500) according to claim 15, further comprising: Recess (534) of the second source feature (248S) and the second drain feature (248D) below one of the uppermost of the second channel layers (208); and Deposition (536) of a dielectric layer (252) over the second source feature (248S) and the second drain feature (248D), wherein the dielectric layer (252) is adjacent to the uppermost of the second channel layers (208). [17] Method (100, 300, 500, 700, 900, 1100) according to claim 15 or 16, further comprising: Forming (106, 306, 506, 706, 906, 1106) a first busbar (211) under the first stack (204b); Forming (140, 340, 540, 740, 940, 1130) a second busbar above the second stack (204a); Forming (128, 140, 328, 340, 528, 540, 728, 740, 928, 940, 1122, 1130) of first interconnect features (238, 266) that electrically couple the first source feature (228S) and the second source feature (248S) to the first busbar (211); and Forming (128, 140, 328, 340, 528, 540, 728, 740, 928, 940, 1122, 1130) of second interconnect features (270, 268) that electrically couple the first drain feature (228D) and the second drain feature (248D) to the second busbar.

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