Sample inspection facility and sample inspection procedures

Abstract

Inspection device (100), comprising: an optical image acquisition mechanism (150) configured to acquire an optical image of each of a plurality of regions on a substrate to be inspected on which a pattern is formed; a plurality of comparison circuits (108) configured to individually perform comparison processing of comparing the optical image with a reference image corresponding to the optical image; an inspection abnormality determination circuit (132) configured to determine, based on comparison results generated in the plurality of comparison circuits, whether there is a region having an inspection abnormality in the plurality of regions; a malfunction diagnosis circuit (134) configured to diagnose whether a comparison circuit that performed comparison processing for the region determined to have the inspection abnormality in the plurality of regions has a malfunction; and an assignment processing circuit (136) configured to individually assign regions of the plurality of regions where comparison processing is to be performed to comparison circuits that are not diagnosed as malfunctions in the plurality of comparison circuits, and to exclude a comparison circuit that is diagnosed as malfunctioning from a target to which a region is assigned.

Description

BACKGROUND OF THE INVENTIONField of the InventionEmbodiments of the present invention relate to a pattern inspection apparatus and a pattern inspection method. For example, they relate to an apparatus and method for inspecting one of defects of a pattern of an exposure mask used in the production of semiconductor devices.Description of Related ArtWith recent advances in high integrations and large capacitances of large scale integrated circuits (LSI), the line width (critical dimension) required for circuits of semiconductor elements is becoming narrower. Such semiconductor elements are fabricated by circuit formation by exposing and transferring a pattern to a wafer by a reduction projection exposure apparatus known as a stepper, using an original or "master" pattern (also called a mask or reticle, hereinafter referred to generally as a mask) on which a circuit pattern has been formed.Since LSI production requires enormous production costs, it is essential to improve the yield. One of the major factors that lowers the yield of LSI production is pattern defects on a mask for exposing / transferring an ultrafine pattern to a semiconductor wafer by the photolithography technology. In recent years, as dimensions of LSI patterns formed on a semiconductor wafer are miniaturized, dimensions to be detected as a pattern defect have become extremely small. Therefore, the pattern inspection device for inspecting defects of a transfer mask used in the production of LSI must be extremely accurate.As the inspection method, there is, for example, a "die-to-die inspection" or a "die-to-database inspection.". The die-to-die inspection method compares data of optical images of identical patterns at different positions on the same mask. The die-to-database inspection method inputs, to an inspection device, write data (design data) generated by converting pattern-designed CAD data into a writing device specific format to be input to the writing device when a pattern is written on the mask, generates a reference image based on the input writing data, and compares the first generated reference image with an optical image that is measurement target data obtained by imaging the pattern.The time for inspection can be reduced by performing the comparison processing described above using a plurality of processing circuits in parallel.As an inspection result, if defects are found to have occurred frequently, the cause may be a case where the inspection mask itself has a problem or a case where the inspection device has a malfunction (is out of operation). For example, if defects frequently occur at a feitage or night, the manufacturer of the device must take urgent measures to avoid a long downtime of the inspection device. Accordingly, in a case of such frequent defects, a method that diagnoses the cause by the inspection device itself and avoids a long downtime even if the device itself malfunctions is required.Although not related to the diagnosis of malfunction (failure) of an inspection device, a method of performing writing on the substrate under three conditions is disclosed: normal conditions, safe conditions, and accelerated conditions, and dedurating that, if there is a difference between the number of defects in a region written under the safe conditions and the number of defects in a region written under the accelerated conditions, the defects are caused by the electron beam writing device (see, for example, Japanese Patent Application Laid-Open No. JP 2011-129624 A). However, this method is based on a condition that the inspection device operates in a normal state, and therefore it is difficult to take measures against a malfunction of the inspection device itself.The prior art comprises the following documents:DE 10 2014 204 876 A1 describes an inspection method and an inspection device, which comprise: virtually dividing a sample in which a plurality of chip patterns are formed into a plurality of strip-shaped strips along a predetermined direction to acquire an optical image of the chip pattern in each of the strips, carrying out filtering on the basis of construction data of the chip pattern to generate a reference image associated with the optical image, comparing the chip pattern using a cube-to-database method, and comparing a repeating pattern area in the chip pattern using a cell method, determining a dimension difference or / and a dimension ratio between a pattern of the optical image and a pattern of the reference image compared to the pattern of the optical image by the cube-to-database method, and determining a dimension distribution of the optical image by the cube-to-database method; and determining a dimension distribution of the plurality of chip patterns from the dimension difference or / and the dimension ratio.US 2010 / 0 188 655 A1 describes an inspection system for inspecting a surface of a wafer / mask / reticle, which comprises a modular array. The modular assembly may include a plurality of time delay integration (TDI) sensor modules, each TDI sensor module having a TDI sensor and a plurality of localized circuitry for driving and processing the TDI sensor. At least one of the localized circuits may control a clock associated with the TDI sensor. At least one light guide may be used to distribute an illumination source among the plurality of TDI sensor modules. The plurality of TDI sensor modules may be positioned to accommodate one and the same test region or different test regions. The plurality of TDI sensor modules may be identical or provide different levels of integration. The spacing between the modules may be chosen to provide 100 percent coverage of the inspection area in one pass or a partial coverage requiring two or more passes for complete coverage.SUMMARY OF THE INVENTIONThe above problem is solved by the subject matter of the independent claims. Examples and technical descriptions of apparatuses, products, and / or methods in the specification and / or the drawings that do not fall under the claims are not illustrated as embodiments of the invention, but as background or examples useful for understanding the invention. According to an aspect of an example, a pattern inspection device includes an optical image acquisition mechanism configured to acquire an optical image of each of a plurality of regions on a substrate to be inspected on which a pattern is formed, a plurality of comparison circuits configured to individually perform comparison processing of comparing the optical image with a reference image corresponding to the optical image, an abnormality determination circuit configured to determine whether there is a region having an inspection abnormality in the plurality of regions based on comparison results generated in the plurality of comparison circuits, a malfunction diagnosis circuit configured to diagnose whether a comparison circuit that performed comparison processing for the region determined to have the inspection abnormality, in the plurality of regions having a malfunction, and an assignment processing circuit configured to assign individually regions of the plurality of regions where comparison processing is to be performed, comparison circuits not diagnosed as malfunctions in the plurality of comparison circuits, and exclude a comparison circuit diagnosed as a malfunction from a target to which a region is assigned.According to another aspect of an example, a pattern inspection method includes acquiring an optical image of each of a plurality of regions on a substrate to be inspected on which a pattern is formed; performing comparison processing of comparing the optical image with a reference image corresponding to the optical image using each of a plurality of comparison circuits, and outputting each of comparison results; determining, based on the comparison results generated in the plurality of comparison circuits, whether there is a region having an inspection abnormality in the plurality of regions; diagnosing whether a comparison circuit performing comparison processing for the region determined to have the inspection abnormality has a malfunction in the plurality of regions; excluding a comparing circuit diagnosed as a malfunction in the plurality of comparing circuits from a target to which a region is assigned and assigning regions where comparing processing has not yet been performed in the plurality of regions to comparing circuits not diagnosed as malfunctions.According to still another aspect of an example, a pattern inspection device includes an optical image acquisition mechanism configured to acquire an optical image of a plurality of regions on a substrate to be inspected on which a pattern is formed, a plurality of comparison circuits each configured to include a plurality of sub-comparison circuits that individually perform comparison processing of comparing the optical image with a reference image corresponding to the optical image, an abnormality determination circuit configured to determine whether there is a region having an inspection abnormality in the plurality of regions based on comparison results generated in the plurality of sub-comparison circuits; a malfunction diagnosis circuit configured to diagnose whether a sub-comparison circuit that has performed comparison processing for the region determined to have the inspection abnormality malfunctions in the plurality of regions, and an assignment processing circuit configured to individually assign regions of the plurality of regions where comparison processing is to be performed to sub-comparison circuits that are not diagnosed as malfunctions in the plurality of sub-comparison circuits that include a sub-comparison circuit diagnosed as a malfunction, and exclude the sub-comparison circuit diagnosed as a malfunction from a target to which a region is assigned.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 illustrates a configuration of a pattern inspection device according to a first embodiment; FIG. 2 is a conceptual diagram illustrating an inspection region according to the first embodiment; FIG. 3 is a flowchart showing main steps of an inspection method according to the first embodiment; FIG. 4 illustrates filter processing according to the first embodiment; FIG. 5 shows an example of an internal configuration of an assignment processing circuit according to the first embodiment; FIG. 6 shows an example of region assignment according to the first embodiment; FIG. 7 shows an example of the internal configuration of each comparison circuit according to the first embodiment; FIG. 8 shows an example of the internal configuration of an inspection abnormality determination circuit according to the first embodiment; FIGS. 9A and 9B illustrate a method for diagnosing a malfunction according to the first embodiment; FIG. 10 shows an example of the post-diagnosis assignment processing for malfunction according to the first embodiment; FIGS. 11A and 11B illustrate a method for diagnosing a malfunction according to a second embodiment; FIG. 12 shows an example of the internal configuration of each comparison circuit according to a modified example of each embodiment; FIGS. 13A and 13B illustrate a method for diagnosing a malfunction according to a modified example of each embodiment; and FIG. 14 shows an example of post-diagnosis assignment processing for malfunction according to a modified example of each embodiment.DETAILED DESCRIPTION OF THE INVENTIONEmbodiments below describe an inspection device and a method capable of, when defects occur frequently, avoiding a long downtime even in the case where the inspection device is out of service.First EmbodimentFIG. 1 illustrates a configuration of a pattern inspection device according to a first embodiment.As shown in FIG. 1, an inspection device 100 that inspects defects of a pattern formed on an inspection target substrate, such as a mask, includes an optical image acquisition mechanism 150, and a control system circuit 160.The optical image acquisition mechanism 150 includes a light source 103, an illumination optical system 170, an XYθ stage 102 movably disposed, a magnifying optical system 104, a TDI (Time Delay Integration) sensor 105, a sensor circuit 106, a stripe pattern memory 123, a laser length measurement system 122, and an auto loader 130. A substrate 101 conveyed from the auto loader 130 is placed on the XYθ table 102. The substrate 101 is, for example, an exposure photomask used for transferring the print of a pattern to a semiconductor substrate such as a wafer. A plurality of figure patterns to be inspected are formed on the photomask. The substrate 101 is placed on the XYθ table 102 with its pattern-binding surface facing downward, for example.In the control system circuit 160, a control computer 110 which controls the inspection device 100 as a whole is connected via a bus 120 to a position circuit 107, a plurality of comparison circuits 108 (108a, 108b, 108c and so forth), a reference image generation circuit 112, an auto loader control circuit 113, a table control circuit 114, an inspection abnormality determination circuit 132, a malfunction diagnosis circuit 134, an assignment processing circuit 136, a magnetic disk drive 109, a memory 111, a magnetic tape drive 115, a flexible disk drive (FD) 116, a CRT 117, a pattern monitor 118 and a printer 119. The sensor circuit 106 is connected to the stripe pattern memory 123, which is connected to the plurality of comparison circuits 108. The XYθ table 102 is driven by the x, y, and θ axis motors, and serves as an example of the stage. The reference image generating circuit 112 is connected to the plurality of comparing circuits 108. As bus 120, for example, a 10 Gbit Ethernet cable is used.Each "..circuit" such as the position circuit 107, the plurality of comparison circuits 108 ( 108 a, 108 b, 108 c, and so on), the reference image generation circuit 112, the auto-loader control circuit 113, the table control circuit 114, the inspection abnormality determination circuit 132, the malfunction diagnosis circuit 134, and the assignment processing circuit 136 includes processing circuits. As processing circuits, for example, an electric circuit, a computer, a processor, a circuit board, a quantum circuit, a semiconductor device, or the like can be used. Each "..circuit" may use common processing circuits (the same processing circuit) or different processing circuits (separate processing circuits). For example, each "..circuit" such as the position circuit 107, the plurality of comparison circuits 108, the reference image generation circuit 112, the auto loader control circuit 113, the table control circuit 114, the inspection abnormality determination circuit 132, the malfunction diagnosis circuit 134, and the assignment processing circuit 136 may be configured and executed by the control computer 110. Input data necessary for the position circuit 107, the plurality of comparison circuits 108, the reference image generation circuit 112, the auto loader control circuit 113, the table control circuit 114, the inspection abnormality determination circuit 132, the malfunction diagnosis circuit 134, and the assignment processing circuit 136, and operated (calculated) results are stored in a memory (not shown) or the memory 111 each time. A program for causing a computer to execute the processing or the like may be stored on a recording medium such as a hard disk drive 109, magnetic tape drive 115, FD 116, ROM (Read Only Memory), or the like.In the inspection device 100, a high-magnification inspection optical system is configured of the light source 103, the XYθ table 102, the illumination optical system 170, the magnification optical system 104, the TDI sensor 105, and the sensor circuit 106. The XYθ table 102 is driven by the table control circuit 114 under the control of the control computer 110. The XYθ table 102 can be moved by a drive system, such as a three-axis (X, Y, and θ) motor, that drives the table in directions x, y, and θ. For example, a stepping motor may be used as each of these X, Y and θ motors. The XYθ table 102 is movable in the horizontal direction and the rotational direction by the X, Y, and θ axis motors. The moving position of the substrate 101 placed on the XYθ table 102 is measured by the laser length measurement system 122, and is supplied to the position circuit 107. The transfer (feeding) processing of the substrate 101 from the auto loader 130 to the XYθ table 102 and from the XYθ table 102 to the auto loader 130 is controlled by the auto loader control circuit 113.Write data (design data) used as a basis for forming patterns on the inspection substrate 101 is input from the outside of the substrate 101 and stored in the hard disk drive 109. The write data defines a plurality of figure patterns, and each figure pattern is usually configured by combining a plurality of element figures. Such a figure pattern may be configured by a figure. Then, each pattern corresponding to and based on each figure pattern defined by the write data is formed on the inspection substrate 101.FIG. 1 shows configuration elements necessary for describing the first embodiment. It is understood that other configuration elements that are usually necessary for the inspection device 100 may also be included therein.FIG. 2 is a conceptual diagram registering an inspection region according to the first embodiment. As shown in FIG. 2, an inspection region 10 (the entire inspection region) of the substrate 101 is virtually divided into a plurality of strip-shaped inspection strips 20 each having a width W in the Y direction, for example, the width W being a sensing width of the TDI sensor 105. Specifically, with respect to each of the inspection strips 20, the inspection device 100 captures (captures) an image of a figure pattern arranged in the strip region concerned with laser light (inspection light) imaging in the longitudinal direction (the x direction) of the strip region concerned with each inspection strip 20. In order to prevent a missing image, it is preferable that a plurality of inspection stripes 20 are set such that adjacent inspection stripes 20 overlap each other by a predetermined span width.The TDI sensor 105, which continuously moves relatively in the x direction by the movement of the XYθ table 120, acquires an optical image. The TDI sensor 105 continuously captures optical images all having the scanning width W as shown in FIG. 2, in other words, while moving relatively in the integration direction of the TDI sensor 105, the TDI sensor 105 captures optical images of a plurality of figure patterns formed on the substrate 101. According to the first embodiment, after capturing (acquiring) an optical image in one inspection strip 20, the TDI sensor 105 moves in the Y direction to the position of the next inspection strip 20, and similarly, continuously captures another optical image having the scanning width W while moving in the direction opposite to the last image capturing direction. Thereby, the image capturing in forward (FWD) and reverse (BWD) directions is repeated, namely changing the direction reverse in proceeding and returning.In an actual inspection, as shown in FIG. 2, the stripe region image of each inspection stripe 20 is divided into images of a plurality of rectangular (including square) frame regions 30. Then, the inspection is performed for each image of the frame region 30. It is divided into 512x512 pixels, for example. Therefore, a reference image to be compared with a drain frame image 31 of the frame region 30 is similarly generated for each frame region 30.The direction of image capturing is not limited to repeating the forward (FWD) and backward (BWD) movement. Images can be taken in a fixed direction. For example, FWD and FWD may be repeated, or alternatively, BWD and BWD may be repeated.FIG. 3 is a flowchart showing main steps of an inspection method according to the first embodiment. In FIG. 3, the inspection method of the first embodiment performs a series of steps: a sampling step (S 102), a reference image generation step (S 104), a region assignment step (S 106), a plurality of comparison steps (S 110) implemented in parallel, an inspection abnormality determination step (S 120), a malfunction diagnosis step (S122), and a comparison circuit exclusion step (S 140).In the scanning step (S 120), the optical image acquisition mechanism 150 acquires optical images of a plurality of regions on a substrate to be inspected on which a pattern is formed. Specifically, first, the optical image acquisition mechanism 150 scans the inspection strip 20 with laser beams (inspection light) so as to acquire, for each inspection strip 20, an image of the strip region by the TDI sensor 105. Further detailed operations are as follows: the XYθ table 102 is moved to the position where an inspection strip 20 can be imaged. A pattern formed on the substrate 101 is irradiated with laser light (for example, DUV light) serving as inspection light whose wavelength is equal to or shorter than that of light in the ultraviolet region from the appropriate light source 103 through the illumination optical system 170. A light that has passed through the substrate 101 is enlarged by the enlarging optical system 104 to form an image on the TDI sensor 105 (an example of a sensor) as an optical image to be input thereto.A pattern image focused / formed on the TDI sensor 105 is photo-electrically converted by each photodiode of the TDI sensor and further analog-digital (A / D) converted by the sensor circuit 106. Then, pixel data for the inspection strip 20 to be measured is stored in the strip pattern memory 123. In capturing (capturing) an image of the pixel data (stripe region image), for example, a dynamic range where the case of 60% of the illumination light amount is incident is the maximum gray level is used as the dynamic range of the TDI sensor 105. Measurement data (pixel data) is 8-bit unsigned data, for example, and indicates a grayscale level (light intensity) / brightness for each pixel.In the reference image generation step (S 104), the reference image generation circuit 112 generates a reference image serving as a reference using figure pattern data (design data). Specifically, it operates as follows: The reference image generating circuit 112 inputs figure pattern data (design data) with respect to each frame region 30 of the inspection strip 20, and converts each figure pattern defined by the input figure pattern data into image data of binary and multiple values.Basic figures defined by the figure pattern data are, for example, rectangles and triangles. For example, figure data defining the shape, size, position and the like of each pattern figure is stored using information such as coordinates (x, y) of the reference position of the figure, lengths of sides of the figure, and a figure code serving as an identifier for identifying the figure type such as rectangles, triangles and the like.When design pattern data used as the figure data is input to the reference image generating circuit 112, the data is developed into data of each figure. Then, the figure code, the figure dimensions and the like indicating the figure shape of all the figure data are interpreted. Then, the reference image generating circuit 112 develops all figure data into design pattern image data of binary or plural values as a pattern to be arranged in squares in units of rasters of predetermined quantizing dimensions, and outputs the developed data. In other words, the reference image generation circuit 112 reads out design data, calculates the occupancy of a figure in the design pattern for each square region obtained by virtually dividing the frame region square in units of predetermined dimensions, and outputs n bits of occupancy data (design image data). For example, it is preferable to set a square as one pixel. assuming that one pixel has a resolution of 1 / 2 8(=1 / 256) the occupancy in each pixel is calculated by assigning small regions corresponding to the region of figures arranged in the pixel concerned and corresponding to each 1 / 256 resolution. Then, 8-bit occupancy data is generated. Such square regions (inspection pixels) may correspond to (match) pixels of measurement data.Next, the reference image generation circuit 112 performs appropriate filter processing, using a filter function, on design image data of a design pattern, which is image data of a figure.FIG. 4 illustrates filter processing according to the first embodiment. Pixel data of the optical image captured from the substrate 101 is in a state affected by filtering due to resolution characteristics etc. of the optical system used for image capturing, in other words, in an analog state that continuously changes. Therefore, as shown in FIG. 4, for example, the optical image is different from the developed image (design image) whose image intensity (grayscale value) is represented by digital values. On the other hand, in figure pattern data converted from contour data, since pattern codes, etc. are used for defining as described above, image intensity (gray scale level) of developed design images may be digital values. Accordingly, the reference image generation circuit 112 performs image processing (filter processing) on the developed image to generate a reference image close to the optical image. Thereby, it is possible to match design image data, which is image data on the design side whose image intensity (grayscale level) is in digital values, with image generation characteristics of measurement data (optical image).FIG. 5 shows an example of an internal configuration of an assignment processing circuit according to the first embodiment. As shown in FIG. 5, a storage device 57 such as a magnetic disk drive, an assignment processing unit 56, and a malfunction determination unit 58 are arranged in the assignment processing circuit 136. Each of the "units" such as the allocation processing unit 56 and the malfunction determination unit 58 includes processing circuits. As the processing circuits, for example, an electric circuit, a computer, a processor, a circuit board, a quantum circuit, a semiconductor circuit, or the like can be used. Each of the "units" may use common processing circuits (the same processing circuits) or different processing circuits (separate processing circuits). Input data and calculated results required in the assignment processing unit 56 and the malfunction determination unit 58 are stored in a memory (not shown) in the assignment processing circuit 136 or the memory 118 each time.In the region assignment step (S 106), the assignment processing unit 56 assigns the structural bodies 20 (region) where comparison processing is to be performed to the comparison circuit 108 that has not been diagnosed as malfunction (failure) in a plurality of comparison circuits 108.FIG. 6 shows an example of region assignment according to the first embodiment. FIG. 6 shows the case where ten comparison circuits 108 are installed in the inspection device 100. In FIG. 6, inspection strips 20, for example, are individually assigned corresponding to a comparison circuit 108. For example, the inspection strip 1 is assigned to the comparison circuit 1. The inspection strip 2 is assigned to the comparison circuit 2. The inspection strip 3 is assigned to the comparison circuit 3. Subsequently, similarly, the inspection stripes 4 to 10 are individually assigned to the comparison circuits 4 to 10.Under the control of the control computer 110, a stripe region image (stripe data) acquired in the scanning step including data indicating the position of the substrate 101 on the XYθ table 102 output from the position circuit 107 is sent to the comparison circuit 108 assigned with the inspection stripe 20 whose stripe region image has been acquired. Since the scanning step is performed for each inspection strip 20, each time scanning is performed for the inspection strip 20, a strip region image of the inspection strip 20 concerned is sent to the comparison circuit 108 to which the inspection strip 20 concerned has been assigned. Similarly, data of a generated reference image of each frame region 30 is sequentially sent to the comparing circuit 108 to which the inspection strip 20 where the frame region concerned is located has been assigned. For example, each time a reference image for an inspection strip 20 is generated, data of the reference image of the inspection strip 20 concerned is sent to the comparing circuit 108 to which the inspection strip 20 concerned has been assigned.In the plurality of comparison steps (S 110), a plurality of comparison circuits 108 individually perform comparison processing of comparing an optical image (images) and a reference image (images) corresponding to the optical image (images) to assign corresponding one or more inspection stripes 20 in a plurality of structural bodies 20 (regions).FIG. 7 shows an example of the internal configuration of each comparison circuit according to the first embodiment. As shown in FIG. 7, there are storage devices 70, 71, 72, and 76 arranged in each comparison circuit 108, such as magnetic disk drives, a frame image generation unit 74, an alignment unit 78, and a comparison processing unit 79. As the processing circuits, for example, an electric circuit, a computer, a processor, a circuit board, a quantum circuit, a semiconductor device, or the like can be used. Each of the "units" may use common processing circuits (the same processing circuits) or different processing circuits (separate processing circuits). Data and calculated results required in the frame image generating unit 74, the aligning unit 78, and the comparison processing unit 79 are stored in a memory (not shown) in the comparing circuit 108 or a memory 111 each time.Stripe data (stripe region image) input to each comparing circuit 108 is stored in the storage device 70 in the corresponding comparing circuit 108. Reference image data input to each comparing circuit 108 is stored in the storage device 72 in the corresponding comparing circuit 108.In each comparison circuit 108, first, the frame image generation unit 74 generates a plurality of frame images 31 by dividing the fringe region image (optical image) by a predetermined width. Specifically, as shown in FIG. 2, the stripe region image is divided into frame images of a plurality of rectangular frame regions 30. For example, it is divided into 512 × 512 pixels in size. Data of each frame region 30 is stored in the storage device 76.Next, the alignment unit 78 reads out, for each frame region 30, a corresponding frame image 31 and a corresponding reference image from the storage devices 72 and 76, and performs alignment (position adjustment) of the frame image 31 and the corresponding reference image based on a predetermined algorithm. For example, the alignment is performed by the least squares method.The comparison processing unit 79 (comparison unit) compares the frame image 31 with the reference image corresponding to the frame image 31 concerned. Here, the comparison processing unit 79 compares, for each pixel, both the images based on predetermined determination conditions to determine whether or not there is a defect such as a shape defect. As the determination conditions, for example, a predetermined algorithm is used, based on which the two images are compared with each other for each pixel to determine whether or not a defect exists. For example, for each pixel, a difference between the pixel value of the optical image and the pixel value of the reference image is calculated, and it is determined that there is a defect if the difference value is larger than a threshold value Th. Then, the comparison result is output to the storage device 71. Moreover, the comparison result may be outputted to, for example, the magnetic disk drive 109, the magnetic tape drive 115, the flexible disk drive (FD) 116, the CRT 117, the pattern monitor 118, or alternatively outputted from the printer 119.Although the case of performing the die-to-database inspection is described in the above example, the die-to-die inspection may also be used. In this case, with respect to frame regions of dies 1 and 2, for die-to-die inspection, the comparison circuit 108 uses a frame image (optical image) of the die 2 as a reference (reference image). First, for each frame region 30 on which the die-to-die inspection is performed, the alignment unit 78 reads out the frame image 31 of the die 1 and a corresponding frame image of the die 2 from the storage device 76, and performs alignment between the frame images of the dies 1 and 2 based on a predetermined algorithm. For example, the alignment is performed by the least squares method. Then, for each frame region where the die-to-die inspection is performed, the comparison processing unit 79 (comparison unit) compares, for each pixel, the frame image 31 of the die 1 with corresponding frame image of the die 2.Each of a plurality of comparison circuits 108 individually starts comparison processing when the input of the stripe image and the reference image of an assigned inspection stripe 20 has been completed. Therefore, comparison processing can be performed in parallel by two or more comparison circuits in a plurality of comparison circuits 108.In the inspection abnormality determination step (S 120), based on comparison circuits generated in a plurality of comparison circuits 108, the inspection abnormality determination circuit 132 (inspection abnormality determination unit) determines whether or not there is an inspection strip 20 in which an abnormality occurs in the comparison in a plurality of inspection strips 20.FIG. 8 shows an example of the internal configuration of an inspection abnormality determination circuit according to the first embodiment. As shown in FIG. 8, a number-of-defects in-frame calculation unit 50, a number-of-defects in-strip calculation unit 52, and an inspection abnormality determination unit 54 are arranged in the inspection abnormality determination circuit 132. Each of the "units" such as the number-of-defects in-frame calculation unit 50, the number-of-defects in-strip calculation unit 52, and the inspection abnormality determination unit 54 includes processing circuits. As the processing circuits, for example, an electric circuit, a computer, a processor, a circuit board, a quantum circuit, a semiconductor device, or the like can be used. Each of the "units" may use common processing circuits (the same processing circuits) or different processing circuits (separate processing circuits). Input data required in the number-of-defects in-frame calculation unit 50, the number-of-defects in-strip calculation unit 52, and the inspection abnormality determination unit 54 and calculated results are stored in a memory (not shown) in the inspection abnormality determination circuit 132 or the memory 111 each time.For each inspection strip 20, the number-of-defects in-frame calculation unit 50 calculates, for each frame region 30, the number of defects in each frame with reference to a result of the comparison processing. Moreover, the number-of-defects in-strip calculation unit 52 calculates, for each inspection strip 20, the number of defects in each inspection strip by summing the number of defects in respective frames.The inspection abnormality determination unit 54 determines, for each inspection strip 20, whether the number of defects is greater than or equal to a threshold value Tth 1. Moreover, for each inspection strip 20, the inspection abnormality determination unit 54 determines, for each frame region 30, whether the number of defects is greater than or equal to a threshold Tth 2. Thereby, the inspection strip 20 in which the number of defects is greater than or equal to the threshold value Tth 1 is detected as an inspection strip 20 having an inspection abnormality. Similarly, in the case where the defects whose number is greater than or equal to the threshold Tth 2 exist in a biased state in a certain range in the inspection strip 20, the frame region 30 corresponding to a certain area is detected as a frame region 30 having an inspection abnormality.When the inspection strip 20 having an inspection abnormality or the frame region 30 having an inspection abnormality is detected, the control computer 110 promptly interrupts (sets) the comparison processing performed by all the comparison circuits 108. Alternatively, when comparison processing currently performed in the inspection strip 20 is completed, the control computer waits or is "on standby" without performing comparison processing of the next inspection strip 20.In the malfunction diagnosis step (S122), the malfunction diagnosis circuit 134 diagnoses whether or not the comparison circuit 108 that has performed comparison processing for the inspection strip 20 determined to have an inspection abnormality has a malfunction.FIGS. 9A and 9B illustrate a method for diagnosing a malfunction according to the first embodiment. FIG. 9A shows the case where an abnormality occurred in comparison in the inspection strip 1 for which the comparison circuit 1 performed comparison processing. According to the first embodiment, defining the comparison circuit 108 (here, as an example, the comparison circuit 1) that performed comparison processing for the inspection strip 20 (here, as an example, the inspection strip 1) has been determined to have an inspection abnormality as a candidate for the malfunction, the malfunction diagnosis circuit 134 makes two or more comparison circuits 108 that contain the candidate for the malfunction perform comparison processing in parallel for the inspection strip 20 that has been determined to have the inspection abnormality. In FIG. 9B, for example, all the comparison circuits 1 to 10 are allowed to perform comparison processing for the same inspection strip 1. However, it is not limited thereto. As mentioned above, if two or more comparing circuits 108 including a comparing circuit which is the candidate for malfunction are left, it is accepted to perform comparison processing for the same inspection strip 1. As data of a fringe image, those which have already been acquired may be used. Similarly, as data of a reference image, those which have already been generated may be used. However, this is not limited thereto. Although it requires time, the scanning may be performed again to acquire data, and alternatively a reference image may be generated again.Then, based on comparison results generated in parallel in two or more comparison circuits, it is diagnosed whether or not the comparison circuit (here, as an example, the comparison circuit 1) which is the candidate for malfunction has a malfunction. Specifically, if an inspection abnormality is detected in comparison processing performed by the comparison circuit (here, as an example, the comparison circuit 1) which is the candidate for malfunction and no inspection abnormality is detected in the comparison processing performed by another comparison circuit 108, the malfunction diagnosis circuit 134 diagnoses that the comparison circuit (here, as an example, the comparison circuit 1) which is the candidate for malfunction has a malfunction. Moreover, even if an inspection abnormality is not determined in the comparison processing performed by the comparison circuit (here, as an example, the comparison circuit 1) that is the candidate for malfunction, if its number of defects in the comparison processing is larger than that of another comparison circuit 108, it is acceptable to diagnose that the comparison circuit (here, as an example, the comparison circuit 1) that is the candidate for malfunction has a malfunction. If an inspection abnormality in the comparison processing is also detected in another comparison circuit 108, the malfunction diagnosis circuit 134 determines that there is no device malfunction (failure) but that the substrate 101 itself has a defect. Information to the comparison circuit 108 determined as a malfunction is output from the assignment processing circuit 136, and the information (for example, identification information) input to the assignment processing circuit 136 is stored in the storage device 57. Then, the control computer 110 controls to resume the comparison processing.In the comparison circuit exclusion step (S 140), the assignment processing unit 56 excludes the comparison circuit 108 (for example, the comparison circuit 1) diagnosed as a malfunction from the assignment target to which an inspection strip is assigned. Then, the assignment processing unit 56 individually assigns the inspection strips 20 where the comparison processing is to be performed to the comparison circuits 108 (for example, the comparison circuits 2 to 10) that are not diagnosed as malfunctions in a plurality of comparison circuits 108.FIG. 10 shows an example of post-diagnosis assignment processing for malfunction according to the first embodiment. FIG. 10 shows the case where the comparison circuit 1 is diagnosed as a malfunction, for example. If comparison processing is promptly interrupted when an abnormality in the comparison processing is determined, the comparison processing has not been completed with respect to not only the inspection strips 1 but also the inspection strips 2 to 10. Therefore, with reference to identification information to the malfunction comparison circuit stored in the storage device 57, the assignment processing unit 56 assigns the inspection strips 1 to 9 to the comparison circuits 2 to 10 again.If, when an inspection abnormality is determined in the comparison processing, the control computer waits without comparison processing of the next inspection strip 20 after completion of the comparison processing for the inspection strips currently being performed, the comparison processing for the inspection strips 2 to 10 has been finished. In this case, since it is not necessary to perform the comparison processing in an overlapping manner, the assignment processing unit 56 assigns the inspection strip 1 to the comparison circuit 2 again and assigns the inspection strips 11 to 18 that are before the comparison processing to the comparison circuits 3 to 10.The comparison circuits 2 to 10 individually perform comparison processing for each subsequent inspection strip 20 assigned.As described above, by detecting a malfunction comparing circuit 108 and excluding it from the assignment target to which an inspection strip is assigned, the comparison processing can be continued using the remaining comparing circuits 108.As described above, according to the first embodiment, when defects frequently occur even if the inspection device 100 malfunctions, it is possible to avoid a long downtime. Therefore, for example, taking urgent countermeasures at a feitage or at night can be reduced.Second EmbodimentAlthough in the first embodiment, two or more comparison circuits including a comparison circuit that is a candidate for malfunction perform comparison processing for the inspection strip 20 determined to have an inspection abnormality, embodiments are not limited thereto. A second embodiment describes a configuration in which regions for comparison processing are shifted to make the comparison processing new. The configuration of the inspection device 100 is the same as that of FIG. 1 The flowchart of an inspection method is the same as that of FIG. 3 In the second embodiment, the contents of each step except the malfunction diagnosis step (S122) are the same as those of the first embodiment.FIGS. 11A and 11B illustrate a method for diagnosing malfunction according to the second embodiment. Similarly to FIG. 9A, FIG. 11A shows the case where an abnormality occurred in the inspection strip 1 for which the comparison circuit 1 performed comparison processing.According to the second embodiment, in the malfunction diagnosis step (S122), defining the comparison circuit 108 (here, as an example, the comparison circuit 1) which performed comparison processing for the inspection strip 20 (here, as an example of the inspection strip 1) to have an inspection abnormality as a candidate for malfunction, the malfunction diagnosis circuit 134 shifts the assignment target and re-assigns each of the plurality of inspection strips 20 including the inspection strip 20 (here, as an example, the inspection strip 1) determined to have the inspection abnormality not to re-assign the inspection strip 20 determined to have the inspection abnormality to the comparison circuit 108 that is the candidate for malfunction. Then, a plurality of comparison circuits 108 perform parallel comparison processing for the inspection strips 20 that have been shifted and allocated. In FIG. 11B, for example, the comparison circuits 1 to 9 perform comparison processing for the inspection strips 2 to 10, and the comparison circuit 10 performs comparison processing for the inspection strip 1 determined to have an inspection abnormality. As data of a strip image of each inspection strip 20, the one that has already been acquired can be used. Similarly, as data of a reference image, the one which has already been generated can be used.Based on comparison results generated in a plurality of comparison circuits 108 to which the inspection stripes 20 have been assigned, it is diagnosed whether or not the comparison circuit (here, as an example, the comparison circuit 1) which is the candidate for the malfunction has a malfunction. For example, if an inspection abnormality in the comparison processing determined to have an inspection abnormality for which the comparison circuit 10 performs the comparison processing is performed again, and an inspection abnormality in the inspection strip 2 for which the comparison circuit 1 which is the candidate for the malfunction that performed the comparison processing is detected, it is diagnosed that the comparison circuit (here, as an example, the comparison circuit 1) which is the candidate for the malfunction has a malfunction. If an inspection abnormality is not detected in the comparison processing performed in the inspection strip 2 for which the comparison circuit 1 is the candidate for the malfunction performed by the comparison processing and an inspection abnormality is detected in the comparison processing for the inspection strip 1 for which the comparison circuit 10 performed the comparison processing, it is determined that there is no device malfunction (failure) but that the substrate 101 itself has a defect. Information about the comparison circuit 108 determined as a malfunction is output to the assignment processing circuit 136.As described above, by detecting the malfunction comparing circuit 108 and excluding it from the assignment target to which an inspection strip is assigned, similarly to the first embodiment, the comparison processing using the remaining comparing circuits 108 can be continued.Third EmbodimentAlthough in the first and second embodiments, the diagnosis for malfunction existence is performed after checking whether or not the comparison circuit which is a candidate for the malfunction actually has a malfunction, embodiments are not limited thereto. The third embodiment describes a configuration where the examination is omitted if a malfunction actually occurs. The configuration of the inspection device 100 is the same as that of FIG. 1 The flowchart of an inspection method is the same as that of FIG. 3 In the third embodiment, the contents of each step except the malfunction diagnosis step (S122) are the same as those of the first embodiment.According to the third embodiment, in the malfunction diagnosis step (S122), the malfunction diagnosis circuit 134 promptly diagnoses that the comparison circuit that performed the comparison processing for the inspection strip 20 determined to be abnormal in comparison has a malfunction. Information about the comparison circuit 108 determined as a malfunction is output to the assignment processing circuit 136.As described above, by diagnosing the comparison circuit 108 having an assumed malfunction (failure) to be a malfunction comparison circuit and excluding it from the assignment target to which the inspection strip 20 is assigned, similarly to the first and second embodiments, the comparison processing using the remaining comparison circuits 108 can be continued. Thus, in the third embodiment, since it is not checked whether or not a comparison circuit actually malfunctions, the time period for resuming the comparison processing can be reduced.Although in each embodiment described above, it is diagnosed for each comparison circuit 108 whether or not there is a malfunction, embodiments are not limited thereto.FIG. 12 shows an example of the internal configuration of each comparison circuit according to a modified example of each embodiment. As shown in FIG. 12, in each of a plurality of comparison circuits 108, there are arranged storage devices 70, 72, and 76, such as magnetic disk drives, the frame image generation unit 74, and a plurality of sub-comparison circuits 1 to 10.Comparison processing for each frame region 30 in the inspection strip 20 assigned to the comparison circuit 108 is performed in parallel decentralized individually by each of the sub-comparison circuits 1 to 10. Thereby, the comparison processing time can be reduced.FIGS. 13A and 13B illustrate a method for diagnosing a malfunction according to a modified example of each embodiment. FIG. 13A shows the case where comparison processing is performed for the k-th inspection strip 20 by the comparison circuit k. Frame regions 1 to 10 in the k-th inspection strip 20 are individually assigned to a corresponding one of a plurality of sub-comparison circuits 1 to 10 in the comparison circuit k. Then, each of the sub-comparison circuits 1 to 10 performs comparison processing for the allocated frame region 30.In the case of FIG. 13A, an abnormality occurs in the comparison processing for the frame region 1 performed by the sub-comparison circuit 1. The abnormality in the comparison processing may be determined by the inspection abnormality determination unit 54 based on the number of defects calculated by the number-of-defects in-frame calculation unit 50.The method for diagnosing a malfunction may be carried out by replacing a comparison circuit described in any one of the first to third embodiments with a sub-comparison circuit. For example, the case associated with the use of the first embodiment will be described below. Defining the sub-comparison circuit 1 that performed the comparison processing for the frame region 30 (here, as an example, the frame 1) determines to have an inspection abnormality as a candidate for a malfunction, the malfunction diagnosis circuit 134 makes two or more sub-comparison circuits 1 to 10 including the candidate for the malfunction perform comparison processing in parallel for the frame region 30 determined to have the inspection abnormality. In the case of FIG. 13B, for example, all of the sub-comparison circuits 1 to 10 are left to perform comparison processing for the same frame 1.Then, based on comparison results generated in parallel in two or more sub-comparison circuits, it is diagnosed whether or not the sub-comparison circuit (here, as an example, the sub-comparison circuit 1) which is the candidate for the malfunction has a malfunction. Specifically, if an inspection abnormality is detected in the comparison processing performed by the sub-comparison circuit (here, as an example, the sub-comparison circuit 1) which is the candidate for the malfunction and no inspection abnormality is detected in the comparison processing performed by another sub-comparison circuit, the malfunction diagnosis circuit 134 diagnoses that the sub-comparison circuit (here, as an example, the sub-comparison circuit 1) which is the candidate for the malfunction has a malfunction. Moreover, even if an inspection abnormality is not determined in the comparison processing performed by the sub-comparison circuit (here, as an example, the sub-comparison circuit 1) which is the candidate for the malfunction, if its number of defects in the comparison processing is larger than that of another sub-comparison circuit, it is acceptable to diagnose that the sub-comparison circuit (here, as an example, the sub-comparison circuit 1) which is the candidate for the malfunction is malfunctioning. If an inspection abnormality is detected also in the comparison processing performed by another sub-comparison circuit, the malfunction diagnosis circuit 134 determines that there is no device malfunction (failure) but that the substrate 101 itself has a defect. Information on the sub-comparison circuit determined as a malfunction is output to the assignment processing circuit 136, and the information (for example, identification information) input to the assignment processing circuit 136 is stored in the storage device 57. Then, the control computer 110 controls resumption of the comparison processing.In the comparison circuit exclusion step (S 140), the assignment processing unit 56 excludes the comparison circuit 108 (for example, the sub comparison circuit 1) diagnosed as a malfunction from the assignment target to which the frame region 30 is assigned. Then, the assignment processing unit 56 individually assigns the frame regions 30 where comparison processing is to be performed to the sub-comparison circuits (for example, the sub-comparison circuits 2 to 10) that are not diagnosed as malfunctions in a plurality of sub-comparison circuits 1 to 10.FIG. 14 shows an example of post-diagnosis assignment processing for malfunction according to a modified example of each embodiment. FIG. 14 shows the case where, for example, the sub-comparison circuit 1 is diagnosed as a malfunction. If comparison processing is promptly interrupted when an abnormality in the comparison processing is determined, the comparison processing has completed not only with respect to the frame 1 but also the frame regions 2 to 10.The sub-comparison circuits 2 to 10 individually perform the comparison processing for each subsequent frame region 30.As described above, by detecting a malfunction sub-comparison circuit and excluding it from the assignment target to which the frame region 30 is assigned, the comparison processing using the remaining sub-comparison circuits can be continued.Embodiments have been explained with reference to specific examples described above. However, the present invention is not limited to these specific examples. For example, although a transmission illumination optical system using a transmitted light is described as the illumination optical system 170 in embodiments, it is not limited thereto. For example, a reflection illumination optical system with a reflected light may also be used. Alternatively, a transmitted light and a reflected light may be simultaneously used by combining a transmission illumination optical system and a reflection illumination optical system.While the device configuration, the control method, and the like that are not directly necessary for explaining the present invention are not described, some or all of them may be appropriately selected and used on a case-by-case basis as appropriate.In addition, any other pattern developing device and pattern inspection methods that contain elements of the present invention and that can be appropriately modified by those skilled in the art are included within the scope of the present invention.

Claims

An inspection apparatus (100) comprising: an optical image acquisition mechanism (150) configured to acquire an optical image of each of a plurality of regions on a substrate to be inspected on which a pattern is formed; a plurality of comparison circuits (108) configured to individually perform comparison processing of comparing the optical image with a reference image corresponding to the optical image; an inspection abnormality determination circuit (132) configured to determine whether there is a region having an inspection abnormality in the plurality of regions based on comparison results generated in the plurality of comparison circuits; a malfunction diagnosis circuit (134) configured to diagnose whether a comparison circuit that performed comparison processing for the region determined to have the inspection abnormality in the plurality of regions has a malfunction; and an assignment processing circuit (136) configured to individually assign regions of the plurality of regions where comparison processing is to be performed to comparison circuits that are not diagnosed as malfunctions in the plurality of comparison circuits, and exclude a comparison circuit diagnosed as a malfunction from a target to which a region is assigned.The inspection device according to claim 1, wherein the inspection abnormality determination circuit (132) includes a calculation circuit (50) that calculates, for each first region, the number of errors in each first region with reference to a result of the comparison processing; a calculation circuit (52) that calculates, for each second region including a plurality of first regions, the number of errors in each second region by summing up the number of errors in the respective first regions; and an inspection abnormality determination circuit (54) that determines, for each second region, whether the number of errors is equal to or greater than a threshold value.The inspection device according to claim 1, wherein the assignment processing circuit (136) includes a storage device (57) that stores information on a malfunctioned comparison circuit; and an assignment processing circuit (56) that individually assigns the areas of the plurality of areas in which comparison processing is to be performed to comparison circuits that are not diagnosed as malfunctions in the plurality of comparison circuits and excludes the malfunctioned comparison circuit from the target to which the area is assigned based on the information on a malfunctioned comparison circuit.A pattern inspection method comprising: acquiring an optical image of each of a plurality of regions on a substrate to be inspected on which a pattern is formed; performing comparison processing of comparing the optical image with a reference image corresponding to the optical image using each of a plurality of comparison circuits, and outputting each of comparison results; determining, based on the comparison results generated in the plurality of comparison circuits, whether there is a region having an inspection abnormality in the plurality of regions; diagnosing whether a comparison circuit that performed comparison processing for the region determined to have the inspection abnormality has a malfunction in the plurality of regions; excluding a comparing circuit diagnosed as a malfunction in the plurality of comparing circuits from a target to which a region is assigned and assigning regions where comparing processing has not yet been performed in the plurality of regions to comparing circuits not diagnosed as malfunctions.The pattern inspection method according to claim 4, wherein defining the comparison circuit that has performed the comparison processing for the region for which the abnormality in the inspection has been detected as a candidate for a malfunction comprises causing at least two comparison circuits that include the candidate for a malfunction to perform comparison processing for the region for which the abnormality in the inspection has been detected in parallel, and diagnosing, based on the comparison results generated in the at least two comparison circuits, whether the comparison circuit that is the candidate for a malfunction has a malfunction.The pattern inspection method according to claim 5, wherein in a case where abnormality in inspection is detected in the comparison processing performed by the comparison circuit that is the candidate for malfunction and no abnormality in inspection is detected in the comparison processing performed by another comparison circuit, it is diagnosed that the comparison circuit that is the candidate for malfunction has malfunction.The pattern inspection method according to claim 5, wherein in a case where abnormality is not detected in the inspection in the comparison processing performed by the comparison circuit which is a candidate for a malfunction but the number of errors in the comparison processing performed by the comparison circuit which is a candidate for a malfunction is larger than in the comparison processing performed by another comparison circuit, it is diagnosed that the comparison circuit which is a candidate for a malfunction has a malfunction.The pattern inspection method according to claim 4, wherein defining the comparison circuit that has performed the comparison processing for the region for which the abnormality in the inspection has been detected as a candidate for a malfunction comprises shifting the assignment target and individually re-assigning the regions including the region for which the abnormality in the inspection has been detected to the plurality of comparison circuits so as not to re-assign the region for which the abnormality in the inspection has been detected to the comparison circuit that is a candidate for a malfunction, and diagnosing whether the comparison circuit that is the candidate for a malfunction has a malfunction based on the comparison results generated in the plurality of comparison circuits to which the regions have been re-assigned, and based on the comparison results.The pattern inspection method according to claim 8, wherein in a case where an abnormality in the inspection is not detected in the comparison processing performed again in the region for which the irregular inspection is detected, and an abnormality in the inspection is detected in the comparison processing performed in a region at a shifted assignment target for which the comparison circuit that is a candidate for a malfunction has performed the comparison processing, it is diagnosed that the comparison circuit that is a candidate for a malfunction has a malfunction.The pattern inspection method according to claim 4, wherein the comparison circuit that has performed the comparison processing for the region where the abnormality in the inspection has been detected is diagnosed to have a malfunction.A pattern inspection apparatus (100) comprising: an optical image acquisition mechanism (150) configured to acquire an optical image of a plurality of regions on a substrate to be inspected on which a pattern is formed; a plurality of comparison circuits (108) each configured to include a plurality of sub-comparison circuits that individually perform comparison processing of comparing the optical image with a reference image corresponding to the optical image; an abnormality determination circuit (132) configured to determine whether there is a region having an inspection abnormality in the plurality of regions based on comparison results generated in the plurality of sub-comparison circuits; a malfunction diagnosis circuit (134) configured to diagnose whether a sub-comparison circuit that has performed comparison processing for the region determined to have the inspection abnormality malfunctions in the plurality of regions; and an assignment processing circuit (136) configured to individually assign regions of the plurality of regions where comparison processing is to be performed to sub-comparison circuits that are not diagnosed as malfunctions in the plurality of sub-comparison circuits that include a sub-comparison circuit diagnosed as a malfunction, and exclude the sub-comparison circuit diagnosed as a malfunction from a target to which a region is assigned.A pattern inspection method comprising: acquiring an optical image of each of a plurality of regions on a substrate to be inspected on which a pattern is formed; individually performing comparison processing for comparing the optical image with a reference image belonging to the optical image using each of a plurality of sub-comparison circuits, each of a plurality of comparison circuits (108) being configured to include the plurality of sub-comparison circuits, and outputting each of the comparison results; determining, based on the comparison results generated in the plurality of sub-comparison circuits, whether there is a region having abnormality in inspection in the plurality of regions; diagnosing whether a sub-comparison circuit that has performed comparison processing for the region for which the abnormality of the inspection has been detected in the plurality of regions has a malfunction; and individually assigning regions of the plurality of regions in which comparison processing is to be performed to sub-comparison circuits that are not diagnosed as malfunctions in the plurality of sub-comparison circuits including a sub-comparison circuit in which a malfunction has been diagnosed, and excluding the sub-comparison circuit in which the malfunction has been diagnosed from a target to which a region is assigned.The pattern inspection method according to claim 12, wherein defining the sub-comparison circuit that has performed the comparison processing for the region determined to have the inspection abnormality as a candidate for the malfunction, the diagnosing comprises causing the at least two sub-comparison circuits including the candidate for the malfunction to perform comparison processing in parallel for the region determined to have the inspection abnormality, and diagnosing, based on comparison results generated in the at least two sub-comparison circuits, whether the sub-comparison circuit that is the candidate for the malfunction has a malfunction.The pattern inspection method according to claim 12, wherein the sub-comparison circuit defining the comparison processing for the region determined to have the inspection abnormality as a candidate for the malfunction, wherein the diagnosing comprises shifting the assignment target and individually re-assigning the plurality of regions including the region determined to have the inspection abnormality to the plurality of sub-comparison circuits so as not to re-assign the region determined to have the inspection abnormality to the sub-comparison circuit which is the candidate for the malfunction, and diagnosing, based on the comparison results generated in the plurality of sub-comparison circuits to which the regions have been re-assigned, whether the comparison circuit which is the candidate for the malfunction, a malfunction has occurred.

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