Semiconductor memory device with a dielectric composite film structure and method for forming the same

Abstract

Semiconductor device (100), comprising: a substrate (210) having a storage region (212) and an edge region (214); a transistor (LT) having a metal gate (MG) located in the peripheral region (214); a dielectric composite film structure (101) overlying the metal gate (MG) of the transistor (LT), the dielectric composite film structure (101) comprising a first layer of dielectric material (102) and a second layer of dielectric material (103) over the first layer of dielectric material (102), and the second layer of dielectric material (103) having a greater density than a density of the first layer of dielectric material (102); and at least one memory cell (SGMC1, SGMC2) located in the memory region (212), wherein a lower surface of the dielectric composite film structure (101) is coplanar with an upper surface of the at least one memory cell (SGMC1, SGMC2).

Description

BACKGROUND

[0001] The semiconductor integrated circuit (IC) industry has experienced exponential growth over the past decades. As ICs have evolved, functional density (i.e., the number of interconnected components per chip area) has generally increased, while geometry size (i.e., the smallest component (or circuit) that can be created using a manufacturing process) has decreased.

[0002] Super Flash technology has enabled designers to create cost-effective and high-performance programmable system-on-chip (SOC) solutions through the use of split-gate flash memory cells. The aggressive scaling of third-generation embedded Super Flash (ESF3) enables flash memory with high memory array density.

[0003] From the document US 2019 / 0 304 991 A1, a three-dimensional semiconductor memory device is known, which comprises a substrate with a memory region and an edge region. A transistor having a metal gate is arranged in the edge region, with a hard mask arranged over the metal gate and a dummy sacrificial layer arranged over the hard mask. Another semiconductor device is also known from the document US 2020 / 0 168 701 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 is a vertical cross-sectional view of a memory device according to various embodiments of the present disclosure. Fig. 2 is a vertical cross-sectional view of an exemplary intermediate structure for forming a memory device comprising a substrate, first and second dielectric layers, and a patterned mask, according to various embodiments of the present disclosure. Fig. 3 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process that removes the second dielectric layer, the first dielectric layer, and portions of the substrate from the storage region, according to various embodiments of the present disclosure. Fig. 4 is a vertical cross-sectional view of the exemplary intermediate structure showing a dielectric material layer deposited over the recessed surface of the substrate in the storage region, according to various embodiments of the present disclosure. Fig. 5 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process that removes a portion of the second dielectric layer from the edge region and a portion of a dielectric material layer from the storage region, according to various embodiments of the present disclosure. Fig. 6 is a vertical cross-sectional view of the exemplary intermediate structure showing a second dielectric layer over the tunnel layer in the memory region and in the edge region and a patterned mask over the second dielectric layer in the memory region and a portion of the edge region, according to various embodiments of the present disclosure. Fig. 7 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process that removes a portion of the second dielectric layer in the edge region, according to various embodiments of the present disclosure. Fig. 8 is a vertical cross-sectional view of the exemplary intermediate structure showing a plurality of isolation features extending through the first and second dielectric layers and into the substrate in the memory region and in the edge region, according to various embodiments of the present disclosure. Fig. 9 is a vertical cross-sectional view of the exemplary intermediate structure showing a third dielectric material layer over the top surfaces of the second dielectric layer and the isolation features, a fourth dielectric material layer over a top surface of the third dielectric material layer, and a patterned mask over a top surface of the fourth dielectric material layer, according to various embodiments of the present disclosure. Fig. 10 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process that removes portions of the fourth dielectric layer, the third dielectric layer, and the second dielectric layer from the memory region and exposes isolation features and the top surface of the tunnel layer in the memory region, according to various embodiments of the present disclosure. Fig. 11 is a vertical cross-sectional view of the exemplary intermediate structure showing a continuous floating gate layer over the tunnel layer and the first isolation features in the memory region and over the fourth dielectric layer and the second isolation feature in the edge region, according to various embodiments of the present disclosure. Fig. 12 is a vertical cross-sectional view of the exemplary intermediate structure following a planarization process to remove portions of the floating gate layer and the fourth dielectric material layer above a top surface of the third dielectric material layer, according to various embodiments of the present disclosure. Fig. 13 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process that recesses the floating gate layer and the first isolation features in the memory region, according to various embodiments of the present disclosure. Fig. 14 is a vertical cross-sectional view of the exemplary intermediate structure of Fig. 13 along a horizontal direction relative to that shown in Fig. 2-13 is rotated by 90°. Fig. 15 is a vertical cross-sectional view of the exemplary intermediate structure showing a barrier layer, a control gate layer, a hard mask, and a patterned mask formed over the memory region and the edge region, according to various embodiments of the present disclosure. Fig. 16 is a vertical cross-sectional view of the exemplary intermediate structure showing multiple memory stacks above the floating gate layer in the memory region, according to various embodiments of the present disclosure. Fig. 17 is a vertical cross-sectional view of the exemplary intermediate structure showing sidewall structures formed over the side surfaces of the memory stacks, according to various embodiments of the present disclosure. Fig. 18 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process to remove portions of the floating gate layer and the tunnel layer from the memory region, according to various embodiments of the present disclosure. Fig. 19 is a vertical cross-sectional view of the exemplary intermediate structure showing intergate dielectric layers formed over the side surfaces of the memory stacks, according to various embodiments of the present disclosure. Fig. 20 is a vertical cross-sectional view of the exemplary intermediate structure showing common source regions between adjacent pairs of memory stacks formed via a masked implantation process, according to various embodiments of the present disclosure. Fig. 21 is a vertical cross-sectional view of the exemplary intermediate structure showing the intergate dielectric layers removed from the side surfaces of the memory stacks adjacent to the common source regions, according to various embodiments of the present disclosure. Fig. 22 is a vertical cross-sectional view of the exemplary intermediate structure showing common dielectric source layers over the common source regions and over the side surfaces of the memory stacks, according to various embodiments of the present disclosure. Fig. 23 is a vertical cross-sectional view of the exemplary intermediate structure showing a dielectric select gate layer over the substrate in the memory region, a conductive material layer over the memory region and the edge region of the intermediate structure, and a BL coating over the conductive material layer, according to various embodiments of the present disclosure. Fig. 24 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process that removes the BL coating from the intermediate structure and the conductive material layer over the edge region and removes the conductive material layer within the storage region of the intermediate structure, according to various embodiments of the present disclosure. Fig. 25 is a vertical cross-sectional view of the exemplary intermediate structure showing a hard mask layer over the storage region and the edge region of the intermediate structure, according to various embodiments of the present disclosure. Fig. 26 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process that removes the hard mask layer from the edge region and over top surfaces of the memory stacks in the memory region and removes portions of the hard mask layer and the conductive material layer between adjacent pairs of memory stacks, according to various embodiments of the present disclosure. Fig. 27 is a vertical cross-sectional view of the example intermediate structure following an additional etch process that removes a dielectric material layer and a portion of dielectric material layer from the edge region of the example structure, according to various embodiments of the present disclosure. Fig. 28 is a vertical cross-sectional view of the exemplary intermediate structure showing a BL coating over the exemplary intermediate structure, according to various embodiments of the present disclosure. Fig. 29 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process that removes the BL liner and additional portions of the memory stacks and the hard mask layer from the memory region, according to various embodiments of the present disclosure. Fig. 30 is a vertical cross-sectional view of the exemplary intermediate structure showing a liner layer over exposed surfaces of the exemplary intermediate structure, according to various embodiments of the present disclosure. Fig. 31 is a vertical cross-sectional view of the exemplary intermediate structure showing a finishing layer formed over the liner layer and a BARC layer over the finishing layer, according to various embodiments of the present disclosure. Fig. 32 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process to remove the BARC layer and reduce the thickness of the termination layer over the exemplary intermediate structure, according to various embodiments of the present disclosure. Fig. 33 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process to remove the termination layer, the liner layer, dielectric material layers, and the control gate layer from the edge region, according to various embodiments of the present disclosure. Fig. 34 is a vertical cross-sectional view of the exemplary intermediate structure following an additional etch process to remove the barrier layer and the third dielectric layer from the edge region of the exemplary intermediate structure, according to various embodiments of the present disclosure. Fig. 35 is a vertical cross-sectional view of the exemplary intermediate structure showing additional termination material over the storage region and the edge region, according to various embodiments of the present disclosure. Fig. 36 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process to remove the termination layer from the edge region, according to various embodiments of the present disclosure. Fig. 37 is a vertical cross-sectional view of the exemplary intermediate structure following an additional etch process to remove the second dielectric material layer from the edge region, according to various embodiments of the present disclosure. Fig. 38 is a vertical cross-sectional view of the exemplary intermediate structure illustrating a masked ion implantation process performed in a first portion of the edge region, according to various embodiments of the present disclosure. Fig. 38 is a vertical cross-sectional view of the exemplary intermediate structure showing a masked ion implantation process performed in a second portion of the edge region, according to various embodiments of the present disclosure. Fig. 40 is a vertical cross-sectional view of the example intermediate structure showing a layer of gate dielectric material over the example structure, a sacrificial gate material layer over the layer of gate dielectric material, and a hard mask layer over the sacrificial gate material layer, according to various embodiments of the present disclosure. Fig. 41 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process to remove the hard mask layer and a portion of the sacrificial gate material layer above the termination layer, according to various embodiments of the present disclosure. Fig. 42 is a vertical cross-sectional view of the exemplary intermediate structure showing a plurality of gate stacks formed over the layer of gate dielectric material in the edge region, according to various embodiments of the present disclosure. Fig. 43 is a vertical cross-sectional view of the exemplary intermediate structure showing gate stack side seal layers over the side surfaces of the gate stacks, according to various embodiments of the present disclosure. Fig. 44 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process that removes the gate dielectric material layer and the termination layer from the memory region, according to various embodiments of the present disclosure. Fig. 45 is a vertical cross-sectional view of the exemplary intermediate structure schematically illustrating an ion implantation process for forming source and drain regions for logic transistors that may subsequently be formed in the edge region, according to various embodiments of the present disclosure. Fig. 46 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process to remove portions of the gate dielectric material layer from the edge region and the formation of main sidewall spacers over the select gates in the memory region and main sidewall spacers over the gate stacks in the edge region, according to various embodiments of the present disclosure. Fig. 47 is a vertical cross-sectional view of the exemplary intermediate structure showing metal silicide regions on exposed surfaces of the substrate, according to various embodiments of the present disclosure. Fig. 48 is a vertical cross-sectional view of the exemplary intermediate structure following a planarization process that removes the remaining portions of the hard mask and the select gate hard mask layer from the memory region and the remaining portions of the hard mask layer from the gate stacks in the edge region, according to various embodiments of the present disclosure. Fig. 49 is a vertical cross-sectional view of the exemplary intermediate structure showing a contact etch stop layer (CESL) conformally formed over the intermediate structure and an interlayer dielectric (ILD) layer formed over the CESL, according to various embodiments of the present disclosure. Fig. 50 is a vertical cross-sectional view of the exemplary intermediate structure following a planarization process that removes the ILD layer and the CESL over the top surfaces of the control gates, select gates, and erase gates in the memory region and over the top surfaces of the sacrificial gate material layers in the edge region, according to various embodiments of the present disclosure. Fig. 51 is a vertical cross-sectional view of the exemplary intermediate structure showing metal gates formed in the edge region, according to various embodiments of the present disclosure. Fig. 52 is a vertical cross-sectional view of the exemplary intermediate structure showing a first layer of dielectric material over the edge region and over the control gates of the memory cells in the memory region, according to various embodiments of the present disclosure. Fig. 53 is a vertical cross-sectional view of the exemplary intermediate structure showing a second layer of dielectric material over the first layer of dielectric material in the edge region, according to various embodiments of the present disclosure. Fig. 54 is a vertical cross-sectional view of the exemplary intermediate structure showing metal silicide layers over the top surfaces of the select gates and the erase gates in the memory region, according to various embodiments of the present disclosure. Fig. 55 is a vertical cross-sectional view of the exemplary intermediate structure showing an interlayer dielectric (ILD) layer over the intermediate structure, metal features over the ILD layer, and conductive vias extending between the metal features and the memory cells and the logic transistors, according to various embodiments of the present disclosure. Fig. 56 is a flow diagram illustrating a general method of manufacturing a memory device according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements such that the first and second structural elements may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplification and clarity and does not in itself imply any relationship between the different embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "underlying," "beneath," "under," "overlying," "upper," and the like may be used herein for ease of description to describe the relationship of one element or structural element to another element(s) or structural element(s) as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0007] The present disclosure is directed to semiconductor devices and, in particular, to semiconductor memory devices having memory cells and logic transistors formed on a common substrate.

[0008] Fig. 1 illustrates a cross-sectional view of a memory device 100 according to various embodiments of the present disclosure. In some embodiments, the memory device 100 may be an ESF3 memory device, or a so-called "third generation SUPERFLASH" memory device 100. For example, the ESF3 memory device 100 may include an array of symmetric split-gate cells SGMC1, SGMC2. Each split-gate memory cell SGMC1, SGMC2 may include a source region CS, a drain region DR, and a channel region CR disposed therebetween. In the ESF3 architecture, the source regions CS for each of the split-gate memory cells SGMC1, SGMC2 may be a common source region CS shared with its neighboring cell. Each split-gate memory cell (e.g., SGMC1 and SGMC2) may include its own drain region DR. A person of ordinary skill in the art would understand that the source regions CS may also be assigned to the drain regions DR.Therefore, in other embodiments, the adjacent split-gate memory cells may share a common drain region DR.

[0009] Within each split-gate cell SGMC1, SGMC2, a floating gate FG may be arranged above the channel region CR of the split-gate cell SGMC1, SGMC2. Furthermore, a control gate CG may be arranged above the floating gate FG. A select gate SG may be arranged on one side of the floating gate FG and the control gates CG (e.g., between an individual source / drain region CS, DR of the SF3 memory cell and a sidewall of the floating gate FG and / or control gate CFG). An erase gate EG may be arranged above a common source / drain region CS between the split-gate cells SGMC1 and SGMC2. At least one split-gate cell SGMC1, SGMC2 may be configured to store a variable charge level on its floating gate FG, wherein the level of this charge corresponds to a data state stored in the cell split-gate cell SGMC, SGMC2 and may be stored non-volatilely so that the stored charge / data persists in the absence of power.

[0010] A typical flash memory cell uses a floating gate FG to store a bit through the presence or absence of a charge. If the floating gate FG is not charged (i.e., neutral), the device operates similarly to a conventional MOSFET. For example, a positive charge in the control gate CF creates a channel CR in the semiconductor material substrate 210 that carries a current from the source CS to the drain region DR. However, in cases where the floating gate FG is negatively charged, this charge somewhat shields the channel region CR from the control gate CG and prevents the formation of a channel between the source CS and drain DR. The threshold voltage V th is the voltage applied to the control gate CG at which a transistor becomes conductive. The presence or absence of charge results in a more positive or negative threshold voltage V thIn flash memory terms, programming (inserting electrons into the floating gate FG) means writing a 0, while erasing (removing charge from the floating gate FG) means resetting the flash memory contents to 1; in other words, a programmed cell stores a logical 0, while an erased (also known as flashed) split-gate memory cell SGMC1, SGMC2 stores a logical 1.

[0011] In various embodiments, an ESF3 memory device 100 as shown in Fig. 1, an array of split-gate memory cells SGMC1, SGMC2 within a memory region 212 of the device 100. In some embodiments, at least some of the split-gate memory cells SGMC1, SGMC2 may share a common drain region DR with a neighboring cell along a first horizontal direction (HD1). The select gates SG, which may also be referred to as word lines WLs, may be located between split-gate memory cells SGMCs of the array along a second horizontal direction (HD2, see Fig. 2) that is perpendicular to the first horizontal direction (HD1). In embodiments, adjacent split-gate memory cells (SGMCs) may be separated from each other along the second horizontal direction (HD2) by isolation features, such as trench isolation (STI) features.

[0012] Again in relation to Fig. 1, according to various embodiments, the memory device 100 may also include an edge region 214. The edge region 214 may include a plurality of logic transistors LT1, LT2. Each of the logic transistors LT1, LT2 may have a metal gate MG arranged above a channel region CR of the logic transistor LT1, LT2 and source and drain regions SD on both sides of the metal gate MG. The logic transistors LT1, LT2 in the edge region 214 may form logic components such as memory selectors, power gates, and input / output elements of the memory device 100.

[0013] Again in relation to Fig. 1, a composite dielectric film structure 101 may extend over each of the metal gates MG of the logic transistors LT1, LT2 within the edge region 214 of the memory device 100. The composite dielectric film structure 101 may include at least two layers of dielectric material 102, 103. In some embodiments, each of the layers of dielectric material 102, 103 may have a thickness of at least about 5 nm, such as between about 5 nm and about 30 nm (e.g., between ~5 nm and ~15 nm). A total thickness of the composite dielectric film structure 101 may be between about 10 nm and about 60 nm (e.g., between ~10 nm and about 45 nm), which may provide adequate protection for the metal gates MG during fabrication of the memory device 100.

[0014] In various embodiments, the dielectric composite film structure 101 may include a first layer of dielectric material 102. The first layer of dielectric material 102 may overlie a top surface of the metal gates MG of the logic transistors LT1, LT2. In some embodiments, the first layer of dielectric material 102 may directly contact the top surface of the metal gates MG of the logic transistors LT1, LT2. The first layer of dielectric material 102 may be composed of a suitable dielectric material, such as an oxide or nitride material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). In some embodiments, the first layer of dielectric material 102 may be composed of silicon oxide formed using a tetraethoxysilane (TEOS) precursor.In some embodiments, the first layer of dielectric material 102 may be a photoresist protective oxide (RPO) material. Other suitable dielectric materials are within the contemplated scope of the disclosure. In some embodiments, the first layer of dielectric material 102 may have good adhesion properties, including good adhesion to the material(s) of the metal gates MG of the logic transistors LT1, LT2.

[0015] The dielectric composite film structure 101 may include a second layer of dielectric material 103 that may overlie the first layer of dielectric material 102. In some embodiments, the second layer of dielectric material 103 may directly contact the first layer of dielectric material 102. The second layer of dielectric material 103 may have a different composition and / or different physical properties than the first layer of dielectric material 102. In various embodiments, the second layer of dielectric material 103 may have a density that is greater than a density of the first layer of dielectric material 102. For example, the second layer of dielectric material 103 may have a density that is at least 10%, such as at least 50%, including at least 100%, greater than a density of the first layer of dielectric material 102.In some embodiments, the second layer of dielectric material 103 may have a lower etch rate (ie, higher etch resistance) than the material of the first layer of dielectric material 102.

[0016] The second layer of dielectric material 103 may be composed of a suitable dielectric material, such as an oxide or nitride material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). In some embodiments, the second layer of dielectric material 103 may be composed of a buffer oxide material, a silicon nitride material, a high-temperature oxide (HTO) material, and the like. Other suitable dielectric materials are within the contemplated scope of the disclosure.In some embodiments, the dielectric composite film structure 101 may include one or more additional layers of dielectric material, where the one or more additional layers may be located between the first layer of dielectric material 102 and the top surface of the metal gates MG of the logic transistors LT1, LT2, between the first layer of dielectric material 102 and the second layer of dielectric material 103, and / or above the second layer of dielectric material 103.

[0017] Again in relation to Fig. 1, in some embodiments, an isolation structure element IF2, such as a trench isolation structure (STI) element, may be located between the memory cells SGMC1, SGMC2 of the memory region 212 and the logic transistors LT1, LT2 of the edge region 214 of the memory device 100. A peripheral edge of the isolation structure element IF2 may define a boundary 430 between the memory region 212 and the edge region 214 of the memory device 100. In various embodiments, a peripheral edge 431 of the dielectric compound film structure 101 may be within ±300 nm (e.g., ±200 nm, such as ±100 nm) of the boundary 430 between the memory region 212 and the edge region 214 of the memory device 100.By providing the peripheral edge 431 within ±300 nm of the boundary 430 between the memory region 212 and the edge region 214, the composite dielectric film structure 101 may not extend too far into the memory region 212 where it might interfere with subsequent processing steps used to form the memory cells SGMC1, SGMC2, while also ensuring that the dielectric film structure 101 extends sufficiently within the edge region 213 to protect the metal gates MG of the logic transistors LT. Therefore, in various embodiments, the composite dielectric film structure 101 may not extend beyond a top surface of the memory cells SGMC1, SGMC2 of the memory region 212. In some embodiments, a bottom surface of the composite dielectric film structure 101 may be substantially coplanar with a top surface of the memory cells SGMC1, SGMC2 of the memory region 212.

[0018] In various embodiments, an interlayer dielectric material (ILD) layer 412 may overlie the upper surfaces of the memory cells SGMC1, SGMC2 in the memory region 212 and overlie the upper surface of the composite dielectric film structure 101 in the edge region 214 of the memory device 100. A plurality of conductive vias 110 may extend through the interlayer dielectric material layer 412. In the memory region 212 of the memory device 100, conductive vias 110 may electrically contact drain regions DR of the memory cells SGMC1, SGMC2 and may electrically connect the memory cells SGMC1, SGMC2 to overlying metal structure element(s) 112 of the memory device 100.In the edge region 214 of the memory device 100, conductive vias 110 may extend through the dielectric composite film structure 101 and may electrically contact respective source and drain regions SD of the logic transistors LT1, LT2. The conductive vias 110 may electrically connect the logic transistors LT1, LT2 to overlying metal structure element(s) 112 of the memory device 100. In various embodiments, the dielectric composite film structure 101 may extend continuously between the conductive vias 110 within the edge region 214 of the memory device 100.

[0019] In some embodiments, a top surface of the semiconductor material substrate 210 on which the split-gate memory cells SGMC1, SGMC2 are located within the memory region 212 of the device 100 may be recessed relative to the top surface of the semiconductor material substrate 210 on which the logic transistors LT1, LT2 are located within the peripheral region 214 of the device 100.

[0020] In various embodiments, a composite dielectric film structure 101 in a peripheral region 214 of the memory device 100 may provide enhanced protection for logic transistors LT1, LT2 within the peripheral region. In particular, the composite dielectric film structure 101 may protect the integrity of the metal gates MG of the logic transistors LT1, LT2. In some cases, processing steps during the fabrication of a memory device 100 may generate metal deposits from the metal material(s) (e.g., aluminum) forming the metal gate (MG) structures of the logic transistors LT1, LT2. The presence of these metal deposits may create weak points, such as sidewall pinholes, in a dielectric material layer subsequently formed over the metal gate MG structures.During subsequent manufacturing steps, such as a wet etch step following silicidation of the select gates SG and erase gates EG of the memory cells, portions of the metal gate(s) MG may be inadvertently etched through the weak points in the overlying dielectric layer. This could negatively impact the performance of the memory device 100. In various embodiments, by providing a composite dielectric film structure 100 over the metal gates MG of the logic transistors LT1, LT2 in the edge region 214 of the memory device 100, the metal gates MG may be better protected from etch damage, which may improve performance and yield of memory devices 100. In addition to memory devices, such as an ESF3 memory device 100 as shown in FIG. Fig. 1, a composite dielectric film structure 101 as shown and described herein may be used in other types of integrated circuit (IC) devices, including devices having metal gate structures that may include a composite dielectric film structure 101 over the gate structure(s) to prevent metal gate etch damage and / or metal gate delamination.

[0021] Fig. 2 to 55 are sequential vertical cross-sectional views illustrating an intermediate structure during a method of manufacturing a memory device 100, such as a memory device as shown in Fig. 1, in accordance with some embodiments. It is understood that additional steps may be implemented before, during, or after the method, and some of the described steps may be replaced or omitted for other embodiments of the method.

[0022] Fig. 2 is a vertical cross-sectional view of the exemplary intermediate structure comprising a substrate 210, a first dielectric layer 220 and a second dielectric layer 230, and a patterned mask PR according to various aspects of the present disclosure. With respect to Fig. 2, the substrate is shown in vertical cross-section along the horizontal direction HD2. Therefore, the Fig. 2 shown cross-sectional view relative to the orientation of Fig. 1, which is a vertical cross-sectional view of the memory device 100 along the horizontal direction HD1, rotated by 90°. In various embodiments, the substrate 210 may be a semiconductor material substrate such as a bulk silicon substrate, a germanium substrate, an interconnect substrate, or other suitable substrate. In some embodiments, the substrate 210 may include an epitaxial layer overlying a bulk semiconductor, a silicon germanium layer overlying bulk silicon, a silicon layer overlying bulk silicon germanium, or a semiconductor-on-insulator (SOI) structure. The substrate 210 may include a storage region 212 and an edge region 214. The edge region 214 may be positioned to surround the storage region 212.

[0023] Again in relation to Fig. 2, a first dielectric layer 220 may be formed over the substrate 210. The first dielectric layer 220 may include, for example, a dielectric material such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), high-k materials, other non-conductive materials, or combinations thereof. Other suitable dielectric materials are within the contemplated scope of the disclosure.

[0024] A second dielectric material layer 230 may be formed over the first dielectric layer 220. The dielectric material layer 230 may include a suitable dielectric material, such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), high-k materials, other non-conductive materials, or combinations thereof. In one non-limiting embodiment, the first dielectric material layer 220 may include silicon oxide, and the second dielectric material layer 230 may include silicon nitride. In various embodiments, a thickness of the second dielectric material layer 230 may be greater than a thickness of the first layer 220.

[0025] The first dielectric material layer 220 and the second dielectric material layer 230 may be deposited using any suitable deposition process. Herein, "suitable deposition processes" may include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a high-density plasma CVD (HDPCVD) process, a low-pressure CVD process, a metal-organic CVD (MOCVD) process, a plasma-enhanced CVD (PECVD) process, a sputtering process, laser ablation, or the like.

[0026] Again in relation to Fig. 2, a patterned mask, such as a photoresist mask PR, may be formed over the second dielectric layer 230 in the edge region 214 of the intermediate structure. The patterned mask may be formed by depositing a layer of photoresist material over the second dielectric layer 230 and lithographically patterning the photoresist material to form a patterned mask PR covering the second dielectric layer 230 in the edge region 214 of the intermediate structure. The second dielectric layer 230 may be exposed through the patterned mask PR in the storage region 212 of the intermediate structure.

[0027] Fig. 3 is a vertical cross-sectional view of the exemplary intermediate structure following an etching process that removes the second dielectric layer 230, the first dielectric layer 220, and portions of the substrate 210 from the storage region 212 of the intermediate structure. With reference to Fig. 3. Following the etching process, the upper surface of the substrate 210 in the storage region 212 may be recessed relative to the upper surface of the substrate 210 in the edge region 214. Following the etching process, the patterned mask may be removed using a suitable process, such as by ashing or by dissolution with a solvent.

[0028] Fig. 4 is a vertical cross-sectional view of the exemplary intermediate structure showing a dielectric material layer 220A deposited over the recessed surface of the substrate 210 in the storage region 212. In embodiments, the dielectric material layer 220A deposited over the recessed surface of the substrate 210 may be the same dielectric material as the material of the first dielectric layer 220 (e.g., silicon oxide). The dielectric material layer 220A may have a vertical height greater than the distance by which the substrate 210 is recessed in the storage region 212. Therefore, the side surface of the dielectric material layer 220A may contact the exposed side surface of the dielectric layer 220 such that layers 220 and 220A may be continuous. The dielectric material layer 220A may be deposited using a suitable deposition method, as previously described.

[0029] Fig. 5 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process that removes a portion of the second dielectric layer 230 from the edge region 214 and a portion of the dielectric material layer 220A from the storage region 212. With reference to Fig. 5, in various embodiments, the exemplary intermediate structure may be etched using an etching process having a higher etch rate for the material of the dielectric material layer 220A than for the material of the second dielectric material layer 230. Therefore, as in Fig. 5, a greater thickness of the dielectric material layer 220A may be removed from the storage region 212 than the thickness of the second dielectric material layer 230 removed from the edge region 214. In some embodiments, following the etching process, the thickness of the remaining dielectric material layer 220A in the storage region 212 may be approximately the same as the thickness of the first dielectric material layer 220 in the edge region 214. As shown in Fig. 5, the dielectric material layer 220A in the storage region 212 may be continuous with the first dielectric material layer 220 in the edge region 214, and layers 220A and 220 may collectively be referred to as a tunnel layer 220.

[0030] Fig. 6 is a vertical cross-sectional view of the exemplary intermediate structure showing a second dielectric layer 230 over the tunnel layer 220 in the memory region 212 and in the edge region 214 and a patterned mask PR over the second dielectric layer 230 in the memory region 212 and a portion of the edge region 214. With reference to Fig. 6, additional dielectric material may be deposited over the second dielectric layer 230 in the edge region 214 and over the tunnel layer 220 in the storage region. The additional dielectric material may be the same material as the material of the second dielectric layer 230. Therefore, the additional dielectric material may increase the thickness of the second dielectric layer 230 in the edge region 214 and may extend the second dielectric layer 230 into the storage region 212. In various embodiments, the additional dielectric material may include silicon nitride and may be deposited using a suitable deposition method, as previously described.

[0031] Again in relation to Fig. 6, a patterned mask, such as a photoresist mask PR, may be formed over the second dielectric layer 230 in the storage region 212 and in a portion of the peripheral region 214. The patterned mask may be formed by depositing a layer of photoresist material over the second dielectric layer 230 and lithographically patterning the photoresist material to form a patterned mask PR covering the second dielectric layer 230 in the storage region 212 and a portion of the peripheral region 214. The second dielectric layer 230 may be exposed by the patterned mask PR in the remainder of the peripheral region.

[0032] Fig. 7 is a vertical cross-sectional view of the exemplary intermediate structure following an etching process that removes a portion of the second dielectric layer 230 in the edge region 214 of the intermediate structure. With reference to Fig. 7, following the etching process, a thickness of the second dielectric layer 230 in the edge region 214 may be reduced. In some embodiments, following the etching process, the thickness of the second dielectric layer 230 in the edge region 214 may be less than the thickness of the second dielectric layer 230 in the storage region 212. Following the etching process, the patterned mask may be removed using a suitable process, such as by ashing or by dissolution with a solvent.

[0033] Fig. 8 is a vertical cross-sectional view of the exemplary intermediate structure showing a plurality of isolation structure elements IF1, IF2 extending through the first dielectric layer 220 and second dielectric layer 214 and into the substrate 210 in the storage region 212 and the edge region 214 of the exemplary structure. With reference to Fig. 8, isolation structure elements IF1, IF2 can be formed by applying and structuring a photoresist layer (not shown in Fig. 8) over the top surface of the second dielectric layer 230 and performing an anisotropic etch process to remove portions of the second dielectric layer 230, the first dielectric layer 220, and the substrate 210, and forming a plurality of trenches through the first and second dielectric layers 220, 230 and in an upper portion of the substrate 210. The photoresist layer may subsequently be removed, for example, by ashing or by dissolution with a solvent. A dielectric material may be deposited in the trenches, and a planarization process, such as a chemical mechanical planarization (CMP) process, may be performed to remove excess portions of the dielectric material over the top surface of the second dielectric layer 230 and provide an intermediate structure having a planar top surface, as shown in Fig. 8. Following the planarization process, the remaining portions of the dielectric material filling the trenches may form isolation feature elements IF1 and IF2, which may be trench isolation structures (STI structures). Each of the isolation feature elements IF1, IF2 may be embedded within the second dielectric layer 230, the first dielectric layer / tunnel layer 220, and the substrate 210. In various embodiments, the dielectric material of the isolation feature elements IF1, IF2 may include an oxide material and / or other suitable dielectric materials.

[0034] A first plurality of isolation structure elements IF1 may be located in the memory region 212 and in the edge region 214. Each of the first plurality of isolation structure elements IF1 may extend in a first horizontal direction HD1 that is perpendicular to the second horizontal direction HD2. Therefore, the first plurality of isolation structure elements IF1 may separate the memory region 212 and the edge region 214 into a plurality of active regions 232 and 234, respectively, that extend along the first horizontal direction HD1. In some embodiments, the isolation structure elements IF1 within the memory region 212 may have a bottom surface that is at a depth below a depth of the bottom surfaces of the isolation structure elements IF1 within the edge region 214.

[0035] Again in relation to Fig. 8, a second isolation structure element IF2 may be located between the memory region 212 and the edge region 214 of the exemplary structure. As previously described with respect to Fig. 1, the edge region of the second isolation structure element IF2 adjacent to the memory region 212 may define the boundary 430 between the memory region 212 and the edge region 214. The second isolation structure element IF2 may extend in the first horizontal direction HD1, which is perpendicular to the second horizontal direction HD2. In some embodiments, the second isolation structure element IF2 may extend continuously around the entire memory region 212. As shown in Fig. 8, the top surface of the substrate 210 may contact a first side of the second isolation feature IF2 in the edge region 214, and the top surface of the substrate 210 may contact a second side of the second isolation feature IF2 in the storage region 212, where the top surface of the substrate 210 in the storage region 212 may be vertically recessed relative to the top surface of the substrate 210 in the edge region 214. The second isolation feature IF2 may have a lateral thickness (i.e., along HD2) that is greater than the lateral thicknesses of the first plurality of isolation features IF1.

[0036] Fig. 9 is a vertical cross-sectional view of the exemplary intermediate structure showing a third dielectric material layer 240 over the upper surfaces of the second dielectric layer 230 and the isolation structure elements IF1, IF2, a fourth dielectric material layer 241 over a top surface of the third dielectric material layer 240, and a patterned mask PR over a top surface of the fourth dielectric material layer 241. With reference to Fig. 9, the third dielectric material layer 240 may be composed of the same dielectric material as the second dielectric material layer 230. In various embodiments, the third dielectric material layer 230 may be composed of silicon nitride. The fourth dielectric material layer 241 may be formed over the top surface of the third dielectric material layer 240. The fourth dielectric material layer 241 may be composed of a different dielectric material than the material of the third dielectric material layer 240. In some embodiments, the fourth dielectric material layer 241 may be composed of an oxide material (e.g., silicon oxide), such as resist protection oxide (RPO) material.The third dielectric material layer 240 and fourth dielectric material layer 241 may be deposited using a suitable deposition method as previously described.

[0037] Again in relation to Fig. 9, a patterned mask, such as a photoresist mask PR, may be formed over the fourth dielectric layer 241 in the edge region 214 of the intermediate structure. The patterned mask may be formed by depositing a layer of photoresist material over the fourth dielectric layer 241 and lithographically patterning the photoresist to form a patterned mask PR covering the fourth dielectric layer 241 in the edge region 214 of the intermediate structure. As in Fig. 9, the edge of the mask PR may be located above the upper surface of the second isolation structure element IF2.

[0038] Fig. 10 is a vertical cross-sectional view of the exemplary intermediate structure following an etching process that removes portions of the fourth dielectric layer 241, the third dielectric layer 240, and the second dielectric layer 230 from the storage region 212 and exposes isolation features IF1, IF2 and the top surface of the tunnel layer 220 in the storage region 212 of the exemplary structure. With respect to Fig. 10, the exemplary structure may be etched through the patterned mask PR to remove the portions of the fourth dielectric layer 241, the third dielectric layer 240, and the second dielectric layer 230 exposed by the mask. The etching process may stop at the tunnel layer 220. The etching process may be a selective etching process that preferentially etches the materials of the fourth dielectric layer 241, the third dielectric layer 240, and the second dielectric layer 230 relative to the materials of the isolation features IF1, IF2 and the tunnel layer 220.As a non-limiting example, the etching process may include a first etching step that removes the fourth dielectric layer 241, which may be an oxide material, followed by a second etching step that preferentially etches the material of the second and third dielectric material layers 230, 240, which may be nitride materials, relative to the material of the tunnel layer 220 and the isolation features IF1, IF2, which may be composed of oxide materials. Following the etching process, the first isolation features IF1 may protrude above the upper surface of the tunnel layer 220, as shown in FIG. Fig. 10. In addition, the etching process may remove portions of the layers 240 and 241 exposed by the patterned mask PR above the second isolation structure element IF2. Therefore, portions of the top surface and lateral side surface of the second isolation structure element IF2 may be exposed following the etching process, as shown in Fig. 10. Following the etching process, the patterned mask PR may be removed using a suitable process, such as by ashing or by dissolution using a solvent.

[0039] Fig. 11 is a vertical cross-sectional view of the exemplary intermediate structure showing a continuous floating gate layer 243L over the tunnel layer 220 and the first isolation structure elements IF1 in the memory region 212 and over the fourth dielectric layer 241 and the second isolation structure element IF2 in the edge region 214. With respect to Fig. 11, in some embodiments, the continuous floating gate layer 243L may be composed of a semiconductor material such as polysilicon. In other embodiments, the continuous floating gate layer 243L may include metal, metal alloys, single-crystalline silicon, or combinations thereof. Other suitable materials for the continuous floating gate layer 243L are within the contemplated scope of the disclosure. The continuous floating gate layer 243L may be deposited using a suitable deposition method, as previously described.

[0040] Fig. 12 is a vertical cross-sectional view of the exemplary intermediate structure following a planarization process to remove portions of the floating gate layer 243L and the fourth dielectric material layer 241 above a top surface of the third dielectric material layer 240. With respect to Fig. 12, the exemplary structure may be subjected to a planarization process, such as a chemical mechanical planarization (CMP) process. The planarization process may remove portions of the floating gate layer 243L. The planarization may also remove the remaining portion of the fourth dielectric material layer 241 and expose the top surface of the third dielectric material layer 240 in the edge region 214. Following the planarization process, the exemplary intermediate structure may have a planar top surface formed by the top surface of the continuous floating gate layer 243L in the memory region 212 and the top surface of the third dielectric material layer 240 in the edge region 214 of the exemplary structure.

[0041] Fig. 13 is a vertical cross-sectional view of the exemplary intermediate structure following an etching process that recesses the floating gate layer 243 and the first isolation features IF1 in the memory region 212. With reference to Fig. 13, the exemplary structure may be subjected to an etch process that removes the floating gate layer 243 above the upper surfaces of the isolation features IF1, IF2 and deepens the height of the floating gate layer 243 within the memory region 212. The etch process may also remove portions of the isolation features IF1 and IF2. In embodiments, the first isolation features IF1 may be etched at a higher etch rate than the floating gate layer 243 such that, following the etch process, the upper surface of the floating gate layer 243 may be above the upper surfaces of the first isolation features IF1 in the memory region 212.The etching process may also remove a portion of the second isolation structure element IF2 such that a top surface of the second isolation structure element IF2 adjacent to the memory region 212 may be substantially coplanar with the top surfaces of the first isolation structure elements IF1 and may be below the top surface of the floating gate layer 243.

[0042] Again in relation to Fig. 13, following the etching process, the floating gate layer 243 may comprise a plurality of discrete floating gate layers 243 separated by first isolation structure elements IF1 within the memory region 212. Each of the discrete floating gate layers 243 may be located within an active region 232 of the memory region 212 and may extend continuously along the first horizontal direction HD1 (i.e., into and out of the side in Fig. 13). In each of the active regions 232, a tunnel layer 220 may be located between the floating gate layer 243 and the top surface of the substrate 210.

[0043] Fig. 14 is a vertical cross-sectional view of the exemplary intermediate structure of Fig. 13, which is shown along the horizontal direction HD1. Therefore, the cross-sectional view of the Fig. 14 shown intermediate structure by 90° relative to the one shown in Fig. 2-13 shown orientation. With respect to Fig. 14, an active region 232 of the memory region 212 is shown having a tunnel layer 220 above the top surface of the substrate 210 and a floating gate layer 243 above the tunnel layer 220. Fig. 14 also shows an active region 234 of the edge region 214 of the intermediate structure. Active regions 232 and 234 may be separated by a second isolation feature, IF2. In some embodiments, the active region 243 of the edge region may include one or more first isolation feature elements, IF1. The one or more first isolation feature elements IF1 may be located between portions of the active region 243 on which logic transistors may subsequently be formed.

[0044] Fig. 15 is a vertical cross-sectional view of the exemplary intermediate structure showing a barrier layer 245, a control gate layer 247, a hard mask HM, and a patterned mask PR formed over the memory region 212 and the edge region 214 of the exemplary structure. With reference to Fig. 15, the barrier layer 245 may be conformally deposited over the third dielectric layer 240 in the edge region 214 and over the floating gate layer 243 in the memory region 212. The barrier layer 245 may also be deposited over the side surface and top surface of the second isolation structure element IF2.

[0045] In some embodiments, the barrier layer 245 and the tunnel layer 220 may be formed from the same material. In other embodiments, the barrier layer 245 and the tunnel layer 220 may be formed from different materials. That is, the barrier layer 245 may, for example, include a dielectric material such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), high-k materials, other non-conductive materials, or combinations thereof. In some embodiments, the barrier layer 245 may be composed of a multi-layer structure that may include different dielectric materials. Other suitable dielectric materials are within the contemplated scope of the disclosure.

[0046] Again in relation to Fig. 15, the control gate layer 247 may be conformally deposited over the barrier layer 245. In some embodiments, the control gate layer 247 may be composed of a semiconductor material such as polysilicon. In other embodiments, the control gate layer 247 may include metal, metal alloys, single-crystalline silicon, or combinations thereof. Other suitable materials for the control gate layer 247 are within the contemplated scope of the disclosure.

[0047] Again in relation to Fig. 15, the hard mask HM may be conformally deposited over the control gate layer 247. In various embodiments, the hard mask HM may have a multi-layer structure comprising different dielectric material layers. In one non-limiting example, the hard mask HM may have a nitride-oxide-nitride ("NON" structure) structure and may include a layer 249 of nitride material (e.g., silicon nitride) deposited over the control gate layer 247, a layer 250 of oxide material (e.g., silicon oxide) deposited over nitride layer 249, and another layer 251 of nitride material (e.g., silicon nitride) deposited over the oxide layer 250.

[0048] Again in relation to Fig. 15, a patterned mask, such as a photoresist mask PR, may be formed over the hard mask HM in the memory region 212 and in the edge region 214 of the intermediate structure. The patterned mask PR may be formed by depositing a layer of photoresist material over the fourth dielectric layer 241 and lithographically patterning the photoresist material to form a patterned mask PR. In embodiments, the patterned mask PR may cover the entire edge region 214 of the intermediate structure. The patterned mask PR may cover portions of the memory region 212 that may correspond to the locations of memory cells that may subsequently be formed.

[0049] Fig. 16 is a vertical cross-sectional view of the exemplary intermediate structure showing a plurality of memory stacks MS1, MS2, MS3, MS4 above the floating gate layer 243 in the memory region 212 of the intermediate structure. With reference to Fig. 16, an anisotropic etch process may be performed to remove portions of the hard mask HM, the control gate layer 247, and the barrier layer 245 exposed by the patterned mask PR. The etch process may stop at the floating gate layer 243. Following the etch process, multiple memory stacks MS1-MS4 may be disposed above the floating gate layer 243 in the memory region 212. Each memory stack MS1-MS4 may include a barrier layer 245 above the floating gate layer 243, a control gate CG above the barrier layer 245, and a hard mask HM above the control gate CG. Following the etch process, the patterned mask PR may be removed using a suitable process, such as by ashing or by dissolution using a solvent.

[0050] Fig. 17 is a vertical cross-sectional view of the exemplary intermediate structure showing sidewall structures 270 formed over the side surfaces of the memory stacks MS1-MS4. With reference to Fig. 17, the sidewall structures 270 may include one or more dielectric materials over the exposed side surfaces of the hard mask HM, the control gate CG, and the barrier layer 245 in each of the memory stacks MS1-MS4. In some embodiments, the sidewall structures 270 may include a multi-layer structure including different dielectric material layers. In one non-limiting example, the sidewall structures 270 may include an oxide-nitride-oxide ("ONO") structure including a first oxide layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer.In embodiments, the sidewall structures 270 may be formed by conformally depositing layer(s) of dielectric material, such as ONO layers, over the intermediate structure, including over the top surface and side surfaces of the memory stacks MS1-MS4, over the top surface of the floating gate layer 243 in the memory region 212, and over the exposed side surfaces of layers 240, 245, 247, 249, 250, and 251, and over the top surface of the hard mask HM in the edge region 214. In some embodiments, an anisotropic etching process, such as a reactive ion etching process, may be used to remove horizontally extending portions of the dielectric material layer(s) while leaving sidewall structures 270 over vertically extending surfaces.In some embodiments, the sidewall structures 270 may include ONO layers, and the anisotropic process may remove the second oxide layer and the nitride layer of the ONO layers over horizontally extending surfaces and may leave the first oxide layer 270a of the ONO layers over horizontally extending surfaces of the intermediate structure.

[0051] Fig. 18 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process to remove portions of the floating gate layer 243 and the tunnel layer 220 from the storage region 212 of the intermediate structure. With reference to Fig. 18, an anisotropic etch process may be used to remove the floating gate layer 243 and the tunnel layer 220 between the respective memory stacks MS1-MS2. The etch process may also remove the first oxide layer 270a over horizontally extending surfaces of the intermediate structure. Portions of the floating gate layer 243 and the tunnel layer 220 underlying the memory stacks MS1-MS4 may be protected from being etched by the memory stacks MS1-MS4 in a self-aligned etch process. Following the etch process, each of the memory stacks MS1-MS4 in the memory region 212 may include a tunnel layer 220 over the substrate 210, a floating gate FG over the tunnel layer 220, a barrier layer 245 over the floating gate FG, a control gate CG over the barrier layer 245, and a hard mask HM over the control gate CG.Sidewall structures 270 may extend over the side surfaces of the hard mask HM, the control gate CG and the barrier layer 245 and may contact a top surface of the floating gate FG.

[0052] Fig. 19 is a vertical cross-sectional view of the exemplary intermediate structure showing intergate dielectric layers 280 formed over the side surfaces of the memory stacks MS1-MS4. With reference to Fig. 19, the intergate dielectric layers 280 may comprise one or more dielectric materials over the sidewall structures 270 and over the exposed side surfaces of the floating gate FG and tunnel layer 220 in each of the memory stacks MS1-MS4. In some embodiments, the intergate dielectric layers 280 may be composed of an oxide material, such as a high-temperature oxide (HTO). Other suitable dielectric materials, including oxides, nitrides, multilayer structures (e.g., ONO structures), and combinations thereof, are within the contemplated scope of the disclosure.

[0053] In various embodiments, the intergate dielectric layers 280 may be formed in a manner similar to that previously described with respect to the sidewall structures 270. In particular, a continuous intergate dielectric layer 280 may be conformally deposited over the intergate structure, and an anisotropic etch process may be used to remove horizontally extending portions of the intergate dielectric layer 280. Following the etch process, the intergate dielectric layer 280 may remain over the vertically extending surfaces comprising the side surfaces of the memory stacks MS1-MS4.

[0054] Fig. 20 is a vertical cross-sectional view of the exemplary intermediate structure showing common source regions CS formed between adjacent pairs of memory stacks using a masked implantation process. Fig. 20, a patterned mask, such as a photoresist mask PR, may be formed over the memory region 212 and the edge region 214 of the intermediate structure. The patterned mask may be formed by depositing a layer of photoresist material over the intermediate structure and lithographically patterning the photoresist material to form a patterned mask PR. The patterned mask may include openings exposing portions of the substrate 210 between pairs of adjacent memory stacks MS1-MS4 within the memory region 212. An ion implantation process may be performed through the patterned mask PR to form common source regions CS in the substrate 210 between the pairs of adjacent memory stacks MS1-MS4.

[0055] Fig. 21 is a vertical cross-sectional view of the exemplary intermediate structure showing the intergate dielectric layers 280 removed from the side surfaces of the memory stacks MS1-MS4 adjacent to the common source regions CS. With respect to Fig. 21, an etching process may be used to remove the intergate dielectric layers 280 adjacent to the common source regions CS along the side surfaces of the memory stacks MS1-MS4. The intergate dielectric layers 280 that do not adjoin the common source regions CS may remain on the side surfaces of the memory stacks MS1-MS4.

[0056] Fig. 22 is a vertical cross-sectional view of the exemplary intermediate structure showing common dielectric source layers 281 over the common source regions CS and over the side surfaces of the memory stacks MS1-MS4. With respect to Fig. 23, the common source dielectric layers 281 may be composed of a suitable dielectric material, such as an oxide material (e.g., silicon oxide). The common source dielectric layers 281 may be formed over the common source regions CS using, for example, surface oxidation, CVD, other suitable deposition techniques, or the like. In some embodiments, forming the common source dielectric layer 281 may include depositing a dielectric layer material and etching portions of the dielectric layer that are not located between the memory stacks MS1, MS2 or MS3, MS4, such that the remaining portion of the dielectric layer forms the common source dielectric layer 281 over the common source region CS and over the side surfaces of the memory stacks MS1-MS4.

[0057] Fig. 23 is a vertical cross-sectional view of the exemplary intermediate structure, showing a dielectric select gate layer 282 over the substrate 210 in the storage region 212, a conductive material layer 283 over the storage region 212 and the edge region 214 of the intermediate structure, and a bottom layer (BL) coating 285 over the conductive material layer 283. The BL coating 285 may be composed of a suitable material, such as an organic photoresist, that can provide a substantially planar top surface over the exemplary intermediate structure. With respect to Fig. 23, a select gate dielectric layer 282 may be formed over the surface of the substrate 210 between each pair of memory stacks MS1-MS4 sharing a common source region CS. The select gate dielectric layer 282 may be composed of a suitable dielectric material, such as an oxide material (e.g., silicon oxide). The select gate dielectric layer 282 may be formed between the pairs of memory stacks MS1-MS4 using, for example, surface oxidation, CVD, other suitable deposition techniques, or the like.In some embodiments, forming the select gate dielectric layer 282 may include depositing a dielectric layer material and etching portions of the dielectric layer that are not between pairs of memory stacks MS1-MS4 that share a common source region CS, such that the remaining portion of the dielectric layer forms the select gate dielectric layer 282 between pairs of memory stacks MS1-MS4 that share a common source region CS.

[0058] Again in relation to Fig. 23, a conductive material layer 283 may be formed over the storage region 212 and the edge region 214 of the intermediate structure. The conductive material layer 283 may be formed from a suitable electrically conductive material, such as a doped polysilicon material. In other embodiments, the conductive material layer 283 may include metal, metal alloys, doped amorphous silicon, or combinations thereof. Other suitable materials for the conductive material layer 283 are within the contemplated scope of the disclosure. The conductive material layer 283 may be deposited using a suitable deposition process, as previously described. In various embodiments, a BL coating 285 may be deposited over the top surface of the conductive material layer 283.

[0059] Fig. 24 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process that removes the BL coating 285 from the intermediate structure and the conductive material layer 283 from above the edge region 214 and recesses the conductive material layer 283 within the storage region 212 of the intermediate structure. With respect to Fig. 24, the exemplary structure may be subjected to an etch process that removes the entire BL coating 285. The etch process may also remove the conductive material layer 283 from the edge region 214 and may remove portions of the conductive material layer 283 from the memory region 212 such that the memory stacks MS1-MS4 protrude above the top surface of the conductive material layer 283. In various embodiments, the height of the conductive material layer 283 may be recessed such that the top surface of the conductive material layer 283 is approximately coplanar with the top surface of the control gates CG within the memory stacks MS1-MS4. The conductive material layer 283 may form select gates SG and erase gates EG of the memory cells formed in the memory region 212 of the exemplary structure.

[0060] Fig. 25 is a vertical cross-sectional view of the exemplary intermediate structure showing a hard mask layer 287 over the storage region 212 and the edge region 214 of the intermediate structure. With reference to Fig. 25, the hard mask layer 287 may be composed of a dielectric material, such as a nitride material (e.g., silicon nitride). Other suitable dielectric materials are within the contemplated scope of the disclosure. The hard mask layer 287 may protect and help define the select gates SG and erase gates EG of the memory cells subsequently formed in the memory region 212. The hard mask layer 287 may be conformally deposited using a suitable deposition method, as previously described.

[0061] Fig. 26 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process that removes the hard mask layer 287 from the edge region 214 and above upper surfaces of the memory stacks MS1-MS4 in the memory region 212 and removes portions of the hard mask layer 287 and the conductive material layer 283 between adjacent pairs of memory stacks MS1-MS4. With respect to Fig. 26, the example structure may be subjected to an etch process that may remove the hard mask layer 287 from the edge region 214 of the example structure and may also remove portions of the hard mask layer 287 and the conductive material layer 283 from the memory region 212 of the example structure. In the edge region 214, the etch process may remove the hard mask layer 287 and may remove a portion of the dielectric material layer 251. In the memory region 212, the etch process may remove the hard mask layer 287 above the upper surfaces of the memory stacks MS1-MS4 and may also remove at least a portion of the topmost layer (i.e., dielectric material layer 251) of the hard masks HM of each of the memory stacks MS1-MS4.Following the etching process, the remaining portions of the hard mask layer 287 may be adjacent to the side surfaces of each of the memory stacks MS1-MS4 and overlying the remaining portions of the conductive material layer 283. Between adjacent pairs of memory stacks MS1-MS4 sharing a common source region CS, the hard mask layer 287 and the conductive material layer 283 may be completely removed to form gaps between the pairs of memory stacks MS1-MS4. In embodiments, a top surface of the substrate 210 may be exposed in each of the gaps.

[0062] Fig. 27 is a vertical cross-sectional view of the exemplary intermediate structure following an additional etch process that removes the dielectric material layer 251 and a portion of the dielectric material layer 250 from the edge region 214 of the exemplary structure. With reference to Fig. 27, the exemplary structure may be subjected to an additional etching process that may remove a remaining portion of the dielectric material layer 251 and further remove a portion of the dielectric material layer 250 from the edge region 214. A mask (not shown) Fig. 27) may cover the storage region 212 to protect the storage region 212 from being etched. In some embodiments, the mask may extend over a portion of the second isolation feature IF2 such that, following the etching process, a small portion of the dielectric material layer 251 may remain above the second isolation feature IF2.

[0063] Fig. 28 is a vertical cross-sectional view of the exemplary intermediate structure showing a BL coating 288 over the exemplary intermediate structure.

[0064] Fig. 29 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process that removes the BL liner 288 and additional portions of the memory stacks MS1-MS4 and the hard mask layer 287 from the memory region 212. With respect to Fig. 29, the etching process may remove the dielectric material layer 250 of the hard masks HM in each of the memory stacks MS1-MS4. The etching process may also remove portions of the hard mask layer 287 such that, following the etching process, the dielectric material layer 249 of the hard masks HM defines the top surface of each of the memory stacks MS1-MS4 and the top surface of the hard mask layer 287 is substantially coplanar with the top surface of each of the memory stacks MS1-MS4.

[0065] Fig. 30 is a vertical cross-sectional view of the exemplary intermediate structure showing a lining layer 291 over exposed surfaces of the exemplary intermediate structure. With reference to Fig. 30, the liner layer 291 may include a dielectric material, such as an oxide material, conformally deposited over the exposed surfaces of the exemplary structure in the storage region 212 and the edge region 214. The liner layer 291 may be formed using a suitable deposition process, as previously described.

[0066] Fig. 31 is a vertical cross-sectional view of the exemplary intermediate structure showing a finishing layer 293 formed over the liner layer 291 and a BARC layer 295 formed over the finishing layer 293. With reference to Fig. 31, in various embodiments, a termination layer 293 may protect the structures in the memory region 212 during subsequent processing steps to form logic transistors in the edge region 214. In some embodiments, the termination layer 293 may be composed of a semiconductor material, such as amorphous silicon or polysilicon. Other suitable materials for the termination layer 293 are within the contemplated scope of the disclosure. The termination layer 293 may be deposited using a suitable deposition process, as previously described.

[0067] Fig. 32 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process to remove the BARC layer 295 and reduce the thickness of the termination layer 293 over the exemplary intermediate structure. With respect to Fig. 31, following the etching process, the terminating layer 293 may have a substantially planar upper surface. A patterned mask, PR, may be formed over the upper surface of the terminating layer 293. The patterned mask may be formed by depositing a layer of photoresist material over the terminating layer 293 and lithographically patterning the photoresist material to form a patterned mask PR. As shown in Fig. As shown in Figure 32, the patterned mask PR may completely cover the storage region 212 and may partially extend into the edge region 214. In embodiments, the peripheral edge of the patterned mask PR may be above the second isolation feature IF2. The remaining portion of the edge region 214 may be exposed by the patterned mask PR.

[0068] Fig. 33 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process to remove the termination layer 293, the liner layer 291, the dielectric material layer 250, the dielectric material layer 249, and the control gate layer 247 from the edge region 214 of the exemplary intermediate structure. With respect to Fig. 33, an anisotropic etch process may be performed through the patterned mask PR to remove portions of the cap layer 293, the liner layer 291, the dielectric material layer 250, the dielectric material layer 249, and the control gate layer 247 from the edge region 214. In some embodiments, the etch process may stop at the barrier layer 245. The etch process may expose side surfaces of the cap layer 293, the liner layer 291, the dielectric material layer 249, and the control gate layer 247 above the second isolation feature IF2. Following the etch process, the patterned mask PR may be removed using a suitable process, such as by ashing or by dissolution using a solvent.

[0069] Fig. 34 is a vertical cross-sectional view of the exemplary intermediate structure following an additional etch process to remove the barrier layer 245 and the third dielectric layer 240 from the edge region 214 of the exemplary intermediate structure. With reference to Fig. 34, an etching process, which may be a wet etching process (e.g., a hydrofluoric acid etch), may be performed to remove the barrier layer 245 and the third dielectric layer 240 from the edge region 214 and to expose the upper surfaces of the second dielectric material layer 230 and the second isolation feature IF2 in the edge region 214. The etching process may also recess the upper surface of the first isolation feature IF1 with respect to the upper surface of the second dielectric material layer 230. The etching process may also recess portions of the liner layer 291 and the dielectric material layer 250 that overlie the second isolation feature IF2. During the etching process, the termination layer 293 may protect the storage region 212 from being etched.

[0070] Fig. 35 is a vertical cross-sectional view of the exemplary intermediate structure showing additional termination material over the storage region 212 and the edge region 214. With respect to Fig. 35, in embodiments, the additional termination material may be composed of the same material as the existing termination layer 293, or may be composed of a different material than the material of the existing termination layer 293. In some embodiments, the additional termination material may be a semiconductor material, such as amorphous silicon or polysilicon. Other suitable materials are within the contemplated scope of the disclosure. The additional termination material may be deposited using a suitable deposition process, as previously described. The additional termination material may increase the thickness of the termination layer 293 in the storage region 212 and may extend the termination layer 293 to cover the edge region 214 of the example intermediate structure.

[0071] Fig. 36 is a vertical cross-sectional view of the exemplary intermediate structure following an etching process to remove the termination layer 293 from the edge region 214 of the exemplary intermediate structure. With respect to Fig. 36, an etch process may be performed to remove portions of the termination layer 293 and expose the upper surfaces of the second dielectric layer 230 and the isolation features IF1, IF2 in the edge region 214. The etch process may also reduce a thickness of the termination layer 293 in the memory region 212. Following the etch process, the termination layer 293 may have a tapered sidewall above the second isolation feature IF2.

[0072] Fig. 37 is a vertical cross-sectional view of the exemplary intermediate structure following an additional etch process to remove the second dielectric material layer 230 from the edge region 214. With respect to Fig. 37, an etching process, which may be a wet etching process (e.g., a hydrofluoric acid etch), may be performed to remove the second dielectric material layer 230 from the edge region 214 and expose the top surface of the first dielectric material layer / tunnel layer 220. Following the etching process, the first and second isolation features IF1, IF2 may protrude above the top surface of the first dielectric material layer / tunnel layer 220.

[0073] Fig. 38 is a vertical cross-sectional view of the exemplary intermediate structure showing a masked ion implantation process performed in a first portion 310 of the edge region 214. Fig. 39 is a vertical cross-sectional view of the exemplary intermediate structure showing a masked ion implantation process performed in a second region 320 of the edge region 214. With respect to Fig. 38 and Fig. 39, an ion implantation process may be performed through a patterned mask PR in portions 310, 320 of the edge region 214, in which logic transistors may subsequently be formed. In some embodiments, different types of logic transistors may be formed in different portions of the edge region 214. For example, in one non-limiting embodiment, a first logic transistor may be formed in the first portion 310 of the edge region 214, and a second logic transistor, which may be a high-voltage logic transistor, may be formed in the second portion 320 of the edge region. Following the implantation process(es), the patterned mask(s) PR may be removed by a suitable process, such as by ashing or by dissolution with a solvent.

[0074] Fig. 40 is a vertical cross-sectional view of the exemplary intermediate structure showing a layer of gate dielectric material 330 over the exemplary structure, a sacrificial gate material layer 340 over the layer of gate dielectric material 330, and a hard mask layer 350 over the sacrificial gate material layer 340. With respect to Fig. 40, in some embodiments, the first dielectric material layer / tunnel layer 220 may be removed from the edge region 214 (e.g., by etching), either before or after the steps described in Fig. 38 and Fig. 39. In some embodiments, a planarization process, such as CMP and / or etching, may be performed such that the upper surfaces of the isolation features IF1, IF2 may be coplanar with the upper surface of the substrate 210 in the edge region 214. Then, a layer of gate dielectric material 330 may be deposited over the exemplary intermediate structure, including over the upper surface of the termination layer 293 in the memory region 212, over the tapered sidewall of the termination layer 293, and over the upper surfaces of the isolation features IF1, IF2 and the substrate 210 in the edge region 214.The layer of gate dielectric material 330 may include a suitable dielectric material, such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-silica (HfO2-Al2O3), combinations thereof, and the like. Other suitable dielectric materials are within the contemplated scope of the disclosure. The layer of gate dielectric material 330 may be deposited using a suitable deposition process, as previously described.

[0075] In some embodiments, a thickness of the layer of gate dielectric material 330 may vary in different regions of the edge region 214. In one non-limiting example, a thickness of the layer of gate dielectric material 330 in the first region 310 of the edge region 214, in which a logic transistor may subsequently be formed, may be less than the thickness of the layer of gate dielectric material 330 in the second region 320 of the edge region 214, in which a high-voltage logic transistor may subsequently be formed. In some embodiments, the layer of gate dielectric material 330 may have different compositions in different regions 310, 320 of the edge region 214.

[0076] Again in relation to Fig. 40, a sacrificial gate material layer 340 may be formed over the layer of gate dielectric material 330. In various embodiments, the sacrificial gate material layer 340 may be used to fabricate dummy gate structures that may subsequently be replaced with metal gates (e.g., using an RPG process). In some embodiments, the sacrificial gate material layer 340 may be composed of a semiconductor material, such as polysilicon. Other suitable materials are within the contemplated scope of the disclosure. The sacrificial gate material layer 340 may be deposited using a suitable deposition process, as previously described.

[0077] Again in relation to Fig. 40, a hard mask layer 350 may be formed over the sacrificial gate material layer 340. The hard mask layer 350 may be composed of a suitable dielectric material, such as a nitride or oxide material, or combinations thereof. The hard mask layer 350 may be deposited using a suitable deposition process, as previously described.

[0078] Fig. 41 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process to remove the hard mask layer 350 and a portion of the sacrificial gate material layer 340 above the termination layer 293. With respect to Fig. 41 can be a structured mask (not in Fig. 41) may be formed over the hard mask layer 350 in the edge region 214. An etching process may be performed through the mask to remove the hard mask layer 350 and a portion of the sacrificial gate material layer 340 above the termination layer 293. The mask may prevent the hard mask layer 350 and the sacrificial gate material layer 340 from being etched in the edge region 214.

[0079] Fig. 42 is a vertical cross-sectional view of the exemplary intermediate structure showing a plurality of gate stacks GS1, GS2, and GS3 formed over the layer of gate dielectric material 330 in the edge region 214 of the exemplary intermediate structure. With reference to Fig. 42, the plurality of gate stacks GS1, GS2, GS3 may be formed in a similar manner to the plurality of memory stacks MS1-MS4 as previously described with respect to Fig. 15 and Fig. 16. In particular, a structured mask, such as a photoresist mask PR (not shown in Fig. 42) may be formed over the example intermediate structure. The mask may be lithographically patterned such that the mask covers selected portions of the hard mask layer 350 corresponding to the locations of gate stacks that may subsequently be formed in the edge region 214. An anisotropic etch process may be performed to remove portions of the hard mask layer 530 and the sacrificial gate material layer 340 exposed by the mask. The etch process may stop at the layer of gate dielectric material 330. Following the etch process, a plurality of gate stacks GS1-GS3 may overlie the layer of gate dielectric material 330 in the edge region 214. Each gate stack GS1-GS3 may include a sacrificial gate material layer 340 over the layer of gate dielectric material 330 and a hard mask layer 350 over the sacrificial gate material layer 340.Following the etching process, the patterned mask PR can be removed using a suitable process, such as by ashing or by dissolution using a solvent.

[0080] Fig. 43 is a vertical cross-sectional view of the exemplary intermediate structure showing gate stack side seal layers 351 over the side surfaces of the gate stacks GS1-GS3. With respect to Fig. 43, the gate stack side seal layers 351 may include one or more dielectric materials over the exposed side surfaces of the hard mask layer 350 and the sacrificial gate material layer 340 in each of the gate stacks GS1-GS3. In one non-limiting embodiment, the gate stack side seal layers 351 may include a nitride material, such as silicon nitride. In embodiments, the gate stack side seal layers 351 may be formed by conformally depositing a layer of dielectric material over the intermediate structure and performing an anisotropic etch process, such as a reactive ion etch process, to remove horizontally extending portions of the dielectric material layer(s) while leaving the gate stack seal layers 351 over the side surfaces of the gate stacks GS1-GS3.

[0081] Fig. 44 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process that removes the layer of gate dielectric material 330 and the termination layer 293 from the storage region 212 of the exemplary intermediate structure. With respect to Fig. 44, an etch process may be performed to remove the layer of gate dielectric material 330 and the termination layer 297. In some embodiments, the etch process may also remove the liner layer 291 (see Fig. 30). During the etching process, the edge region 214 may be covered by a mask to prevent etching of the edge region. The etching process may expose the top surfaces of the memory stacks MS1-MS4, the top and side surfaces of the select gate hard mask layer 287, side surfaces of the conductive material layer 283, and top surfaces of the substrate 210 in the memory region 212. In some embodiments, following the etching process, an ion implantation process may optionally be performed to form active regions (e.g., drain regions) in the substrate 210 between adjacent pairs of memory stacks MS1-MS4.

[0082] Fig. 45 is a vertical cross-sectional view of the exemplary intermediate structure, schematically illustrating an ion implantation process for forming source and drain regions ST for logic transistors that are subsequently formed in the edge region 214 of the exemplary intermediate structure. With reference to Fig. 45, one or more ion implantation processes may be performed in the edge region 214 to form active regions (i.e., source and drain regions SD) in the substrate 210 adjacent to the gate structures GS1, GS2. In embodiments, the one or more ion implantation processes may be masked implantation processes that are masked by a patterned mask (not shown in Fig. 45 shown).

[0083] Fig. 46 is a vertical cross-sectional view of the exemplary intermediate structure following an etch process to remove portions of the gate dielectric material layer 330 from the edge region 214 and the formation of main sidewall spacers 297 over the select gates SG in the memory region 212 and main sidewall spacers 353 over the gate stacks GS in the edge region 214. With respect to Fig. 46, an anisotropic etch process may be performed to remove exposed portions of the gate dielectric material layer 330 from the edge region 214. Portions of the gate dielectric material 330 underlying the gate stacks GS1-GS3 may be protected from being etched by the gate stacks GS1-GS3. Following the etch process, discrete gate dielectric layers 330 may be disposed beneath each of the gate stacks GS1-GS3.

[0084] Again in relation to Fig. 46, an etching process may also be used to expose the upper surface of the second isolation structure element IF2. In embodiments, the etching process may expose the upper surface of the second isolation structure element IF2 in a central portion of the second isolation structure element IF2. In edge portions of the second isolation structure element IF2, the overlying materials may not be completely removed by the etching process and may form dummy structures (i.e., non-functional structures) above the surface of the second isolation structure element IF2. As shown in Fig. For example, as shown in Figure 46, gate stack GS3 partially overlying second isolation structure element IF2 may be partially etched during the etching process. The partially etched gate stack GS3 may form a dummy structure overlying second isolation structure element IF2. A second dummy structure comprising a portion of control gate layer 247 may be overlying an edge region of second isolation structure element IF2 adjacent to memory region 212.

[0085] Again in relation to Fig. 46, a first plurality of main sidewall spacers 297 may be formed over the side surfaces of the select gates SG and the select gate hard mask layer 287 in the memory region 212, and a second plurality of main sidewall spacers 353 may be formed over side surfaces of the gate stacks GS in the edge region 214. The main sidewall spacers 297, 353 may be composed of a suitable dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, a high-k dielectric, combinations thereof, and the like. Other suitable dielectric materials are within the contemplated scope of the disclosure. The first plurality of main sidewall spacers 297 and the second plurality of main sidewall spacers 353 may be formed of the same material(s) or of different material(s).The main sidewall spacers 297, 353 may be formed by any suitable process, such as CVD, plasma enhanced chemical vapor deposition (PECVD), or LPCVD.

[0086] Fig. 47 is a vertical cross-sectional view of the exemplary intermediate structure showing metal silicide regions 355 on exposed surfaces of the substrate 210. With respect to Fig. 47, a thin layer of metal, such as Ti, Ni, W, etc., may be deposited on the exposed top surface of the substrate 210 in the storage region 212 and in the edge region 214. The metal may be heated to react the metal with the substrate and form metal silicide regions 355. The metal silicide regions 355 may overlie active regions (i.e., source and drain regions) of the substrate 210 and may provide an electrical contact layer to the respective source and drain regions DR, SD of the example structure.

[0087] Fig. 48 is a vertical cross-sectional view of the exemplary intermediate structure following a planarization process that removes the remaining portions of the hard mask HM and the select gate hard mask layer 287 from the memory region 212 and the remaining portions of the hard mask layer 350 from the gate stacks GS1-GS3 in the edge region 214. With respect to Fig. 48, a planarization process, such as a CMP and / or etching process, may be performed to remove the remaining portions of the hard mask HM from the memory stacks MS1-MS4, the select gate hard mask layer 287 over the select gates SG and the erase gates EG, and the hard mask layer 350 from the gate stacks GS1-GS3. Following the planarization process, the top surfaces of the control gates CG, the select gates SG, and the erase gates EG may be exposed in the memory region 212, and the top surfaces of the sacrificial gate material layers 340 may be exposed in the edge region 214. In various embodiments, the top surfaces of the control gates CG, the select gates SG, the erase gates EG, and the sacrificial gate material layers 340 may be substantially coplanar.

[0088] Fig. 49 is a vertical cross-sectional view of the exemplary intermediate structure showing a contact etch stop layer (CESL) 357 conformally formed over the intermediate structure and an interlayer dielectric (ILD) layer 410 formed over the CESL 357. With respect to Fig. 49, CESL 357 and ILD layer 410 may each be composed of a suitable dielectric material, such as silicon oxide, silicon nitride, silicon carbide, phosphosilicate glass (PSG), undoped silicate glass (USG), a doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Other dielectric materials are within the contemplated scope of the disclosure. In various embodiments, CESL 357 may be composed of a different material than ILD layer 410. In some embodiments, CESL 357 may be an etch stop layer having different etch properties (i.e., higher etch resistance) than the material of ILD layer 410. In one non-limiting embodiment, ILD layer 410 may include phosphosilicate glass (PSG), and CESL 357 may include silicon nitride.The CESL 357 and ILD layer 410 may each be deposited using suitable deposition techniques as previously described.

[0089] Fig. 50 is a vertical cross-sectional view of the exemplary intermediate structure following a planarization process that removes the ILD layer 410 and the CESL 357 over the top surfaces of the control gates CG, select gates SG, and erase gates EG in the memory region 212 and over the top surfaces of the sacrificial gate material layers 340 in the edge region 214. With respect to Fig. 50, a planarization process, such as a CMP and / or etch process, may be performed to remove portions of the ILD layer 410 and the CESL 357. Following the planarization process, the top surfaces of the control gates CG, the select gates SG, and the erase gates EG may be exposed in the memory region 212, and the top surfaces of the sacrificial gate material layers 340 may be exposed in the edge region 214. In various embodiments, the top surfaces of the control gates CG, the select gates SG, the erase gates EG, and the sacrificial gate material layers 340 may be substantially coplanar.

[0090] Fig. 50 additionally illustrates the structure of memory cells MC1-MC4 within the memory region 212 of the exemplary structure. As previously discussed, each functional memory cell MC in the memory region 212 may include a select gate SG, a floating gate FG, a control gate CG, and an erase gate EG, which it shares with an adjacent memory cell MC. In some embodiments, at least some of the memory cells MC may be dummy memory cells (i.e., non-functional memory cells), including at least some of the memory cells adjacent to the edge region 214. As in Fig. 50, memory cell MC4, for example, does not have a select gate SG and may be a dummy memory cell (ie, non-functional memory cell).

[0091] Fig. 51 is a vertical cross-sectional view of the exemplary intermediate structure showing metal gates MG1, MG2 formed in the edge region 214. With respect to Fig. 51, an etch process may be performed to remove the sacrificial gate material layers 340 from the gate stacks GS1 and GS2 in the edge region 214. In various embodiments, the etch process may be performed through a patterned mask (not shown in Fig. 51) having openings corresponding to the locations of the gate stacks GS1 and GS2. Following the etching process to remove the sacrificial gate material layers 340, the patterned mask may be removed. A layer of metal material may then be deposited to fill the openings formed in the gate stacks GS1, GS2, and a planarization process (e.g., a CMP process) may be used to remove any excess metal material over the openings, leaving metal gates MG1, MG2 in the respective gate stacks GS1, GS2. The metal gates MG1, MG2 may be composed of a suitable metallic material, such as aluminum (Al), tantalum (Ta), tungsten (W), titanium (Ti), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), alloys thereof, combinations thereof, and the like. Other suitable metallic materials are within the contemplated scope of the disclosure.In some embodiments, each of the metal gates MG may be composed of the same material. Alternatively, different materials may be used in different gate stacks GS1, GS2 in the edge region 214.

[0092] Fig. 51 additionally illustrates the structure of logic transistors LT1, LT2 within the edge region 214 of the exemplary structure. As previously discussed, each functional logic transistor LT in the edge region may include a metal gate MG above a channel region CR of the substrate 210. A gate dielectric layer 330 may be disposed between the metal gate MG and the channel region CR. Source and drain regions SD may be located on either side of the metal gate MG. The logic transistors LT1, LT2 in the edge region 214 may form logic devices such as memory selectors, power gates, and input / output elements. As previously discussed, different logic transistors LT in different areas of the edge region 214 may have different structures and / or perform different functions. For example, logic transistor LT1 in the illustrated Fig. 51, logic transistor LT2 in region 310 may be a logic transistor and logic transistor LT2 in region 320 may be a high voltage logic transistor.

[0093] In some embodiments, at least some of the gate structures in the edge region may be dummy structures (i.e., non-functional structures), including at least some of the gate structures adjacent to the edge region 214. As in Fig. For example, as shown in Figure 51, gate structure GS3 does not have a metal gate and may be a dummy gate structure (i.e., non-functional structure).

[0094] Fig. 52 is a vertical cross-sectional view of the exemplary intermediate structure showing a first layer of dielectric material 102 over the edge region 214 and over the control gates CG of the memory cells MC in the memory region 212. With reference to Fig. 52, in some embodiments, a continuous first layer of dielectric material 102 may be deposited over the exemplary intermediate structure, including over the upper surfaces of the logic transistors LT in the edge region 214 and over the upper surfaces of the memory cells MC in the memory region 212. In some embodiments, the first layer of dielectric material 102 may be patterned to remove portions of the layer 102 in the memory region 212. For example, a patterned mask, such as a photoresist mask (not shown) Fig. 52) may be formed over the continuous first layer of dielectric material 212. The mask may be lithographically patterned such that the mask covers selected portions of the first layer of dielectric material 102, including portions of the first layer of dielectric material 102 that overlie the edge region 214 and portions of the first layer of dielectric material 102 that overlie the control gates GC of the memory cells MC. An anisotropic etch process may be performed to remove portions of the first layer of dielectric material 102 exposed through the mask. The etch process may expose portions of the memory region 212, including the top surfaces of the select gates SG and the erase gates EG of the memory cells MC, through the first layer of dielectric material 102.Following the etching process, the mask can be removed using a suitable process, such as ashing or dissolution using a solvent.

[0095] The first layer of dielectric material 102 may be composed of a suitable dielectric material, such as an oxide or nitride material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). In some embodiments, the first layer of dielectric material 102 may be composed of silicon oxide formed using a tetraethoxysilane (TEOS) precursor. In some embodiments, the first layer of dielectric material 102 may be a resist protective oxide (RPO) material. Other suitable dielectric materials are within the contemplated scope of the disclosure. In some embodiments, the first layer of dielectric material 102 may have good adhesion properties, including good adhesion to the material(s) of the metal gates MG of the logic transistors LT1, LT2.The first layer of dielectric material 102 may be deposited using a suitable deposition process as previously discussed.

[0096] Fig. 53 is a vertical cross-sectional view of the exemplary intermediate structure showing a second layer of dielectric material 103 over the first layer of dielectric material 102 in the edge region 214. With respect to Fig. 53, a multilayer dielectric composite film structure 101 may be formed in the edge region 214 of the exemplary intermediate structure by depositing at least one additional layer of dielectric material 103 over the first layer of dielectric material 102. In some embodiments, a continuous second layer of dielectric material 103 may be deposited over the exemplary intermediate structure. A patterned mask, such as a photoresist mask (not shown) Fig. 53), may be formed over the continuous second layer of dielectric material 103, as previously described. The patterned mask may cover the second layer of dielectric material 103 in the edge region 214 and may expose the second layer of dielectric material 103 in the memory region 212. An etching process may remove the second layer of dielectric material 103 from the memory region 212, while the second layer of dielectric material 103 may overlie the first layer of dielectric material 102 in the edge region 214 to form a composite dielectric film structure 101 in the edge region 214. In embodiments, the composite dielectric film structure 101 may extend continuously over the edge region 214, including over the metal gates MG of the logic transistors LT.Following the etching process, the mask can be removed using a suitable process, such as ashing or dissolution using a solvent.

[0097] The second layer of dielectric material 103 may be composed of a suitable dielectric material, such as an oxide or nitride material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). In some embodiments, the second layer of dielectric material 103 may be composed of a buffer oxide material, a silicon nitride material, a high-temperature oxide (HTO) material, and the like. Other suitable dielectric materials are within the contemplated scope of the disclosure. The second layer of dielectric material 103 may have a different composition and / or different physical properties than the first layer of dielectric material 102. In various embodiments, the second layer of dielectric material 103 may have a density that is greater than a density of the first layer of dielectric material 102.For example, the second layer of dielectric material 103 may have a density that is at least 10%, such as at least 50%, including at least 100%, greater than a density of the first layer of dielectric material 102. In some embodiments, the second layer of dielectric material 103 may have a lower etch rate (i.e., higher etch resistance) than the material of the first layer of dielectric material 102. The second layer of dielectric material 103 may be deposited using a suitable deposition method, as previously described.

[0098] Fig. 54 is a vertical cross-sectional view of the exemplary intermediate structure showing metal silicide layers 380 over the top surfaces of the select gates SG and the erase gates EG in the memory region 212. With respect to Fig. 53, a silicidation process may be performed to form metal silicide layers 380 over the upper surfaces of the select gates SG and the erase gates EG of the memory cells MC in the memory region 212 of the exemplary intermediate structure. In various embodiments, a thin layer of metal material, such as Co, Ni, Ti, Ta, W, alloys thereof, or the like, may be deposited over the exposed surfaces of the select gates SG and the erase gates EG. The metal may be heated to react the metal with the silicon material of the select gates SG and the erase gates EG to form metal silicide layers 380 over the upper surfaces of the select gates SG and the erase gates EG. In one non-limiting example, the metal may be annealed at a temperature in the range of 750-1000°C for 1-2 hours. Alternatively, the metal may be laser annealed for microseconds to seconds, depending on the power of the laser.During the silicidation process, the control gates CG may be protected by the first layer of dielectric material 102 such that no metal silicide layers are formed over the control gates CG.

[0099] Following the formation of metal silicide layers 380 over the select gates SG and erase gates EC, an etching process, such as a wet etch, may be performed to remove any excess metal from the exemplary intermediate structure. During the etching process, the dielectric composite film structure 101 may protect the metal gates MG in the edge region 214 from being etched. As previously discussed, a dielectric composite film structure 101 over the edge region 214 may provide improved protection for the metal gates MG. In particular, weak points in the first layer of dielectric material 102, such as weak points due to the presence of metal deposits from the metal gates MG, may be eliminated due to the presence of a multilayer dielectric composite film structure 101, as shown in Fig. 54, does not result in etching damage to the underlying metal gates MG.

[0100] In various embodiments, a peripheral edge 431 of the composite dielectric film structure 101 may be within ±300 nm (e.g., ±200 nm, such as ±100 nm) of the boundary 430 between the storage region 212 and the edge region 214. This may prevent the composite dielectric film structure 101 from extending too far into the storage region 212, which could interfere with the silicidation process as previously described, or from the dielectric film structure 101 not extending far enough within the edge region 214, which could result in insufficient protection for the metal gates MG of the logic transistors LT.

[0101] Fig. 55 is a vertical cross-sectional view of the exemplary intermediate structure, showing an interlayer dielectric (ILD) layer 412 over the intermediate structure, metal features 112 over the ILD layer 412, and conductive vias 110 extending between the metal features 112 and the memory cells MC and the logic transistors LT. With reference to Fig. 55, the ILD layer 412 may be composed of a suitable dielectric material, such as silicon oxide, silicon nitride, silicon carbide, phosphosilicate glass (PSG), undoped silicate glass (USG), a doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Other dielectric materials are within the contemplated scope of the disclosure. The ILD layer 412 may be deposited using a suitable deposition process, as previously described. In embodiments, a planarization process may be used to provide a planar top surface of the ILD layer 412.

[0102] Again in relation to Fig. 55, the conductive vias 110 may be formed by forming via openings through ILD layers 410 and 412 and through the dielectric composite film structure 101 in the edge region 214 using an anisotropic etch process. In the memory region 212, the via openings may extend to the CESL 357 that lies above each of the drain regions DR of the memory cells MC. In the edge region 214, the via openings may extend to the CESL 357 that lies above each of the source and drain regions SD of the logic transistors. The via openings may extend through the CESL 357 using an etch process to form the contact regions 355 (see Fig. 47) overlying each of the respective source and drain regions DR, SD. Then, the via openings may be filled with a conductive material, such as Cu, Ni, Ti, W, Al, alloys thereof, and the like, to form the conductive vias 110 contacting the respective source and drain regions DR, SD.

[0103] Metal features 112, such as conductive lines, may be formed over the ILD layer 412 and may contact one or more conductive vias 110. In some embodiments, the metal features 112 may be at least partially embedded within the ILD layer 412 such that a bottom surface of the metal features 112 may be below a top surface of the ILD layer 412. In some embodiments, a distance between the bottom surface of a metal feature 112 embedded in the ILD layer 412 and the top surface of the ILD layer 412 may be ≤ 30 nm.

[0104] Fig. 56 is a flow diagram illustrating a general method 500 for manufacturing a memory device 100 according to various embodiments of the present disclosure. With reference to Fig. 2-51 and 56, in step 502 of method 500, a memory cell MC may be formed in a memory region 212 of a substrate 210. With respect to Fig. 2-51 and 56, in step 504 of method 500, a transistor LT having a metal gate MG may be formed in an edge region 214 of the substrate 210. With respect to Fig. 52-54 and 56, in step 506 of method 500, a composite dielectric film structure 101 may be formed over the metal gate MG of the transistor LT in the edge region 214 of the substrate 210. The composite dielectric film 101 may include a first dielectric layer 102 and a second dielectric layer 103 over the first dielectric layer 102, where the second dielectric layer 103 may have a greater density than a density of the first dielectric layer 102.

[0105] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims.

Claims

[1] A semiconductor device (100) comprising: a substrate (210) having a storage region (212) and an edge region (214); a transistor (LT) having a metal gate (MG) located in the peripheral region (214); a dielectric composite film structure (101) overlying the metal gate (MG) of the transistor (LT), the dielectric composite film structure (101) comprising a first layer of dielectric material (102) and a second layer of dielectric material (103) over the first layer of dielectric material (102), and the second layer of dielectric material (103) having a greater density than a density of the first layer of dielectric material (102); and at least one memory cell (SGMC1, SGMC2) located in the memory region (212), wherein a lower surface of the dielectric composite film structure (101) is coplanar with an upper surface of the at least one memory cell (SGMC1, SGMC2). [2] The semiconductor device (100) of claim 1, wherein the first layer of dielectric material (102) contacts a top surface of the metal gate (MG) of the transistor (LT). [3] The semiconductor device (100) of claim 1 or 2, wherein each of the first layer of dielectric material (102) and the second layer of dielectric material (103) has a thickness ranging between 5 nm and 30 nm. [4] The semiconductor device (100) of any preceding claim, wherein the first layer of dielectric material (102) includes a dielectric material including at least one of silicon oxide formed using a tetraethoxysilane precursor and a photoresist protective oxide material. [5] The semiconductor device (100) of any preceding claim, wherein the second layer of dielectric material (103) includes a dielectric material including at least one of a buffer oxide material, a silicon nitride material, and a high temperature oxide material. [6] Semiconductor device (100) according to one of the preceding claims, wherein the at least one memory cell (SGMC1, SGMC2) comprises: a floating gate (FG); a control gate (CG) located above the floating gate (FG); and a select gate (SG) located on a first side of the floating gate (FG) and the control gate (CG), wherein the lower surface of the dielectric composite film structure (101) is coplanar with an upper surface of the control gate (CG). [7] The semiconductor device (100) according to claim 6, wherein the at least one memory cell (SGMC1, SGMC2) further comprises: an erase gate (EG) located on a second side of the floating gate (FG) and the control gate (CG), wherein a metal silicide layer (380) is located on an upper surface of the select gate (SG) and on an upper surface of the erase gate (EG). [8] The semiconductor device (100) according to any preceding claim, wherein the semiconductor device (100) comprises a plurality of transistors (LT1, LT2) having a metal gate (MG) located in the peripheral region (214) and a plurality of memory cells (SGMC1, SGMC2) located in the memory region (212), and wherein the compound dielectric film structure (101) overlies the metal gates (MG) of the plurality of transistors (LT1, LT2) located in the peripheral region (212), and the compound dielectric film structure (101) does not overlie the plurality of memory cells (SGMC1, SGMC2) located in the memory region (212). [9] A semiconductor device (100), comprising: a substrate (210) having a storage region (212) and an edge region (214); a plurality of memory cells (SGMC1, SGMC2) located in the memory area (212); several transistors (LT1, LT2) located in the peripheral region (214); and a dielectric composite film structure (101) comprising at least two dielectric material layers (102, 103) extending over the plurality of transistors (LT1, LT2) in the peripheral region (214), wherein a peripheral edge (431) of the dielectric composite film structure (101) lies within 300 nm of a boundary between the storage region (212) and the peripheral region (214); wherein a lower surface of the dielectric composite film structure (101) is coplanar with an upper surface of the plurality of memory cells (SGMC1, SGMC2). [10] The semiconductor device (100) of claim 9, wherein the boundary between the storage region (212) and the edge region (214) is defined by a peripheral edge of an isolation structure element (IF2) located in the substrate (210). [11] The semiconductor device (100) of claim 9 or 10, wherein an upper surface of the substrate (210) in the storage region (212) is recessed relative to an upper surface of the substrate (210) in the edge region (214). [12] The semiconductor device (100) of any one of the preceding claims 9 to 11, further comprising a plurality of conductive vias (110) extending through the dielectric composite film structure (101), wherein the dielectric composite film structure (101) extends continuously between the conductive vias (110) in the edge region (214). [13] A semiconductor device (100) according to any one of the preceding claims 9 to 12, wherein each of the transistors (LT1, LT2) in the peripheral region (214) has a metal gate (MG) and the dielectric composite film structure (101) overlies the metal gates (MG) of the plurality of transistors (LT1, LT2) in the peripheral region (214). [14] A semiconductor device (100) according to any one of the preceding claims 9 to 13, wherein the dielectric composite film structure (101) comprises at least two dielectric material layers (102, 103) having different compositions and / or physical properties. [15] A method of manufacturing a semiconductor device (100), comprising: Forming a memory cell (SGMC1, SGMC2) in a memory region (212) of a substrate (210); Forming a transistor (LT) having a metal gate (MG) in an edge region (214) of the substrate (210); Forming a dielectric composite film structure (101) over the metal gate (MG) of the transistor (LT) in the edge region (214) of the substrate (210), the dielectric composite film structure (101) comprising a first layer of dielectric material (102) and a second layer of dielectric material (103) over the first layer of dielectric material (102), and the second layer of dielectric material (103) having a greater density than a density of the first layer of dielectric material (102), a lower surface of the dielectric composite film structure (101) being coplanar with a top surface of the memory cell (SGMC1, SGMC2), the forming of the dielectric composite film structure (101) comprising: Forming the first layer of dielectric material (102) over the metal gate (MG) of the transistor (LT) in the edge region (214) and over a control gate (CG) of the memory cell (SGMC1, SGMC2) in the memory region (212); and Forming the second layer of dielectric material (103) over the first layer of dielectric material (102) in the edge region (214) to form the dielectric composite film structure (101), wherein the dielectric composite film structure (101) does not extend over the memory cell (SGMC1, SGMC2) in the memory region (212) of the semiconductor device (100); and Performing a wet etch to remove a metal material from the semiconductor device (100), wherein the dielectric composite film structure (101) protects the metal gate (MG) of the transistor (LT) in the edge region (214) from being etched. [16] The method of claim 15, further comprising: Forming a metal silicide layer (380) over a top surface of at least one of a select gate (SG) and an erase gate (EG) of the memory cell (SGMC1, SGMC2), wherein a portion of the first layer of dielectric material (102) overlies the control gate (CG) of the memory cell (SGMC1, SGMC2) during formation of the metal silicide layer (380). [17] The method of claim 16, wherein forming the metal silicide layer (380) comprises: Depositing a metal layer over at least one of the select gate (SG) and the erase gate (EG) of the memory cell (SGMC1, SGMC2); and Heating the metal layer to form a metal silicide layer (355) over a top surface of at least one of the select gate (SG) and the erase gate (EG) of the memory cell (SGMC1, SGMC2), wherein excess metal is removed from the semiconductor device (100) during the wet etching. [18] Method according to one of the preceding claims 15 to 17, further comprising: Forming a conductive via (110) through the dielectric composite film structure (101) and electrically contacting a source or drain region (SD) of the transistor (LT) in the edge region (214).

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