Heat dissipation structures for semiconductor devices and manufacturing processes

Abstract

Semiconductor package containing: a semiconductor die (200) comprising a substrate (202), a front interconnect structure (120) on a front side of the substrate (202) and a rear interconnect structure (140) on a back side of the substrate (202) opposite the front interconnect structure (120); an auxiliary die (210) which is arranged on the front-side interconnect structure (120); a heat dissipation structure (212) on the auxiliary die (210), wherein the heat dissipation structure (212) is thermally connected to the semiconductor die (200) and the auxiliary die (210); a redistribution structure (230) on the rear interconnect structure (140) opposite the substrate (202), wherein the redistribution structure (230) is electrically connected to the semiconductor die (200); and an encapsulation material (228) on the redistribution structure (230), wherein the encapsulation material (228) encapsulates the semiconductor die (200), the auxiliary die (210) and the heat dissipation structure (212).

Description

BACKGROUND

[0001] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers onto a semiconductor substrate. These different material layers are then structured by lithography to create circuit components and elements.

[0002] The semiconductor industry is continuously improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the smallest feature size, thus enabling the integration of more components in a given area. However, reducing the smallest feature size introduces additional problems that need to be addressed.

[0003] Heat dissipation structures for semiconductor devices are known, for example, from WO 2019 / 132958 A1, US 2022 / 0093512 A1 and US 2019 / 0096791 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows an example of a nanostructured field-effect transistor (nano-FET) in a three-dimensional view according to some embodiments. The Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6A, Fig. 6B, Fig. 6C, Fig. 7A, Fig. 7B, Fig. 7C, Fig. 8A, Fig. 8B, Fig. 8C, Fig. 9A, Fig. 9B, Fig. 9C, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 11A, Fig. 11B, Fig. 11C, Fig. 11D, Fig. 12A, Fig. 12B, Fig. 12C, Fig. 12D, Fig. 12E, Fig. 13A, Fig. 13B, Fig. 13C, Fig. 14A, Fig. 14B, Fig. 14C, Fig. 15A, Fig. 15B, Fig. 15C, Fig. 16A, Fig. 16B, Fig. 16C, Fig. 17A, Fig. 17B, Fig. 17C, Fig. 18A, Fig. 18B, Fig. 18C, Fig. 19A, Fig. 19B, Fig. 19C, Fig. 20A, Fig. 20B, Fig. 20C, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 22A, Fig. 22B, Fig. 22C, Fig. 23A, Fig. 23B, Fig. 23C, Fig. 24A, Fig. 24B, Fig. 24C, Fig. 25A, Fig. 25B, Fig. 25°C, Fig. 26A, Fig. 26B, Fig. 26C, Fig. 27A, Fig. 27B and Fig. Figure 27C shows sectional views of intermediate stages in the fabrication of nano-FETs according to some embodiments. The Fig. 28, Fig. 29, Fig. 30, Fig. 31, Fig. 32, Fig. 33, Fig. 34, Fig. 35, Fig. 36, Fig. 37, Fig. 38, Fig. 39, Fig. 40, Fig. 41, Fig. 42, Fig. 43, Fig. 44A, Fig. 44B, Fig. 45A, Fig. 45B, Fig. 46, Fig. 47, Fig. 48A, Fig. 48B, Fig. 48C, Fig. 49, Fig. 50A, Fig. 50B, Fig. 50C, Fig. 51, Fig. 52, Fig. 53, Fig. 54, Fig. 55, Fig. 56, Fig. 57, Fig. 58, Fig. 59A, Fig. 59B, Fig. 59C and Fig. Figure 60 shows sectional and top-down views of intermediate stages in the manufacture of packaged semiconductor devices with heat dissipation structures according to some embodiments. DETAILED DESCRIPTION

[0005] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0007] Various embodiments provide packaged semiconductor devices incorporating heat dissipation structures and methods for their fabrication. The packaged semiconductor devices can have a front-side interconnect structure (also referred to as a back-end-of-line interconnect structure (BEOL interconnect structure)) and a rear-side interconnect structure (also referred to as a buried power network (BPN)) on opposite sides of a device layer (such as a device layer with transistor structures).By providing the backside interconnect structure, the number of layers required for the frontside interconnect structure can be reduced, and the backside interconnect structure can have wider conductors than the frontside interconnect structure, both of which result in improved speed performance and energy efficiency. In various embodiments, heat dissipation structures can be fabricated in the frontside interconnect structure, the backside interconnect structure, and / or the device layer; connected to the frontside interconnect structure; connected to the backside interconnect structure; connected to side faces of the semiconductor devices; combinations thereof; or the like, to dissipate heat generated in the semiconductor devices.The heat dissipation structures can include thermally conductive dummy structural elements, a front heat spreader, a rear heat spreader, a conductive cap heat spreader, a lateral heat spreader, or combinations thereof. Integrating the heat dissipation structures improves heat dissipation (e.g., transient heat output), enhances device performance, and reduces device failures.

[0008] Embodiments are described below in a specific context, namely a die featuring nanostructured field-effect transistors (nano-FETs). However, various embodiments can be applied to dies featuring other types of transistors (e.g., fin field-effect transistors (FinFETs), planar transistors, or the like) instead of, or in combination with, the nano-FETs.

[0009] Fig. Figure 1 shows an example of nanoFETs (e.g., nanowire FETs, nanolayer FETs (nanoFETs), or the like) in a three-dimensional view according to some embodiments. The nanoFETs have nanostructures 55 (e.g., nanolayers, nanowires, or the like) over fins 66 on a substrate 50 (e.g., a semiconductor substrate). The nanostructures 55 act as channel regions for the nanoFETs. The nanostructures 55 can be p-nanostructures, n-nanostructures, or a combination thereof. Insulation regions 68 are arranged between adjacent fins 66, which can project over and between adjacent insulation regions 68. Although the insulation regions 68 are described and depicted as regions separated from the substrate 50, the term "substrate" used here can refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the insulation regions.And although the lower parts of the fins 66 are depicted as a single material connected to the substrate 50, the lower parts of the fins 66 and / or the substrate 50 may consist of a single material or a plurality of materials. In this context, the fins 66 denote the portion that extends between the adjacent insulation areas 68.

[0010] Dielectric gate layers 100 are arranged over the top and side walls of the fins 66 and along the top, side walls, and bottom surfaces of the nanostructures 55. Gate electrodes 102 are arranged over the dielectric gate layers 100. Epitaxial source / drain regions 92 are arranged on the fins 66 on the sides opposite the dielectric gate layers 100 and the gate electrodes 102.

[0011] Fig. Figure 1 shows further reference cross-sections that will be used in later figures. A cross-section AA' runs along a longitudinal axis of a gate electrode 102 and, for example, in a direction perpendicular to the direction of current flow between epitaxial source / drain regions 92 of a nanoFET. A cross-section BB' is parallel to the cross-section AA' and extends through epitaxial source / drain regions 92 of several nanoFETs. A cross-section CC' is perpendicular to the cross-section AA' and is parallel to a longitudinal axis of a fin 66 of the nanoFET and runs, for example, in a direction of current flow between the epitaxial source / drain regions 92 of the nanoFET. For clarity, later figures refer to these reference cross-sections.

[0012] Some embodiments discussed here are related to nanoFETs fabricated using a gate-last process. A gate-first process can be used in some embodiments. Furthermore, aspects used in planar devices, such as planar FETs or fin field-effect transistors (FinFETs), are considered in some embodiments.

[0013] The Fig. Figures 2 to 27C are sectional views of intermediate stages in the fabrication of nano-FETs according to some embodiments. Fig. 2 to 5, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22A, 23A, 24A, 25A, 26A and 27A show the reference cross-section A-A', which is in Fig. 1 is shown. Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 12D, Fig. 13B, Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B, Fig. 18B, Fig. 19B, Fig. 20B, Fig. 21B, Fig. 22B, Fig. 23B, Fig. 24B, Fig. 25B, Fig. 26B and Fig. 27B shows the reference cross-section B-B', which is in Fig. 1 is shown. Fig. 6C, Fig. 7C, Fig. 8C, Fig. 9C, Fig. 10C, Fig. 11C, Fig. 11D, Fig. 12C, Fig. 12E, Fig. 13C, Fig. 14C, Fig. 15C, Fig. 16C, Fig. 17C, Fig. 18C, Fig. 19C, Fig. 20C, Fig. 21C, Fig. 22C, Fig. 23C, Fig. 24C, Fig. 25°C, Fig. 26C and Fig. 27C show the reference cross-section C-C', which is in Fig. 1 is shown. In the Fig. 28, Fig. 29, Fig. 30, Fig. 31, Fig. 32, Fig. 33, Fig. 34, Fig. 35, Fig. 36, Fig. 37, Fig. 38, Fig. 39, Fig. 40, Fig. 41, Fig. 42, Fig. 43, Fig. 44, Fig. 45, Fig. 46, Fig. 47, Fig. 48, Fig. 49, Fig. 50, Fig. 51, Fig. 52, Fig. 53, Fig. 54, Fig. 55, Fig. 56, Fig. 57, Fig. 58, Fig. 59 to Fig. 60 discusses heat dissipation structures that can be used to improve heat dissipation from nano-FETs manufactured according to the processes of Fig. They can be manufactured from 2 to 27C. The heat dissipation structures can alternatively be used for other semiconductor devices, such as FinFETs, planar transistors, and the like.

[0014] In Fig. 2. A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a solid semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate comprises a layer of semiconductor material fabricated on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is fabricated on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used.In some embodiments, the semiconductor material of substrate 50 may comprise: germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0015] The substrate 50 has an n-region 50N and a p-region 50P. The n-region 50N can be used to fabricate n-type devices, such as NMOS transistors, e.g., n-nanoFETs. The p-region 50P can be used to fabricate p-type devices, such as PMOS transistors, e.g., p-nanoFETs. The n-region 50N can be physically separated from the p-region 50P (as represented by the dividing line 20), and any number of device structure elements (e.g., other active devices, doped regions, isolation structures, or the like) can be placed between the n-region 50N and the p-region 50P. Although an n-range 50N and a p-range 50P are shown, any number of n-ranges 50N and p-ranges 50P can be provided.

[0016] Furthermore, in Fig. 2. A multilayer stack 64 is fabricated on the substrate 50. The multilayer stack 64 has alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustrative purposes, and as will be discussed in more detail below, the second semiconductor layers 53 are removed and the first semiconductor layers 51 are patterned to fabricate channel regions of the nanoFETs in the n-region 50N and the p-region 50P. In these embodiments, the channel regions in both the n-region 50N and the p-region 50P can have the same material composition (e.g., silicon or another semiconductor material) and can be fabricated simultaneously.

[0017] In some embodiments, the second semiconductor layers 53 can be removed and the first semiconductor layers 51 can be structured to create channel regions of nanoFETs in the n-region 50N, and the first semiconductor layers 51 can be removed and the second semiconductor layers 53 can be structured to create channel regions of nanoFETs in the p-region 50P. In some embodiments, the first semiconductor layers 51 can be removed and the second semiconductor layers 53 can be structured to create channel regions of nanoFETs in the n-region 50N, and the second semiconductor layers 53 can be removed and the first semiconductor layers 51 can be structured to create channel regions of nanoFETs in the p-region 50P.In some embodiments, the first semiconductor layers 51 can be removed and the second semiconductor layers 53 can be structured to produce channel regions of nano-FETs in both the n-region 50N and the p-region 50P.

[0018] For illustrative purposes, the depicted multilayer stack 64 comprises three layers of the first semiconductor layers 51 and three layers of the second semiconductor layers 53. In some embodiments, the multilayer stack 64 can have any number of first semiconductor layers 51 and second semiconductor layers 53. Each of the layers of the multilayer stack 64 can be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. In some embodiments, the first semiconductor layers 51 can be fabricated from a first semiconductor material suitable for p-nanoFETs, such as silicon germanium or the like.The second semiconductor layers 53 can be made from a second semiconductor material suitable for n-nanoFETs, such as silicon, silicon carbide, or the like. For illustrative purposes, the multilayer stack 64 shown has a bottom first semiconductor layer 51 made of the first semiconductor material. In some embodiments, the multilayer stack 64 can also be manufactured such that it has a bottom second semiconductor layer 53 made of the second semiconductor material.

[0019] The first and second semiconductor materials can be materials exhibiting high etch selectivity with respect to each other. Therefore, the first semiconductor layers 51 of the first semiconductor material can be removed without substantially removing the second semiconductor layers 53 of the second semiconductor material. This allows the second semiconductor layers 53 to be structured to fabricate channel regions of nanoFETs. Similarly, in embodiments where the second semiconductor layers 53 are removed and the first semiconductor layers 51 are structured to fabricate channel regions, the second semiconductor layers 53 of the second semiconductor material can be removed without substantially removing the first semiconductor layers 51 of the first semiconductor material. This allows the first semiconductor layers 51 to be structured to fabricate channel regions of nanoFETs.

[0020] In Fig. 3. Fins 66 are fabricated in the substrate 50, and nanostructures 55 are fabricated in the multilayer stack 64. In some embodiments, the nanostructures 55 and the fins 66 can be fabricated in the multilayer stack 64 and the substrate 50, respectively, by etching trenches into the multilayer stack 64 and the substrate 50. The etching can be performed using any suitable etching process, such as reactive ion beam etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching process can be anisotropic. In the production of the nanostructures 55 by etching the multilayer stack 64, first nanostructures 52A-C (collectively referred to as first nanostructures 52) can be defined from the first semiconductor layers 51 and second nanostructures 54A-C (collectively referred to as second nanostructures 54) can be defined from the second semiconductor layers 53.The first nanostructures 52 and the second nanostructures 54 can be collectively referred to as the nanostructures 55.

[0021] The fins 66 and the nanostructures 55 can be structured using any suitable method. For example, the fins 66 and the nanostructures 55 can be structured using one or more photolithographic processes, such as dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithographic and self-aligning processes, enabling the creation of structures with, for example, grid spacings smaller than those achievable with a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is produced over a substrate and then structured using a photolithographic process. Spacers are produced along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can then be used to structure the fins 66 and the nanostructures 55.

[0022] In Fig. 3. For illustrative purposes, the fins 66 and the nanostructures 55 in the n-region 50N and the p-region 50P are shown to have substantially the same widths. In some embodiments, the widths of the fins 66 and the nanostructures 55 in the n-region 50N may be greater than or less than the widths of the fins 66 and the nanostructures 55 in the p-region 50P. While each of the fins 66 and the nanostructures 55 is shown to have a uniform width throughout, in some embodiments the fins 66 and / or the nanostructures 55 may have other sidewalls, such as conical sidewalls. In this respect, the width of each of the fins 66 and / or the nanostructures 55 may increase continuously in one direction towards the substrate 50. In these embodiments, each of the nanostructures 55 in a vertical stack may have a different width and be trapezoidal.

[0023] In Fig. 4. Shallow trench isolation areas (STI areas) 68 are produced adjacent to the fins 66. The STI areas 68 can be produced by depositing an insulating material over the substrate 50, the fins 66, and the nanostructures 55, and between adjacent fins 66 and nanostructures 55. The insulating material can be an oxide (such as silicon dioxide), a nitride, the like, or a combination thereof, and can be produced by high-density plasma vapor deposition (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulating materials deposited by a suitable method can also be used. In the illustrated embodiment, the insulating material is silicon dioxide deposited by an FCVD process.After the insulating material has been deposited, a tempering process can be carried out. In some embodiments, the insulating material is deposited in such a way that excess insulating material covers the nanostructures 55. Although the insulating material is shown as a single layer, in some embodiments multiple layers can be used. For example, in some embodiments a coating (not shown separately) can be produced along the surfaces of the substrate 50, the fins 66, and the nanostructures 55. Subsequently, a filler material, such as the materials discussed above, can be produced over the coating.

[0024] A removal process is then applied to the insulating material to remove excess insulating material covering the nanostructures 55. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, may be used. The planarization process exposes the nanostructures 55 so that, upon completion of the planarization process, the top surfaces of the nanostructures 55 and the insulating material are at the same level.

[0025] The insulating material is then recessed to create the STI regions 68. The insulating material is recessed such that the nanostructures 55 and the fins 66 protrude between adjacent STI regions 68 in the n-region 50N and the p-region 50P. Top surfaces of the STI regions 68 can have a flat surface as shown, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions 68 can be produced flat, convex, and / or concave by suitable etching. The STI regions 68 can be recessed using a suitable etching process, such as one that is selective for the insulating material (e.g., one that etches the insulating material at a higher rate than the nanostructures 55). As shown in Fig. As shown in Figure 4, the upper surfaces of the STI regions 68 can be arranged above the upper surfaces of the fins 66. In some embodiments, however, the upper surfaces of the STI regions 68 can be arranged at the same level as or below the upper surfaces of the fins 66. In some embodiments, oxide removal with dilute hydrofluoric acid (dHF acid) can be used to etch back the insulating material.

[0026] The foregoing with reference to the Fig. 2, Fig. 3 to Fig. The process described in Section 4 is only one example of how the fins 66 and the nanostructures 55 can be fabricated. In some embodiments, the fins 66 and / or the nanostructures 55 can be fabricated using a mask and an epitaxial growth process. For example, a dielectric layer can be fabricated over a top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be grown epitaxially in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 66 and / or the nanostructures 55. The epitaxial structures can comprise alternating layers of the semiconductor materials discussed above, such as the first semiconductor material and the second semiconductor material.In some embodiments where epitaxial structures are grown epitaxially, the epitaxially grown materials can be doped in situ during growth, thus eliminating the need for prior and / or subsequent implantations. In some embodiments, in-situ and implantation doping can be used simultaneously.

[0027] Furthermore, the first semiconductor layers 51 (and the resulting first nanostructures 52) and the second semiconductor layers 53 (and the resulting second nanostructures 54) are presented and discussed here only for illustrative purposes as having the same materials in the p-region 50P and the n-region 50N. In some embodiments, one or both of the first semiconductor layers 51 and the second semiconductor layers 53 may have different materials or be produced in a different order in the p-region 50P and the n-region 50N.

[0028] In Fig. 4. Suitable wells (not shown separately) can be fabricated in the fins 66, the nanostructures 55, and / or the STI regions 68. In embodiments with different well types, various implantation steps for the n region 50N and the p region 50P can be achieved using a photoresist or other masks (not shown separately). For example, a photoresist can be fabricated over the fins 66 and the STI regions 68 in the n region 50N and the p region 50P. The photoresist is structured to expose the p region 50P. The photoresist can be fabricated using a spin-depositing process and can be structured using suitable photolithography techniques.Once the photoresist has been structured, implantation with n-dopers is performed in the p-region 50P, and the photoresist can act as a mask to prevent implantation of n-dopers in the n-region 50N. The n-dopers can be phosphorus, arsenic, antimony, or the like, up to a concentration in the range of approximately 10. 13 atoms / cm² 3 up to about 10 14 atoms / cm² 3 The photoresist is implanted into the area. After implantation, it is removed, for example, using a suitable detachment process.

[0029] Before or after implantation of the p-region 50P, a photoresist or other masks (not shown separately) are fabricated over the fins 66, the nanostructures 55, and the STI regions 68 in the p-region 50P and the n-region 50N. The photoresist is structured to expose the n-region 50N. The photoresist can be fabricated using a spin-casting process and can be structured using suitable photolithography techniques. Once the photoresist has been structured, p-doping is implanted into the n-region 50N, and the photoresist can act as a mask to prevent p-doping from being implanted into the p-region 50P. The p-doping materials can be boron, boron fluoride, indium, or the like, up to a concentration of approximately 10¹³ atoms / cm². 3 up to about 1014 atoms / cm² 3The photoresist is implanted into the area. After implantation, it can be removed, for example, using a suitable detachment process ("ashing").

[0030] Following the implantation of the n-region 50N and the p-region 50P, a tempering process can be performed to repair implantation damage and activate the implanted p- and / or n-doping materials. In some embodiments, the grown materials of epitaxial fins can be doped in situ during growth, thus eliminating the need for implantation. In some embodiments, in-situ and implantation doping can be used together.

[0031] In Fig. In step 5, a dielectric dummy layer 70 is produced on the fins 66 and / or the nanostructures 55. The dielectric dummy layer 70 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like. The dielectric dummy layer 70 can be deposited using suitable methods or grown thermally.

[0032] A dummy gate layer 72 is fabricated over the dielectric dummy layer 70, and a mask layer 74 is fabricated over the dummy gate layer 72. The dummy gate layer 72 can be deposited over the dielectric dummy layer 70 and then planarized, for example, by CMP. The dummy gate layer 72 can be a conductive or non-conductive material and can be selected from a group that includes: amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering, or other methods for depositing the selected material. The dummy gate layer 72 can be made from other materials which have high etch selectivity with respect to the etching of the STI areas 68.

[0033] The mask layer 74 can be deposited over the dummy gate layer 72. The mask layer 74 can, for example, comprise silicon nitride, silicon oxide nitride, or the like. In the illustrated embodiment, a single dummy gate layer 72 and a single mask layer 74 are produced across the n-region 50N and the p-region 50P. It should be noted that the dielectric dummy layer 70 is shown, for illustrative purposes only, to cover only the fins 66 and the nanostructures 55. In some embodiments, the dielectric dummy layer 70 can be deposited such that it covers the STI regions 68. In this case, the dielectric dummy layer 70 can extend between the dummy gate layer 72 and the STI regions 68.

[0034] The Fig. Figures 6A to 27C show various further steps in the manufacture of devices of the embodiments. Fig. 6A to 27C show structural elements either in the n-region 50N or the p-region 50P. In the Fig. 6A to 6C can use mask layer 74 (see Fig. 5) are structured using suitable photolithography and etching techniques to fabricate masks 78. The structure of the masks 78 can be transferred to the dummy gate layer 72 and the dielectric dummy layer 70 to fabricate dummy gates 76 and dummy gate dielectrics 71, respectively. The dummy gates 76 cover respective channel regions of the nanostructures 55. The structure of the masks 78 can be used to physically separate each dummy gate 76 from adjacent dummy gates 76. The dummy gates 76 can have a longitudinal direction that is perpendicular to the longitudinal direction of the respective fins 66 and nanostructures 55.

[0035] In the Fig. In steps 7A to 7C, a first spacer layer 80 and a second spacer layer 82 are produced over the structures, each located in the Fig. Figures 6A to 6C are shown. The first spacer layer 80 and the second spacer layer 82 are subsequently structured to act as spacers when creating self-adjusting source / drain regions. In the Fig. In steps 7A to 7C, the first spacer layer 80 is produced on the top surfaces of the STI regions 68; the top surfaces and side walls of the nanostructures 55 and the masks 78; and the side walls of the dummy gates 76, the dummy gate dielectrics 71, and the fins 66. The second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 can be produced from silicon oxide, silicon nitride, silicon oxide nitride, or the like using processes such as thermal oxidation or by CVD, ALD, or the like. The second spacer layer 82 can be produced from a material having a different etching rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxide nitrides, or the like, and can be deposited by CVD, ALD, or the like.

[0036] After the first spacer layer 80 has been produced and before the second spacer layer 82 is produced, implantations can be performed to create lightly doped source / drain regions (LDD regions) (not shown separately). In embodiments with different device types, similar to the above described above, Fig. In the implantation process discussed above, a mask, such as a photoresist, can be fabricated over the n-region 50N while exposing the p-region 50P, and suitable dopants (e.g., p-dopers) can be implanted into the exposed fins 66 and the nanostructures 55 in the p-region 50P. The mask can then be removed. The n-dopers can be any of the previously discussed n-dopers, and the p-dopers can be any of the previously discussed p-dopers.The lightly doped source / drain regions can have a concentration of dopants in the range of approximately 1×10. 15 atoms / cm² 3 up to about 1×10 19 atoms / cm² 3 exhibiting [unclear]. A tempering process can be performed to repair implant damage and activate the implanted dopants.

[0037] In the Fig. In steps 8A to 8C, the first spacer layer 80 and the second spacer layer 82 are etched to produce first spacers 81 and second spacers 83, respectively. As will be discussed in more detail below, the first spacers 81 and the second spacers 83 serve to self-align subsequently fabricated source / drain regions and to protect the sidewalls of the fins 66 and / or the nanostructures 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like.In some embodiments, the material of the second spacer layer 82 has a different etching rate than the material of the first spacer layer 80, so that the first spacer layer 80 can act as an etch stop layer when the second spacer layer 82 is patterned, and the second spacer layer 82 can act as a mask when the first spacer layer 80 is patterned. For example, the second spacer layer 82 can be etched using an anisotropic etching process, with the first spacer layer 80 acting as an etch stop layer. Remaining portions of the second spacer layer 82 form the second spacers 83, as shown in [Figure]. Fig. 8B is shown. The second spacers 83 then act as a mask, while exposed parts of the first spacer layer 80 are etched to form the first spacers 81, as shown in the Fig. 8B and Fig. 8C is shown.

[0038] As in Fig. As shown in Figure 8B, the first spacers 81 and the second spacers 83 are arranged on side walls of the nanostructures 55 and the fins 66. As shown in Fig. As shown in Figure 8C, in some embodiments the second spacer layer 82 above the first spacer layer 80 adjacent to the masks 78, the dummy gates 76, and the dummy gate dielectrics 71 can be removed, and the first spacers 81 are arranged on side walls of the masks 78, the dummy gates 76, and the dummy gate dielectrics 71. In some embodiments, a portion of the second spacer layer 82 above the first spacer layer 80 adjacent to the masks 78, the dummy gates 76, and the dummy gate dielectrics 71 can remain.

[0039] It should be noted that the preceding disclosure generally describes a process for fabricating spacers and LDD regions. Other processes and sequences can be used. For example, fewer or more spacers can be used, other step sequences can be used (e.g., the first spacers 81 can be structured before the deposition of the second spacer layer 82), additional spacers can be fabricated and removed, and / or the like. Furthermore, the n- and p-devices can be fabricated using other structures and steps.

[0040] In the Fig. In embodiments 9A to 9C, first recesses 86 and second recesses 87 are fabricated in the nanostructures 55, the fins 66, and the substrate 50. Epitaxial materials, which can be used as source / drain regions and / or dummy regions, are then fabricated in the first recesses 86 and the second recesses 87. The first recesses 86 can extend through the first nanostructures 52A-52C and the second nanostructures 54A-54C and into the fins 66 and the substrate 50. In some embodiments, the top surfaces of the STI regions 68 can be at the same level as the bottom surfaces of the first recesses 86. In some embodiments, the top surfaces of the STI regions 68 can be located above or below the bottom surfaces of the first recesses 86.The second recesses 87 can extend through the first nanostructures 52A-52C and the second nanostructures 54A-54C and into the fins 66 and the substrate 50 to a depth greater than that of the first recesses 86. The undersides of the second recesses 87 can be located below the undersides of the first recesses 86 and the tops of the STI regions 68.

[0041] The first recesses 86 and the second recesses 87 can be produced by etching the nanostructures 55, the fins 66, and the substrate 50 using anisotropic etching processes such as RIE, NBE, or the like. The first spacers 81, the second spacers 83, and the masks 78 mask portions of the nanostructures 55, the fins 66, and the substrate 50 during the etching processes used to produce the first recesses 86 and the second recesses 87. A single etching process or multiple etching processes can be used to etch each layer of the nanostructures 55, the fins 66, and the substrate 50. With timed etching processes, the etching can be stopped after the first recesses 86 and the second recesses 87 have reached the desired depths.The second recesses 87 can be etched using the same processes as those used to etch the first recesses 86 and for a further etching process before or after the etching of the first recesses 86. In some embodiments, areas corresponding to the first recesses 86 can be masked while the further etching process for the second recesses 87 is carried out.

[0042] In the Fig. In steps 10A to 10C, portions of the sidewalls of the layers of the multilayer stack 64, which were fabricated from the first semiconductor material (e.g., the first nanostructures 52) and which were exposed by the first recesses 86 and the second recesses 87, are etched to create sidewall recesses 88 in the n-region 50N and the p-region 50P. Sidewalls of the first nanostructures 52 adjacent to the sidewall recesses 88 in Fig. Although nanostructures 10C are shown as straight, their sidewalls can also be concave or convex. The sidewalls can be etched using isotropic etching processes, such as wet etching or the like. In an embodiment where the second nanostructures 54 comprise, for example, Si or SiC, and the first nanostructures 52 comprise, for example, SiGe, a wet or dry etching process using hydrogen fluoride, another fluorine-based etchant, or the like can be used to etch the sidewalls of the first nanostructures 52 in the n-region 50N and the p-region 50P.

[0043] In the Fig. In steps 11A to 11D, the first inner spacers 90 are produced in the side wall recess 88. The first inner spacers 90 can be produced by depositing an inner spacer layer (not shown separately) over the area in the Fig. The structures shown in Figures 10A to 10C are fabricated. The first inner spacers 90 act as isolation structure elements between subsequently fabricated source / drain regions and gate structures. As will be discussed in more detail below, the source / drain regions are fabricated in the first recesses 86 and the second recesses 87, while the first nanostructures 52 are replaced with corresponding gate structures.

[0044] The inner spacer layer can be deposited by a conformal deposition process such as CVD, ALD, or the like. The inner spacer layer can be made of a material such as silicon nitride or silicon oxide nitride, although any suitable material, such as materials with low dielectric constants (low-k materials) having a k-value less than approximately 3.5, can be used. The inner spacer layer can then be anisotropically etched to fabricate the first inner spacers 90. While the outer sidewalls of the first inner spacers 90 are shown as flush with the sidewalls of the second nanostructures 54, the outer sidewalls of the first inner spacers 90 can extend beyond the sidewalls of the second nanostructures 54 or be recessed relative to the sidewalls of the second nanostructures 54.

[0045] The outer side walls of the first inner spacers 90 in Fig. Although 11C are shown as straight, the outer side walls of the first inner spacers 90 can also be concave or convex. Fig. Figure 11D, for example, shows an embodiment in which the sidewalls of the first nanostructures 52 are concave, the outer sidewalls of the first inner spacers 90 are concave, and the first inner spacers 90 are recessed relative to the sidewalls of the second nanostructures 54. The inner spacer layer can be etched by an anisotropic etching process, such as RIE, NBE, or the like. The first inner spacers 90 can be used to prevent damage to subsequently fabricated source / drain regions (such as the epitaxial source / drain regions 92, which are described below with reference to the Fig. (discussed in sections 12A to 12E) to prevent damage caused by subsequent etching processes, such as etching processes for manufacturing gate structures.

[0046] In the Fig. In 12A to 12E, epitaxial materials 91 are produced in the second recesses 87, and epitaxial source / drain regions 92 are produced in the first recesses 86 and the second recesses 87. In some embodiments, the epitaxial materials 91 in the second recesses 87 can be sacrificial materials that are later removed to accommodate backside vias (such as the backside vias 130 described below with reference to the Fig. (discussed in sections 26A to 26C). In some embodiments, the epitaxial source / drain regions 92 can apply a mechanical stress to the second nanostructures 54, thereby improving performance.

[0047] As in Fig. As shown in Figure 12C, the epitaxial source / drain regions 92 are fabricated in the first recesses 86 and the second recesses 87 such that each dummy gate 76 is positioned between respective adjacent pairs of epitaxial source / drain regions 92. In some embodiments, the first spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and the first inner spacers 90 are used to separate the epitaxial source / drain regions 92 from the first nanostructures 52 by a suitable lateral distance, so that the epitaxial source / drain regions 92 do not short-circuit with subsequently fabricated gates of the resulting nano-FETs.

[0048] The epitaxial materials 91 can be grown in such a way that the upper surfaces of the epitaxial materials 91 are aligned with the lower surfaces of the first recesses 86 (see Fig. 11A to 11D) and the top surfaces of the STI regions 68 are at the same level. In some embodiments, however, the top surfaces of the epitaxial materials 91 can be arranged above or below the top surfaces of the STI regions 68. The epitaxial materials 91 can be epitaxially grown in the second recesses 87 using a process such as CVD, ALD, VPE, MBE, or the like. The epitaxial materials 91 can comprise any suitable material, such as silicon germanium or the like. The epitaxial materials 91 can be made from materials that exhibit high etch selectivity with respect to materials of the substrate 50, the epitaxial source / drain regions 92, and dielectric layers (such as the STI regions 68 and a dielectric layer 125, which are described below with reference to the Fig. 24A to 24C are discussed). In this respect, the epitaxial materials 91 can be removed and replaced with backside vias without substantially removing the epitaxial source / drain regions 92, the substrate 50, or the STI regions 68.

[0049] The epitaxial source / drain regions 92 in the n-region 50N, e.g., the NMOS region, can be fabricated by masking the p-region 50P, e.g., the PMOS region. The epitaxial source / drain regions 92 are then epitaxially grown in the first recesses 86 and the second recesses 87 in the n-region 50N. The epitaxial source / drain regions 92 can comprise any acceptable material suitable for n-nanoFETs. For example, if the second nanostructures 54 are made of silicon, the epitaxial source / drain regions 92 can comprise materials that impart tensile stress to the second nanostructures 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain regions 92 may have surfaces that are raised above the respective top surfaces of the nanostructures 55 and may have facets.

[0050] The epitaxial source / drain regions 92 in the p-region 50P, e.g., the PMOS region, can be fabricated by masking the n-region 50N, e.g., the NMOS region. The epitaxial source / drain regions 92 are then epitaxially grown in the first recesses 86 and the second recesses 87 in the p-region 50P. The epitaxial source / drain regions 92 can comprise any acceptable material suitable for p-nanoFETs. For example, if the second nanostructures 54 are made of silicon, the epitaxial source / drain regions 92 can comprise materials that exert compressive stress on the second nanostructures 54, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like. The epitaxial source / drain regions 92 may also have surfaces that are raised above the respective top surfaces of the nanostructures 55 and may have facets.

[0051] The epitaxial source / drain regions 92, the first nanostructures 52, the second nanostructures 54, the fins 66, and / or the substrate 50 can be implanted with dopants to fabricate source / drain regions, similar to the process discussed above for fabricating lightly doped source / drain regions, followed by a annealing process. The source / drain regions can have a doping concentration of between approximately 1 × 10 19 atoms / cm² 3 and about 1×10 21 atoms / cm² 3 exhibit. The n- and / or p-doping agents for source / drain regions can be any of the dopants discussed above. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0052] As a result of the epitaxial processes by which the epitaxial source / drain regions 92 are produced in the n-region 50N and the p-region 50P, the top surfaces of the epitaxial source / drain regions 92 exhibit facets that extend laterally outward beyond the side walls of the nanostructures 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same nanoFET to merge, as described by Fig. Figure 12D shows that in some embodiments, adjacent epitaxial source / drain regions 92 remain separated after completion of the epitaxial process, as shown by Fig. 12B is shown. In the Fig. 12B and Fig. In the embodiments shown in Figure 12D, the first spacers 81 can be manufactured such that they extend to the top surfaces of the STI areas 68 and thereby block epitaxial growth. In some embodiments, the spacer etching used to manufacture the first spacers 81 can be adjusted to remove the spacer material, allowing the epitaxially grown area to extend to the surface of the STI area 68.

[0053] The epitaxial source / drain regions 92 can have one or more semiconductor material layers. For example, the epitaxial source / drain regions 92 can have a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers can be used for the epitaxial source / drain regions 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C can be made of different semiconductor materials and can be doped with different doping concentrations. In some embodiments, the first semiconductor material layer 92A can have a doping concentration that is lower than that of the second semiconductor material layer 92B and higher than that of the third semiconductor material layer 92C.In embodiments in which the epitaxial source / drain regions 92 have three semiconductor material layers, the first semiconductor material layer 92A can be deposited, the second semiconductor material layer 92B can be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C can be deposited over the second semiconductor material layer 92B.

[0054] Fig. Figure 12E shows an embodiment in which the side walls of the first nanostructures 52 are concave, the outer side walls of the first inner spacers 90 are concave, and the first inner spacers 90 are recessed relative to the side walls of the second nanostructures 54. As shown in Fig. As shown in Figure 12E, the epitaxial source / drain regions 92 can be made in contact with the first inner spacers 90 and can extend beyond side walls of the second nanostructures 54.

[0055] In the Fig. In 13A to 13C, a first interlayer dielectric (ILD) 96 (ILD: interlayer dielectric) is applied over the respective layer in the Fig. The structure shown in Figures 12A to 12C is deposited. The first ILD 96 can be made from a dielectric material and can be deposited by any suitable process, such as CVD, plasma-enhanced chemical vapor deposition (PECVD), or FCVD. Dielectric materials can be phosphor silicate glass (PSG), borosilicate glass (BSG), boron-doped phosphor silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials produced by a suitable process can be used. In some embodiments, a contact etch stop layer (CESL) 94 is arranged between the first ILD 96 and the epitaxial source / drain regions 92, the masks 78, the first spacers 81, the second spacers 83, and the STI regions 68.The CESL 94 may contain a dielectric material, such as silicon nitride, silicon oxide, silicon oxide nitride or the like, which has a different etch rate than the material of the first ILD 96 located above it.

[0056] In the Fig.In steps 14A to 14C, a planarization process, such as a CMP, can be performed to bring the top surfaces of the first ILD 96 and the CESL 94 to the same level as the top surfaces of the dummy gates 76 or the masks 78. The planarization process can also remove the masks 78 on the dummy gates 76 and portions of the first spacers 81 along the side walls of the masks 78. After the planarization process, the top surfaces of the dummy gates 76, the first spacers 81, the first ILD 96, and the CESL 94 can be at the same level within the process variations. Accordingly, the top surfaces of the dummy gates 76 are exposed by the first ILD 96. In some embodiments, the masks 78 can remain, and in this case, top surfaces of the first ILD 96 are brought to the same level as top surfaces of the masks 78, the first spacers 81 and the CESL 94 by the planarization process.

[0057] In the Fig. In steps 15A to 15C, the dummy gates 76 and the masks 78, if present, are removed in one or more etching steps, producing recesses 98. Portions of the dummy gate dielectrics 71 within the recesses 98 are also removed. In some embodiments, the dummy gates 76 and the dummy gate dielectrics 71 are removed by an anisotropic dry etching process. For example, the etching process may involve a dry etching process using one or more reactive gases, which selectively etches the dummy gates 76 at a higher rate than the first ILD 96, the CESL 94, or the first spacers 81. Each of the recesses 98 exposes portions of nanostructures 55 and / or overlays portions of nanostructures 55 that function as channel regions in subsequently completed nanoFETs. Parts of the nanostructures 55, which function as the channel regions, are arranged between adjacent pairs of the epitaxial source / drain regions 92.During removal, the dummy gate dielectrics 71 can be used as etch stop layers when etching the dummy gates 76. The dummy gate dielectrics 71 can then be removed after the dummy gates 76 have been removed.

[0058] In the Fig. In figures 16A to 16C, the first nanostructures 52 are removed by enlarging the recesses 98. The first nanostructures 52 can be removed by performing an isotropic etching process, such as wet etching or the like, using etchants that are selective towards the materials of the first nanostructures 52, while the second nanostructures 54, the substrate 50, the STI regions 68, the first ILD 96, the CESL 94, the first spacers 81, and the first inner spacers 90 remain relatively unetched compared to the first nanostructures 52. In embodiments where the second nanostructures 54 comprise, for example, Si or SiC, and the first nanostructures 52 comprise, for example, SiGe, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to remove the first nanostructures 52.

[0059] In the Fig. In sections 17A to 17C, dielectric gate layers 100 and gate electrodes 102 for replacement gates are fabricated. The dielectric gate layers 100 are conformally deposited in the recesses 98. The dielectric gate layers 100 can be fabricated on the top, side, and bottom surfaces of the second nanostructures 54. The dielectric gate layers 100 can also be deposited on the top surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the STI regions 68.

[0060] According to some embodiments, the dielectric gate layers 100 comprise one or more dielectric layers, such as an oxide, a metal oxide, the like, or combinations thereof. For example, in some embodiments, the dielectric gate layers 100 may have a silicon oxide layer and a metal oxide layer over the silicon oxide layer. In some embodiments, the dielectric gate layers 100 comprise a high-k dielectric material, and in these embodiments, the dielectric gate layers 100 may have a k-value greater than approximately 7.0, and they may comprise a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the dielectric gate layers 100 may be the same or different in the n-region 50N and the p-region 50P.The manufacturing processes for the dielectric gate layers 100 can include molecular beam deposition (MBD), ALD, PECVD or the like.

[0061] The gate electrodes 102 are deposited over the dielectric gate layers 100 and fill the remaining portions of the recesses 98. The gate electrodes 102 can be made of a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Fig. 17A and Fig. Although single-layer gate electrodes 102 are shown in Figure 17C, for example, the gate electrodes 102 can have any number of coating layers, any number of work function adjustment layers, and a filler material. Any combination of the layers that form the gate electrodes 102 can be deposited between adjacent second nanostructures 54.

[0062] The fabrication of the dielectric gate layers 100 in the n-region 50N and the p-region 50P can be carried out simultaneously, so that the dielectric gate layers 100 in each region are made of the same materials, and the fabrication of the gate electrodes 102 can be carried out simultaneously, so that the gate electrodes 102 in each region are made of the same materials. In some embodiments, the dielectric gate layers 100 in each region can be fabricated using different processes, so that the dielectric gate layers 100 can be made of different materials and / or have a different number of layers, and / or the gate electrodes 102 can be fabricated using different processes in each region, so that the gate electrodes 102 can be made of different materials and / or have a different number of layers.Different masking steps can be used to mask and expose appropriate areas when different processes are used.

[0063] After filling the recesses 98, a planarization process, such as CMP, can be performed to remove excess portions of the dielectric gate layers 100 and the material of the gate electrodes 102, with these excess portions located above the top surfaces of the first ILD 96, the first spacers 81, and the CESL 94. The remaining portions of the material of the gate electrodes 102 and the dielectric gate layers 100 thus form substitute gate structures of the resulting nanoFETs. The gate electrodes 102 and the dielectric gate layers 100 can be collectively referred to as the “gate structures.”

[0064] In the Fig. In steps 18A to 18C, the gate structures (which have the dielectric gate layers 100 and the corresponding gate electrodes 102 located above them) are recessed, creating recesses directly above each of the gate structures and between opposing portions of the first spacers 81. Gate masks 104, having one or more layers of a dielectric material such as silicon nitride, silicon oxide nitride, or the like, are filled into the recesses, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD 96, the CESL 94, and the first spacers 81. Gate contacts produced later (such as the gate contacts 114, which are described below with reference to the Fig. 20A and Fig. 20C will be discussed) penetrate through the gate masks 104 to contact the top of the recessed gate electrodes 102.

[0065] How further through the Fig. As shown in Figures 18A to 18C, a second ILD 106 is deposited over the first ILD 96, the CESL 94, and the gate masks 104. In some embodiments, the second ILD 106 is a flowable layer produced by FCVD. In other embodiments, the second ILD 106 is made from a dielectric material, such as PSG, BSG, BPSG, USG, or the like, and can be deposited by any suitable method, such as CVD, PECVD, or the like.

[0066] In the Fig. In embodiments 19A to 19C, the second ILD 106, the first ILD 96, the CESL 94, and the gate masks 104 are etched to form recesses 108 that expose the surfaces of the epitaxial source / drain regions 92 and / or the gate structures. The recesses 108 can be produced by etching using an anisotropic etching process, such as RIE, NBE, or the like. In some embodiments, the recesses 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; through the gate masks 104 using a second etching process; and through the CESL 94 using a third etching process. A mask, such as a photoresist, can be produced and structured over the second ILD 106 to mask parts of the second ILD 106 from the first etching process and the second etching process.In some embodiments, the etching process may be over-etching, and therefore the recesses 108 may extend into the epitaxial source / drain regions 92 and / or the gate structures. The undersides of the recesses 108 may be at the same level as the tops of the epitaxial source / drain regions 92 and / or the gate structures (e.g., at the same level as the substrate 50 or equidistant from the substrate 50), or lower than the tops of the epitaxial source / drain regions 92 and / or the gate structures (e.g., closer to the substrate 50). Fig. Although in 19C the recesses 108 are shown to expose the epitaxial source / drain regions 92 and the gate structures in the same cross-section, in some embodiments the epitaxial source / drain regions 92 and the gate structures can be exposed in different cross-sections, thereby reducing the risk of short-circuiting subsequently manufactured contacts.

[0067] After the recesses 108 have been produced, initial silicide regions 110 are produced over the epitaxial source / drain regions 92. In some embodiments, the initial silicide regions 110 are produced by first depositing a metal (not shown separately) that can react with the semiconductor materials of the underlying epitaxial source / drain regions 92 (e.g., silicon, silicon-germanium, germanium, or the like) to form silicide or germanide regions. The metal may comprise nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other high-melting-point metals, rare-earth metals, or alloys thereof. The metal can be deposited over the exposed portions of the epitaxial source / drain regions 92, and then a thermal annealing process can be performed to produce the initial silicide regions 110.The non-reacting portions of the deposited metal are then removed, for example, by an etching process. Although the first silicide regions 110 are referred to as silicide regions, they can also be germanide regions or silicon-germanide regions (e.g., regions containing silicon and germanium) or the like. In one embodiment, the first silicide regions 110 contain TiSi and have thicknesses ranging from about 2 nm to about 10 nm.

[0068] In the Fig. In embodiments 20A to 20C, source / drain contacts 112 and gate contacts 114 (also referred to as contact connectors) are manufactured in the recesses 108. The source / drain contacts 112 and the gate contacts 114 can each comprise one or more layers, such as barrier layers, diffusion layers, and conductive filler materials. In some embodiments, for example, the source / drain contacts 112 and the gate contacts 114 each have a barrier layer and a conductive filler material. The source / drain contacts 112 and the gate contacts 114 are each electrically connected to the underlying conductive structural element (e.g., the gate electrodes 102 or the first silicide regions 110 above the epitaxial source / drain regions 92 in the illustrated embodiment).The gate contacts 114 are electrically connected to the gate electrodes 102, and the source / drain contacts 112 are electrically connected to the first silicide regions 110 above the epitaxial source / drain regions 92. The barrier layer can be titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive filler material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, can be performed to remove excess portions of the source / drain contacts 112 and the gate contacts 114, with the excess portions located above the top surfaces of the second ILD 106.

[0069] The Fig. Figures 20A to 20C show a source / drain contact 112 extending to each of the epitaxial source / drain regions 92, but the source / drain contacts 112 can also be omitted for certain epitaxial source / drain regions 92. As discussed below, conductive lines (e.g., busbars) can subsequently be connected through a rear side of one or more of the epitaxial source / drain regions 92. For these specific epitaxial source / drain regions 92, the source / drain contacts 112 can be omitted, or they can be dummy contacts that are not electrically connected to the conductive lines located above them (such as the conductive structural elements 122, which are described below with reference to the Fig. 21A to 21C will be discussed) and connected.

[0070] With the processes of Fig. In stages 2 to 20C, a device layer 109 is fabricated, comprising a plurality of active devices. While the device layer 109 is described as comprising nanoFETs, other embodiments may include device layers 109 comprising other types of transistors, such as planar FETs, FinFETs, thin-film transistors (TFTs), or the like. The device layer may comprise the epitaxial source / drain regions 92, the second nanostructures 54, and the gate structures (comprising the dielectric gate layers 100 and the gate electrodes 102). A first interconnect structure (such as the front-facing interconnect structure 120, described below with reference to the Fig. 21A to 21C) can be fabricated over a front face of the device layer 109, and a second interconnect structure (such as the rear interconnect structure 140, which is discussed below with reference to the Fig. (discussed in sections 27A to 27C) can be produced via a back side of the device layer 109.

[0071] The Fig. Figures 21A to 27C show intermediate steps in the fabrication of front-side and back-side interconnect structures on the device layer 109. The front-side and back-side interconnect structures can each include conductive structural elements that are electrically connected to devices in the device layer 109 (e.g., the nano-FETs). Fig. Figures 21A to 27C with the suffix "A" show a sectional view along line AA'. Fig. 1. Figures ending in "B" show a sectional view along line BB'. Fig. Figures 1 and ending in "C" show a sectional view along line CC'. Fig. 1. The process steps that are described in the Fig. The descriptions in sections 21A to 27C can be applied to both the n-region 50N and the p-region 50P. As noted above, a backside conductive structural element (e.g., a backside via or a busbar) can be electrically connected to one or more of the epitaxial source / drain regions 92. Therefore, the source / drain contacts 112 can optionally be omitted from the epitaxial source / drain regions 92.

[0072] In the Fig. At 21A to 21C, a front-facing interconnect structure 120 is fabricated on the second ILD 106. The front-facing interconnect structure 120 can be described as a front-facing interconnect structure because it is fabricated on a front side of the device layer 109 (e.g., a side of the device layer 109 facing the substrate 50 on which the active devices are fabricated).

[0073] The front-facing interconnect structure 120 can comprise one or more layers of conductive structural elements 122, which are fabricated in one or more dielectric stack layers 124. Each of the dielectric stack layers 124 can comprise a dielectric material, such as a dielectric low-k material, an extremely low-k (ELK) material, or the like. The dielectric layers 124 can be deposited using a suitable process, such as CVD, ALD, PVD, PECVD, or the like.

[0074] The conductive structural elements 122 can include conductive conductors and conductive vias that connect the layers of conductive conductors. The conductive vias can extend through each of the dielectric layers 124 to provide vertical connections between layers of conductive conductors. The conductive structural elements 122 can be fabricated by any suitable process, such as a Damascene process, a dual Damascene process, or the like.

[0075] In some embodiments, the conductive structural elements 122 can be fabricated using a damascene process in which a respective dielectric layer 124 is structured using a combination of photolithography and etching techniques to create grooves corresponding to the desired structure of the conductive structural elements 122. An optional diffusion barrier layer and / or an optional bonding layer can be deposited, and the grooves can then be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide, combinations thereof, or the like, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, cobalt, ruthenium, combinations thereof, or the like.In one embodiment, the conductive structural elements 122 can be produced by depositing a seed layer of copper or a copper alloy and filling the grooves by electroplating. A CMP process or the like can be used to remove excess conductive material from a surface of the respective dielectric layer 124 and to planarize the surfaces of the dielectric layer 124 and the conductive structural elements 122 for subsequent processing.

[0076] The Fig. Figures 21A to 21C show four layers of conductive structural elements 122 and dielectric layers 124 in the front interconnect structure 120. It should be understood, however, that the front interconnect structure 120 can have any number of conductive structural elements 122 arranged in any number of dielectric layers 124. The front interconnect structure 120 can be electrically connected to the gate contacts 114 and the source / drain contacts 112 to form functional circuits. In some embodiments, the functional circuits formed by the front interconnect structure 120 can include logic circuits, memory circuits, image sensor circuits, or the like.

[0077] In the Fig. In steps 22A to 22C, a support substrate 180 is bonded to a top surface of the front interconnect structure 120 by means of a first bond layer 182A and a second bond layer 182B (collectively referred to as bond layers 182). The support substrate 180 can be a glass substrate, a ceramic substrate, a wafer (e.g., a silicon wafer), or the like. The support substrate 180 can provide structural support during subsequent processing steps and in the completed device.

[0078] In various embodiments, the support substrate 180 can be bonded to the front interconnect structure 120 using a suitable process, such as dielectric-dielectric bonding or the like. The dielectric-dielectric bonding process can include the deposition of the first bond layer 182A on the front interconnect structure 120. In some embodiments, the first bond layer 182A comprises silicon oxide (e.g., a high-density plasma oxide (HDP oxide) or the like) deposited by CVD, ALD, PVD, or the like. The second bond layer 182B can also be an oxide layer produced prior to bonding on a surface of the support substrate 180 using, for example, CVD, ALD, PVD, thermal oxidation, or the like. Other suitable materials can be used for the first bonding layer 182A and the second bonding layer 182B.

[0079] The dielectric-dielectric bonding process can further include performing a surface treatment on the first bond layer 182A and / or the second bond layer 182B. This surface treatment can include plasma treatment, which can be performed in a vacuum environment. Following plasma treatment, the surface treatment can further include a cleaning process (e.g., rinsing with demineralized water or the like) performed on one or more of the bond layers 182. The support substrate 180 is then aligned with the front interconnect structure 120, and the two are pressed together to initiate pre-bonding of the support substrate 180 to the front interconnect structure 120. Pre-bonding can be performed at room temperature (e.g., between approximately 21 °C and approximately 25 °C).After pre-bonding, a tempering process can be carried out, for example, by heating the front interconnect structure 120 and the support substrate 180 to a temperature of about 170 °C.

[0080] After the carrier substrate 180 has been bonded to the front-side interconnect structure 120, the following can be done in the Fig. 22A to 22C the device is turned over so that the back side of the device layer 109 faces upwards. The back side of the device layer 109 can refer to a side opposite the front side of the device layer 109.

[0081] In the Fig. In sections 23A to 23C, a thinning process is performed on the back side of the substrate 50. The thinning process may include a planarization process (e.g., mechanical grinding, CMP, or the like), a re-etching process, a combination thereof, or the like. The thinning process may expose surfaces of the epitaxial materials 91 facing the front-side interconnect structure 120. Furthermore, a portion of the substrate 50 may remain above the device layer 109 after the thinning process. As described in the Fig. As shown in Figures 23A to 23C, after the thinning process the back surfaces of the substrate 50, the epitaxial materials 91, the STI areas 68, and the fins 66 can be at the same level. In some embodiments, the fins 66 and the substrate 50 can be removed and replaced by a dielectric material that may be the same as or similar to the material of the second ILD 106.

[0082] In the Fig. In steps 24A to 24C, remaining portions of the fins 66 and the substrate 50 are removed and replaced with a dielectric layer 125. The fins 66 and the substrate 50 can be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. The etching process can be selective with respect to the material of the fins 66 and the substrate 50 (e.g., etching the material of the fins 66 and the substrate 50 at a faster rate than the material of the STI regions 68, the dielectric gate layers 100, the epitaxial source / drain regions 92, the epitaxial materials 91, and the first inner spacers 90).After etching the fins 66 and the substrate 50, surfaces of the STI areas 68, the dielectric gate layers 100, the epitaxial source / drain areas 92, the epitaxial materials 91 and the first internal spacers 90 can be exposed.

[0083] The dielectric layer 125 is then deposited on the back side of the device layer 109 in recesses formed by removing the fins 66 and the substrate 50. The dielectric layer 125 can be deposited over the STI regions 68, the dielectric gate layers 100, the epitaxial source / drain regions 92, the epitaxial materials 91, and the first inner spacers 90. The dielectric layer 125 can physically contact the surfaces of the STI regions 68, the dielectric gate layers 100, the epitaxial source / drain regions 92, the epitaxial materials 91, and the first inner spacers 90. The dielectric layer 125 can be substantially similar to the second ILD 106 described above with reference to the Fig. 18A to 18C. For example, the dielectric layer 125 can be produced from a similar material and using a similar process as the second ILD 106. As described in the Fig. As shown in Figures 24A to 24C, a CMP process or the like can be used to remove material from the dielectric layer 125 such that the top surfaces of the dielectric layer 125 are at the same level as the top surfaces of the STI areas 68 and the epitaxial materials 91. In some embodiments, the substrate 50 and the fins 66 can be left untouched or replaced by the dielectric layer 125 and can remain as part of the device layer 109.

[0084] In the Fig. In steps 25A to 25C, the epitaxial materials 91 are removed to form recesses 128, and second silicide regions 129 are produced in the recesses 128. The epitaxial materials 91 can be removed by a suitable etching process, which may be an isotropic etching process, such as a wet etching process. The etching process can exhibit high etch selectivity towards the epitaxial materials 91. Therefore, the epitaxial materials 91 can be removed without substantially removing materials of the dielectric layer 125, the STI regions 68, or the epitaxial source / drain regions 92. The recesses 128 can expose sidewalls of the STI regions 68, backsides of the epitaxial source / drain regions 92, and sidewalls of the dielectric layer 125.

[0085] Second silicide regions 129 can then be produced in the recesses 128 on the back sides of the epitaxial source / drain regions 92. The second silicide regions 129 can be added to the first silicide regions 110 described above with reference to the Fig. The silicide ranges described in sections 19A to 19C may be similar. For example, the second silicide ranges 129 can be produced using a similar material and process as the first silicide ranges 110.

[0086] In the Fig. In components 26A to 26C, backside vias 130 are created in the recesses 128. The backside vias 130 can extend through the dielectric layer 125 and the STI regions 68 and can be electrically connected to the epitaxial source / drain regions 92 via the second silicide regions 129. The backside vias 130 can be connected to the source / drain contacts 112, which were described above with reference to the Fig. The processes described in sections 20A to 20C may be similar. For example, the backside vias 130 can be manufactured using a similar material and process as the source / drain contacts 112. The backside vias 130 may be made of copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, ruthenium, or the like. A planarization process, such as CMP, can be performed to remove excess portions of the backside vias 130, such excess portions being located above the top surfaces of the STI areas 68 and the dielectric layer 125.

[0087] In the Fig. In sections 27A to 27C, remaining parts of a backside interconnect structure 140 are fabricated across the backside vias 130, the dielectric layer 125, and the STI areas 68. The backside interconnect structure 140 can be described as a backside interconnect structure because it is fabricated on the back side of the device layer 109 (e.g., a side of the device layer 109 facing the side of the device layer 109 on which active devices are fabricated). The backside interconnect structure 140 comprises conductive traces 132, a dielectric layer 134, conductive structural elements 136, dielectric layers 137, a redistribution layer 138, and a passivation layer 139. The dielectric layer 134 can be fabricated using materials and methods described above with reference to the Fig. Materials and methods described in sections 18A to 18C for the second ILD 106 are the same or similar.

[0088] The conductive lines 132 are fabricated in the dielectric layer 134. Fabricating the conductive lines 132 can involve structuring recesses in the dielectric layer 134, for example, using a combination of photolithography and etching processes. A structure of the recesses in the dielectric layer 134 can correspond to a structure of the conductive lines 132. The conductive lines 132 are then fabricated by depositing a conductive material in the recesses. In some embodiments, the conductive lines 132 have a metal layer, which can be a single layer or a composite layer comprising multiple sublayers made of different materials. In some embodiments, the conductive lines 132 have copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, or the like.An optional diffusion barrier layer and / or an optional adhesive layer can be deposited before the recesses are filled with the conductive material. Suitable materials for the barrier / adhesive layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide, or the like. The conductive lines 132 can be fabricated using, for example, CVD, ALD, PVD, plating, or the like. The conductive lines 132 are electrically connected to the epitaxial source / drain regions 92 via the backside vias 130 and the secondary silicide areas 129. A planarization process (e.g., CMP, grinding, etching, or the like) can be performed to remove excess portions of the conductive lines 132 that have been fabricated over the dielectric layer 134.

[0089] In some embodiments, the conductive lines 132 are rear-side busbars, which are conductive lines that electrically connect the epitaxial source / drain regions 92 to a reference voltage, a supply voltage, or the like. Advantages can be gained by placing the busbars on the rear side of the semiconductor die instead of on the front side. For example, the gate density of the nanoFETs and / or the interconnect density of the front-side interconnect structure 120 can be increased. Furthermore, wider busbars can be accommodated on the rear side of the semiconductor die, thereby reducing resistance and increasing the efficiency of the power supply to the nanoFETs. For example, the width of the conductive lines 132 can be at least twice the width of conductive first-level lines (e.g., of the conductive structural elements 122) of the front-side interconnect structure 120.

[0090] The remainder of the backside interconnect structure 140 can be similar to the frontside interconnect structure 120. For example, the backside interconnect structure 140 can be fabricated using materials and processes that are the same as or similar to those used for the frontside interconnect structure 120. The backside interconnect structure 140 can have stacked layers of conductive structural elements 136 fabricated in dielectric stacked layers 137. The conductive structural elements 136 can have conductive traces (e.g., for routing to and from subsequently fabricated contact pads and conductive connecting elements, such as external connecting elements). The conductive structural elements 136 can have conductive vias extending into the dielectric layers 137 to provide a vertical connection between stacked layers of the conductive traces.The conductive structural elements 136 can include one or more embedded passive devices, such as resistors, capacitors, inductors, or the like. The embedded passive devices can be integrated into the conductive traces 132 (e.g., the busbar) to provide circuits (e.g., power circuits) on the back side of the nanoFETs.

[0091] The redistribution layer 138 and the passivation layer 139 are produced over the conductive structural elements 136 and the dielectric layers 137. The passivation layer 139 can comprise polymers such as PBO, polyimide, BCB, or the like. In some embodiments, the passivation layer 139 can comprise inorganic dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxide nitride, or the like. The passivation layer 139 can be deposited, for example, by CVD, PVD, ALD, or the like.

[0092] The redistribution layer 138 is manufactured through the passivation layer 139 up to the conductive structural elements 136. In some embodiments, the redistribution layer 138 can be used to provide input / output connections to other electrical components, such as other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, or the like. The redistribution layer 138 can be described as rear-side input / output pads that can provide signal, supply voltage, and / or ground connections to the nanoFETs. The redistribution layer 138 can be used to provide a heat dissipation path from the device layers 109 through the rear-side interconnect structure 140.The redistribution layer 138 may have one or more layers of copper, nickel, gold or the like, which may be produced by a plating process or the like.

[0093] As will be discussed below, the structure of the Fig. 27A to 27C may be part of a device die. Fig. Figure 27C, for example, shows a region 181 of a device die 200, which is located in Fig. Figure 28 is shown and discussed below. The device-Die 200 can be used for a majority of the structures of the Fig. 27A to 27C, which are arranged in a horizontal plane.

[0094] The Fig. 28, Fig. 29, Fig. 30, Fig. 31, Fig. 32, Fig. 33, Fig. 34, Fig. 35, Fig. 36, Fig. 37, Fig. 38, Fig. 39, Fig. 40, Fig. 41, Fig. 42 to Fig. Figure 43 shows embodiments in which heat dissipation structures include a thermally conductive cap 212 (shown in the Fig. 30, Fig. 31, Fig. 32, Fig. 33, Fig. 34, Fig. 35, Fig. 36, Fig. 37, Fig. 38, Fig. 39, Fig. 40, Fig. 41, Fig. 42 to Fig. 43) which is provided via an auxiliary die 210 attached to the front interconnect structure 120. The thermally conductive cap 212 is an example of a conductive cap heat spreader located in a device die 200 (e.g., a device die with nano-FETs manufactured according to the processes of Fig. The auxiliary die 210 is an example of a front-facing heat distributor that dissipates heat generated in the device die 200. The thermally conductive cap 212 and the auxiliary die 210 are thermally connected to each other and to the device die 200. By providing the thermally conductive cap 212 and the auxiliary die 210 above the device die 200, heat dissipation from the device die 200 is improved. This improves device performance and reduces device failures caused by heat generated in the device die 200.

[0095] In Fig. 28 A device die 200 is attached to a support substrate 202 by means of a release layer 204. With the processes of Fig. 2 to 27C are used to manufacture connected devices that are integrated into the device die 200. The device die 200 can have a plurality of the structures that are in the Fig. 27A to 27C are shown and are arranged horizontally adjacent to each other. Fig. Figure 27C, for example, shows a detailed view of area 181 of the device die 200. Fig. 28. In some embodiments, the device die 200 can be a busbar die comprising the front interconnect structure 120 over a front side of the device layer 109 and the rear interconnect structure 140 over a back side of the device layer 109.

[0096] In Fig. Figure 28 shows an uppermost of the dielectric layers 124 such that it covers an uppermost layer of the conductive structural elements 122; however, in some embodiments, the upper surfaces of the uppermost dielectric layer 124 and the upper surfaces of the uppermost layer of the conductive structural elements 122 may be at the same level. The device layer 109 is shown to comprise the substrate 50; however, the substrate 50 may be replaced by the dielectric layer 125. Fig. Figure 28 shows a simplified view in which certain structural elements of the preceding figures have been omitted or changed for the sake of clarity.

[0097] The device die 200 is attached to the support substrate 202 by means of the release layer 204. The support substrate 202 can be a glass substrate, a ceramic substrate, a wafer (e.g., a silicon wafer), or the like. The support substrate 202 can provide structural support during subsequent processing steps. The release layer 204 can be made of a polymer-based material that can be removed along with the support substrate 202 from the structures fabricated over it in later steps. In some embodiments, the release layer 204 is a heat-removable, epoxy-based material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release layer.In some embodiments, the release layer 204 can be an ultraviolet adhesive (UV adhesive) that loses its adhesive strength when irradiated with UV light. The release layer 204 can be dispersed and cured as a liquid, or it can be a laminate layer with which the support substrate 202 is coated, or the like. The top surface of the release layer 204 can be leveled and can have a high degree of planarity. The device die 200 can be turned over, and the rear interconnect structure 140 can be attached to the support substrate 202 by means of the release layer 204.

[0098] The support substrate is unbonded to separate (or "unbond") the support substrate 180 from the front interconnect structure 120. In some embodiments, unbonding involves projecting light, such as laser light or ultraviolet (UV) light, onto the bonding layers 182, so that the bonding layers 182 degrade due to the heat of the light and the support substrate 180 can be removed. A major surface of the dielectric layer 124, or surfaces of the dielectric layer 124 and the conductive structural elements 122, may be exposed after the support substrate 180 and the bonding layers 182 have been removed.

[0099] In Fig. In Figure 29, an auxiliary die 210 is attached to the device die 200. The auxiliary die 210 is a rigid structure that is attached to the device die 200 to provide structural or mechanical stability and heat dissipation. The auxiliary die 210 can be bonded to a top surface of the front interconnect structure 120 of the device die 200 by means of a first bond layer 206A and a second bond layer 206B (collectively referred to as bond layers 206). The auxiliary die 210 is thermally connected to the device die 200 by means of the bond layers 206. The auxiliary die 210 can have a substrate with high thermal conductivity that is used as part of a heat dissipation structure and conducts heat away from the device die 200. In some embodiments, the auxiliary die 210 can have silicon, silicon carbide, aluminum nitride, or the like. In some embodiments, the auxiliary die 210 can be an empty die, as in Fig. Figure 29 shows an example. In some embodiments, the auxiliary die 210 can include active or passive devices, various conductive structural elements such as metal pillars, interconnect structures, vias, other thermally conductive structural elements, or the like. The auxiliary die 210 can have a thickness T1 in the range of approximately 25 µm to approximately 775 µm. By providing the auxiliary or support substrate 210 with a thickness in the specified range, sufficient heat dissipation is provided without unduly increasing the thickness of the packaged or encapsulated semiconductor device containing the auxiliary die 210. The auxiliary die 210 can be integrated to improve the structural and mechanical stability of the packaged semiconductor device while simultaneously providing improved heat dissipation from the device die 200.This improves the device performance and reduces device errors caused by heat generated in the device die 200.

[0100] The auxiliary die 210 can be bonded to the front interconnect structure 120 of the device die 200 using a suitable method, such as dielectric-dielectric bonding or the like. The dielectric-dielectric bonding process can include the deposition of the first bond layer 206A on the front interconnect structure 120. In some embodiments, the first bond layer 206A comprises silicon oxide (e.g., a high-density plasma oxide (HDP oxide) or the like) deposited by CVD, ALD, PVD, or the like. The second bond layer 206B can similarly comprise an oxide layer produced on a surface of the auxiliary die 210 prior to bonding, for example, by CVD, ALD, PVD, thermal oxidation, or the like. Other suitable materials can be used for the first bonding layer 206A and the second bonding layer 206B.The dielectric-dielectric bonding process can be described with reference to the . Fig. 22A to 22C are identical or similar to the dielectric-dielectric bonding process discussed above.

[0101] In Fig. In 29, an insulating layer 208 is further produced over the auxiliary die 210. The insulating layer 208 can comprise polymers such as PBO, polyimide, BCB, or the like. In some embodiments, the insulating layer 208 can comprise inorganic dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxide nitride, or the like. The insulating layer 208 can be deposited, for example, by CVD, PVD, ALD, or the like.

[0102] In Fig. In section 30, a thermally conductive cap 212 is fabricated over the insulating layer 208. The thermally conductive cap 212 can be a structure with high thermal conductivity, serving as a heat dissipation structure to conduct heat away from the device die 200. The thermally conductive cap 212 can be thermally connected to the device die 200 via the auxiliary die 210. The insulating layer 208 can be integrated to electrically isolate the thermally conductive cap 212 from the device die 200, so that the thermally conductive cap 212 is electrically floating (i.e., has no electrical connection to any electrical signals).

[0103] The fabrication of the thermally conductive cap 212 comprises the following: depositing a passivation material 218 over the insulating layer 208, structuring the passivation material 218 to create an opening that exposes the insulating layer 208, depositing a seed layer 214 in the opening, and depositing a conductive filler material 216 over the seed layer 214 and filling the opening. The passivation material 218 may comprise polymers, such as PBO, polyimide, BCB, or the like. In some embodiments, the passivation material 218 may comprise inorganic dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxide nitride, or the like. The passivation material 218 may be deposited, for example, by CVD, PVD, ALD, or the like. The passivation material 218 may be structured using a combination of photolithography and etching processes.

[0104] The thermally conductive cap 212 comprises the seed layer 214 and the conductive filler material 216. The seed layer 214 can be a metal layer, which may be a single layer or a composite layer comprising multiple sublayers made of different materials. In some embodiments, the seed layer 214 comprises a titanium layer and a copper layer over the titanium layer. The seed layer 214 can be produced, for example, by physical vapor deposition (PVD) or the like. The conductive filler material 216 can be produced over the seed layer 214 by plating, e.g., electroplating or electroless plating or the like. The conductive filler material 216 can comprise copper, nickel, another metal, a metal alloy, or the like. A planarization process (e.g.,A CMP (chemical machining), grinding, or etching process, or the like, can be performed to remove excess portions of the thermally conductive cap 212 that have been fabricated over the passivation material 218. The thermally conductive cap 212 can have a thickness T2 in the range of about 1 µm to about 50 µm. The ratio of thickness T2 to thickness T1 can be in the range of about 10% to about 60%. By providing the thermally conductive cap 212 with a thickness in the specified range, sufficient heat dissipation is provided without unduly increasing the thickness of the packaged semiconductor device containing the thermally conductive cap 212. The device die 200, the auxiliary die 210, and the thermally conductive cap 212 collectively form a die structure 300.The thermally conductive cap 212 can be thermally connected to the device die 200 via the auxiliary die 210 and electrically insulated from the device die 200 by the auxiliary die 210 and the insulating layer 208. The thermally conductive cap 212 can be integrated to provide better heat dissipation from the device die 200. This improves device performance and reduces device failures caused by heat generated in the device die 200.

[0105] In Fig. 31 The die structure 300 is turned over, attached to a support substrate 220, and vias 226 are made over the support substrate 220. The die structure 300 can be attached to the support substrate 220 with an adhesive 224 applied to the thermally conductive cap 212 and the passivation material 218, and a release layer 222 attached to the support substrate 220.

[0106] The support substrate 220 can be a glass substrate, a ceramic substrate, a wafer (e.g., a silicon wafer), or the like. The support substrate 220 can provide structural support during subsequent processing steps. The release layer 222 can be made of a polymer-based material that can be removed along with the support substrate 220 from the structures fabricated above it in later steps. In some embodiments, the release layer 222 is a heat-removable, epoxy-based material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release layer. In some embodiments, the release layer 222 can be an ultraviolet (UV) adhesive that loses its adhesive properties when irradiated with UV light.The release layer 222 can be distributed as a liquid and cured, or it can be a laminate layer with which the support substrate 220 is coated, or the like. The top surface of the release layer 222 can be leveled and can have a high degree of planarity. The die structure 300 can be turned over, and the thermally conductive cap 212 and the passivation material 218 can be attached to the support substrate 220 by means of the release layer 222.

[0107] The die structure 300 can be bonded to the support substrate 220 using the adhesive 224. The adhesive 224 is applied to the undersides of the thermally conductive cap 212 and the passivation material 218, and the die structure 300 is bonded to the support substrate 220 using this adhesive. The adhesive 224 can be any suitable adhesive, epoxy, die attach film (DAF), or the like. The adhesive 224 can be applied to the undersides of the thermally conductive cap 212 and the passivation material 218, applied over the surface of the support substrate 220, or the like.

[0108] The vias 226 are fabricated on the release layer 222 and extend away from the substrate 220. To fabricate the vias 226, a seed layer (not shown separately) is produced, for example, over the release layer 222. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising multiple sublayers made of different materials. In one particular embodiment, the seed layer has a titanium layer and a copper layer over the titanium layer. The seed layer can be fabricated using, for example, PVD or the like. A photoresist is fabricated and patterned on the seed layer. The photoresist can be produced by spin deposition or the like and exposed to light for patterning. The structure of the photoresist corresponds to the conductive vias.Structuring creates openings through the photoresist to expose the seed layer. A conductive material is then fabricated within these openings and on the exposed portions of the seed layer. This conductive material can be produced by plating, such as electroplating or electroless plating. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, or similar. The photoresist and any portions of the seed layer where the conductive material has not been fabricated are then removed. The photoresist can be removed using a suitable stripping or removal technique, such as oxygen plasma. After the photoresist has been removed, the exposed portions of the seed layer are then removed using a suitable etching process, such as wet or dry etching.The remaining parts of the seed layer and the conductive material form the vias 226.

[0109] The support substrate is unbonded to detach (or "unbond") the support substrate 202 from the rear interconnect structure 140. In some embodiments, unbonding involves projecting light, such as laser light or ultraviolet (UV) light, onto the release layer 204, causing the release layer 204 to decompose due to the heat of the light and allowing the support substrate 202 to be removed. The surfaces of the passivation layer 139 and the redistribution layer 138 may be exposed after the removal of the support substrate 202 and the release layer 204.

[0110] In Fig. 32 An encapsulation material 228 is produced on and around the various components. For example, the encapsulation material 228 can be produced on the vias 226, on the release layer 222 over the support substrate 220, and on and around the vias 226 and the die structure 300. After production, the encapsulation material 228 encapsulates the vias 226 and the die structure 300. The encapsulation material 228 can be a molding compound, an epoxy, or the like. The encapsulation material 228 can be applied by compression molding, heat pressing, or the like, and can be produced over the support substrate 220 in such a way that the vias 226 and / or the die structure 300 are buried or covered. The encapsulation material 228 can be applied in a liquid or semi-liquid form and then hardened.The top surfaces of the encapsulation material 228 can be aligned with the top surfaces of the vias 226. The vias 226 can be referred to as form vias.

[0111] In Fig. 32 A planarization process is further performed on the encapsulation material 228 to expose the vias 226 and the die structure 300. The planarization process can also remove material from the vias 226, the redistribution layer 138, and / or the passivation layer 139 until the redistribution layer 138, the vias 226, and the passivation layer 139 are exposed. After the planarization process, the top surfaces of the vias 226, the redistribution layer 138, the passivation layer 139, and the encapsulation material 228 are essentially coplanar within the process variations. The planarization process can be, for example, a CMP, a grinding process, or the like. In some embodiments, the planarization can be omitted, for example, if the vias 226 and / or the redistribution layer 138 are already exposed.

[0112] In Fig. A redistribution structure 230 is fabricated over the encapsulation material 228, the vias 226, the redistribution layer 138, and the passivation layer 139. The redistribution structure 230 can be similar to the front interconnect structure 120 and the back interconnect structure 140. For example, the redistribution structure 230 can be fabricated using materials and processes that are identical or similar to those used for the front interconnect structure 120 and the back interconnect structure 140. The redistribution structure 230 can include stacked layers of conductive structural elements 232 fabricated in dielectric stacked layers 234. The conductive structural elements 232 can include conductive traces (e.g., for routing to and from subsequently fabricated contact pads and conductive interconnects).The conductive structural elements 232 can have conductive vias extending into the dielectric layers 234 to establish a vertical connection between stacked layers of the conductive conductors. The conductive structural elements 232 can have one or more embedded passive devices, such as resistors, capacitors, inductors, or the like. The embedded passive devices can be integrated into the die structure 300 to provide circuits.

[0113] In Fig. In the following embodiments, a passivation layer 236, contact bumps (UBMs) 238 (UBM: underbump metallization), and conductive connecting elements 240 (also referred to as external connecting elements) are produced over the redistribution structure 230. The passivation layer 236 can comprise polymers such as PBO, polyimide, BCB, or the like. In some embodiments, the passivation layer 236 can comprise inorganic dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxide nitride, or the like. The passivation layer 236 can be deposited by CVD, PVD, ALD, or the like.

[0114] The UBMs 238 are fabricated through the passivation layer 236 up to the conductive structural elements 232 in the redistribution structure 230. The conductive connecting elements 240 are fabricated on the UBMs 238. The UBMs 238 may have one or more layers of copper, nickel, gold, or the like, fabricated by a plating process or the like. The conductive connecting elements 240 (e.g., solder balls) are fabricated on the UBMs 238. Fabricating the conductive connecting elements 240 may involve placing solder balls on the exposed portions of the UBMs 238 and then melting the solder balls. In some embodiments, fabricating the conductive connecting elements 240 involves performing a plating step to fabricate solder areas over the uppermost conductive structural elements 232 and then melting the solder areas.The UBMs 238 and the conductive connectors 240 can be used to provide input / output connections to other electrical components, such as other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, or the like. The UBMs 238 and the conductive connectors 240 can also be configured as rear-facing input / output pads that provide signal, supply voltage, and / or ground connections to the nanoFETs described above.

[0115] The UBMs 238 and the conductive interconnects 240 can be thermally connected to the rear interconnect structure 140 via the redistribution structure 230. Consequently, the redistribution structure 230 can improve heat dissipation away from the active devices in the device die 200 through the rear interconnect structure 140 to the outside of a packaged semiconductor device. The die structure 300, the encapsulation material 228, the vias 226, the redistribution structure 230, the passivation layer 236, the UBMs 238, and the conductive interconnects 240 collectively form a first package component 350.

[0116] In Fig. 35 The first package component 350 is turned over; the support substrate 220 is removed; a passivation layer 242 is formed over the encapsulation material 228, the vias 226, and the die structure 300; and a second package component 360 is joined to the first package component 350. Unbonding of the support substrate is performed to separate (or "unbond") the support substrate 220 from the encapsulation material 228, the vias 226, and the adhesive 224. In some embodiments, unbonding involves projecting light, such as laser light or ultraviolet (UV) light, onto the release layer 222, so that the release layer 222 decomposes due to the heat of the light and the support substrate 220 can be removed. The surfaces of the encapsulation material 228, the vias 226 and the adhesive 224 can be exposed after removal of the support substrate 220 and the release layer 222.A top surface of the adhesive 224 can be aligned with top surfaces of the encapsulation material 228.

[0117] The passivation layer 242 can be produced on the encapsulation material 228, the vias 226, and the adhesive 224. The passivation layer 242 can be produced in contact with the encapsulation material 228, the vias 226, and the adhesive 224. In some embodiments, the passivation layer 242 is produced from a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In some embodiments, the passivation layer 242 is produced from a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. The passivation layer 242 can be produced by any suitable deposition process, such as spin deposition, CVD, lamination, or a combination thereof.

[0118] Conductive interconnects 244 are manufactured such that they extend through the passivation layer 242 to contact the vias 226. Openings are created through the passivation layer 242 to expose portions of the vias 226. The openings can be created, for example, by laser drilling, etching, or the like. The conductive interconnects 244 are formed in the openings. The conductive interconnects 244 may contain flux and can be manufactured in a flux dipping process. In some embodiments, the conductive interconnects 244 contain a conductive paste, such as solder paste, silver paste, or the like, and are dispensed in a printing process.In some embodiments, the conductive connectors 244 can be manufactured in a similar manner to the conductive connectors 240 and can be made from a similar material. The conductive connectors 244 can be used to bond the second package component 360 to the first package component 350.

[0119] The second package component 360 can comprise a substrate 248 and one or more stacks of stack dies 362 (e.g., a first stack die 362A and a second stack die 362B) connected to the substrate 248. Fig. Figure 35 shows a stack of stack dies 362 (362A and 362B), but in some embodiments, a plurality of stacks of stack dies 362 (each with one or more stack dies) can be arranged side by side and connected to the same surface of the substrate 248. The substrate 248 can be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, composite materials such as silicon-germanium, silicon carbide, gallium arsenic, indium arsenic, indium phosphide, silicon-germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like can be used. Furthermore, the substrate 248 can be a silicon-on-insulator (SOI) substrate.In general, an SOI substrate comprises a layer of a semiconductor material, such as epitaxial silicon, germanium, silicon-germanium, SOI, silicon-germanium-on-insulator (SGOI), or combinations thereof. In some embodiments, the substrate 248 is based on an insulating core, such as a glass fiber-reinforced resin core. The core material may be a glass fiber resin, such as FR4. In some embodiments, the core material may comprise bismaleimide triazine resin (BT resin), other printed circuit board materials or layers, or the like. Build-up layers, such as an Ajinomoto build-up layer (ABF) or other laminates, may also be used for the substrate 248. The substrate 248 may incorporate active and passive devices (not shown separately).A wide variety of devices, such as transistors, capacitors, resistors, combinations thereof, and the like, can be used to meet the structural and functional design requirements of the second package component, 360. These devices can be manufactured using appropriate methods.

[0120] The substrate 248 can have 250 metallization layers (not shown separately) in addition to conductive vias. The metallization layers can be fabricated over the active and passive devices and are designed to connect the various devices to form functional circuits. The metallization layers can be made of alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias connecting the conductive material layers. The metallization layers can be fabricated by a suitable process (such as a Damascene process, a dual-Damascene process, or the like). In some embodiments, the substrate 248 is essentially free of active and passive devices.

[0121] The substrate 248 can have the following: bond pads 252 on a first side of the substrate 248, which connect to the stack dies 362, and bond pads 246 on a second side of the substrate 248, the second side being opposite the first side of the substrate 248 to connect to the conductive connecting elements 244. In some embodiments, the bond pads 246 and the bond pads 252 are produced by creating recesses (not shown separately) in the dielectric layers (not shown separately) on the first and second sides of the substrate 248. The recesses can be produced such that the bond pads 246 and the bond pads 252 can be embedded in the dielectric layers. In some embodiments, the recesses are omitted, and the bond pads 246 and the bond pads 252 can be produced on the dielectric layer.In some embodiments, the bond pads 246 and the bond pads 252 have a thin seed layer (not shown separately) made of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive material of the bond pads 246 and the bond pads 252 can be deposited over the thin seed layer. The conductive material can be produced by an electrochemical plating process, a currentless plating process, CVD, ALD, PVD, the like, or a combination thereof. In some embodiments, the conductive material of the bond pads 246 and the bond pads 252 is copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.

[0122] In some embodiments, the bond pads 246 and the bond pads 252 are UBMs comprising three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. Other arrangements of materials and layers, such as a chromium / chromium-copper alloy / copper / gold arrangement, a titanium / titanium-tungsten / copper arrangement, or a copper / nickel / gold arrangement, can also be used to fabricate the bond pads 246 and the bond pads 252. In some embodiments, the conductive vias 250 extend through the substrate 248 and connect at least one of the bond pads 246 to at least one of the bond pads 252.

[0123] In the illustrated embodiment, the stacked dies 362 are connected to the substrate 248 by wire bonds 256, although other connections, such as conductive bumps, can also be used. In some embodiments, the stacked dies 362 are stacked memory dies. The stacked dies 362 can, for example, comprise low-power (LP) double data rate (DDR) memory modules, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or similar memory modules. The stacked dies 362 and the wire bonds 256 can be encapsulated with a molding material 254. The molding material 254 can be applied to the stacked dies 362 and the wire bonds 256 by compression molding. In some embodiments, the molding material 254 is a molding compound, a polymer, an epoxy, a silicon oxide filler, the like, or a combination thereof. A hardening process can be carried out to harden the molding material 254.The curing process can be thermal curing, UV curing, the like, or a combination thereof. After curing the mold material 254, a planarization step, such as grinding, is performed to remove excess parts of the mold material 254 and provide an essentially planar surface for the second package component 360.

[0124] After the second package component 360 has been fabricated, it is mechanically and electrically bonded to the first package component 350 by means of the conductive connectors 244, the bond pads 246, and the vias 226. In some embodiments, the stacked dies 362 can be connected to the device die 200 by means of the wire bond connections 256, the bond pads 252, the conductive vias 250, the bond pads 246, the conductive connectors 244, the vias 226, the redistribution structure 230, and the rear interconnect structure 140. In some embodiments, a solder resist (not shown separately) is fabricated on the side of the substrate 248 facing the stacked dies 362. The conductive connecting elements 144 can be arranged in openings in the solder resist to be electrically and mechanically connected to conductive structural elements (e.g.to be connected to the bond pads 246 in the substrate 248. The solder resist can be used to protect areas of the substrate 248 from external damage. In some embodiments, the conductive connecting elements 244 have an epoxy flux (not shown) that is applied to them before they are melted with at least a portion of the epoxy flux remaining after the second package component 360 has been attached to the first package component 100.

[0125] An underfill 258 is produced between the first package component 350 and the second package component 360, surrounding the conductive connecting elements 244. The underfill can reduce mechanical stresses and protect the connection points created by the melting of the conductive connecting elements 244. The underfill 258 can be produced by a capillary flow process after the second package component 360 has been attached, or it can be produced by a suitable deposition process before the second package component 360 is attached. In embodiments where the epoxy flux is applied, it can act as the underfill 258. The first package component 350, the second package component 360, and the intermediate structures used to connect the second package component 360 to the first package component 350 (e.g.,the passivation layer 242, the conductive connecting elements 244, the underfill 258), collectively form a packaged semiconductor device 600.

[0126] The auxiliary die 210 and the thermally conductive cap 212 are heat dissipation structures fabricated on the front face of the device die 200. The auxiliary die 210 can be described as a front-facing heat distributor. The thermally conductive cap 212 can be described as a conductive cap heat distributor. The auxiliary die 210 and the thermally conductive cap 212 are thermally connected to the device die 200 and improve heat dissipation from the device die 200. This improves device performance and reduces device failures caused by heat generated in the device die 200. The auxiliary die 210 also improves the structural and mechanical stability of the first package component 350.

[0127] The Fig. 36, Fig. 37, Fig. 38, Fig. 39, Fig. 40, Fig. 41, Fig. 42 to Fig. Figure 43 shows various configurations of the thermally conductive cap 212 according to some embodiments. Fig. 36, Fig. 37, Fig. 38 to Fig. 39 show sectional views, while the Fig. 40, Fig. 41, Fig. 42 to Fig. 43 top-down views are shown. Various structural elements, such as the vias 226, are shown in the Fig. 40, Fig. 41, Fig. 42 to Fig. 43 has been omitted for the sake of simplicity and clarity. Fig. Figure 36 shows an embodiment in which the thermally conductive cap 212 is produced before the passivation material 218 is manufactured. As in Fig. As shown in Figure 36, side surfaces of the conductive filler material 216 can be aligned with side surfaces of the seed layer 214 and side surfaces of the conductive filler material 216, and the seed layer 214 can be in contact with the passivation material 218.

[0128] Fig. Figure 37 shows an embodiment in which the thermally conductive cap 212 is produced and the passivation material 218 is omitted. As in Fig. As shown in Figure 37, side surfaces of the conductive filler material 216 and the seed layer 214 can be aligned with side surfaces of the insulating layer 208, and side surfaces of the conductive filler material 216 and the seed layer 214 can be in contact with the encapsulation material 228. The thermally conductive cap 212 can be thermally connected to the device die 200 and electrically isolated from the device die 200. In some embodiments, the thermally conductive cap 212 can be electrically floating. By omitting the passivation material 218, the machining steps and the cost of manufacturing the thermally conductive cap 212 can be reduced, while still providing better heat dissipation from the thermally conductive cap 212 and the auxiliary die 210.

[0129] Fig. Figure 38 shows an embodiment in which the thermally conductive cap 212 protrudes from the encapsulation material 228 and the adhesive 224 is omitted. As in Fig. As shown in Figure 36, side faces of the conductive filler material 216 can be aligned with side faces of the seed layer 214, and side faces of the conductive filler material 216 and the seed layer 214 can be in contact with the passivation material 218. Top faces of the vias 226 can be at the same level as top faces of the encapsulation material 228, top faces of the passivation material 218 can be at the same level as top faces of the conductive filler material 216, and the top faces of the passivation material 218 and the conductive filler material 216 can be arranged above the top faces of the vias 226 and the encapsulation material 228. In some embodiments, the vias 226 can also protrude from the encapsulation material 228 and can be at the same level as the top faces of the conductive filler material 216 and / or the passivation material 218.A first planarization process, such as CMP, can be performed after the fabrication of the encapsulation material 228 to expose the top surfaces of the vias 226 and the thermally conductive cap 212. Subsequently, one or more wet etching processes can be performed, exhibiting high etch selectivity between the encapsulation material 228 and the vias 226 and / or the thermally conductive cap 212, causing the thermally conductive cap 212 and / or the vias 226 to protrude from the back surface of the encapsulation material 228, as shown in [Figure]. Fig. Figure 38 shows that the thermally conductive cap 212 can be thermally connected to the device die 200 and electrically isolated from it. In some embodiments, the thermally conductive cap 212 can be electrically floating. By positioning the thermally conductive cap 212 to protrude from the back side of the encapsulation material 228, improved heat dissipation can be provided while reducing the thickness of the packaged semiconductor device.

[0130] Fig. Figure 39 shows an embodiment in which the thermally conductive cap 212 is produced and the passivation material 218 is omitted. As in Fig. As shown in Figure 39, side surfaces of the conductive filler material 216 can be aligned with side surfaces of the seed layer 214, and side surfaces of the conductive filler material 216 and the seed layer 214 can be in contact with the passivation material 218. The thermally conductive cap 212 can be fabricated using methods that are similar to those used for the vias 226 with reference to Figure 39. Fig. 31. The methods discussed above are the same as or similar to those described above. The thermally conductive cap 212 can be thermally connected to the device die 200 and electrically isolated from the device die 200. In some embodiments, the thermally conductive cap 212 can be electrically floating. By omitting the passivation material 218, machining steps and costs for manufacturing the thermally conductive cap 212 can be reduced, while still providing better heat dissipation from the thermally conductive cap 212 and the auxiliary die 210.

[0131] The Fig. 40, Fig. 41, Fig. 42 to Fig. Figure 43 shows top-down views of the encapsulation material 228, the thermally conductive cap 212, and the auxiliary die 210 according to some embodiments. Certain structural elements, such as the vias 226, are shown in the Fig. 40, Fig. 41, Fig. 42 to Fig. 43 has been omitted for the sake of simplicity and clarity. Fig. 40 shows the embodiment of Fig. 35, wherein the passivation material 218 surrounds the thermally conductive cap 212. Side faces of the passivation material 218 can be aligned with side faces of the underlying auxiliary die 210. As in Fig. As shown in Figure 40, the seed layer 214 can enclose side surfaces of the conductive filler material 216, the passivation material 218 can enclose side surfaces of the seed layer 214, and the encapsulation material 228 can enclose side surfaces of the passivation material 218. The thermally conductive cap 212 can be thermally connected to the device die 200 and electrically insulated from the device die 200. In some embodiments, the thermally conductive cap 212 can be electrically floating. In the embodiment of Fig. 40 The thermally conductive cap 212 has a large surface area, approximately 50% to 100% of the surface area of ​​the auxiliary die 210 and / or the device die 200, thus providing better heat dissipation through the thermally conductive cap 212. This improves device performance and reduces device defects caused by heat generated in the device die 200.

[0132] Fig. Figure 41 shows an embodiment in which the thermally conductive cap 212 is manufactured in segments that are separated from one another. Each of the segments of the thermally conductive cap 212 can be separated from adjacent segments by a gap. The gap separating each of the segments of the thermally conductive cap from adjacent segments can have a width greater than about 10 µm. Fig. Figure 41 shows the thermally conductive cap 212 with six segments, but the thermally conductive cap 212 can have more or fewer segments. The thermally conductive cap 212 can be manufactured using methods that are similar to those used for the vias 226 with reference to Fig. 31. The procedures discussed above are the same or similar. As in Fig. As shown in Figure 41, the encapsulation material 228 can extend between the segments of the thermally conductive cap 212 and fill the gaps between them. By manufacturing the thermally conductive cap 212 with multiple segments and filling the gaps between the segments with the encapsulation material 228, the mechanical stress resulting from differences in the coefficients of thermal expansion (CTE) between the thermally conductive cap 212 and the encapsulation material 228 is reduced, thereby decreasing package deformation, reducing device errors, and improving device performance.

[0133] Fig. Figure 42 shows an embodiment in which the thermally conductive cap 212 is manufactured over a hot spot in the device die 200. Although the thermally conductive cap 212 is shown with a circular shape, it can have any suitable shape, such as a square, rectangular, oval, or other shape. By placing the thermally conductive cap 212 over a hot spot of the device die 200, the area of ​​the thermally conductive cap 212 is reduced, thereby lowering costs, while still providing better heat dissipation. This improves device performance and reduces device failures caused by heat generated in the device die 200.

[0134] Fig. Figure 43 shows an embodiment in which the thermally conductive cap 212 has segments and at least a portion of the thermally conductive cap 212 is manufactured over a hot spot in the device die 200. Although the thermally conductive cap 212 is shown with rectangular segments, the various segments of the thermally conductive cap 212 can have any suitable shape, such as square, rectangular, oval, circular, or the like. By positioning the thermally conductive cap 212 over a hot spot of the device die 200, the area of ​​the thermally conductive cap 212 is reduced, thereby lowering costs while still providing better heat dissipation. This improves device performance and reduces device failures caused by heat generated in the device die 200.By manufacturing the thermally conductive cap 212 with multiple segments and filling gaps between the segments with the encapsulation material 228, the mechanical stress resulting from differences in the coefficients of thermal expansion (CTE) between the thermally conductive cap 212 and the encapsulation material 228 is reduced, thereby reducing package deformation, reducing device errors, and improving device performance.

[0135] By integrating the auxiliary die 210 and the thermally conductive cap 212 in the embodiments of the Fig. 28, Fig. 29, Fig. 30, Fig. 31, Fig. 32, Fig. 33, Fig. 34, Fig. 35, Fig. 36, Fig. 37, Fig. 38, Fig. 39, Fig. 40, Fig. 41, Fig. 42 to Fig. 43. The structural and mechanical stability of a packaged semiconductor device is improved, while better heat dissipation from the device die 200 is provided. This improves device performance and reduces device failures caused by heat generated in the device die 200.

[0136] The Fig. Figures 44A to 48C show embodiments in which heat dissipation structures include an auxiliary die 310 attached to the front interconnect structure 120 and an interposer die 320 attached to the rear interconnect structure 140. The auxiliary die 310 is an example of a front heat distributor located in a device die 200 (e.g., a device die containing nanoFETs fabricated according to the processes described in the Fig. The interposer die 320 is an example of a rear-facing heat distributor that dissipates heat generated in a device die 200. By placing the auxiliary die 310 and the interposer die 320 above the device die 200, heat dissipation from the device die 200 is improved. This improves device performance and reduces device failures caused by heat generated in the device die 200.

[0137] In the Fig. 44A and Fig. 44B a rear interconnect structure 140 of a device die 200 is attached to a support substrate 202 by means of a release layer 204, and an auxiliary die 310 is attached to a front interconnect structure 120 of the device die 200 by means of bond layers 260. Fig. Figure 44B shows a detailed view of the bonding between the bond layers 260 of the auxiliary die 310 and the device die 200 in an area 261 of Fig. 44A. The rear interconnect structure 140 can be connected using the detachable layer 204 in the same or a similar manner as described with reference to Fig. 28 above, to which the carrier substrate 202 is attached.

[0138] The auxiliary die 310 is a rigid structure attached to the device die 200 to provide structural or mechanical stability and heat dissipation. The auxiliary die 310 can be bonded to a top surface of the front interconnect structure 120 of the device die 200 by means of a first bond layer 260A and a second bond layer 260B (collectively referred to as bond layers 260). The auxiliary die 310 can include an auxiliary or support substrate 312, which may be a substrate with high thermal conductivity. The support substrate 312 is used as part of a heat dissipation structure that draws heat away from the device die 200. In some embodiments, the support substrate 312 may comprise silicon, silicon carbide, aluminum nitride, or the like. In some embodiments, the support substrate 312 may be an empty die, as described in the Fig. 44A and Fig. Figure 44B shows that in some embodiments the support substrate 312 may include active and / or passive devices, various conductive structural elements such as metal columns, interconnect structures, vias, other thermally conductive structural elements, or the like.

[0139] The auxiliary die 310 can have a dielectric layer 316, which is produced over the support substrate 312, and conductive structural elements 314, which extend through the dielectric layer 316 into the support substrate 312. The dielectric layer 316 can comprise polymers, such as PBO, polyimide, BCB, or the like. In some embodiments, the dielectric layer 316 can comprise inorganic dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxide nitride, or the like. The dielectric layer 316 can be deposited, for example, by CVD, PVD, ALD, or the like. In some embodiments, the dielectric layer 316 can be produced by thermal oxidation.

[0140] The conductive structural elements 314 can be produced by creating openings extending through the dielectric layer 316 and into the support substrate 312, and filling the openings with suitable conductive materials. The openings can be produced using suitable photolithography and etching processes. The openings can be filled with copper, a copper alloy, silver, gold, tungsten, tantalum, aluminum, aluminum alloys, a combination thereof, or the like, using PVD, ALD, electrochemical plating, electroless plating, a combination thereof, or the like. In some embodiments, a coating and / or an adhesive layer can be produced in the openings before the openings are filled with the suitable conductive materials.The coating can comprise dielectric material, such as silicon oxide, silicon nitride, silicon oxide nitride, or the like, or combinations thereof. The adhesive layer can comprise Ta, TaN, Ti, TiN, or combinations thereof. A planarization process (e.g., CMP, grinding, etching, or the like) can be performed to remove excess portions of the conductive structural elements 314 that have been fabricated over the dielectric layer 316. The conductive structural elements 314 can be thermally conductive dummy structural elements. The conductive structural elements 314 can be fabricated in the auxiliary die 310 to improve heat dissipation from the device die 200 to the auxiliary die 310. This improves device performance and reduces device failures caused by heat generated in the device die 200.

[0141] The auxiliary die 310 can be bonded to the front-facing interconnect structure 120 using a suitable method, such as dielectric-dielectric bonding or the like. The dielectric-dielectric bonding process can include the deposition of the first bond layer 260A on the front-facing interconnect structure 120. In some embodiments, the first bond layer 260A comprises silicon oxide (e.g., a high-density plasma oxide (HDP oxide) or the like) deposited by CVD, ALD, PVD, or the like. The second bond layer 260B can similarly comprise an oxide layer produced on a surface of the auxiliary die 310 prior to bonding, using, for example, CVD, ALD, PVD, thermal oxidation, or the like. Other suitable materials can be used for the first bonding layer 260A and the second bonding layer 260B.The dielectric-dielectric bonding process can be described with reference to the . Fig. The dielectric-dielectric bonding process discussed above is identical or similar to that described in sections 22A to 22C. The auxiliary die 310 can be integrated to provide better heat dissipation from the device die 200. This improves device performance and reduces device failures caused by heat generated in the device die 200.

[0142] In the Fig. 45A and Fig. 45B will describe the structure of Fig. 44A and Fig. 44B is turned over and attached to a support substrate 220, the support substrate 202 is removed, an interposer die 320 is attached to the rear interconnect structure 140 of the device die 200, and vias 226 are made over the support substrate 220. The auxiliary die 310 can be attached to the support substrate 220 by means of an adhesive 224 applied to the auxiliary die 310 and a release layer 222 attached to the support substrate 220. The support substrate 220, the release layer 222, and the adhesive 224 can be used to those described with reference to Fig. 31 above, are the same or similar.

[0143] The support substrate is unbonded to detach (or "unbond") the support substrate 202 from the rear interconnect structure 140. In some embodiments, unbonding involves projecting light, such as laser light or ultraviolet (UV) light, onto the release layer 204, causing the release layer 204 to decompose due to the heat of the light and allowing the support substrate 202 to be removed. The surfaces of the passivation layer 139 and the redistribution layer 138 may be exposed after the removal of the support substrate 202 and the release layer 204.

[0144] The interposer die 320 can be attached to the device die 200 by hybrid bonding or the like. The interposer die 320 can comprise an interposer substrate 322, a bonding layer 324, a passivation layer 326, electrically conductive vias 327, and thermally conductive vias 325. The interposer substrate 322 can comprise a semiconductor substrate, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The interposer substrate 322 can comprise other semiconductor materials, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; exhibit an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.Other substrates, such as multilayer or gradient substrates, can also be used. The interposer substrate 322 can be free of active devices and can establish connections between the external devices of the rear interconnect structure 140. The interposer substrate 322 can optionally include passive devices.

[0145] The bonding layer 324 can be produced over the interposer substrate 322 using, for example, CVD, ALD, PVD, thermal oxidation, or the like. In some embodiments, the bonding layer 324 comprises silicon oxide (e.g., a high-density plasma oxide (HDP oxide) or the like). Other suitable materials can be used for the bonding layer 324. The passivation layer 326 can comprise polymers such as PBO, polyimide, BCB, or the like. In some embodiments, the passivation layer 326 can comprise inorganic dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxide nitride, or the like. The passivation layer 326 can be deposited, for example, by CVD, PVD, ALD, or the like.

[0146] The interposer substrate 322 can feature electrically conductive vias 327 and thermally conductive vias 325 (sometimes referred to as silicon vias or substrate vias (TSVs)) and can further feature metallization layers (not shown separately). The metallization layers can be designed to connect various devices to form functional circuits. The metallization layers can be made of alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper), with vias connecting the layers of conductive materials.The electrically conductive vias 327, the thermally conductive vias 325 and the metallization layers can be produced by any suitable process (such as a deposition process, a damascene process, a dual damascene process or the like).

[0147] The electrically conductive vias 327 can be electrically connected to active devices of the device layer 109 via the rear interconnect structure 140. The thermally conductive vias 325 can be dummy structural elements that are not electrically connected to the active devices of the device layer 109 via the rear interconnect structure 140. The thermally conductive vias 325 can be thermally connected to dummy structural elements of the rear interconnect structure 140. Fig. Figure 45B, for example, shows a detailed view of the bonding between thermally conductive structural elements 328 in the rear interconnect structure 140 and the thermally conductive vias 325 in the interposer die 320 in an area 321 of Fig. 45A. The thermally conductive structural elements 328 can be manufactured using materials and processes that comply with the requirements of the Fig. The materials and methods discussed above are the same as or similar to those described in sections 27A to 27C for the conductive structural elements 136 and the redistribution layer 138. The thermally conductive structural elements 328 can be dummy structural elements that are not electrically connected to the active devices of the device layer 109. In some embodiments, the thermally conductive vias 325 and the thermally conductive structural elements 328 can be electrically floating. By providing the thermally conductive vias 325 and the thermally conductive structural elements 328 in the interposer die 320 and the backside interconnect structure 140, respectively, heat dissipation from the device die 200 through the backside interconnect structure 140 and the interposer die 320 is improved.This improves device performance and reduces device defects caused by heat generated in the device die 200. The thermally conductive structural elements 328 are optional and can be omitted in some embodiments, as shown in . Fig. 45A is shown.

[0148] In some embodiments, the interposer die 320 can be bonded to the device die 200 by hybrid bonding. For example, the bond layer 324 of the interposer die 320 can be bonded directly to the passivation layer 139 of the device die 200, and the electrically conductive vias 327 and the thermally conductive vias 325 of the interposer die 320 can be bonded directly to the redistribution layer 138 and the thermally conductive structural elements 328 of the device die 200. In one embodiment, the bond between the bond layer 324 and the passivation layer 139 can be an oxide-oxide bond or the like.In the hybrid bonding process, the electrically conductive vias 327 and the thermally conductive vias 325 are bonded directly to the redistribution layer 138 and the thermally conductive structural elements 328, respectively, via direct metal-to-metal bonding. Consequently, electrical and thermal connections between the interposer die 320 and the device die 200 are established by the physical connection of the electrically conductive vias 327 and the thermally conductive vias 325 to the redistribution layer 138 and the thermally conductive structural elements 328, respectively. The device die 200, the auxiliary die 310, and the interposer die 320 collectively form a die structure 302.The direct thermal connections between the thermally conductive vias 325 and the thermally conductive structural elements 328 further improve heat dissipation from the device die 200 through the rear interconnect structure 140 and the interposer die 320. This improves device performance and reduces device defects caused by heat generated in the device die 200.

[0149] For example, the hybrid bonding process can be initiated by applying a surface treatment to the bonding layer 324 of the interposer die 320 and / or the passivation layer 139 of the device die 200. The surface treatment can include plasma treatment. The plasma treatment can be performed in a vacuum environment. After the plasma treatment, the surface treatment can further include a cleaning process (e.g., rinsing with demineralized water or the like) applied to the bonding layer 324 and / or the passivation layer 139. The hybrid bonding process can then be continued to align the electrically conductive vias 327 and the thermally conductive vias 325 with the redistribution layer 138 and the thermally conductive structural elements 328.The hybrid bonding process includes a pre-bonding step in which the electrically conductive vias 327 and the thermally conductive vias 325 are brought into physical contact with the redistribution layer 138 and the thermally conductive structural elements 328, respectively. Pre-bonding can be performed at room temperature (e.g., between approximately 21 °C and approximately 25 °C). The hybrid bonding process then continues with an annealing process at a temperature of approximately 150 °C to approximately 400 °C for a duration of approximately 0.5 to approximately 3 hours. The tempering process causes the metal of the electrically conductive vias 327 and the thermally conductive vias 325 (e.g. copper) and the metal of the redistribution layer 138 and the thermally conductive structural elements 328 (e.g. copper) to interdiffusion with each other, thereby creating a direct metal-to-metal bond.Tempering allows covalent bonds to be formed between the bonding layer 324 and the passivation layer 139. In some embodiments, other bonding parameters and / or methods (e.g., solder bonding) can be used.

[0150] The vias 226 are fabricated on the release layer 222 and extend away from the substrate 220. To fabricate the vias 226, a seed layer (not shown separately) is produced, for example, over the release layer 222. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising multiple sublayers made of different materials. In one particular embodiment, the seed layer has a titanium layer and a copper layer over the titanium layer. The seed layer can be fabricated, for example, by PVD or the like. A photoresist is fabricated and patterned on the seed layer. The photoresist can be produced by spin coating or the like and can be exposed to light for patterning. The structure of the photoresist corresponds to conductive vias.Structuring creates openings through the photoresist to expose the seed layer. A conductive material is then deposited in the openings of the photoresist and on the exposed portions of the seed layer. This conductive material can be produced by plating, such as electroplating or electroless plating, or similar processes. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, or similar. The photoresist and portions of the seed layer where the conductive material has not been deposited are removed. The photoresist can be removed using a suitable stripping or removal process, such as oxygen plasma. Once the photoresist has been removed, any remaining exposed portions of the seed layer are removed, for example, using a suitable etching process, such as wet or dry etching.The remaining parts of the seed layer and the conductive material form the vias 226.

[0151] In Fig. 46 An encapsulation material 228 is fabricated on and around the die structure 302, the support substrate 220, and the vias 226; a redistribution structure 230 is fabricated over the encapsulation material 228, the vias 226, and the die structure 302; and a passivation layer 236, UBMs 238, and conductive interconnects 240 are fabricated over the redistribution structure 230. The encapsulation material 228 can be fabricated using materials and methods described with reference to Fig. 32 materials and processes discussed above are identical or similar. The redistribution structure 230 can have stacked layers of the conductive structural elements 232, which are fabricated in the dielectric stacked layers 234. The redistribution structure 230 can be fabricated using materials and processes that are identical or similar to those discussed above. Fig. 33 materials and processes discussed above are identical or similar. The passivation layer 236, the UBMs 238 and the conductive connecting elements 240 can be produced using materials and processes that are identical or similar to those described in reference to Fig. 34 materials and processes discussed above are the same or similar. The die structure 302, the encapsulation material 228, the vias 226, the redistribution structure 230, the passivation layer 236, the UBMs 238 and the conductive connecting elements 240 collectively form a first package component 352.

[0152] In Fig. 47 The first package component 352 is turned over; the support substrate 220 is removed; a passivation layer 242 is produced over the encapsulation material 228, the vias 226 and the die structure 302; and a second package component 360 is joined to the first package component 352. The processes that are carried out in Fig. 47 are carried out, are the same or similar to those carried out with reference to Fig. 35 above. The first package component 352, the second package component 360, and the intermediate structures used to connect the second package component 360 to the first package component 352 (e.g., the passivation layer 242, the conductive interconnects 244, the underfill 258) collectively form a packaged semiconductor device 602. The packaged semiconductor device 602 can be a package-on-package (PoP) structure comprising an integrated fan-out package (InFO package), which can be a wafer-level package with high-density redistribution layers.

[0153] The auxiliary die 310 is a heat dissipation structure fabricated on the front side of the device die 200 and can be described as a front-side heat spreader. The auxiliary die 310 can be integrated into the packaged semiconductor device 602. Fig. 47 are integrated to improve the structural and mechanical stability of the first package component 352 while simultaneously providing better heat dissipation. The interposer die 320 is a heat dissipation structure fabricated on the back side of the device die 200 and can be described as a backside heat distributor. The interposer die 320 provides electrical connections and improves heat dissipation. This improves device performance and reduces device failures caused by heat generated in the device die 200.

[0154] The Fig. Figures 48A to 48C show alternative configurations for bonding an auxiliary die 310A to a device die 200 and for providing a heat dissipation path from the device die 200 through an interposer die 320 and a redistribution structure 230A. Fig. 48A and Fig. 48B, the auxiliary die 310A comprises: devices 318 manufactured on a support substrate 312; metallization layers 319 on the devices 318 and the support substrate 312; a dielectric layer 316 over the metallization layers 319; a second bonding layer 260B over the dielectric layer 316; and conductive structural elements 314A and thermally conductive structural elements 317 extending through the second bonding layer 260B and the dielectric layer 316. Fig. Figure 48B shows a detailed view of area 263 of Fig. 48A. The auxiliary die 310A is attached to the device die 200 by hybrid bonding or the like. The device die 200, the auxiliary die 310A, and the interposer die 320A collectively form a die structure 302A. The die structure 302A, the encapsulation material 228, the vias 226, the redistribution structure 230A, the passivation layer 236, the UBMs 238, and the conductive connecting elements 240 collectively form a first package component 352A.

[0155] The devices 318 can include active and / or passive devices. A wide variety of devices, such as transistors, capacitors, resistors, combinations thereof, and the like, can be used to meet the structural and functional design requirements of the die structure 302A. The devices can be fabricated using suitable methods. The auxiliary die 310A can also include metallization layers 319. The metallization layers 319 can be fabricated over the devices 318 and are designed to connect the devices 318 to form functional circuits. The metallization layers 319 can be made of alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper) with vias connecting the conductive material layers.The metallization layers 319 can be produced using any suitable process (such as a deposition process, a damascene process, a dual damascene process or the like).

[0156] The dielectric layer 316 and the second bond layer 260B can be used by those who, with reference to the Fig. 44A and Fig. 44B above, are identical or similar. The conductive structural elements 314A and the thermally conductive structural elements 317 can be manufactured using materials and processes that are identical to those discussed with reference to the Fig. 44A and Fig. 44B for the fabrication of the conductive structural elements 314 are the same as or similar to the materials and methods discussed above, except that the conductive structural elements 314A and the thermally conductive structural elements 317 are fabricated after the fabrication of the second bond layer 260B and extend through the second bond layer 260B and the dielectric layer 316. The conductive structural elements 314A can provide electrical connections between the devices 318 of the auxiliary die 310A and the device die 200. The conductive structural elements 314A can be electrically connected to the conductive structural elements 122 of the front interconnect structure 120 and the metallization layers 319. The thermally conductive structural elements 317 can be dummy structural elements that are thermally conductive and are not electrically connected to the devices 318 or active devices of the device die 200.In some embodiments, the thermally conductive structural elements 317 can be electrically floating. The thermally conductive structural elements 317 can be manufactured in the auxiliary die 310A to improve heat dissipation from the device die 200 to the auxiliary die 310A. This improves device performance and reduces device defects caused by heat generated in the device die 200.

[0157] The front interconnect structure 120 of the device die 200 further comprises conductive structural elements 262 bonded to the conductive structural elements 314A. The conductive structural elements 262 can be manufactured using materials and methods that meet the requirements described in the Fig. 44A and Fig. 44B for the fabrication of the conductive structural elements 314, the materials and methods discussed above are the same as or similar to those used. The conductive structural elements 262 can be fabricated to extend through the first bond layer 260A and the topmost dielectric layer 124 of the front interconnect structure 120. The conductive structural elements 262 can provide electrical connections between the devices 318 of the auxiliary die 310A and the device die 200. The conductive structural elements 262 can be electrically connected to the conductive structural elements 122 of the front interconnect structure 120 and the conductive structural elements 314A.

[0158] The auxiliary die 310A can be bonded to the front interconnect structure 120 of the device die 200 by hybrid bonding, whereby this can be a similar or identical process to the one described above with reference to the Fig. 45A and Fig. The hybrid bonding process described in Section 45B is particularly relevant. Specifically, dielectric-dielectric bonds, such as oxide-oxide bonds, can be formed between the second bond layer 260B and the first bond layer 260A. Metal-metal bonds can be formed between the conductive structural elements 314A and the conductive structural elements 262. Direct thermal connections between the conductive structural elements 314A and the conductive structural elements 262 further improve heat dissipation from the device die 200 through the front interconnect structure 120 and the auxiliary die 310A. This improves device performance and reduces device failures caused by heat generated in the device die 200.

[0159] Also in the Fig. 48A and Fig. 48C provides a heat dissipation path from the device die 200 through the interposer die 320 and the redistribution structure 230A. Fig. Figure 48C shows a detailed view of area 330 of the Fig. 48A. As in the Fig. 48A and Fig. As shown in Figure 48C, the redistribution structure 230A has thermally conductive structural elements 329. The thermally conductive structural elements 329 can include UBMs 238 and / or conductive connecting elements 240. The thermally conductive structural elements 329 in the redistribution structure 230A can be described with reference to Fig. 33 above-discussed conductive structural elements 232 are the same as or similar to them. The thermally conductive structural elements 329, which include the UBMs 238 and the conductive connecting elements 240, may include the same or similar UBMs 238 and conductive connecting elements 240 as those discussed with reference to Fig. 34 above. The thermally conductive structural elements 329 can be dummy structural elements that are thermally conductive and are not electrically connected to active devices of the device die 200. In some embodiments, the thermally conductive structural elements 329 can be electrically floating. The thermally conductive structural elements 329 can be thermally connected to the thermally conductive vias 325 to provide a heat dissipation path through the interposer die 320 and the redistribution structure 230A to an outside of a packaged semiconductor device. Consequently, the thermally conductive structural elements 329 can further improve heat dissipation from the device die 200 through the backside interconnect structure 140, the interposer die 320, and the redistribution structure 230A.This improves the device performance and reduces device errors caused by heat generated in the device die 200.

[0160] The Fig. 49, Fig. 50, Fig. 51, Fig. 52, Fig. 53, Fig. 54, Fig. 55, Fig. 56, Fig. 57 to Fig. Figure 58 shows embodiments in which heat dissipation structures comprise: an auxiliary die 210 attached to a front interconnect structure 120 of a device die 200, thermally conductive structural elements 507 or thermally conductive structural elements 513 attached to side faces of the device die 200, and thermally conductive vias 141 or thermally conductive structural elements 510 fabricated through portions of the device die 200. The auxiliary die 210 is an example of a front heat distributor located in the device die 200 (e.g., a device die with nanoFETs fabricated according to the processes of Fig. The thermally conductive structural elements 507 / 513 are examples of lateral heat distributors that dissipate heat generated in the device die 200. The thermally conductive vias 141 / thermally conductive structural elements 510 are examples of thermally conductive dummy structural elements that dissipate heat generated in the device die 200. By providing the auxiliary die 210, the thermally conductive structural elements 507 / 513, and the thermally conductive vias 141 / thermally conductive structural elements 510, heat dissipation from the device die 200 is improved. This improves device performance and reduces device failures caused by heat generated in the device die 200.

[0161] Fig. 49 shows a structure that corresponds to the structure in Fig. 29 is similar, except that thermally conductive vias 141 are manufactured such that they extend through the rear interconnect structure 140 and the insulating layer 208 has been omitted. In particular, the structure of Fig. 49 a device die 200, which is attached to a support substrate 202 by means of a release layer 204, and an auxiliary die 210, which is attached to the device die 200 by means of bond layers 206. Although the auxiliary die 210 is shown to be attached to the device die 200 by means of bond layers 206, in some embodiments the auxiliary die 210 is replaced by an auxiliary die 310, which is produced by means of materials and methods that are the same or similar to those described with reference to the Fig. 44A, Fig. 44B, Fig. 48A and Fig. The materials and methods discussed in Section 48B are to which the device die 200 is attached. The device die 200, the auxiliary die 210, and the thermally conductive cap 212 collectively form a die structure 304.

[0162] The thermally conductive vias 141 can be fabricated to extend through the passivation layer 139, the dielectric layers 137, and the dielectric layer 134. The thermally conductive vias 141 can be dummy structural elements that are not electrically connected to the active devices of the device layer 109. In some embodiments, the thermally conductive vias 141 can be electrically floating. The thermally conductive vias 141 can be fabricated by etching openings extending through the passivation layer 139, the dielectric layers 137, and the dielectric layer 134, and filling the openings with a thermally conductive material. The thermally conductive vias 141 can each have one or more layers, such as barrier layers, diffusion layers, and conductive filler materials.In some embodiments, for example, the thermally conductive vias 141 may each comprise a barrier layer and a conductive filler material. The barrier layer may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive filler material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess portions of the thermally conductive vias 141, such excess portions being located above the top surfaces of the passivation layer 139. The thermally conductive vias 141 provide a heat dissipation path away from the device layer 109 of the device die 200, thereby improving heat dissipation from the device die 200.This improves the device performance and reduces device errors caused by heat generated in the device die 200.

[0163] In the Fig. At temperatures from 50A to 50C, the die structure 304 is turned over, attached to a support substrate 220, the support substrate 202 is removed, and thermally conductive structural elements 507 are fabricated above the support substrate 220 adjacent to the die structure 304. The rear interconnect structure 140 of the die structure 304 can be attached to the support substrate 220 by means of a release layer 222, which is attached to the support substrate 220. The support substrate 220 and the release layer 222 can be described in relation to Fig. 31 have been discussed, are the same or similar. The carrier substrate 202 can be associated with a process similar to that discussed with reference to Fig. The process discussed in section 31 is similar or comparable to the device die being removed by 200.

[0164] A passivation layer 502 is produced over the support substrate 220 and the die structure 304. The passivation layer 502 can comprise polymers such as PBO, polyimide, BCB, or the like. In some embodiments, the passivation layer 502 can comprise non-organic dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxide nitride, or the like. The passivation layer 502 can comprise materials with high thermal conductivity, such as aluminum nitride (AlN). The passivation layer 502 can be deposited, for example, by CVD, PVD, ALD, or the like. The passivation layer 502 can be deposited by a conformal deposition process and can extend along horizontal top surfaces of the release layer 222 and the die structure 304 and vertical side surfaces of the die structure 304.

[0165] The thermally conductive structural elements 507 are fabricated on the passivation layer 502 adjacent to the die structure 304. The thermally conductive structural elements 507 can be fabricated, for example, by fabricating a seed layer 504 over the passivation layer 502. In some embodiments, the seed layer 504 is a metal layer, which can be a single layer or a composite layer comprising multiple sublayers made of different materials. In a particular embodiment, the seed layer 504 has a titanium layer and a copper layer over the titanium layer. The seed layer 504 can be fabricated, for example, using PVD or the like. A photoresist (not shown separately) is fabricated and patterned on the seed layer 504. The photoresist can be fabricated by spin coating or the like and can be exposed for patterning.The structure of the photoresist corresponds to the thermally conductive structural elements 507. By structuring, openings are created through the photoresist to expose the seed layer 504. A conductive material 506 is produced in the openings of the photoresist and on the exposed portions of the seed layer 504. The conductive material 506 can be produced by plating, such as electroplating or electroless plating, or the like. The conductive material 506 can be a metal, such as copper, titanium, tungsten, aluminum, or the like. The photoresist and portions of the seed layer 504 on which the conductive material 506 has not been deposited are removed. The photoresist can be removed by a suitable stripping or delamination process, e.g., using an oxygen plasma or the like. Once the photoresist has been removed, exposed portions of the seed layer 504, e.g.,The remaining portions of the seed layer 504 and the conductive material 506 form the thermally conductive structural elements 507. A planarization process, such as CMP, can be performed to remove excess portions of the passivation layer 502, the seed layer 504, and the conductive material 506, where these excess portions are located above the top surfaces of the die structure 304. Therefore, the top surfaces of the passivation layer 502, the seed layer 504, and the conductive material 506 can be at the same level as the top surfaces of the die structure 304 (e.g., the top surfaces of the passivation layer 139, the redistribution layer 138, and the thermally conductive vias 141). The thermally conductive structural elements 507 can be produced with widths W1 perpendicular to side surfaces of the die structure 304 in a range of about 1 µm to about 100 µm.This provides better heat dissipation through the thermally conductive structural elements 507, without the thermally conductive structural elements 507 extending into keep-out zones between the die structure 304 and subsequently manufactured vias (such as the vias 226, which are described below with reference to . Fig. 51 will be discussed) extend.

[0166] The Fig. 50B and Fig. Figure 50C shows top-down views of various embodiments of the thermally conductive structural elements 507. As shown in Fig. As shown in Figure 50B, the thermally conductive structural elements 507 can be interconnected structures that enclose the side faces of the die structure 304. This provides improved heat dissipation through the thermally conductive structural elements 507. In the Fig. In the embodiment shown in Figure 50C, the thermally conductive structural elements 507 are separated into segments. As will be discussed in detail below, an encapsulation material (such as the encapsulation material 228, which is described below with reference to Figure 50C) can be used to encapsulate these elements. Fig. (discussed in Section 51) between adjacent segments of the thermally conductive structural elements 507. Manufacturing the thermally conductive structural elements 507 in segments reduces costs and mechanical stress resulting from differences in the coefficients of thermal expansion (CTE) between the thermally conductive structural elements 507 and the encapsulation material, thereby reducing package deformation, reducing fixture defects, and improving fixture performance. The thermally conductive structural elements 507 manufactured in segments also provide better heat dissipation. This improves fixture performance and reduces fixture defects caused by heat generated in the fixture die 200.

[0167] In Fig. 51. Vias 226 are fabricated on the support substrate 220, and an encapsulation material 228 is fabricated on and around the support substrate 220, the vias 226, and the die structure 304. The vias 226 and the encapsulation material 228 can be fabricated using materials and processes that comply with the requirements of the Fig. 31 and Fig. 32 materials and processes discussed above are the same or similar. The vias 226 can be separated from the thermally conductive structural elements 507 by a distance D1 perpendicular to the side faces of the die structure 304 (referred to as a keep-out zone) in a range of about 1 µm to about 10 µm or greater than about 1 µm. This ensures sufficient isolation of the vias 226 and the thermally conductive structural elements 507, thereby improving device performance and reducing device defects. After the vias 226 and the encapsulation material 228 have been fabricated, a planarization process is performed on the encapsulation material 228 to expose the vias 226, the thermally conductive structural elements 507, and the die structure 304.The planarization process can also remove material from the vias 226, the redistribution layer 138, the thermally conductive vias 141, the thermally conductive structural elements 507, and / or the passivation layer 139 until the redistribution layer 138, the thermally conductive vias 141, the thermally conductive structural elements 507, and the vias 226 are exposed. After the planarization process, the top surfaces of the vias 226, the redistribution layer 138, the thermally conductive vias 141, the passivation layer 139, the thermally conductive structural elements 507, and the encapsulation material 228 are essentially coplanar within the process variations. The planarization process can be, for example, a CMP, a grinding process, or the like.In some embodiments, planarization can be omitted, for example, if the vias 226, the thermally conductive vias 141, the thermally conductive structural elements 507, and / or the redistribution layer 138 are already exposed.

[0168] In Fig. 52 A redistribution structure 230 is fabricated over the encapsulation material 228, the vias 226, and the die structure 304, and a passivation layer 236, UBMs 238, and conductive interconnects 240 are fabricated over the redistribution structure 230. The redistribution structure 230 can be similar to the front interconnect structure 120 and the back interconnect structure 140. For example, the redistribution structure 230 can be fabricated using the same or similar materials and processes as the front interconnect structure 120 and the back interconnect structure 140. The redistribution structure 230 can include stacked layers of conductive structural elements 232 fabricated in dielectric stacked layers 234. The redistribution structure 230 can further include thermally conductive structural elements 239, which are manufactured in the dielectric stack layers 234.The conductive structural elements 232 can have conductive traces (e.g., for routing to and from subsequently fabricated contact pads and conductive interconnects). The conductive structural elements 232 can have conductive vias extending into dielectric layers 234 to provide a vertical connection between stacked layers of the conductive traces. The conductive structural elements 232 can have one or more embedded passive devices, such as resistors, capacitors, inductors, or the like. The embedded passive devices can be integrated into the die structure 304 to provide circuitry.

[0169] The thermally conductive structural elements 239 can thermally connect the thermally conductive vias 141 to the thermally conductive structural elements 507. The thermally conductive structural elements 239 can have conductive conductors (e.g., for routing between the thermally conductive vias 141 and the thermally conductive structural elements 507). The thermally conductive structural elements 239 can have conductive vias that extend into the dielectric layers 234 to provide a vertical connection between stack layers of the conductive conductors.The thermally conductive structural elements 507 can be thermally connected to the device die 200 via the thermally conductive structural elements 239 and the thermally conductive vias 141, and the thermally conductive structural elements 507, the thermally conductive structural elements 239, and the thermally conductive vias 141 can each be electrically isolated from the device die 200. In some embodiments, the thermally conductive structural elements 507, the thermally conductive structural elements 239, and the thermally conductive vias 141 can be electrically floating. By providing the thermally conductive structural elements 239, the heat dissipation from the device layer 109 of the device die 200 through the thermally conductive vias 141 to the thermally conductive structural elements 507 is improved, thereby improving heat dissipation.This improves the device performance and reduces device errors caused by heat generated in the device die 200.

[0170] The passivation layer 236, the UBMs 238 and the conductive connecting elements 240 can be manufactured using materials and processes that comply with the requirements referred to in Fig. 34 materials and processes discussed above are identical or similar. The die structure 304, the thermally conductive structural elements 507, the passivation layer 502, the encapsulation material 228, the vias 226, the redistribution structure 230, the passivation layer 236, the UBMs 238 and the conductive connecting elements 240 collectively form a first package component 354.

[0171] In Fig. 53 The first package component 354 is turned over; the support substrate 220 is removed; and the second package component 360 is connected to the first package component 354. The in Fig. 53 processes carried out are the same as or similar to the processes carried out with reference to Fig. 35 have been discussed. The first package component 354, the second package component 360 and the intermediate structures used to connect the second package component 360 to the first package component 354 (e.g. the passivation layer 242, the conductive connecting elements 244, the underfill 258) collectively form a packaged semiconductor device 604.

[0172] The thermally conductive structural elements 507 are heat dissipation structures fabricated on side faces of the die structure 304, which can be referred to as lateral heat spreaders. The thermally conductive vias 141 and the thermally conductive structural elements 239 are heat dissipation structures that provide a heat dissipation path from the device layer 109 of the device die 200 to the thermally conductive structural elements 507 and which can be referred to as thermally conductive dummy structural elements. The thermally conductive structural elements 507, the thermally conductive vias 141, and the thermally conductive structural elements 239 can be integrated into the packaged semiconductor device 604 of Fig. 53 are integrated to improve heat dissipation from active devices of the device die 200. This improves device performance and reduces device failures caused by heat generated in the device die 200.

[0173] Fig. Figure 54 shows an embodiment in which the seed layer 504 of the thermally conductive structural elements 507, which are described above with reference to the Fig. As discussed in sections 50A to 53, the auxiliary die 210 is replaced with a thermal interface material 508, and heat dissipation paths are provided in the auxiliary die 210 and the device die 200. The heat dissipation paths can be provided from the device layer 109 through the front interconnect structure 120 and the auxiliary die 210, and from the device layer 109 through the rear interconnect structure 140. The device die 200, the auxiliary die 210, and the thermally conductive cap 212 collectively form a die structure 306. As discussed in Fig. As shown in Figure 54, the front interconnect structure 120, the fixture layer 109, and the rear interconnect structure 140 have thermally conductive structural elements 510, and the auxiliary die 210 has a thermally conductive via 512. The thermally conductive structural elements 510 in the front interconnect structure 120, the fixture layer 109, and the rear interconnect structure 140 can be connected to the conductive structural elements 122, the rear vias 130, the conductive traces 132, the conductive structural elements 136, and the redistribution layer 138, which are described with reference to the Fig. 21A to 27C discussed above, are the same or similar.

[0174] The Auxiliary Die 210, which is in Fig. As shown in Figure 54, the thermally conductive via 512 (sometimes referred to as silicon vias or substrate vias (TSVs)) has and may further include metallization layers (not shown separately). The metallization layers can be designed to provide heat dissipation paths through the auxiliary die 210. The metallization layers can be fabricated from alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper) with vias connecting the conductive material layers. The thermally conductive via 512 and the metallization layers can be fabricated by any suitable process (such as a deposition process, a damascene process, a dual-damascene process, or the like).

[0175] The thermally conductive structural elements 510 and the thermally conductive via 512 can be dummy structural elements that are thermally conductive and not electrically connected to active devices of the device die 200. In other words, the thermally conductive structural elements 510 and the thermally conductive via 512 are thermally connected to active devices of the device die 200 and are electrically isolated from active devices of the device die 200. In some embodiments, the thermally conductive structural elements 510 and the thermally conductive via 512 can be electrically floating. The thermally conductive structural elements 510 and the thermally conductive via 512 provide heat dissipation paths through both the front interconnect structure 120 and the rear interconnect structure 140 to an outside of a packaged semiconductor device.Consequently, the thermally conductive structural elements 510 and the thermally conductive via 512 improve heat dissipation from the device die 200. This improves device performance and reduces device defects caused by heat generated in the device die 200.

[0176] The seed layer 504 of the thermally conductive structural elements 507, which above with reference to the Fig. Sections 50A to 53 have been discussed, and will be discussed in Fig. 54 is replaced by a thermal interface material 508. Therefore, the thermally conductive structural elements 507 comprise the conductive material 506 and the thermal interface material 508. The passivation layer 502 can be produced using materials and processes that comply with the requirements of the Fig. The materials and processes discussed above in sections 50A to 50C are identical or similar. The thermal interface material 508 is then applied to the passivation layer 502. The thermal interface material 508 may comprise, among other things, thermal grease, phase-change material, a metal-filled polymer matrix, other polymer materials, solder paste, solder alloys of lead, tin, indium, silver, copper, bismuth, combinations thereof, or the like. The thermal interface material 508 can be used to bond the conductive material 506 to the underlying structures. In these embodiments, the conductive material 506 can be produced separately and attached to the thermal interface material 508.The conductive material 506 can be made from a material with high thermal conductivity, such as a metal like copper, steel, iron, nickel, silver, gold, tungsten, aluminium, cobalt, ruthenium, combinations thereof or the like.

[0177] The conductive material 506 can provide mechanical reinforcement for the die structure 306, prevent deformation of the die structure 306, and provide better heat dissipation for the die structure 306. This improves device performance and reduces device defects caused by heat generated in the device die 200. By fixing the conductive material 506 using the thermal interface material 508, mechanical stress resulting from differences in the coefficients of thermal expansion (CTE) between the conductive material 506 and the die structure 306 is reduced, thereby reducing package deformation, decreasing device defects, and improving device performance.

[0178] In Fig. 55. Vias 226 are fabricated on the substrate 220; an encapsulation material 228 is fabricated on the substrate 220, the vias 226, the thermally conductive structural elements 507, and the die structure 306, and around the vias 226 and the thermally conductive structural elements 507; a redistribution structure 230 is fabricated over the encapsulation material 228, the vias 226, the thermally conductive structural elements 507, and the die structure 306; and a passivation layer 236, UBMs 238, and conductive interconnects 240 are fabricated over the redistribution structure 230. The vias 226 and the encapsulation material 228 can be fabricated using materials and processes that meet the requirements referred to in the Fig. 31, Fig. 32 and Fig. 51 materials and processes discussed above are identical or similar. After the vias 226 and the encapsulation material 228 have been fabricated, a planarization process is performed on the encapsulation material 228 to expose the vias 226, the thermally conductive structural elements 507, and the die structure 300. The planarization process can also remove material from the vias 226, the thermally conductive structural elements 507, the thermally conductive structural elements 510, the redistribution layer 138, and / or the passivation layer 139 until the redistribution layer 138, the thermally conductive structural elements 507, the thermally conductive structural elements 510, and the vias 226 are exposed.The top surfaces of the vias 226, the redistribution layer 138, the thermally conductive structural elements 510, the passivation layer 139, the thermally conductive structural elements 507, and the encapsulation material 228 are essentially coplanar after the planarization process, within the range of process variations. The planarization process can be, for example, a CMP, a grinding process, or the like. In some embodiments, planarization can be omitted if, for example, the vias 226, the thermally conductive structural elements 507, the thermally conductive structural elements 510, and / or the redistribution layer 138 are already exposed.

[0179] The redistribution structure 230 can be similar to the front-side interconnect structure 120 and the rear-side interconnect structure 140. For example, the redistribution structure 230 can be manufactured using the same or similar materials and processes as the front-side interconnect structure 120 and the rear-side interconnect structure 140. The redistribution structure 230 can have stacked layers of conductive structural elements 232, which are manufactured in dielectric stacked layers 234. The redistribution structure 230 can further have thermally conductive structural elements 239, which are manufactured in the dielectric stacked layers 234. The conductive structural elements 232 can have conductive traces (e.g., for routing to and from subsequently manufactured contact pads and conductive connecting elements).The conductive structural elements 232 can have conductive vias extending into the dielectric layers 234 to provide a vertical connection between stacked layers of the conductive conductors. The conductive structural elements 232 can have one or more embedded passive devices, such as resistors, capacitors, inductors, or the like. The embedded passive devices can be integrated into the die structure 300 to provide circuits.

[0180] The thermally conductive structural elements 239 thermally connect the thermally conductive structural elements 510 to the thermally conductive structural elements 507. The thermally conductive structural elements 239 can have conductive conductors (e.g., for routing between the thermally conductive structural elements 510 and the thermally conductive structural elements 507). The thermally conductive structural elements 239 can have conductive vias that extend into the dielectric layers 234 to provide a vertical connection between stack layers of the conductive conductors.The thermally conductive structural elements 507 can be thermally connected to the device die 200 by the thermally conductive structural elements 239 and the thermally conductive structural elements 510, and the thermally conductive structural elements 507, the thermally conductive structural elements 239, and the thermally conductive structural elements 510 can each be electrically isolated from the device die 200. In some embodiments, the thermally conductive structural elements 507, the thermally conductive structural elements 239, and the thermally conductive structural elements 510 can be electrically floating. By providing the thermally conductive structural elements 239, the heat dissipation from the device layer 109 of the device die 200 is improved by the thermally conductive structural elements 510 up to the thermally conductive structural elements 507, thereby improving the heat dissipation.This improves the device performance and reduces device errors caused by heat generated in the device die 200.

[0181] The passivation layer 236, the UBMs 238 and the conductive connecting elements 240 can be produced using materials and processes that comply with the requirements referred to in the Fig. 34 and Fig. 52 materials and processes discussed above are identical or similar. The die structure 300, the thermally conductive structural elements 507, the passivation layer 502, the encapsulation material 228, the vias 226, the redistribution structure 230, the passivation layer 236, the UBMs 238 and the conductive connecting elements 240 collectively form a first package component 356.

[0182] In Fig. At step 56, the first package component 356 is flipped; the carrier substrate 220 is removed; and a second package component 360 is connected to the first package component 356. The processes that occur in Fig. 53 are carried out, are the same as or similar to the processes described in the Fig. 35 and Fig. 53 above. The first package component 356, the second package component 360 and the intermediate structures used to connect the second package component 360 to the first package component 356 (e.g. the passivation layer 242, the conductive connecting elements 244, the underfill 258) collectively form a packaged semiconductor device 606.

[0183] The thermally conductive structural elements 507 are heat dissipation structures fabricated on side faces of the die structure 300 and can be referred to as lateral heat distributors. The thermally conductive vias 512 and the thermally conductive structural elements 510 are heat dissipation structures that provide a heat dissipation path from the device layer 109 of the device die 200 to the thermally conductive structural elements 507 and through the auxiliary die 210, and can be referred to as thermally conductive dummy structural elements. The auxiliary die 210 is a heat dissipation structure fabricated on a front face of the device die 200 and can be referred to as a front-facing heat distributor.The thermally conductive structural elements 507, the thermally conductive vias 512, the thermally conductive structural elements 510, the auxiliary die 210 and the thermally conductive structural elements 239 can be placed in the packaged semiconductor device 606 of . Fig. Auxiliary die 210 is integrated to improve heat dissipation from active devices of the device die 200. This improves device performance and reduces device failures caused by heat generated in the device die 200. Auxiliary die 210 can also improve the structural and mechanical stability of the first package component 356.

[0184] In the Fig. 57 and Fig. 58 the thermally conductive structural elements 507 of Fig. 53 is replaced with thermally conductive structural elements 513, which are manufactured to integrate lattice parts 517 and / or solid parts 518. The Fig. 57 and Fig. Figure 58 shows top-down views of the lattice parts 517 of the thermally conductive structural elements 513, with side views of the structure created along the reference line AA' shown in the top-down views. The thermally conductive structural elements 513 comprise a seed layer 515 on the passivation layer 502 and a conductive material 514 on the seed layer 515. The seed layer 515 and the conductive material 514 can be produced using materials and processes that are the same as or similar to those of the seed layer 504 and the conductive material 506, respectively, which are described with reference to the Fig. 50A to 50C have been discussed. The photoresist used to structure the seed layer 515 and the conductive material 514 is structured to produce the lattice parts 517 and / or the solid parts 518 of the thermally conductive structural elements 513.

[0185] As in Fig. As shown in Figure 57, the thermally conductive structural elements 513 can have lattice parts 517 which are produced on opposite sides of the die structure 304. The lattice parts 517 can be manufactured in all thermally conductive structural elements 513 that enclose the die structure 304, such as in portions of the thermally conductive structural elements 513 along all four sides of the die structure 304. The die structure 304, the thermally conductive structural elements 513, the passivation layer 502, the encapsulation material 228, the vias 226, the redistribution structure 230, the passivation layer 236, the UBMs 238, and the conductive connecting elements 240 collectively form a first package component 357. The first package component 357, the second package component 360, and the intermediate structures used to connect the second package component 360 to the first package component 357 (e.g.,the passivation layer 242, the conductive connecting elements 244, the underfill 258) collectively form a packaged semiconductor device 608.

[0186] As in Fig. As shown in Figure 58, parts of the thermally conductive structural elements 513 can have the lattice parts 517 (e.g., on the right side of the die structure 304), and parts of the thermally conductive structural elements 513 can have solid parts 518 (e.g., on the left side of the die structure 304). The lattice parts 517 and the solid parts 518 can be produced in any desired part of the thermally conductive structural elements 513. The die structure 304, the thermally conductive structural elements 513, the passivation layer 502, the encapsulation material 228, the vias 226, the redistribution structure 230, the passivation layer 236, the UBMs 238, and the conductive connecting elements 240 collectively form a first package component 358. The first package component 358, the second package component 360, and the intermediate structures used to connect the second package component 360 to the first package component 358 (e.g.,the passivation layer 242, the conductive connecting elements 244, the underfill 258), collectively form a packaged semiconductor device 610.

[0187] In some embodiments, such as those in the Fig. 57 and Fig. In the embodiments shown in Figure 58, the thermally conductive structural elements 513 can be segmented as described above with reference to Fig. 50C has been described, or the seed layer 515 of the thermally conductive structural elements 513 can be replaced by a thermal interface material, as described above with reference to the Fig. 54, Fig. 55 to Fig. As described in Section 56, gaps in the lattice parts 517 of the thermally conductive structural elements 513 can be filled with the encapsulation material 228. By manufacturing the thermally conductive structural elements 513 with the lattice parts 517 and filling the gaps in the lattice parts 517 with the encapsulation material 228, mechanical stress resulting from differences in the coefficients of thermal expansion (CTE) between the thermally conductive structural elements 513 and the encapsulation material 228 is reduced, thereby reducing package deformation, reducing device errors, and improving device performance. Furthermore, heat dissipation from active components of the device die 200 is improved by integrating the thermally conductive structural elements 513.This improves the device performance and reduces device errors caused by heat generated in the device die 200.

[0188] The Fig. Figures 59A to 60 show an embodiment in which heat dissipation structures comprise: an auxiliary die 210 attached to a front interconnect structure 120 of a device die 200, thermally conductive structural elements 507 or thermally conductive structural elements 513 attached to side faces of the device die 200, thermally conductive vias 141 fabricated in a rear interconnect structure 140 of the device die 200, and a thermally conductive cap 516 fabricated on the thermally conductive structural elements 507 / 513 and the auxiliary die 210. The auxiliary die 210 is an example of a front heat distributor fabricated in the device die 200 (e.g., a device die with nanoFETs fabricated according to the processes of Fig. The thermally conductive structural elements 507 / 513 are examples of lateral heat distributors that dissipate heat generated in the device die 200. The thermally conductive vias 141 are examples of thermally conductive dummy structural elements that dissipate heat generated in the device die 200. The thermally conductive cap 516 is an example of a thermally conductive cap heat distributor that dissipates heat generated in the device die 200. By providing the auxiliary die 210, the thermally conductive structural elements 507 / 513, the thermally conductive vias 141, and the thermally conductive cap 516, heat dissipation from the device die 200 is improved. This improves the device performance and reduces device errors caused by heat generated in the device die 200.

[0189] Fig. 59A shows the structure of Fig. 58, after the redistribution structure 230, the passivation layer 236, the UBMs 238 and the conductive connecting elements 240 have been produced; the first package component 358 has been turned over; and the support substrate 220 has been removed. In Fig. In section 59, a planarization process is performed, and a thermally conductive cap 516 is fabricated over the thermally conductive structural elements 513 and the auxiliary die 210. The planarization process can be performed on the vias 226, the encapsulation material 228, the passivation layer 502, the thermally conductive structural elements 513, and the auxiliary die 210. After the planarization process, the top surfaces of the vias 226, the encapsulation material 228, the passivation layer 502, the thermally conductive structural elements 513, and the auxiliary die 210 are essentially coplanar within the process variations. The planarization process can be, for example, a CMP, a grinding process, or the like.

[0190] The thermally conductive cap 516 can be manufactured using similar materials and processes as the thermally conductive cap 212, which is described with reference to Fig. 30 above. For example, the thermally conductive cap 516 can be produced by depositing a seed layer (not shown separately) over the vias 226, the encapsulation material 228, the conductive structural elements 513, the passivation layer 502, and the auxiliary die 210. A photoresist is produced and patterned on the seed layer. A conductive material is produced in openings of the photoresist on exposed portions of the seed layer. The photoresist and portions of the seed layer where the conductive material has not been produced are removed. The remaining portions of the conductive material and the seed layer form the thermally conductive cap 516. The thermally conductive cap 516 can be thermally connected to the thermally conductive structural elements 513 and the auxiliary die 210. In some embodiments, the thermally conductive cap 516 can be electrically floating.By providing the thermally conductive cap 516, heat dissipation from the device die 200 is improved. This improves device performance and reduces device defects caused by heat generated in the device die 200.

[0191] The Fig. 59B and Fig. 59C shows top-down views of the structure of Fig. 59A according to some embodiments. The Fig. 59B and Fig. Figure 59C shows, in particular, top-down views of the encapsulation material 228, the thermally conductive cap 516, the thermally conductive structural elements 507 / 513, the passivation layer 502, the device die 200, and the auxiliary die 210. Certain structural elements, such as the vias 226, are shown in the Fig. 59B and Fig. 59C has been omitted for the sake of simplicity and clarity. Fig. 59B thermally conductive structural elements 507, which, with reference to Fig. 51 above, identical or similar to the encapsulation material 228 discussed above, and the thermally conductive cap 516 has a single, coherent structural element. As in Fig. As shown in Figure 59B, the side faces of the thermally conductive cap 516 can be aligned with the side faces of the thermally conductive structural elements 507. The thermally conductive cap 516 can cover an area that includes the thermally conductive structural elements 507, the passivation layer 502, the device die 200, and the auxiliary die 210. By providing the thermally conductive structural elements 507 to enclose the auxiliary die 210, the device die 200, and the thermally conductive cap 516 as a single, coherent structural element, heat dissipation through the thermally conductive structural elements 507 and the thermally conductive cap 516 is improved. This improves device performance and reduces device failures caused by heat generated in the device die 200.

[0192] In Fig. 59C are the thermally conductive structural elements 513, which are referred to Fig. As discussed in Section 59A, the thermally conductive cap 516 has segments separated by gaps. The thermally conductive structural elements 513 also have segments separated by gaps. Although the thermally conductive structural elements 513 are shown to have nine solid parts 518 and a single lattice part 517, they can have any combination of solid parts 518 and lattice parts 517. Furthermore, the thermally conductive structural elements 513 can be continuous and can be segmented without adjacent segments being separated by gaps. The thermally conductive cap 516 can extend partially over the thermally conductive structural elements 513, the encapsulation material 228, the passivation layer 502, the device die 200, and the auxiliary die 210.

[0193] By manufacturing the thermally conductive structural elements 513 in segments, mechanical stress resulting from differences in the coefficients of thermal expansion (CTE) between the thermally conductive structural elements 513 and the encapsulation material 228 is reduced, thereby reducing package deformation, reducing device errors, and improving device performance. Similarly, by manufacturing the thermally conductive cap 516 in segments, mechanical stress resulting from differences in the coefficients of thermal expansion (CTE) between the thermally conductive cap 516 and a subsequently deposited underfill material (such as the underfill 258, which is described with reference to Fig. (discussed below in section 60) results in a reduction, thereby reducing package deformation, reducing fixture errors, and improving fixture performance. The provision of the thermally conductive structural elements 513 and the thermally conductive cap 516 improves heat dissipation from the fixture die 200. This improves fixture performance and reduces fixture errors caused by heat generated in the fixture die 200.

[0194] In Fig. In step 60, a second package component, 360, is connected to the first package component, 358. The processes that occur in Fig. 53 are carried out, are the same as or similar to the processes described in the Fig. 35, Fig. 53 and Fig. 56 above. As in Fig. As shown in Figure 60, the underfill 258 can be manufactured to enclose the thermally conductive cap 516. Although the thermally conductive cap 516 is shown separated from the substrate 248 by the underfill 258, in some embodiments the substrate 248 can be attached to the first package component 358 in contact with the thermally conductive cap 516. The first package component 358, the second package component 360, and the intermediate structures used to connect the second package component 360 to the first package component 358 (e.g., the passivation layer 242, the conductive connecting elements 244, the underfill 258) collectively form a packaged semiconductor device 612.

[0195] The thermally conductive structural elements 507 / 513 are heat dissipation structures fabricated on side faces of the die structure 304 and can be described as lateral heat distributors. The thermally conductive vias 141 are heat dissipation structures that provide a heat dissipation path from the device layer 109 of the device die 200 through the backside interconnect structure 140 to the thermally conductive structural elements 507 and can be described as thermally conductive dummy structural elements. The auxiliary die 210 and the thermally conductive cap 516 are heat dissipation structures fabricated on a front face of the device die 200. The auxiliary die 210 can be described as a front-facing heat distributor. The thermally conductive cap 516 can be described as a thermally conductive cap heat distributor.The thermally conductive structural elements 507 / 513, the thermally conductive vias 141, the auxiliary die 210 and the thermally conductive cap 516 can be placed in the packaged semiconductor device 612 of . Fig. The auxiliary die 210 is integrated to improve heat dissipation from active devices of the device die 200. This improves device performance and reduces device failures caused by heat generated in the device die 200. The auxiliary die 210 can also improve the structural and mechanical stability of the first package component 358.

[0196] Various embodiments can offer advantages. By integrating the different heat dissipation structures discussed above, the heat dissipation of the encapsulated (packaged) semiconductor devices can be improved. The heat dissipation structures can include front-facing heat spreaders, rear-facing heat spreaders, thermally conductive dummy structural elements, thermally conductive cap heat spreaders, lateral heat spreaders, or any combination thereof. Improving the heat dissipation of packaged semiconductor devices enhances device performance and reduces device failures (defects) caused by heat generated in active components within the packaged semiconductor devices.

[0197] According to one embodiment, a semiconductor package comprises: a semiconductor die with a substrate, a front interconnect structure on a front face of the substrate, and a rear interconnect structure on a rear face of the substrate opposite the front interconnect structure; an auxiliary die arranged on the front interconnect structure; a heat dissipation structure on the auxiliary die, wherein the heat dissipation structure is thermally connected to the semiconductor die and the auxiliary die; a redistribution structure on the rear interconnect structure opposite the substrate, wherein the redistribution structure is electrically connected to the semiconductor die; and an encapsulation material on the redistribution structure and adjacent to side faces of the semiconductor die, the auxiliary die, and the heat dissipation structure.In one embodiment, the semiconductor package further comprises a passivation material extending between the heat dissipation structure and the encapsulation material, wherein the heat dissipation structure includes a metal layer. In another embodiment, the heat dissipation structure includes an interposer between the backside interconnect structure of the semiconductor die and the redistribution structure, wherein the interposer has a thermally conductive via and wherein the thermally conductive via is electrically floating. In another embodiment, the heat dissipation structure surrounds side faces of the semiconductor die and the auxiliary die in a direction perpendicular to a main face of the auxiliary die. In another embodiment, the encapsulation material physically contacts the side faces of the heat dissipation structure.In one embodiment, the auxiliary die has a first thickness in a first direction perpendicular to a main surface of the auxiliary die, wherein the heat dissipation structure has a second thickness in the first direction, and wherein the ratio of the second thickness to the first thickness is from 40% to 60%. In another embodiment, the heat dissipation structure has a plurality of segments, wherein the encapsulation material extends between adjacent segments of the plurality of segments.

[0198] According to another embodiment, a packaged device comprises: a device die having: a gate structure over a semiconductor channel; a first source / drain adjacent to the gate structure and the semiconductor channel; a gate contact connected to a surface of the gate structure facing in a first direction; a front interconnect structure on the gate contact facing in the first direction, the front interconnect structure being connected to the gate contact; a first source / drain contact connected to a surface of the first source / drain facing in a second direction opposite to the first direction; and a rear interconnect structure on the first source / drain contact facing in the second direction, the rear interconnect structure being connected to the first source / drain contact; an auxiliary die,which is thermally connected to the device die; and a first heat dissipation structure that is thermally connected to the device die. In one embodiment, the auxiliary die comprises aluminum nitride. In one embodiment, the auxiliary die is arranged on the front interconnect structure in the first direction, and the first heat dissipation structure is arranged on the auxiliary die in the first direction. In one embodiment, the packaged device further comprises an insulating layer between the auxiliary die and the first heat dissipation structure, the insulating layer comprising silicon nitride. In one embodiment, the auxiliary die is arranged on the front interconnect structure in the first direction,The first heat dissipation structure is arranged on the rear interconnect structure in the second direction and includes an interposer die. In one embodiment, the auxiliary die is arranged on side faces of the device die in a third direction, perpendicular to the first and second directions. In another embodiment, the auxiliary die is connected to the device die by means of a thermal interface material.

[0199] According to yet another embodiment, a method comprises: providing a device die, wherein the device die has: a device layer; a front interconnect structure on a front face of the device layer; and a rear interconnect structure on a back face of the device layer; attaching an auxiliary die to the device die, wherein the auxiliary die is thermally bonded to the device die; attaching a heat dissipation structure to the device die, wherein the heat dissipation structure is thermally bonded to the device die; and encapsulating the device die, the auxiliary die, and the heat dissipation structure with an encapsulation material. In one embodiment, attaching the auxiliary die to the device die comprises fusion bonding the auxiliary die to the front interconnect structure.In one embodiment, attaching the heat dissipation structure to the device die includes hybrid bonding the heat dissipation structure to the rear interconnect structure. In another embodiment, attaching the heat dissipation structure to the device die includes plating the heat dissipation structure onto the auxiliary die opposite the device die. In another embodiment, attaching the heat dissipation structure to the device die includes plating the heat dissipation structure onto side faces of the device die and the auxiliary die. In another embodiment, attaching the heat dissipation structure to the device die includes plating the heat dissipation structure onto the device die, and encapsulating the heat dissipation structure includes producing the encapsulation material between adjacent parts of the heat dissipation structure.

Claims

[1] Semiconductor package containing: a semiconductor die (200) comprising a substrate (202), a front interconnect structure (120) on a front side of the substrate (202) and a rear interconnect structure (140) on a back side of the substrate (202) opposite the front interconnect structure (120); an auxiliary die (210) which is arranged on the front-side interconnect structure (120); a heat dissipation structure (212) on the auxiliary die (210), wherein the heat dissipation structure (212) is thermally connected to the semiconductor die (200) and the auxiliary die (210); a redistribution structure (230) on the rear interconnect structure (140) opposite the substrate (202), wherein the redistribution structure (230) is electrically connected to the semiconductor die (200); and an encapsulation material (228) on the redistribution structure (230), wherein the encapsulation material (228) encapsulates the semiconductor die (200), the auxiliary die (210) and the heat dissipation structure (212). [2] Semiconductor package according to claim 1, further comprising a passivation material extending between the heat dissipation structure (212) and the encapsulation material (228), wherein the heat dissipation structure (212) comprises a metal layer. [3] Semiconductor package according to claim 1 or 2, wherein the heat dissipation structure (212) has an interposer between the backside interconnect structure of the semiconductor die (200) and the redistribution structure (230), wherein the interposer has a thermally conductive via and wherein the thermally conductive via is electrically floating. [4] Semiconductor package according to one of the preceding claims, wherein the heat dissipation structure (212) surrounds side surfaces of the semiconductor die (200) and the auxiliary die (210) in a direction perpendicular to the main surface of the auxiliary die (210). [5] Semiconductor package according to any of the preceding claims, wherein the encapsulation material (228) physically contacts the side surfaces of the heat dissipation structure (212). [6] Semiconductor package according to any of the preceding claims, wherein the auxiliary die (210) has a first thickness in a first direction which is perpendicular to a principal surface of the auxiliary die (210), wherein the heat dissipation structure (212) has a second thickness in the first direction and wherein the ratio of the second thickness to the first thickness is from 40% to 60%. [7] Semiconductor package according to one of the preceding claims, wherein the heat dissipation structure (212) has a plurality of segments, wherein the encapsulation material (228) extends between adjacent segments of the plurality of segments. [8] Packaged device containing: a device die (200) comprising the following: a gate structure (109) over a semiconductor channel; a first source / drain (92) adjacent to the gate structure (109) and the semiconductor channel; a gate contact (114) that is connected to a surface of the gate structure (109) that points in a first direction; a front-side interconnect structure (120) on the gate contact (114) in the first direction, wherein the front-side interconnect structure (120) is connected to the gate contact (114); a first source / drain contact (112) connected to a surface of the first source / drain (92) that points in a second direction opposite to the first direction; and a rear interconnect structure (140) on the first source / drain contact in the second direction, wherein the rear interconnect structure (140) is connected to the first source / drain contact (112); an auxiliary die (210) which is thermally connected to the device die (200); a first heat dissipation structure (212) which is thermally connected to the device die (200), a redistribution structure (230) on the rear interconnect structure (140), wherein the redistribution structure (230) is electrically connected to the device die (200); and an encapsulation material (228) on the redistribution structure (230), wherein the encapsulation material (228) encapsulates the device die (200), the auxiliary die (210) and the heat dissipation structure (212). [9] Packaged device according to claim 8, wherein the auxiliary die (210) comprises aluminium nitride. [10] Packaged device according to claim 8 or 9, wherein the auxiliary die (210) is arranged on the front interconnect structure (120) in the first direction and wherein the first heat dissipation structure (212) is arranged on the auxiliary die (210) in the first direction. [11] Packaged device according to one of claims 8 to 10, further comprising an insulating layer between the auxiliary die (210) and the first heat dissipation structure (212), wherein the insulating layer comprises silicon nitride. [12] Packaged device according to one of claims 8 to 11, wherein the auxiliary die (210) is arranged on the front interconnect structure in the first direction, wherein the first heat dissipation structure is arranged on the rear interconnect structure in the second direction and wherein the first heat dissipation structure has an interposer die. [13] Packaged device according to any one of claims 8 to 12, wherein the auxiliary die (210) is arranged on side surfaces of the device die (200) in a third direction, which is perpendicular to the first direction and the second direction. [14] Packaged device according to claim 13, wherein the auxiliary die (210) is connected to the device die (200) by means of a thermal interface material. [15] Procedure with the following steps: Providing a device die (200), wherein the device die comprises the following: a device layer (109); a front-side interconnect structure (120) on a front side of the device layer (109); and a rear-side interconnect structure (140) on a rear side of the device layer (109); Attaching an auxiliary die (210) to the device die (200), wherein the auxiliary die (210) is thermally connected to the device die (200); Attaching a heat dissipation structure (212) to the device die (200), wherein the heat dissipation structure (212) is thermally connected to the device die (200); and Encapsulation of the device die (200), the auxiliary die (210) and the heat dissipation structure (212) with an encapsulation material (228) on a redistribution structure (230). [16] Method according to claim 15, wherein attaching the auxiliary die (210) to the device die (200) comprises melt bonding the auxiliary die (210) to the front interconnect structure (120). [17] Method according to claim 15 or 16, wherein attaching the heat dissipation structure (212) to the device die (200) comprises hybrid bonding the heat dissipation structure (212) to the rear interconnect structure (140). [18] Method according to any one of claims 15 to 17, wherein attaching the heat dissipation structure (212) to the device die (200) comprises plating the heat dissipation structure (212) onto the auxiliary die (210) opposite the device die (200). [19] Method according to any one of claims 15 to 18, wherein attaching the heat dissipation structure (212) to the device die (200) comprises plating the heat dissipation structure (212) onto side surfaces of the device die (200) and the auxiliary die (210). [20] Method according to any one of claims 15 to 19, wherein attaching the heat dissipation structure (212) to the device die (200) comprises plating the heat dissipation structure (212) onto the device die (200) and wherein encapsulating the heat dissipation structure (212) comprises producing the encapsulation material (228) between adjacent parts of the heat dissipation structure (212).

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