ASSEMBLY LOAD SENSOR BASED ON FUNCTIONAL DEVICE

Abstract

A process that features the following: Providing an excitation signal to an emitter of a first bipolar transistor device, wherein the transistor device has a first and a distinct second collector connected to a base region of the transistor device; In response to the excitation signal, measure a first collector current from the first collector of the transistor device; In response to the excitation signal, measure a second collector current from the second collector of the transistor device; Determining a magnitude difference between the first and second collector currents, wherein the magnitude difference corresponds to a charge carrier mobility property of the base region of the transistor device; and Determination of an indicator for the physical stress on the transistor device based on the magnitude difference between the first and second collector currents.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] This patent application claims the benefit of the priority of the preliminary US patent application with serial number 63 / 233,096 entitled “PACKAGE STRESS SENSOR”, filed on August 13, 2021 (file number 3867.802PRV), and the US patent application with serial number 17 / 816,979 entitled “PACKAGE STRESS SENSOR”, filed on August 2, 2022 (file number 3867.802US2), which are incorporated herein in full by reference. BACKGROUND

[0002] Semiconductors can be subject to mechanical stress, for example due to environmental influences such as temperature or humidity. Stress, or changes in stress, can affect the performance or sensitivity of semiconductor devices.

[0003] The Hall effect refers to a voltage difference that can be generated across an electrical conductor in the presence of a magnetic field. The direction of the generated voltage can be perpendicular to the electric current in the conductor and perpendicular to the magnetic field. A Hall sensor is a magnetic field sensor based on the Hall effect.

[0004] In one example, a Hall sensor can provide an electrical output signal proportional to a component of a magnetic field influencing the sensor. The Hall sensor can include a Hall element or a group of elements and a processor for receiving and interpreting signals from the element or elements. In another example, a Hall sensor has an integrated circuit housed in a package, and the sensor or its assembly may be subject to mechanical stress. When a Hall sensor is used to characterize a magnetic field, it may be desirable to eliminate the effects of mechanical stress on the sensor itself. Similarly, when a stress sensor is used to characterize a stress or a change in a stress, it may be desirable to eliminate any Hall effects that could influence or distort the stress indicator. SUMMARY

[0005] The inventors recognized, among other things, that one of the challenges to be solved is determining a suitable compensation for the assembly stress in packed integrated circuits. The inventors recognized that a solution could include or utilize a sensor designed to measure mechanical stress while simultaneously mitigating the effects of magnetic fields that could otherwise distort a stress measurement. The solution could include characterizing the direction and magnitude of the stress. This information about the direction and magnitude of the stress could then be used, in conjunction with another circuit arrangement, to counteract the influence of the stress on other circuit elements or performance parameters.For example, information about the direction and magnitude of the load can be used to counteract an error term in a voltage or current signal reference generator or to calibrate an offset for a converter circuit.

[0006] In one example, the solution may include or utilize a semiconductor Hall-effect sensor configured to provide information about the assembly stress. In this example, the sensor may comprise a Hall-effect plate and an excitation circuit. The excitation circuit can provide signals to the respective node pairs of the Hall-effect plate. A sensing circuit can receive information about a first electrical signal at a first node pair in response to a first segment of the excitation signal, and it can receive information about a second electrical signal at a second node pair in response to a second segment of the excitation signal. The first and second electrical signals may indicate a charge carrier mobility property of the semiconductor, which can be used to provide an indicator of the physical stress on the sensor.

[0007] In one example, the solution may include or utilize a semiconductor-based stress sensor comprising a bipolar transistor device with multiple (e.g., a first and a second) collector terminals. An excitation circuit may provide an excitation signal to a base-emitter junction of the bipolar transistor device, and an indicator of the physical stress on the semiconductor may be provided based on a relationship between the signals measured at the collector terminals in response to the excitation signal. In one example, the physical stress indicator may be based on a current deflection characteristic of a base region of the transistor device.

[0008] This summary is not intended to provide a complete or exhaustive explanation of the invention. The full description is included to provide further information about the present patent application. Brief description of the different views of the drawings

[0009] In order to easily identify the discussion of any particular element or action, the highest-ranking digit(s) of a reference sign refers to the number of the figure in which that element is first introduced. Fig. Figure 1 generally represents an example of a semiconductor wafer and its crystal planes. Fig. 2A and Fig. 2B generally represent examples of a rectangular Hall plate. Fig. 3A and Fig. 3B generally represent examples of the mechanical stress on a Hall plate. Fig. 4A and Fig. 4B generally represent examples of Hall effect plates with different orientations on a wafer. Fig. Figure 5 generally represents an example of a non-rectangular Hall plate for detecting a load. Fig. 6 represents an aspect of the subject matter in accordance with an embodiment. Fig. Figure 7A generally represents an example of a top view of a physical layout of a first bipolar transistor. Fig. Figure 7B generally represents an example of a cross-sectional view of a physical layout of the first bipolar transistor. Fig. Figure 7C generally represents an example of a schematic diagram of a differential signal measurement circuit. Fig. Figure 8A generally represents an example of a top view of a physical layout of a second bipolar transistor. Fig. Figure 8B generally represents an example of a cross-sectional view of a physical layout of a second bipolar transistor. Fig. Figure 9 generally represents an example of a reference generator circuit built on a semiconductor wafer. Fig. Figure 10 generally represents an example of a method which may involve the use of a bipolar transistor device to provide an indicator of physical stress. Fig. Figure 11 generally represents an example of a reference generator circuit that includes a split-collector bipolar transistor. Fig. Figure 12 is a block diagram that provides an example of a computing device capable of performing aspects of the various techniques discussed here. DETAILED DESCRIPTION

[0010] Integrated circuits (ICs) can be mounted or packed to help protect sensitive components from stress or environmental influences. However, such packing or mounting can be a source of mechanical stress for the semiconductor material within an IC. Mechanical stress can affect or alter circuit behavior, for example, by changing the mobility and scattering factor of charge carriers (such as electrons or holes). Such changes can contribute to drift or offset in parameters such as resistance, magnetic sensitivity, transistor behavior, or piezoelectric effects. In some cases, the mechanical stress may change over time due to external environmental factors or may be altered by long-term drift and material aging.

[0011] To compensate for assembly loads, a load sensor can be configured to detect the stress to which the devices on a specific chip or substrate are subjected. For example, transistors or ground resistors can be used to detect loads by measuring a change in electron mobility (e.g., for n-type materials) or hole mobility (e.g., for p-type materials). However, such devices can be sensitive to the presence of magnetic fields, which can introduce errors into the load measurements. In other words, the Lorentz force can cause a deflection of the current flow in a sensor, such as in the presence of magnetic fields. Furthermore, some load sensors are not configured to detect the direction of the load. Inventors have identified solutions to these and other challenges.

[0012] The inventors recognized that a solution to the load measurement task could include or utilize a sensor designed to measure mechanical load while simultaneously mitigating the effects of magnetic fields that might otherwise distort the load measurement. The solution could include characterizing the load's direction and magnitude. This load direction and magnitude information, in turn, could be used in conjunction with other circuitry to counteract the load's influence on other circuit elements or performance parameters. For example, load direction and magnitude information could be used to counteract an error term in a voltage or current signal reference generator or to calibrate an offset for a converter circuit.

[0013] In one example, the solution might include or utilize a Hall effect sensor. Using the results of multiple measurements, a circuit arrangement could be used to cancel errors due to magnetic fields, estimate sensitivity or drift, or provide appropriate load compensation signals. In another example, the solution might include or utilize multiple semiconductor layers, such as a bipolar transistor with multiple collectors (or a single collector that is forked or further separated to isolate leads). Information about the respective current densities in the different collectors could be used to characterize the direction or magnitude of loads in the assembly containing the transistor.In some examples, the transistor may form part of a reference generator circuit or be used to provide an offset signal to correct another reference generator circuit.

[0014] The various solutions discussed here offer several advantages over previous load sensors. For example, compared to measuring absolute mobility as a resistance or transistor current, using off-diagonal measurements of mobility components in a Hall plate can provide more information about the magnitude and direction of load components. Furthermore, first-order temperature compensation can be achieved by taking the ratio between the off-diagonal component and the absolute resistance. Additionally, the influence of neighboring magnetic fields can be compensated for using two measurements to cancel out the Hall effect voltage.

[0015] Fig. Figure 1 shows a general example of Miller indices for a crystal structure. A semiconductor wafer, e.g. containing silicon, can be cut from a silicon crystal rod such that the wafer surface coincides with a crystallographic plane. Fig. Figure 1 shows a top view of such a semiconductor wafer, which has been cut in the plane designated

[100] and has a “primary face” that indicates the specific crystal orientation. Some wafers have a secondary face to indicate doping of the wafer (e.g., as n- or p-type). The principal crystallographic directions in the wafer plane are shown in Fig. 1 identified. In one example, the circuit structures on a wafer can be arranged such that the side edges or walls of the circuit extend parallel or perpendicular to the wafer surface.

[0016] According to the convention using Miller indices, plane

[110] extends perpendicular to the primary surface and plane

[110] extends parallel to the primary surface. Plane

[010] extends at an angle of +45° and plane

[100] extends at an angle of -45° with respect to the

[110] direction.

[0017] In the example of Fig. 1 defines an angle ϕ with respect to the

[110] plane. The circuit structures built on the

[100] wafer are generally positioned such that the vertical structures extend in the direction ϕ = 0° and the horizontal structures extend in the direction ϕ = 90°. In this orientation, the primary surface can be considered to be parallel to the x-axis, and the edges of the chip (or circuit structures) are generally parallel to the x- and y-axes. In this example, the crystal planes

[100] and

[010] correspond to the diagonal directions of the structures.

[0018] In general, silicon crystals with a

[100] configuration are widely available and commonly used for the fabrication of integrated circuit devices. Accordingly, in the following discussion, it is assumed that a

[100] -type material is used unless specifically stated otherwise. Furthermore, those skilled in the art recognize that other materials may be used in a similar manner.

[0019] Conventional load sensors, such as those with a resistive bridge, can be affected by magnetic fields, which can cause errors in the measured load signal. The inventors recognized that a better way to measure loads could incorporate or utilize a Hall plate, which could, for example, have a generally symmetrical crystalline structure with multiple signal contacts or nodes. Different pairs of nodes can be excited or preloaded by appropriate signals, and the response signals from these different node pairs can be measured. The response signals can then be analyzed together to determine the mobility or deflection characteristics of the electrons (or holes) in the Hall plate.Using the specific deflection characteristic, more accurate information about the assembly load can be determined, while simultaneously eliminating the effects of the Hall effect or the influence of any magnetic field.

[0020] In one example, a Hall plate features a doped semiconductor device with a specific width, length, and thickness. A conventional Hall plate is generally rectangular or square and has two pairs of contacts or nodes: one pair is used for preloading, and the other is used for sensing or measuring. The nodes are located at the corners of the rectangular plate. Generally, a Hall plate is symmetrical about each of the axes connecting the respective node pairs. Hall plates can have other, non-rectangular shapes, such as crosses, hexagons, or others that exhibit symmetry along multiple axes.

[0021] Fig. 2A and Fig. Figure 2B represents general examples of a rectangular first Hall plate 202. The first Hall plate 202 can have a crystalline structure, for example, it can have an epitaxial layer that can be grown or deposited on a substrate such as silicon. In general, the first Hall plate 202 can have one or more layers formed with a precisely defined orientation relative to an orientation of the substrate or seed layer.

[0022] In one example, and independent of mechanical stress effects, the effect of a magnetic field on a Hall plate can be modeled as a bridge. In unloaded silicon, for instance, a Hall voltage measured across a Hall plate can be a function of the preload current applied to the plate and the plate's resistance characteristics.

[0023] To illustrate, we show Fig. 2A and Fig. 2B Examples of the rectangular first Hall plate 202 under different preload conditions. The first Hall plate 202 contains two pairs of oppositely oriented nodes at its corners, a first node pair p1+ and p1-, and a second node pair p2+ and p2-. Fig. Figure 2A shows the first Hall plate 202, which is preloaded by a current signal I applied between nodes p2+ and p2-, and Fig. Figure 2B shows the first Hall plate 202, which is preloaded by the current signal I applied between nodes p1+ and p1-.

[0024] When a Hall plate, such as the first Hall plate 202, is preloaded by an input signal, its sensitivity is a function of the magnitude of the preload signal, a correction factor defined by the geometry of the specific plate, and the plate's resistivity characteristic. The plate's resistivity characteristic, sometimes called the Hall coefficient, is (for an n-type semiconductor) a function of the electron concentration and the Hall factor, and the Hall factor depends, among other things, on temperature and scattering.

[0025] In one example, an ideal Hall plate can be modeled as a symmetrical Wheatstone bridge, which provides a uniform output voltage in the absence of a magnetic field under stable preload conditions. However, a real Hall plate exhibits a variable output voltage due to an offset that can be caused by a magnetic field. This offset can be measured and used to identify or characterize loads on the Hall plate, as further explained here.

[0026] In one example, a Hall plate voltage, V H in the examples of Fig. 2A and Fig. 2B, linearly dependent on the magnitude of the preload signal and can be modeled as: [V1V2]=[RH11RH12RH21RH22][I1I2] where V1 is the voltage between nodes p1+ and p1-, and V2 is the voltage between nodes p2+ and p2-, and where I1 is the current applied between nodes p1+ and p1-, and I2 is the current applied between nodes p2+ and p2-. The voltages V1 and V2 are thus functions of the preload current input signal and the Hall coefficients, or R. Hxx , which describe the resistance behavior of the Hall plate. In other words, the values ​​of the Hall coefficients can be used as a substitute for, or represent, the influence of an external magnetic field on the Hall plate.

[0027] In the example of Fig. 2A is the Hall voltage V H = V1 = R H12 I2. In example of Fig. 2B is V H = V2 = R H21I1. In the example of the first Hall plate 202, the impedance matrix describing the system is antisymmetric in the presence of a magnetic field, and therefore the Hall coefficients corresponding to orthogonal axes can be equal and opposite. That is, R H12 = -R H21 due to the Hall effect.

[0028] In one example, and independent of magnetic field effects, the effect of a mechanical load on a Hall plate can be modeled similarly as a bridge. Fig. 3A and Fig. Figure 3B presents general graphical examples of the mechanical stress on a Hall plate, such as the first Hall plate 202, and its influence on specific off-diagonal mobility properties of the Hall plate. The properties of the first Hall plate 202 can be optimized with respect to its sensitivity to stress, for example, to adapt it to another IC device (e.g., with respect to doping or material type, physical dimensions, etc.) for which stress compensation is desired.

[0029] In unloaded silicon, the electron mobility in the Hall plate can be modeled as a scalar function of the applied preload or the electric field. That is to say: [J1J2]=qμ[E1E2] where J is the electron mobility, E is the applied electric field, q is the electron charge, and µ is a constant based on the properties of silicon itself when unloaded. Under load, the electron mobility can be described by a tensor relation. For example: [J1J2]=q[μ11μ12μ21μ22][E1E2] where µ corresponds to the off-diagonal mobility components of electrons (e.g., for an n-type semiconductor) or holes (e.g., for a p-type semiconductor) or the influence of loads across the entire Hall plate. These off-diagonal mobility coefficients can be measured indirectly, for example, using a bridge model similar to that in Equation 1. That is: [V1V2]=[RS11RS12RS21RS22][I1I2] where R SxxThe coefficients of the resistance tensor, which describe the behavior of the Hall plate under load, are shown. Loads can cause a change in the charge carrier mobility tensor that describes the plate. That is, the resistance of the plate can become direction-dependent, and the off-diagonal components of the mobility tensor cause a current deflection.

[0030] In one example, the off-diagonal coefficients µ can be xx Provide information about the magnitude and direction or sign of the applied load. Furthermore, due to the reciprocity of electron mobility, the off-diagonal coefficient µ can be assumed to be 12 equal to µ 21 is and accordingly R S12 equal to R S21 This reciprocity relationship can be used to determine the magnitude and direction of the mechanical load.

[0031] In an example that features or uses the first Hall plate 202 to characterize the mechanical load, multiple measurements of the first Hall plate 202 can be used to cancel out the influence of magnetic fields on the load. For example, a first measurement can be the measurement of V1 using the in Fig. exhibit the configuration shown in 3A, and a second measurement can be the measurement of V2 using the configuration shown in Fig. exhibit the configuration shown in Figure 3B. The results of the first and second measurements can be processed together to eliminate the components specifying the magnetic field and to isolate the component specifying the load. For example: R12=RS12+RH12 R21=RS21+RH21

[0032] From the preceding discussion, R emerges. H12 = -R H21, and R S12 = R S21Accordingly, the component representing the load can be expressed by R. S12 = R S21 = R 12 + R 21 This can be specified. In other words, the influence of a disturbing magnetic field can be canceled out by summing the results from the first and second measurements, and the remaining load coefficient can correspond to the magnitude of the load. Furthermore, information about the orientation of the Hall plate used in the first and second measurements, as well as the sign of the component RS12, can be used to characterize the direction of the load.

[0033] The sensitivity to or influence of stresses can depend, at least in part, on the orientation of a Hall plate relative to the crystal orientation of the Hall plate substrate. For example, a Hall plate can be used to detect the magnitude and direction of mechanical stresses in or along several different axes, such as by using multiple plates with different orientations on a substrate. Accordingly, multiple Hall plates can be used together to provide more information about the overall stress characteristics of a particular assembly. With each Hall plate, multiple measurements can be performed to characterize the assembly's stress and to eliminate the influence of any magnetic fields.

[0034] Fig. 4A and Fig. 4B generally represent examples that exhibit Hall plates with different orientations on the same first wafer 402, which, for example, has a doped silicon substrate. For example, Fig. Figure 4A represents an example of a second Hall plate 404, which has a first orientation on the first wafer 402, and Fig. Figure 4B shows an example of a third Hall plate 406, which has a second orientation on the same first wafer 402. For clarity, the third Hall plate 406 is shown in Figure 4B, taken from the view of the first wafer 402. Fig. 4A omitted, and the second Hall plate 404 is shown from the view of the first wafer 402 in Fig. 4B omitted. The second Hall plate 404 and the third Hall plate 406 can be located at any position on the first wafer 402, but preferably they could be located close to each other.

[0035] In the example of Fig. 4A and Fig. 4B The first wafer 402 has a specific crystal orientation, wherein, for example, the second Hall plate 404 and the third Hall plate 406 are provided with different orientations with respect to the plane

[100] of the first wafer 402. The second Hall plate 404 can be configured to measure the deviation of the electron mobility in one plane of the first wafer 402, and the third Hall plate 406 can be configured to measure the deviation of the electron mobility in another plane of the first wafer 402. Accordingly, the second Hall plate 404 and the third Hall plate 406 can be used together to provide information about stresses on the first wafer 402 in several different axes corresponding to the different planes.

[0036] Fig. Figure 5 provides a general example of a load sensor system 500 comprising an octagonal Hall plate 502 provided on a

[100] plane of a wafer. The load sensor system 500 may include a preload signal source coupled to the octagonal Hall plate 502 using a preload signal multiplexer circuit 504, and the load sensor system 500 may include a measurement circuit coupled to the octagonal Hall plate 502 using a measurement signal multiplexer circuit 506.

[0037] The octagonal Hall plate 502 has four pairs of nodes (e.g., p1 + / -, p2+ / -, p3+ / -, and p4+ / -), each corresponding to one of its sides. The nodes can be addressed separately by the preload signal multiplexer circuit 504 to receive corresponding excitation signals, and the nodes can be addressed separately by the measurement signal multiplexer circuit 506 to measure corresponding responses to the excitation signals. Multiple excitation signals can be provided, and corresponding multiple response signals can be measured, to characterize the mechanical stress on the octagonal Hall plate 502 in one or more directions, and the effect or influence of any magnetic fields can be canceled out.

[0038] For example, an off-diagonal load resistance or load coefficient for a first plane direction can be specified by: 2RS13=R13+R31

[0039] The external diagonal load resistance or load coefficient for a second plane direction (e.g. rotated by 45 degrees with respect to the first plane direction) can be specified by: 2RS24=R24+R42

[0040] In one example, equations 7 and 8 can be used together to characterize the mechanical load without the influence of a magnetic field in any direction. For instance, the load in any direction can be described using the off-diagonal load components identified in equations 7 and 8 as a linear combination of C1R. S13 + C2R S24 provided, where C1 and C2 are empirically determined coefficients, such as those that can be derived from a load calibration procedure.

[0041] Fig. Section 6 provides a general example of a first method 600, which may involve using a Hall-effect plate sensor to provide information about the physical stress on the sensor or on a semiconductor that incorporates the sensor. In block 602, the first method 600 involves providing an excitation signal to first nodes of a Hall-effect plate that incorporates the sensor. The Hall-effect plate may have a crystalline structure (e.g., a doped semiconductor) provided on or coupled to a substrate that is common to one or more other parts or components whose stress is to be measured. The Hall-effect plate may have a structure symmetrical about at least two axes.The first nodes can be located on opposite sides or border regions of a first axis, and the second nodes can be located on opposite sides or border regions of a second axis. In one example, the first and second axes can be orthogonal.

[0042] In block 604, the first procedure 600 can involve measuring a first response signal at the second node of the Hall plate. In one example, block 602 and block 604 are executed simultaneously, so that the excitation signal in block 602 is provided at the same time as the response in block 604 is measured.

[0043] In block 606, the first procedure 600 involves providing an excitation signal to the second nodes of the Hall plate. In block 608, the first procedure 600 involves measuring a second response signal at the first nodes of the Hall plate. In an example, the same excitation signal can be used at different times for block 602 and for block 606. That is, a voltage or current stimulus signal with first signal properties (e.g., amplitude, duration, waveform morphology, etc.) can be provided to the first nodes to elicit the first response signal, and a stimulus signal with the same first signal property can be provided to the second nodes to elicit the second response signal from the Hall plate.

[0044] In Block 610, the first procedure 600 may involve determining a relationship between the first and second response signals measured in Block 604 and Block 608. This relationship may provide information about the off-diagonal charge carrier mobility property of the Hall plate, which in turn may be used as a substitute for the load on the Hall plate and the semiconductor containing the Hall plate. In one example, Block 610 involves determining a magnitude difference between the first and second response signals. Another example involves summing information about the magnitudes of the first and second response signals and determining a resistivity characteristic of the Hall plate. The resistivity characteristic may be a tensor describing nonlinear properties of the Hall plate.

[0045] In Block 612, the first method 600 may include determining an indicator for the physical stress for the Hall plate sensor or for a semiconductor incorporating the sensor, based on the relationship determined in Block 610.

[0046] Hall sensors are generally optimized in terms of their material composition or orientation to receive or detect a magnetic field. For example, a Hall sensor or Hall plate might incorporate a semiconductor with high charge carrier mobility to help maximize its sensitivity to the influence of small magnetic fields. However, inventors have recognized that a load sensor does not necessarily require or utilize materials with the highest mobility. Instead, it may be desirable to provide a load sensor that is shaped or configured similarly to, or identical in shape to, a device whose effect on the load is desired. For example, it may be desirable to have a device configured similarly or identically (e.g., in terms of size, shape, material composition, location of the component or wafer, etc.) for a specific functional device or IC.) to use as a sensor to detect the load.

[0047] In one example, a layered semiconductor can be used as the special device and sensor. For instance, a bipolar transistor device can be used. The deflection in the layered device can affect the magnitude or direction of the current flow. This deflection can be detected and used as a substitute for or indicator of the mobility in the substrate, which in turn can indicate mechanical stress.

[0048] For example, a bipolar transistor can be equipped with a split collector or multiple collector terminals. The deflection of current between the different collector terminals can cause a voltage difference across the base region of the transistor. This voltage difference, which can manifest as a measurable current difference between the collectors, indicates the transverse mobility of the device.

[0049] Fig. Figure 7A generally represents an example of a top view of a physical layout of a bipolar transistor or split collector first BJT device 700. Fig. Figure 7B generally represents an example of a cross-sectional view of the layout of the first BJT device 700 with split collectors. The representation in Fig. Figure 7B shows a schematic diagram of the first BJT device 70, which illustrates the split collectors. The first PNP BJT device 700 has connections for the emitter, the base, and the two collectors (collector 1 and collector 2), as well as for a body preload signal (VDD). In the example of Fig. 7A and Fig. Figure 7B shows the first BJT device 700 featuring a deep p-tub (DPW) connected to the respective different collector terminals, and the base of the device is implemented with a high-voltage n-tub (HVNM). The first BJT device 700 further features a buried n-type layer (NBL) and various other n-tub (NW) and p-tub (PW) regions. In some examples, the DPW could have a slot or other break in the DPW layer between and separating the collector current paths.

[0050] Fig. Figure 8A generally represents an example of a top view of a physical layout of an NPN bipolar transistor or a second BJT device 800 with split collectors. Fig. Figure 8B generally represents a cross-sectional view of the layout of the second BJT device 800 with split collectors. In the second BJT device 800 example, the buried N-type layer may have a slot or break that increases the resistance between collector terminals C1 and C2. In some examples, a relatively less sensitive current-sensing circuit can be used to measure the collector currents if the internal resistance between the collector terminals is increased.

[0051] If a mechanical load is present, the lateral movement behavior of the first BJT device 700 or the second BJT device 800 can be detected as a differential signal between the collector connections. Fig. Figure 7C shows a general schematic diagram of an amplifier circuit that can be used to measure the differential signal as a voltage signal Vs. In other words, the load-induced deflection current µ12 can cause a voltage difference or irregularity across the base region (e.g., mainly across the base region), such as in the horizontal plane of the BJT device. As a result, a corresponding base-emitter voltage difference exists, and a current flows irregularly or unevenly to the different collector terminals, collector 1 (C1) and collector 2 (C2).

[0052] In one example, the current signals or the differential current signal can be relatively difficult to measure due to the small difference between the signals at the respective collector terminals. One solution to this measurement problem can be the provision of high-resistance collector regions. High-resistance collectors can be achieved, for example, by disconnecting the deep p-trough region (DPW region) in the first BJT device 700, by disconnecting the buried N-type layer in the second BJT device 800, or by increasing the width of the emitter region.

[0053] The current behavior in the base region can be modeled using a tensor relationship between mobility and charge concentration. For example: [J1J2]=qD[μ11μ12μ21μ22][∂1N∂2N] where J1 is the current in the horizontal (deflected) direction, J2 is the current in the vertical (e.g., emitter-to-base region) direction, q is the electron charge, D is a diffusion constant, µ ij where N is the charge carrier mobility (electron or hole mobility), N is the charge concentration, and ∂ j N is the charge concentration gradient.

[0054] In this example, the charge is injected vertically downwards from the emitter terminal towards the base region. Accordingly, ∂1N = 0 and ∂2N > 0. If there is no load on the first BJT device 700, the charge carrier mobility is, for example, zero (e.g., µ). 21= 0), and the current flows vertically (e.g., J1 = 0). Under load, however, the current is deflected (e.g., J1 ≠ 0), and a difference in collector current in the first BJT device 700 can be detected at the terminals of collector 1 and collector 2 (e.g., using the differential sensor in Fig. 7C).

[0055] In one example, the first BJT device 700 or the second BJT device 800, or variations thereof, can incorporate a section of a reference generator circuit, such as a voltage reference generator or current reference generator. A reference generator circuit can be used to provide a reference signal for use in various circuits. For example, a reference signal can be used to provide a stable and accurate preload signal for use by various components or systems, such as amplifiers, comparators, analog-to-digital converters, digital-to-analog converters, oscillators, or phase-locked circuits.

[0056] Several different types of reference generator circuits can be provided. Some examples of the different types include a bandgap reference signal generator, a MOS Vth differential reference signal generator, and a work-effect differential reference signal generator. A bandgap reference signal generator can be provided using bipolar junction transistor (BJT) devices, such as the first BJT 700 or the second BJT 800. The bandgap generator can have voltage sources with positive or negative temperature coefficients, so that when the sources are summed, the temperature dependence of the devices can be canceled out. However, a bandgap reference signal generator can have some limitations, such as susceptibility to substrate noise or load.When the multi-collector BJT device is used in a reference signal generator, any offset due to assembly loading can be detected and attenuated, for example, using information about the differential current signals at the shared collector terminals. In other words, the multi-collector BJT device can incorporate one or more devices that include a bandgap-type reference signal generator, and information about the BJT device's loading can be acquired, for example, using a time-division multiplexing technique with the operation of the reference generator itself.

[0057] In other examples, a BJT-based reference generator circuit may include one or more transistors, and the first BJT device 700, the second BJT device 800, or another multi-collector BJT device may be provided as a clone or replica device for one or more of the transistors in the generator circuit. The BJT device may be physically located near or adjacent to one or more transistors in the reference generator circuit, allowing information about the load on the BJT device to be acquired in real time with the operation of the reference generator circuit. In one example, multiple instances of a multi-collector BJT device may be physically located around or adjacent to different sides of other components of a reference generator.Each of the multiple instances can, for example, be used separately to characterize a load that may unevenly affect the devices containing the generator circuit due to the different physical locations of such devices on the assembly or substrate that has the generator.

[0058] In alternative examples for detecting loads in or around a bandgap-type reference signal generator, current flow through multiple paths in a clamped resistor can be used instead of a multi-collector BJT device. In this example, a clamped resistor can be made of the same material as a base region of a bipolar transistor in the generator circuit. That is, if the bandgap circuit uses an NPN transistor with a p-type base, the clamped resistor can be made of p-type material; if the bandgap circuit uses a PNP transistor with an n-type base, the clamped resistor can be made of n-type material.

[0059] Fig. Figure 9 generally represents an example of a layout 900 for a first IC wafer 902. The first IC wafer 902 can have a first reference generator circuit 904 and a second reference generator circuit 906. Both the first reference generator circuit 904 and the second reference generator circuit 906 can have a transistor-based reference generator circuit (e.g., of the bandgap type) that includes or uses multiple transistors, resistors, or other IC-based components to generate a reference current signal or a reference voltage signal. Sections of the first IC wafer 902 can be cut and packed separately.

[0060] In one example, the first IC wafer 902 has one or more load sensor circuits configured to measure the physical load in different areas of the first IC wafer 902. For example, the first IC wafer 902 can have a first component 910 that has a first load sensor 908a near the first reference generator circuit 904 and a second load sensor 908b near the first reference generator circuit 904. That is, the first reference generator circuit 904 can have or use multiple load sensors that share a common substrate with the reference generator itself, e.g., on the same component. In the example of Fig. In Figure 9, the first load sensor 908a and the second load sensor 908b are provided adjacent to the respective sides or side regions of the circuit arrangement comprising the first reference generator circuit 904. In one example, the first reference generator circuit 904, the first load sensor 908a, and the second load sensor 908b comprise a section of the first IC wafer 902, which may be packed together.

[0061] The first load sensor 908a or the second load sensor 908b can each have transistor devices that are the same size or shape as the transistor devices that comprise the first reference generator circuit 904. That is to say, the first load sensor 908a or the second load sensor 908b can have devices that are clones or replicas of one or more devices in the first reference generator circuit 904. For example, the devices can have the same or substantially the same width, length, material type, or doping characteristics. The devices can be arranged close to each other or side by side so that they can be nearly identical with respect to process-related variations or inconsistencies.

[0062] In one example, the first reference generator circuit 904 includes, or may be coupled to, a processor circuit configured to receive reference signal information from, for example, a bandgap-type reference generator and to receive one or more correction signals from the first load sensor 908a and the second load sensor 908b. The processor circuit may use the one or more correction signals to update or adjust the reference signal information from the reference generator to provide a load-corrected reference signal. The load-corrected reference signal may be a voltage or current reference signal that is unaffected by the influence of assembly loading or deformation of the first IC wafer 902 or of an assembly comprising the first reference generator circuit 904, the first load sensor 908a, and the second load sensor 908b.

[0063] In one example, the second reference generator circuit 906 includes a third load sensor 908c. The third load sensor 908c can itself comprise a section of the second reference generator circuit 906. That is, the second reference generator circuit 906 can be a transistor-based reference generator circuit, and the third load sensor 908c can include a transistor that is used by the second reference generator circuit 906 to generate a reference signal. In one example, the second reference generator circuit 906 includes a multiplexer circuit configured to use the third load sensor 908c to generate the reference signal and to generate a load-indicating correction signal for appropriate time intervals.The second reference generator circuit 906 can be configured to provide a voltage-corrected reference signal based on information from the third load sensor 908c about the load on the third load sensor 908c.

[0064] In other words, the reference circuits can be constructed in various ways. In one example, a reference circuit can have components that are separate from the components of the load-sensing circuit. A load-indicating signal generated by the load-sensing circuit can be used to compensate for the load sensitivity of the reference circuit. In another example, a reference circuit can have a split-collector transistor that functions both as part of a reference signal generator and as part of a load sensor. In a discrete-time implementation, the split-collector transistor can be used as a load sensor during specific time intervals and as a component in a reference signal generator at other time intervals.In a continuous-time implementation, the split-collector transistor can be used simultaneously as a reference generator and a load sensor. In this example, the transistor's base-emitter voltage can represent a section of the reference generator circuit, and at the same time, a difference in the collector current can be measured. This difference is used to generate a load-indicating signal, which can then be used to compensate for load effects on the generated reference signal.

[0065] Fig. Section 10 provides a general example of a second method 1000, which may involve the use of a transistor device to provide an indicator of physical stress. In section 1002, the second method 1000 involves the provision of a bipolar junction transistor (BJT) device with multiple collectors or a forked collector. That is, section 1002 may involve the construction of a BJT device having a collector region connected to two or more discrete terminals. An example of a forked or split-collector BJT device is shown in Fig. 7A and Fig. 7B provided. The BJT device with a forked collector may be subject to current deflection in the base region of the device, for example, when the device is under mechanical stress. Although it is sometimes referred to here as 'forked', it should be understood that the collector may have more than two discrete branches.

[0066] In Block 1004, the second method 1000 involves providing an excitation or drive signal to an emitter of the BJT device. Under suitable preload conditions, the BJT device can be switched on and conduct current from the emitter through the base region and to each of the first and second collector regions and their corresponding first and second collector terminals. Although the examples discussed here feature a two-collector BJT device, devices with more than two collectors can be used similarly. For example, a four-collector bipolar transistor device can be used to identify a load along two different axes.

[0067] In Block 1006, first and second response signals can be measured at the first and second collector terminals, respectively, in response to the excitation signal. Under the influence of assembly deformation or substrate stress, the current flow through the base region of the BJT device may be interrupted or uneven. Accordingly, the response signals may exhibit different magnitude characteristics, which can be analyzed and used to provide information about the magnitude and / or direction of the assembly stress. For example, the second method 1000 in Block 1008 may involve determining a current difference between the first and second response signals. Based on this magnitude difference, an indicator of the physical stress can be provided.Based on the determined current difference, the second method 1000 in block 1010 can provide an indicator for the physical stress on the BJT device.

[0068] In one example, the BJT device in the second method 1000 can be used in or with a reference generator circuit, such as a voltage or current signal generator circuit. In block 1012, the second method 1000 can provide a correction signal for a reference generator circuit based on the physical stress indicator from block 1010. That is, block 1012 can provide the use of the physical stress indicator to provide information about a correction for a reference generator circuit where one or more components of the reference generator circuit are subjected to the same or a similar stress as the BJT device.In some examples, the BJT device is a clone or replica of one or more devices in the reference generator circuit and / or is physically located near one or more devices in the reference generator circuit.

[0069] In one example, the reference generator circuit in block 1014 can include or utilize the BJT device itself. For instance, a base-emitter voltage characteristic (Vbe) of the BJT device can be used, e.g., together with information about a Vbe characteristic of a second device loaded with a different current density, to provide a reference signal, or it can be used by the reference generator circuit to provide a component of another reference signal.

[0070] Fig. Figure 11 provides a general example of a reference generator circuit 1100. The reference generator circuit 1100 features a load-immune voltage reference generator with a PNP-BJT device configured as a load sensor. The reference generator circuit 1100 includes a proportional-to-absolute-temperature (PTAT) voltage generator (left) and a PNP-VBE generator (right). The reference generator circuit 1100 features various amplifier circuits (labeled I0, I1, I2, I3) and a programmable gain amplifier (PGA) that can be chopped to increase accuracy and eliminate drift.

[0071] In one example, the 1100 reference generator circuit features a high-precision PTAT voltage generator comprising transistors Q1 and Q2, amplifier circuits I0, I1, and I2, transistors MN1, MN2, and MP1, and resistors R1-R6. Amplifier circuit I0 provides a PTAT voltage across R3 by forcing equal collector currents in transistors Q1 and Q2. The base current of Q1 is canceled out by the loop formed by amplifier circuit I1 and transistor MN2, and consequently, the voltage drop across R5 can be considered proportional to the absolute temperature without base current error. In this example, the cancellation of the base current of Q1 eliminates errors due to beta variations as a function of load, temperature, and process variation. Amplifier circuit I2 is configured to enforce that the collector currents of transistors Q1 and Q2 are proportional to the absolute temperature.

[0072] In one example, in addition to any assembly load on the reference generator circuit, 1100 silicon dioxide particles in the molding compound used in plastic assemblies can create point loads on the device surface. In some cases, if a silicon dioxide particle exerts a load directly above transistor Q1, the voltage reference may exhibit anomalous performance over temperature. To reduce the effects of these or other local loads, the PTAT voltage generator can change the position of transistor Q1, for example, using dynamic element matching (DEM).

[0073] The PNP VBE generator of the reference generator circuit 1100 can include transistor Q3 and can, for example, be a multi-collector PNP device, such as the first BJT device 700, the second BJT device 800, or another multi-collector BJT device. The VBE generator can further include a control loop, which may include amplifiers I3 and I4. The respective collector currents in transistor Q3 can be detected by the voltage drops across resistors R8-R10, and the PGA can amplify the difference between any two collector currents selected by a multiplexer (MUX). In this example, the output of the PGA can be proportional to the combination of load effects and an initial impedance mismatch of the device. Changes in these differential signals over time can be used to compensate for load effects that manifest in the reference voltage.In one example, amplifier circuit 14 provides a virtual diode connection for transistor Q3 without introducing base current errors. The positive input of amplifier 14 can be implemented with a split MOS input pair to, for example, average all voltage drop signals across resistors R8-R10, instead of as shown in reference generator circuit 1100. The amplifier loop, which includes amplifier I3 and transistor MP2, can control the total collector current flowing through transistor Q3 and ensure that it is proportional to the absolute temperature.

[0074] An analog-to-digital converter (ADC) circuit can be used to measure the three differential signals {VPTAT, AGND}, {PNP VBE+, PNP VBE-}, and {STRESS, AGND} to provide an implicit voltage reference signal for system calibration. In some examples, adding the differential PNP-VBE measurement to a scaled PTAT voltage generates a temperature-compensated first-order voltage, which can be load-compensated using the measured difference in collector currents.

[0075] Fig. Figure 12 is a diagrammatic representation of a machine 1200 in which instructions 1208 (e.g., software, a program, an application, an applet, an app, or other executable code) can be executed to cause the machine 1200 to perform one or more of the methodologies discussed herein. For example, the instructions 1208 can cause the machine 1200 to perform one or more of the procedures described herein, such as, among others, generating or providing excitation signals, measuring response signals, coordinating measurement times or operations of a multiplexer circuit, calculating tensor relations, providing indicators of physical stress for stress sensors, or generating a correction signal for use in a reference generator circuit, a converter circuit, or other circuitry.Instructions 1208 transform the general, unprogrammed machine 1200 into a specific machine 1200 that is programmed to perform the described and illustrated functions in the manner described. The machine 1200 can operate as a standalone device or can be coupled (e.g., networked) with other machines to, for example, coordinate actions or functions across different circuits. In some examples, a mixed-signal circuit implementation using analog-to-digital converter (ADC) and / or digital-to-analog converter (DAC) circuits can be used to measure and generate the analog signals that can be used to control the reference and load sensing circuit arrangement discussed here, while, for example, most of the signal processing is performed using digital technology.In other examples, all the required signal processing in the current, charge and / or voltage domains may feature or use analog signal processing techniques.

[0076] In a networked deployment, the Machine 1200 can operate as a server machine or a client machine in a server-client network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The Machine 1200 can, but is not limited to, be a server computer, a client computer, a personal computer (PC), a tablet computer, a laptop computer, a netbook, a set-top box (STB), a PDA, an entertainment media system, a mobile phone, a smartphone, a mobile device, a wearable device (e.g., a smartwatch), a smart home device (e.g., a smart household appliance), other intelligent devices, a web facility, a network router, a network distributor, a network bridge, or any machine capable of executing the instructions 1208, sequentially or otherwise, specifying the actions to be taken by the Machine 1200.Furthermore, although only a single machine 1200 is depicted, the term “machine” shall be understood to represent a group of machines which individually or collectively execute the instructions 1208 to carry out one or more of the methodologies discussed herein.

[0077] The machine 1200 can include processors 1202, memory 1204, and I / O components 1242, which can be configured to communicate with each other via a bus 1244. In one example embodiment, the processors 1202 (e.g., a central processing unit (CPU), a reduced instruction set (RISC) processor, a complex instruction set (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP), an ASIC, a radio frequency integrated circuit (RFIC), another processor, or any suitable combination thereof) can, for example, include a processor 1206 and a processor 1210, which execute the instructions 1208. The term "processor" is also intended to include multi-core processors, which have two or more independent processors (sometimes called "cores") that can execute instructions simultaneously. Although Fig. As shown in Figure 1202, the machine 1200 can have a single single-core processor, a single multi-core processor (e.g., a multi-core processor), multiple single-core processors, multiple multi-core processors, or any combination thereof.

[0078] Memory 1204 comprises main memory 1212, static memory 1214, and a storage unit 1216, both of which are accessible to the processors 1202 via bus 1244. Main memory 1204, static memory 1214, and storage unit 1216 store instructions 1208, which embody one or more of the methodologies or functions described herein. During their execution by machine 1200, instructions 1208 may reside wholly or partially in main memory 1212, static memory 1214, machine-readable medium 1218, storage unit 1216, at least one of the processors 1202 (e.g., in the processor's cache memory), or a suitable combination thereof.

[0079] The I / O components 1242 can have a variety of components for receiving inputs, providing outputs, producing outputs, transmitting information, exchanging information, taking measurements, and so on. The specific I / O components 1242 included in a particular machine depend on the type of machine. For example, portable machines such as mobile phones may have a touch input device or other such input mechanisms, while a headless server machine is unlikely to have such a touch input device. It should be understood that the I / O components 1242 can have many other components that are included in Fig.Figure 12 is not shown. In various example embodiments, the I / O components 1242 can include output components 1228 and input components 1230. The output components 1228 can include visual components (e.g., a display device such as a plasma display panel (PDP), a light-emitting diode (LED) display, a liquid crystal display (LCD), a projector, or a cathode ray tube (CRT)), acoustic components (e.g., loudspeakers), haptic components (e.g., a vibration motor, resistance mechanisms), other signal generators, or converters. The input components 1230 can include alphanumeric input components (e.g., a keyboard, a touch-sensitive screen configured to receive alphanumeric input, a photo-optical keyboard, or other alphanumeric input components), pointer-based input components (e.g.,a mouse, touchpad, trackball, joystick, motion sensor or other pointing device), tactile input components (e.g. a physical button, a touch-sensitive screen that provides the location and / or force of touches or touch gestures, or other tactile input components), audio input components (e.g. a microphone) and the like.

[0080] In further example embodiments, the I / O components 1242 can include various sensors, such as one or more biometric components 1232, motion components 1234, environmental components 1236, or position components 1238, in addition to a variety of other components. For example, the biometric components 1232 include components for detecting expressions (e.g., hand expressions, facial expressions, vocal expressions, body gestures, or eye movements), for measuring biosignals (e.g., blood pressure, heart rate, body temperature, perspiration, muscle oxygenation, or brain waves), for identifying a person (e.g., voice identification, retinal identification, facial identification, fingerprint identification, or electroencephalogram-based identification), and the like. The motion components 1234 can include the motion sensor 324 and can include, for example, accelerometer components (e.g.,The environmental components 1236 include, for example, light sensor components (e.g., photometers), temperature sensor components (e.g., one or more thermometers detecting ambient temperature), humidity sensor components, pressure sensor components (e.g., barometers), acoustic sensor components (e.g., one or more microphones detecting background noise), proximity sensor components (e.g., infrared sensors detecting nearby objects), gas sensors (e.g., gas detection sensors for detecting concentrations of hazardous gases for safety reasons or for measuring pollutants in the atmosphere), or other components capable of providing indicators, measurements, or signals according to a surrounding physical environment. The position components 1238 include position sensor components (e.g.,a GPS receiver component), altitude sensor components (e.g. altimeter or barometer, which detect the air pressure from which the altitude can be derived), orientation sensor components (e.g. magnetometer) and the like.

[0081] Communication can be implemented using a variety of technologies. The I / O components 1242 also include communication components 1240, which operate to connect the machine 1200 to a network 1220 or devices 1222 via a coupling 1224 or a coupling 1226. For example, the communication components 1240 may include a network interface component or another suitable device as an interface to the network 1220. In other examples, the communication components 1240 may be wired communication components, wireless communication components, cellular communication components, near-field communication (NFC) components, or Bluetooth. ®-components (e.g. Bluetooth) ® Low Energy), Wi-Fi ® -components and other communication components to enable communication via other modalities. The devices 1222 can be another machine or any one from a variety of peripheral devices (e.g., a peripheral device connected via USB).

[0082] Furthermore, the 1240 communication components can detect identifiers or include components used for identifier detection. For example, the 1240 communication components can include radio frequency identification (RFID) reader components, NFC smart tag detection components, optical reader components (e.g., an optical sensor for detecting one-dimensional barcodes such as the Universal Product Code (UPC) barcode, multi-dimensional barcodes, and other optical codes), or acoustic detection components (e.g., microphones for detecting marked tone signals). Additionally, a variety of information can be derived from the 1240 communication components, such as...The location can be determined via Internet Protocol geolocation (IP geolocation), Wi-Fi® signal triangulation, or by detecting an NFC beacon signal that can specify a particular location, and so on. Each of the aforementioned sensors, processors, or other components or circuits may include or use a reference signal generator circuit arrangement and / or a correction circuit arrangement as described herein.

[0083] The various memories (e.g., memory 1204, main memory 1212, static memory 1214, and / or memory of the processors 1202) and / or the memory unit 1216 can store one or more sets of instructions and data structures (e.g., software) that embody or are used by one or more of the methodologies or functions described herein. These instructions (e.g., the instructions 1208), when executed by the processors 1202, perform various operations to implement the disclosed embodiments.

[0084] Instructions 1208 can be sent or received over the network 1220 using a transmission medium via a network interface device (e.g., a network interface component included in the communication components 1240) and using any of a number of known transmission protocols (e.g., Hypertext Transfer Protocol (HTTP)). Similarly, instructions 1208 can be sent or received using a transmission medium via the coupling 1226 (e.g., a peer-to-peer coupling) with the devices 1222.

[0085] Various aspects of the present disclosure, presented here as examples, may contribute to providing a solution for the assembly load problems identified herein.For example, Example 1 is a method comprising measuring a first electrical signal from a first node of a Hall plate, wherein the first electrical signal is a response to a first stimulus and the first electrical signal indicates a charge carrier mobility property of the semiconductor device in a first direction, and measuring a second electrical signal from a second node of the Hall plate, wherein the second electrical signal is a response to a second stimulus and the second electrical signal indicates the charge carrier mobility property of the semiconductor device in the same first direction, and determining an indicator of the physical stress of a semiconductor device incorporating the Hall plate based on a relationship between the first electrical signal and the second electrical signal.

[0086] In Example 2, the subject of Example 1 can involve providing the first stimulus to the second node of the Hall plate and, in response, measuring the first electrical signal, and providing the second stimulus to the first node of the Hall plate and, in response, measuring the second electrical signal.

[0087] In Example 3, the object of Example 2 can include the Hall plate, which has a doped semiconductor that is symmetrical about a first axis extending between the first nodes and about a second axis extending between the second nodes.

[0088] In Example 4, the subject of one or more of Examples 2-3 may include measuring the first electrical signal, which includes measuring a first voltage signal, wherein the first stimulus may include a first current signal, and measuring the second electrical signal, which includes measuring a second voltage signal, wherein the second stimulus may include a second current signal.

[0089] In Example 5, the object of Example 4 can feature the provision of the first and second current signals at different times, whereby the first and second current signals can have a common magnitude characteristic.

[0090] In Example 6, the subject of one or more of Examples 4-5 may involve determining the physical stress indicator, which includes: summing information about the magnitude of the first and second voltage signals to provide a voltage sum, and using the voltage sum and information about the magnitude of the first and second current signals, determining a resistance characteristic of a section of the Hall plate and determining the physical stress indicator (which, for example, provides information about the magnitude of the physical stress on the Hall plate) using the determined resistance characteristic.

[0091] In Example 7, the subject of one or more of Examples 2-6 may include the measurement of the first electrical signal, which includes the measurement of a first current signal, and the first stimulus may include a first voltage signal, and the measurement of the second electrical signal may include the measurement of a second current signal, and the second stimulus may include a second voltage signal.

[0092] In Example 8, the subject of Example 7 can exhibit the provision of the first and second voltage signals at different times.

[0093] In Example 9, the subject of one or more of Examples 1-8 may feature the measurement of the first and second electrical signals, which feature the measurement of information about the same off-diagonal charge carrier mobility components of the Hall plate.

[0094] In Example 10, the object of one or more of Examples 1-9 may feature the provision of a correction signal corresponding to the magnitude or direction of the load indicated by the physical load indicator.

[0095] In Example 11, the subject of one or more of Examples 1-10 may include determining an absolute resistance characteristic of the Hall plate and determining an off-diagonal resistance characteristic of the Hall plate based on the measured first and second electrical signals and providing a temperature compensation signal based on a ratio of the off-diagonal resistance characteristic to the absolute resistance characteristic of the Hall plate.

[0096] Example 12 is a load sensor comprising: a semiconductor device having a Hall plate with a first and a second pair of signal nodes and an excitation circuit configured to provide an excitation signal to the Hall plate using the first or the second pair of nodes, and a processor circuit configured to: receive information about a first electrical signal measured at the first pair of signal nodes, which is a response to a first section of the excitation signal, wherein the first electrical signal indicates a charge carrier mobility property of the semiconductor device in a first direction, and receive information about a second electrical signal measured at the second pair of signal nodes, which is a response to a second section of the excitation signal.where the second electrical signal indicates the charge carrier mobility property of the semiconductor device in the same first direction. Example 12 can include or use the processor circuit to determine an indicator of the physical stress on the semiconductor device based on a relationship between the first and second electrical signals.

[0097] In Example 13, the object of Example 12 can have the Hall plate symmetric about a first axis extending between the first pair of nodes and symmetric about a second axis extending between the second pair of nodes, the first axis being orthogonal to the second axis.

[0098] In Example 14, the subject of one or more of Examples 12-13 may include the excitation circuit configured to provide the first and second parts of the excitation signal at different times.

[0099] In Example 15, the subject of Example 14 may include the excitation circuit configured to provide the first part of the excitation signal to the second pair of nodes, and the excitation circuit configured to provide the second part of the excitation signal to the first pair of nodes.

[0100] In Example 16, the subject of Example 15 may include a multiplexer circuit configured to couple the excitation circuit with the Hall plate nodes.

[0101] In Example 17, the subject of one or more of Examples 12-16 may include the processor circuit configured to: sum voltage magnitude information about the first and second electrical signals to provide a voltage sum, and using the voltage sum and the information about the magnitude of the excitation signal, determine a resistance characteristic of a section of the Hall plate, and determine the indicator of physical stress (which, for example, provides information about a magnitude of the physical stress on the Hall plate) using the determined resistance characteristic.

[0102] In Example 18, the subject of one or more of Examples 12-17 may include the processor circuit configured to provide a compensation signal for the assembly load corresponding to a magnitude or direction of the load specified by the physical load indicator.

[0103] Example 19 is a non-volatile, processor-readable medium containing instructions which, when executed, cause a processor circuit to: control an excitation circuit, provide time-multiplexed first and second current signals to corresponding nodes of a Hall plate, measure a first and a second voltage signal in response to the first and second current signals from the nodes of the Hall plate, determine the off-diagonal charge carrier mobility property of the Hall plate using the measured first and second voltage signals together, and provide an indicator of the magnitude and direction of the physical load on the Hall plate.

[0104] In Example 19, the subject of Example 19 may include instructions to cause the processor circuit to generate a load compensation signal based on the physical load indicator.

[0105] Example 21 is a method comprising: providing an excitation signal to an emitter of a first bipolar transistor device, wherein the transistor device has a first and distinct second collectors connected to a base region of the transistor device. In Example 21, the method may, in response to the excitation signal, include measuring a first collector current from the first collector of the transistor device and, in response to the excitation signal, measuring a second collector current from the second collector of the transistor device and determining a magnitude difference between the first and second collector currents.The size difference can correspond to a charge carrier mobility property of the base region of the transistor device, and the method can further include determining an indicator of the physical stress on the transistor device based on the size difference between the first and second collector currents.

[0106] In Example 22, the subject of Example 21 can exhibit the simultaneous measurement of the first and second collector currents in response to the same excitation signal.

[0107] In Example 23, the subject of Example 22 can include measuring the first and second collector currents, which includes measuring the charge carrier mobility property for a first current flow direction across the base region of the transistor.

[0108] In Example 24, the subject of one or more of Examples 21-21 may include the use of information about a base-emitter voltage (Vbe or VBE) of the transistor device to provide a voltage reference signal.

[0109] In Example 25, the subject of one or more of Examples 21-24 may include determining the indicator for a physical load, which includes determining a current deflection characteristic in the base region of the transistor device, wherein the current deflection characteristic corresponds to a physical load on a semiconductor having the transistor device.

[0110] In Example 26, the subject of one or more of Examples 21-25 may include measuring the first and second collector currents, which includes acquiring information about the base-emitter voltage from a first side of the transistor device corresponding to the first collector, and acquiring information about the base-emitter voltage from a second side of the transistor device corresponding to the second collector, wherein the voltage information specifies a charge carrier mobility tensor describing the deformation of the transistor device under load.

[0111] In Example 27, the subject of one or more of Examples 21-26 may include the provision of a reference voltage or current signal using a bandgap reference generator circuit comprising the transistor device.

[0112] In Example 28, the subject of Example 27 may include the provision of a signal that indicates the physical stress indicator in a time-multiplexed manner with the reference voltage or current signal.

[0113] In Example 29, the subject of one or more of Examples 27-28 may include the provision of a signal that indicates the physical stress indicator simultaneously with the reference voltage or current signal.

[0114] In Example 30, the subject of one or more of Examples 21-29 may include the provision of a reference voltage or current signal using a bandgap-type reference generator circuit having a common substrate (e.g., at least partially shared) with a substrate of the transistor device.

[0115] Example 31 is a semiconductor load sensor comprising: a bipolar transistor device having a first and a second collector terminal, an excitation circuit configured to provide an excitation signal to a base-emitter junction of the bipolar transistor device, and a processor circuit configured to: receive information about a first collector signal measured at the first collector terminal, wherein the first collector signal is a response to the excitation signal and the first collector signal indicates a charge carrier mobility property of the bipolar transistor device in a first direction, and receive information about a second collector signal measured at the second collector terminal.wherein the second collector signal is a response to the excitation signal and the second collector signal indicates the charge carrier mobility property of the semiconductor device in the same first direction, and determining an indicator of the physical stress on the semiconductor device based on a relationship between the first and the second collector signal.

[0116] In Example 32, the subject of Example 31 can exhibit that the first and second collector signals indicate a charge carrier mobility property in a base region of the bipolar transistor device.

[0117] In Example 31, the subject of one or more of Examples 31-32 may have an emitter region, a base region and a collector region of the bipolar transistor device, which are layered in a second direction that is orthogonal to the first direction.

[0118] In Example 34, the subject of one or more of Examples 31-31 may include the processor circuit configured to receive information about the first and second collector signals in response to the same excitation signal.

[0119] In Example 35, the subject of one or more of Examples 31-34 may include determining the indicator for physical stress, which includes determining a current signal strength difference between the first and second collector signals.

[0120] In Example 36, the subject of Example 35 may exhibit that the magnitude difference between the first and second collector signals corresponds to a charge flow deflection in a base region of the bipolar transistor device.

[0121] In Example 37, the subject of one or more of Examples 31-36 can include a reference signal generator circuit comprising several other transistors, and the several other transistors and the bipolar transistor device have at least one section of a common substrate.

[0122] In Example 38, the subject of one or more of Examples 31-37 may include the bipolar transistor device comprising a section of a reference signal generator circuit, and the reference signal generator circuit may be configured to provide a reference signal using information about a base-emitter voltage (Vbe) of the bipolar transistor device.

[0123] In Example 39, the subject of one or more of Examples 31-38 may have the first and second collector terminals provided on opposite sides of the emitter terminal of the bipolar transistor device.

[0124] In Example 40, the subject of one or more of Examples 31-39 can have a surface of the bipolar transistor device having the emitter terminal surrounded by a base terminal, and the first and second collector terminals are separated from the emitter terminal by the base terminal, and the first and second collector terminals are electrically decoupled at the surface.

[0125] Example 41 is a reference signal generator circuit comprising: a first bandgap reference generator circuit having a first section of a semiconductor arrangement configured to provide an uncorrected reference voltage signal; a bipolar transistor device having a first and a second collector terminal, the bipolar transistor device having a common substrate with the first section of the semiconductor arrangement; and an excitation circuit configured to provide an excitation signal to an emitter terminal of the bipolar transistor device. Example 41 may include a processor circuit configured to: receive information about a first collector signal measured at the first collector terminal,wherein the first collector signal is a response to the excitation signal and the first collector signal indicates a charge carrier mobility property of the bipolar transistor device in a first direction, and receiving information about a second collector signal measured at the second collector terminal, wherein the second collector signal is a response to the excitation signal and the second collector signal indicates the charge carrier mobility property of the semiconductor device in the same first direction, and determining an indicator of the physical stress of the semiconductor device based on a relationship between the first and second collector signals, and providing a corrected voltage reference signal based on the uncorrected reference voltage signal and the indicator of physical stress.

[0126] In Example 42, the subject of Example 41 may include the processor circuit designed to determine the indicator of physical stress based on a current difference between the first and second collector signals.

[0127] In Example 41, the subject of one or more of Examples 41-42 may have that the first and second collector signals specify a charge carrier mobility property in a base region of the bipolar transistor device, wherein the charge carrier mobility property is subject to a change depending on a mechanical load applied to the semiconductor arrangement.

[0128] In Example 44, the subject of one or more of Examples 41-41 may exhibit that the uncorrected reference voltage signal is based on a base-emitter voltage characteristic of the bipolar transistor device.

[0129] Example 45 is at least one machine-readable medium containing instructions which, when executed by a processing circuit arrangement, cause the processing circuit arrangement to perform operations to implement one or more of Examples 1-44.

[0130] Example 46 is an institution that has the means to implement one or more of Examples 1-44.

[0131] Example 47 is a system for implementing one or more of Examples 1-44.

[0132] Example 48 is a procedure for implementing one or more of Examples 1-44.

[0133] Each of these non-restrictive examples can stand alone or can be combined in various permutations or combinations with one or more other examples or features discussed elsewhere here.

[0134] This detailed description includes references to the accompanying drawings, which form part of the detailed description. The drawings illustrate specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as "examples." Such examples may include additional elements beyond those shown or described. However, the inventors also include examples in which only the elements shown or described are provided. The inventors include examples that use any combination or permutation of the elements shown or described (or one or more aspects thereof), either in relation to a specific example (or one or more aspects thereof) or in relation to other examples shown or described herein (or one or more aspects thereof).

[0135] In this document, the term "a," as is customary in patent documents, is used to include one or more than one, irrespective of any other instances or uses of "at least one" or "one or more." In this document, the term "or" refers to a non-exclusive "or," meaning that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise specified. In this document, the terms "including" and "in which" are used as simple equivalents of the respective terms "including" and "whereby."

[0136] In the following claims, the terms "comprising" and "incorporating" are used in an open-ended manner, meaning that a system, device, object, assembly, formulation, or process that incorporates elements in addition to those listed in a claim under such a term nevertheless falls within the scope of protection of that claim. Furthermore, in the following claims, the terms "first," "second," "third," etc., are used merely as designations and are not intended to impose numerical requirements on their objects.

[0137] The method examples described here can be implemented, at least partially, by a machine or computer. Some examples may include a computer-readable or machine-readable medium encoded with instructions that can configure an electronic device to execute procedures, circuit operations, or circuit configuration instructions as described in the examples above. An implementation of such procedures may include code such as microcode, assembly language code, code of a higher-level language, or the like. Such code may contain computer-readable instructions for executing various procedures. The code may form sections of computer program products. Furthermore, in one example, the code may be stored tangibly on one or more volatile, non-transient, or non-volatile tangible computer-readable media, such as during execution or at other times.Examples of these tangible, computer-readable media include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact discs and digital video discs), magnetic cassettes, memory cards or sticks, random access memory (RAMs), read-only memory (ROMs), and the like.

[0138] The foregoing description serves for illustration and is not limiting. For example, the examples described above (or one or more aspects thereof) may also be used in combination with one another. Other embodiments may be used, as might be devised by a person skilled in the art after reviewing the foregoing description. The summary is provided to enable the reader to quickly grasp the essence of the technical disclosure. It is given with the understanding that it is not to be used to interpret or limit the scope or meaning of the claims. Furthermore, various features may have been grouped together in the foregoing detailed description to streamline the disclosure. This should not be interpreted as implying that an unclaimed disclosed feature is essential to any claim.Rather, the subject matter of the invention may consist of fewer than all features of a particular disclosed embodiment. Thus, the following claims are hereby included in the detailed description as examples or embodiments, each claim representing a separate embodiment, and it is intended that these embodiments may be combined with one another in various combinations or permutations. The scope of protection of the invention should be determined with reference to the appended claims, together with the full scope of the equivalents to which these claims entitle.

[0139] According to one aspect, a semiconductor-based stress sensor can comprise a bipolar transistor device with first and second collector terminals. An excitation circuit can supply an excitation signal to an emitter terminal of the bipolar transistor device, and an indicator of the physical stress on the semiconductor can be provided based on a relationship between the signals measured at the collector terminals in response to the excitation signal. The signals can indicate a charge carrier mobility characteristic of the semiconductor, which can be used as an indicator of physical stress. In one example, the physical stress indicator is based on a current deflection characteristic of a base region of the transistor device.

Claims

[1] Method comprising the following: Providing an excitation signal to an emitter of a first bipolar transistor device, wherein the transistor device has a first and a distinct second collector connected to a base region of the transistor device; In response to the excitation signal, measure a first collector current from the first collector of the transistor device; In response to the excitation signal, measure a second collector current from the second collector of the transistor device; Determining a magnitude difference between the first and second collector currents, wherein the magnitude difference corresponds to a charge carrier mobility property of the base region of the transistor device; and Determination of an indicator for the physical stress on the transistor device based on the magnitude difference between the first and second collector currents. [2] Method according to claim 1, comprising simultaneous measurement of the first and second collector currents in response to the same excitation signal. [3] Method according to one of the preceding claims, wherein the measurement of the first and second collector current comprises measuring the charge carrier mobility property for a first current flow direction over the base region of the transistor. [4] Method according to any of the preceding claims, comprising using information about a base-emitter voltage (Vbe) of the transistor device to provide a voltage reference signal. [5] Method according to one of the preceding claims, wherein determining the indicator for the physical load comprises determining a current deflection characteristic in the base region of the transistor device, wherein the current deflection characteristic corresponds to a physical load on a semiconductor comprising the transistor device. [6] Method according to one of the preceding claims, wherein the measurement of the first and second collector current comprises acquiring information about the base-emitter voltage from a first side of the transistor device corresponding to the first collector and acquiring information about the base-emitter voltage from a second side of the transistor device corresponding to the second collector, wherein the voltage information specifies a charge carrier mobility tensor describing the deformation of the transistor device under load. [7] Method according to any of the preceding claims, further comprising providing a reference voltage or current signal using a bandgap reference generator circuit comprising the transistor device. [8] Method according to claim 7, further comprising providing a signal indicating the physical load in time-division multiplex with the reference voltage or current signal. [9] Method according to claim 7 or 8, further comprising providing a signal indicating the physical stress indicator simultaneously with the reference voltage or current signal. [10] Method according to any of the preceding claims, further comprising providing a reference voltage or current signal using a bandgap-type reference generator circuit having a common substrate with a substrate of the transistor device. [11] Semiconductor load sensor comprising: a bipolar transistor device having a first and a second collector terminal; an excitation circuit configured to provide an excitation signal to a base-emitter junction of the bipolar transistor device; and a processor circuit that is designed to: Receiving information about a first collector signal measured at the first collector terminal, wherein the first collector signal is a response to the excitation signal and the first collector signal indicates a charge carrier mobility property of the bipolar transistor device in a first direction; Receiving information about a second collector signal measured at the second collector terminal, wherein the second collector signal is a response to the excitation signal and the second collector signal indicates the charge carrier mobility property of the bipolar transistor device in the same first direction; and Determining an indicator for the physical stress of the bipolar transistor device based on a relationship between the first and second collector signals. [12] Semiconductor load sensor according to claim 11, wherein the first and second collector signals indicate a charge carrier mobility property in a base region of the bipolar transistor device. [13] Semiconductor load sensor according to claim 11 or 12, wherein an emitter region, a base region and a collector region of the bipolar transistor device are layered in a second direction which is orthogonal to the first direction. [14] Semiconductor load sensor according to one of claims 11 to 13, wherein the processor circuit is configured to receive information about the first and second collector signals in response to the same excitation signal. [15] Semiconductor load sensor according to one of claims 11 to 14, wherein determining the indicator for the physical load comprises determining a current signal strength difference between the first and the second collector signal and the magnitude difference between the first and the second collector signal corresponds to a charge flow deflection in a base region of the bipolar transistor device. [16] Semiconductor load sensor according to one of claims 11 to 15, further comprising a reference signal generator circuit comprising several other transistors, wherein the several other transistors and the bipolar transistor device share a common substrate. [17] Semiconductor load sensor according to one of claims 11 to 16, wherein the bipolar transistor device comprises a section of a reference signal generator circuit, and wherein the reference signal generator circuit is configured to provide a reference signal using information about a base-emitter voltage (Vbe) of the bipolar transistor device. [18] Semiconductor load sensor according to one of claims 11 to 17, wherein a surface of the bipolar transistor device has the emitter terminal surrounded by a base terminal, and wherein the first and second collector terminals are separated from the emitter terminal by the base terminal and the first and second collector terminals are electrically decoupled at the surface. [19] Reference signal generator circuit comprising the following: a first bandgap reference generator circuit comprising a first section of a semiconductor arrangement and configured to provide an uncorrected reference voltage signal; a bipolar transistor device having a first and a second collector terminal, wherein the bipolar transistor device has a substrate shared with the first section of the semiconductor arrangement; an excitation circuit configured to provide an excitation signal to an emitter terminal of the bipolar transistor device; and a processor circuit that is designed to: Receiving information about a first collector signal measured at the first collector terminal, wherein the first collector signal is a response to the excitation signal and the first collector signal indicates a charge carrier mobility property of the bipolar transistor device in a first direction; Receiving information about a second collector signal measured at the second collector terminal, wherein the second collector signal is a response to the excitation signal and the second collector signal indicates the charge carrier mobility property of the bipolar transistor device in the same first direction; Determining an indicator for the physical stress of the bipolar transistor device based on a relationship between the first and second collector signals; and Providing a corrected voltage reference signal based on the uncorrected reference voltage signal and the physical load indicator. [20] Reference signal generator circuit according to claim 19, wherein the processor circuit is configured to determine the indicator for the physical load based on a current difference between the first and the second collector signal. [21] Reference signal generator circuit according to claim 19, wherein the uncorrected reference voltage signal is based on a base-emitter voltage characteristic of the bipolar transistor device.

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