Semiconductor packages with mixed bond types and their training methods

Abstract

Package, containing: a first interposer (111A) wherein the first interposer (111A) has a first redistribution structure (160); a first die (50A) which is bonded to a first surface of the first redistribution structure (160) by a dielectric-dielectric bond and a metal-metal bond; a second interposer (111B) adjacent to the first interposer (111A), wherein the second interposer (111B) has a second redistribution structure (160); a second die (50B) which is bonded to a first surface of the second redistribution structure (160) by a first lot bond (128); an encapsulation material (133) around the first die (50A) and the second die (50B); and several conductive connectors (128) on a second side of the first redistribution structure (160) opposite the first die (50A) and the second die (50B).

Description

BACKGROUND

[0001] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a wide variety of electronic components (e.g., transistors, diodes, resistors, capacitors, and the like). These improvements in integration density have largely stemmed from repeatedly reducing the minimum feature size, allowing more components to be integrated into a given area. With the increasing demand for ever smaller electronic devices, a need has arisen for smaller and more innovative packaging techniques for semiconductor dies.

[0002] With the further advancement of semiconductor technologies, stacked and bonded semiconductor devices have emerged as an effective alternative for further reducing the physical size of semiconductor devices. In a stacked semiconductor device, active circuits such as logic, memory, and processor circuits are at least partially fabricated on separate substrates and then physically and electrically bonded together to form a functional device. Such bonding processes employ sophisticated techniques, and improvements are desirable.

[0003] WO 2021 / 081855A1 discloses a chip-package-on-package structure comprising: a primary chip stacking unit with multiple isolated and spaced primary pins on a first surface; a first bonding layer on the first surface, the first bonding layer comprising multiple isolated and spaced bonding assemblies, each having at least one bonding section, wherein any two bonding sections are isolated and any two bonding sections have the same cross-sectional area, and the bonding assemblies are each connected to the primary pins;a plurality of secondary chip stacking units provided on a surface of the side of the first interconnect layer facing away from the primary chip stacking unit, wherein the secondary chip stacking units are each provided with a plurality of micro-projecting points that are isolated and spaced apart from one another, and each of the plurality of micro-projecting points is connected to one of the plurality of interconnect arrangements.

[0004] US 2020 / 0111729 A1 discloses a package comprising: an interposer with a first side; a first integrated circuit attached to the first side of the interposer; a second integrated circuit attached to the first side of the interposer; an underfill arranged beneath the first and second integrated circuits; and an encapsulation arranged around the first and second integrated circuits, wherein a first part of the encapsulation extends through the underfill and the first part of the encapsulation is physically located between the first and second integrated circuits and the first part of the encapsulation is planar with the edges of the underfill and the edges of the first and second integrated circuits.

[0005] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been enlarged or reduced as appropriate for clarity of description. Fig. Figure 1 shows a cross-sectional view of an integrated circuit die according to some embodiments. The Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25 to Fig. Figure 26 shows cross-sectional views of intermediate steps during a process for forming a package component. DETAILED DESCRIPTION

[0007] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also cover embodiments in which additional features may be formed between the first and second features, so that the first and second features need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various described embodiments and / or configurations.

[0008] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and similar terms can be used here for the sake of simplicity to describe the relationship of one element or feature to one or more other elements or features, as shown in the figures. These spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative terms used here can be interpreted accordingly.

[0009] Various embodiments provide packaged semiconductor devices featuring mixed bond types at a single interface and methods for forming them. The method includes hybrid bonding of a first die to an interface die and solder bonding of a second die to the interface die adjacent to the first die. A formative compound can be formed around the first and second dies, and the surfaces of the first die, the second die, and the formative compound can be planarized. In some embodiments, the first die can be a logic die, and the second die can be a memory die. In some embodiments, the second die can be a logic die, a passive device die, or a bridge die. The first die and the second die can be electrically interconnected by redistribution layers of the interface die.Bonding the first die to the interface die using hybrid bonding enables the formation of connections with a smaller center-to-center distance between the first die and the interface die, reduces the form factor of packages such as the first die and the interface die, and improves device performance. Bonding the second die to the interface die using solder bonding reduces costs.

[0010] Fig. Figure 1 shows a cross-sectional view of an integrated circuit die 50 according to some embodiments. The integrated circuit die 50 is packaged in subsequent processing to form an integrated circuit package. The integrated circuit die 50 can consist of a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, or the like); a memory die (e.g., a dynamic random-access memory die (DRAM die), a static random-access memory die (SRAM die), a NAND flash memory die, or the like); a power control die (e.g., an integrated power control circuit die (PMIC die)); a radio frequency die (RF die); a sensor die; a microsystems die (MEMS die); a signal processing die (e.g., a digital signal processing die (DSP die)); a front-end die (e.g.an analog front-end die (AFE die); an input / output die (I / A die); a bridge die; the like; or a combination thereof.

[0011] The integrated circuit die 50 can be formed on a wafer, which may have various device regions that are subsequently separated to form multiple integrated circuit dies. The integrated circuit die 50 can be machined according to suitable fabrication processes to form integrated circuits. In some embodiments, the integrated circuit die 50 comprises a semiconductor substrate 52, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may include other semiconductor materials such as germanium; a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.Other substrates, such as multilayer or gradient substrates, can be used. The semiconductor substrate 52 has an active surface (e.g., the one in ). Fig. 1 upward-facing surface), sometimes also called the front, and an inactive surface (e.g., the one in Fig. 1 downward-facing surface), sometimes also referred to as the back.

[0012] Devices 54 (represented by a transistor) can be formed on the front face of the semiconductor substrate 52. The devices 54 can consist of active devices (e.g., transistors, diodes, or the like), capacitors, resistors, or the like. An interlayer dielectric (ILD) 56 is located on the front face of the semiconductor substrate 52. The ILD 56 surrounds the devices 54 and can cover them. The ILD 56 can have one or more dielectric layers formed from materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.

[0013] Conductive connectors 58 extend through the ILD 56 and are electrically and physically connected to the devices 54. In embodiments where the devices 54 are transistors, the conductive connectors 58 can be connected to the gates and source / drain regions (e.g., source regions and / or drain regions) of the transistors. The conductive connectors 58 can be made of tungsten, cobalt, nickel, copper, silver, gold, aluminum, or the like, or combinations thereof. An interconnect structure 60 is formed on the ILD 56 and the conductive connectors 58. The interconnect structure 60 connects the devices 54 to form integrated circuits. In some embodiments, the interconnect structure 60 can be formed by metallization structures in dielectric layers on the ILD 56.The metallization structures feature metal conductors and vias formed in one or more low-k dielectric layers. The metallization structures of the interconnect structure 60 are electrically connected to the devices 54 via the conductive connectors 58.

[0014] The integrated circuit die 50 further comprises pads 62, such as aluminum pads, to which external connections are made. The pads 62 are located on the front face of the semiconductor substrate 52, such as in and / or on the interconnect structure 60. One or more passivation films 64 are located on the integrated circuit die 50, for example, on sections of the interconnect structure 60 and the pads 62. Openings extend through the passivation films 64 to the pads 62. Die connectors 66, such as conductive pillars (e.g., formed from a metal like copper), extend through the openings in the passivation films 64. The die connectors 66 can be physically and electrically connected to the respective pads 62. The die connectors 66 can be formed by plating or the like. The die connectors 66 are electrically connected to the integrated circuits of the integrated circuit die 50.

[0015] Optionally, solder areas (e.g., solder balls or solder bumps) can be arranged on pads 62. The solder balls can be used to perform chip sampling (CP) tests on the integrated circuit die 50. The CP tests can be performed on the integrated circuit die 50 to determine if the integrated circuit die 50 is a known good die (KGD). Thus, only integrated circuit dies 50 that are KGDs are subjected to subsequent processing and packaging. Those that fail the CP test are not packaged. After testing, the solder areas can be removed in subsequent processing steps.

[0016] A dielectric layer 68 may (but need not) be present on the front face of the semiconductor substrate 52, for example, on the passivation films 64 and the die connectors 66. The dielectric layer 68 encapsulates the die connectors 66 laterally, and the dielectric layer 68 is flush with the semiconductor substrate 52 laterally. Initially, the dielectric layer 68 may cover the die connectors 66, so that the uppermost surface of the dielectric layer 68 lies above the uppermost surfaces of the die connectors 66. In embodiments in which the solder areas are arranged on the die connectors 66, the dielectric layer 68 may also bury the solder areas. Alternatively, the solder areas may be removed before the dielectric layer 68 forms.

[0017] The dielectric layer 68 can consist of a polymer such as PBO, polyimide, BCB, or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; similar materials; or a combination thereof. The dielectric layer 68 can be formed by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, the die connectors 66 are exposed by the dielectric layer 68 during the formation of the integrated circuit die 50. In other embodiments, the die connectors 66 remain covered and are exposed during a subsequent process for packaging the integrated circuit die 50. Exposing the die connectors 66 can remove any solder areas that may be present on the die connectors 66.

[0018] In some embodiments, the integrated circuit die 50 consists of a stacked device comprising multiple semiconductor substrates 52. For example, the integrated circuit die 50 may consist of a memory device such as a hybrid memory cube module (HMC module), a high-bandwidth memory module (HBM module), or the like, comprising multiple memory dies. In such embodiments, the integrated circuit die 50 comprises multiple semiconductor substrates 52 interconnected by substrate vias (TSVs). Each of the semiconductor substrates 52 may (but need not) have an interconnect structure 60.

[0019] The Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10 to Fig. Figure 11 shows cross-sectional views of intermediate steps during a process for forming a first packaged component 200 (shown in Fig. 11) according to some examples. To form the first packaged component 200, one or more of the integrated circuit dies 50 can be packaged. The first packaged component 200 can be referred to as a chip-on-wafer-on-substrate package (CoWoS package) or as a system-on-integrated-chip package (SoIC package).

[0020] In Fig. Figure 2 shows an interface die 111 attached to a support substrate 100. The support substrate 100 can consist of a glass support substrate, a ceramic support substrate, or the like. The support substrate 100 can consist of a wafer, so that several packages can be formed simultaneously on the support substrate 100. Although the interface die 111 is described as a die, it can consist of a wafer that can subsequently be singulated.

[0021] A release layer 102 is formed on the support substrate 100. The release layer 102 can be made of a polymer-based material that, together with the support substrate 100, can be removed from the interface die 111 in subsequent steps. In some embodiments, the release layer 102 is an epoxy-based thermal release material that loses its adhesive properties when heated, for example, a light-to-heat conversion release coating (LTHC release coating). In some embodiments, the release layer 102 can consist of an ultraviolet adhesive (UV adhesive) that loses its adhesive properties when exposed to UV radiation, such as radiation from UV light. The release layer 102 can be dispensed as a liquid and cured, can consist of a laminate film that is laminated onto the support substrate 100, or the like.The top surface of the separation layer 102 may be leveled and exhibit a high degree of planarity.

[0022] The interface die 111 can comprise an interface substrate 110, a dielectric layer 112 on the interface substrate 110, and conductive vias 114 in the dielectric layer 112 and the interface substrate 110. The interface substrate 110 can consist of a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer semiconductor substrate, or the like. The interface substrate 110 can be a semiconductor material such as silicon or germanium; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; containing an alloy semiconductor such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.Other substrates, such as multilayer or gradient substrates, can also be used. The interface substrate 110 can be doped or undoped. In some embodiments, the interface substrate 110 is free of active devices, although the interface substrate 110 may have passive devices located in and / or on a front surface of the interface substrate 110 (e.g., the downward-facing surface in the ). Fig. 2), sometimes also referred to as the front side. In embodiments in which integrated circuits are formed in the interface substrate 110, active devices 113 such as transistors, diodes and the like, as well as passive devices such as capacitors, resistors and the like, can be formed in and / or on the front side of the interface substrate 110.

[0023] The dielectric layer 112 can be formed on the interface substrate 110. In some embodiments, the dielectric layer 112 is formed from a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like, and which can be patterned using a lithography mask. In other embodiments, the dielectric layer 112 is formed from a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layer 112 can be formed by spin coating, lamination, CVD, or the like, or a combination thereof.

[0024] In some embodiments, the conductive vias 114 can be formed by creating recesses (not shown separately) in the dielectric layer 112 and the interface substrate 110. The recesses can be formed by etching, milling, laser techniques, a combination thereof, or the like. A dielectric can be formed in the recesses, for example, using an oxidation technique. A barrier layer can be conformally deposited in the openings, for example, by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, and / or the like. The barrier layer can be formed from an oxide, a nitride, a carbide, a combination thereof, or the like. A conductive material can be deposited above the barrier layer and in the recesses.The conductive material can be formed by an electrochemical plating process, CVD, ALD, PVD, a combination thereof, or the like. Examples of conductive materials include copper, tungsten, aluminum, silver, gold, a combination thereof, or the like. Excess conductive material, barrier layer, and dielectric can be removed from the surfaces of the dielectric layer 112 using a planarization process. The planarization process can consist, for example, of chemical-mechanical polishing (CMP), grinding, etching, or the like. Remaining portions of the barrier layer and conductive material form the conductive vias 114.

[0025] In Fig. 3. The back side of the interface substrate 110 is thinned. The interface substrate 110 can be thinned by a planarization process applied to it such that the conductive vias 114 are exposed. Once exposed, the conductive vias 114 extend through the interface substrate 110 and can be referred to as TSVs. Planarization can remove sections of the interface substrate 110 opposite the dielectric layer 112, thus exposing the conductive vias 114. Planarization can be achieved by any suitable process, such as CMP, grinding, etching, or a combination thereof.After planarization, the conductive vias 114 can extend completely through the interface substrate 110 and provide a connection between opposite sides of the interface substrate 110.

[0026] In Fig. 4 A rear interconnect structure 121 is formed on the interface substrate 110. The rear interconnect structure 121 has dielectric layers 116, metallization layers 118 (also referred to as redistribution layers or redistribution lines) in the dielectric layers 116, a dielectric layer 120 and bond pads 122 in the dielectric layer 120.

[0027] The rear interconnect structure 121 can have several metallization layers 118, separated from each other by respective layers of dielectric layers 116. The metallization layers 118 and the bond pads 122 of the rear interconnect structure 121 are electrically connected to the conductive vias 114, and corresponding metallization layers 118 can be physically connected to the conductive vias 114.

[0028] In some embodiments, the dielectric layers 116 are formed from a polymer, which may consist of a photosensitive material such as PBO, polyimide, a BCB-based polymer, or the like, and which can be patterned using a lithography mask. In other embodiments, the dielectric layers 116 are formed from a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layers 116 can be formed by spin coating, lamination, CVD, or the like, or a combination thereof. After each dielectric layer 116 has been formed, it can be patterned to expose underlying conductive features, such as portions of the underlying conductive vias 114 or the underlying metallization layers 118. The patterning can be performed by any suitable process.In embodiments where the dielectric layers 116 contain a photosensitive material, the structuring process can include exposing the dielectric layers 116. The dielectric layers 116 can be developed after exposure. In some embodiments, the structuring of the dielectric layers 116 can include etching using anisotropic etching.

[0029] The metallization layers 118 each have conductive vias and / or conductor tracks. The conductive vias extend through a respective dielectric layer 116, and the conductor tracks extend along the respective dielectric layer 116, such as on a top surface of the respective dielectric layer 116. As an example of forming a metallization layer 118, a seed layer (not shown separately) is formed over the respective underlying features. For example, the seed layer can be formed on a respective dielectric layer 116, in openings extending through the respective dielectric layer 116, and on an underlying feature such as the conductive vias 114 or the metallization layers 118.In some embodiments, the seed layer is a metal layer that may consist of a single layer or a composite layer comprising several sublayers formed from different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using a deposition process such as PVD, CVD, or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and exposed to light for patterning. The structure of the photoresist corresponds to the metallization layer 118. The patterning creates openings through the photoresist that expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer.The conductive material can be formed from the seed layer by plating, such as electroless plating or electroplating, or by the like. The conductive material can be a metal or metal alloy such as copper, titanium, tungsten, aluminum, or the like, or combinations thereof. The photoresist and the portions of the seed layer where the conductive material is not formed are removed. The photoresist can be removed by a suitable ashing or peeling process, for example, using an oxygen plasma or the like. After the photoresist is removed, exposed portions of the seed layer are removed using a suitable etching process, such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the metallization layers 118.

[0030] The dielectric layers 116 and the metallization layers 118 of the backside interconnect structure 121 are shown as an example. More or fewer dielectric layers 116 and metallization layers 118 than shown can be formed in the backside interconnect structure 121 by repeating or omitting the steps described above.

[0031] The dielectric layer 120 is formed over the dielectric layers 116 and the metallization layers 118. The dielectric layer 120 can be made of a material suitable for forming dielectric-dielectric bonds. In some embodiments, the dielectric layer 120 can contain silicon oxide, silicon nitride, silicon oxynitride, or the like. The dielectric layer 120 can be deposited using a suitable deposition process such as PVD, CVD, ALD, or the like.

[0032] The bond pads 122 are formed in the dielectric layer 120. The bond pads 122 are configured for external connection to the rear interconnect structure 121. The bond pads 122 can be formed on and extend along the top surfaces of the dielectric layers 116. The bond pads 122 can be physically and electrically connected to the metallization layers 118. The bond pads 122 can be electrically connected through the metallization layers 118 to the conductive vias 114. The bond pads 122 can be formed from a material and by processes that are the same as or similar to those used for the metallization layers 118. In some embodiments, the bond pads 122 have a different size (e.g., a different thickness) than the metallization layers 118. A planarization step can be performed to flatten the surfaces of the bond pads 122 and the surfaces of the dielectric layer 120.

[0033] In Fig. In Figure 5, a first integrated circuit die 50A is bonded to the backside interconnect structure 121 via hybrid bonding. Any desired type and quantity of integrated circuit dies 50 can be bonded to the backside interconnect structure 121 via hybrid bonding. In the example shown, a single first integrated circuit die 50A is bonded to the backside interconnect structure 121. The first integrated circuit die 50A can consist of a logic device, such as a CPU, a GPU, a SoC, a microcontroller, or the like.

[0034] The first integrated circuit die 50A is bonded to the rear interconnect structure 121 in a hybrid bond configuration. The first integrated circuit dies 50A are oriented with the front facing down, so that the front of the first integrated circuit die 50A faces the rear interconnect structure 121 and the rear of the first integrated circuit die 50A faces away from the rear interconnect structure 121. This can be referred to as a front-to-back (F2B) configuration, since the front of the first integrated circuit die 50A faces the rear of the interface die 121.

[0035] The dielectric layer 68 of the first integrated circuit die 50A can be directly bonded to the dielectric layer 120, and the die connectors 66 of the first integrated circuit die 50A can be directly bonded to the bond pads 122. In some embodiments, the bonds between the dielectric layer 68 and the dielectric layer 120 consist of oxide-oxide bonds or the like. The hybrid bonding process further directly bonds the die connectors 66 of the first IC die 50A to the bond pads 122 via metal-to-metal direct bonding. Thus, the first integrated circuit die 50A is electrically connected to the backside interconnect structure 121 on the interface die 111 through the physical and electrical connection of the die connectors 66 and the bond pads 122. In some embodiments, the interface also has dielectric-metal interfaces between the first integrated circuit die 50A and the rear interconnect structure 121 (e.g., if the die connectors 66 and the bond pads 122 are not perfectly aligned and / or have different widths).

[0036] For example, the hybrid bonding process begins with the application of a surface treatment to the dielectric layer 68 and / or the dielectric layer 120. The surface treatment may include plasma treatment. The plasma treatment may be performed in a vacuum environment. Following the plasma treatment, the surface treatment may further include a cleaning process (e.g., rinsing with deionized water or the like) that can be applied to the dielectric layer 68 and / or the dielectric layer 120. The die connectors of the first integrated circuit die 50A can be aligned with the bond pads 122 of the rear interconnect structure 121. The die connectors 66 can overlap with the corresponding bond pads 122.A pre-bonding step is performed by placing the first integrated circuit die 50A in contact with the dielectric layer 120 and the respective bond pads 122 of the backside interconnect structure 121. Pre-bonding can be carried out at room temperature (e.g., between approximately 21°C and 25°C). After pre-bonding, annealing is performed at a temperature between approximately 150°C and 400°C for a duration of approximately 0.5 hours to 3 hours. This causes the metal of the die connectors 66 (e.g., copper) and the metal of the bond pads 122 (e.g., copper) to interdiffusion, forming direct metal-to-metal bonds.

[0037] The first integrated circuit die 50A is bonded without the use of solder joints (e.g., micro-bumps or similar). Direct bonding of the first integrated circuit die 50A to the backside interconnect structure 121 offers advantages such as a narrower bump center-to-center distance; small form factor packages through the use of hybrid bonds; reduced bond center-to-center distance scalability for chip I / O to achieve high-density die-die interconnects; improved mechanical durability; improved electrical performance; fewer defects; and increased yield. Furthermore, smaller die-to-die distances between the first integrated circuit die 50A and subsequent integrated circuit dies can be achieved, resulting in the benefits of a smaller form factor, higher bandwidth, improved power integrity (PI), improved signal integrity (SI), and lower power consumption.

[0038] In Fig. 6 Bond pads 126 are formed on the bond pads 122 and the dielectric layer 120 of the rear interconnect structure 121, and conductive connectors 128 are formed on the bond pads 126. The bond pads 126 can be formed by forming a seed layer (not shown separately) over the bond pads 122 and the dielectric layer 120. In some embodiments, the seed layer consists of a metal layer, which can be a single layer or a composite layer having several sublayers formed from different materials. In some embodiments, the seed layer has a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using PVD or the like. A photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and exposed to light for patterning.The photoresist structure corresponds to Bondpad 126. The structuring process creates openings through the photoresist, exposing the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. This conductive material can be formed by plating, for example, electroplating or electroless plating, or the like. The conductive material can contain a metal such as copper, titanium, tungsten, aluminum, or the like. The photoresist and the portions of the seed layer where the conductive material is not formed are removed. The photoresist can be removed by a suitable ashing or peeling process, for example, using an oxygen plasma or the like. After the photoresist is removed, exposed portions of the seed layer are removed using a suitable etching process.The remaining sections of the nucleation layer and the conductive material form the bond pads 126.

[0039] The conductive connectors 128 are formed on the bond pads 126. The conductive connectors 128 can consist of ball grid array (BGA) connectors, solder balls, micro-bumps, flip-chip bonding bumps (C4 bumps), bumps formed by ENEPIG (electroless nickel-electroless palladium-gold immersion) technology, or the like. The conductive connectors 128 can be formed from a meltable conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 128 are formed by initially forming a solder layer by vapor deposition, electroplating, printing, solder transfer, ball placement, or the like. After the solder layer has formed on the structure, melting can be performed to shape the material into the desired bump shape.In some embodiments, the bond pads 126 can be omitted and the conductive connectors 128 can be formed on the bond pads 122.

[0040] In Fig. 7. A second integrated circuit die 50B is bonded to the interface die 111 by solder bonding to the backside interconnect structure 121. Any desired type and number of integrated circuit dies 50 can be bonded to the backside interconnect structure 121 by solder bonding. In the example shown, a single second integrated circuit die 50B is bonded to the backside interconnect structure 121. The second integrated circuit die 50B can consist of a memory device, such as a DRAM die, an SRAM die, a NAND flash die, an HMC module, an HBM module, or the like. Although the second integrated circuit die 50B is shown as a single integrated circuit die, the second integrated circuit die 50B can have multiple stacked integrated circuit dies (also called die stacks).

[0041] The second integrated circuit die 50B is attached to the interface die 111 by solder bonds, for example, using the conductive connectors 128. The second integrated circuit die 50B can be positioned on the rear interconnect structure 121, for example, using a pick-and-place tool. Attaching the second integrated circuit die 50B to the interface die 111 can involve positioning the second integrated circuit die 50B on the interface die 111 and soldering the conductive connectors 128. The conductive connectors 128 form connections between the bond pads 126 on the interface die 111 and the die connectors 66 of the second integrated circuit die 50B, electrically connecting the interface die 111 to the second integrated circuit die 50B via the rear interconnect structure 121.

[0042] An underfill material 129 can be formed around the conductive connectors 128 and between the second integrated circuit die 50B and the backside interconnect structure 121. The underfill material 129 can reduce stresses and protect the connections resulting from the melting of the conductive connectors 128. The underfill material 129 can be formed from any suitable underfill material, such as a molding compound, an epoxy, or the like. The underfill material 129 can be formed by a capillary flow process after the second integrated circuit die 50B has been attached to the backside interconnect structure 121, or it can be formed by a suitable deposition process before the second integrated circuit die 50B has been attached to the backside interconnect structure 121.The underfill material 129 can be applied in liquid or semi-liquid form and subsequently cured. In some embodiments, the underfill material 129 is omitted, and the underfill material 129 is omitted in subsequent figures.

[0043] The first integrated circuit die 50A and the second integrated circuit die 50B can be formed by processes of the same technology node or by processes of different technology nodes. For example, the first integrated circuit die 50A can originate from a more advanced process node than the second integrated circuit die 50B. The first integrated circuit die 50A and the second integrated circuit die 50B can have different sizes (e.g., different heights and / or areas) or the same size (e.g., the same height and / or area). Other combinations of integrated circuit dies 50 are possible. In some embodiments, the first integrated circuit die 50A and the second integrated circuit die 50B can have a thickness greater than approximately 100 µm.

[0044] The first integrated circuit die 50A and the second integrated circuit die 50B can be electrically connected to each other via the interface die 111. The first integrated circuit die 50A is physically and electrically connected to the rear interconnect structure 121 by hybrid bonds between the die connectors 66 and the bond pads 122, and the second integrated circuit die 50B is physically and electrically connected to the rear interconnect structure 121 by solder bonds between the die connectors 66 and the bond pads 126. In some embodiments, the first integrated circuit die 50A can consist of a logic die and the second integrated circuit die 50B can consist of a memory die.The first integrated circuit die, 50A, has a relatively smaller center-to-center spacing of the die connectors 66 and a higher circuit density, while the second integrated circuit die, 50B, has a relatively larger center-to-center spacing of the die connectors 66 and a lower circuit density. Bonding the first integrated circuit die, 50A, to the backside interconnect structure 121 by hybrid bonding offers advantages such as a narrower peak center-to-center spacing, higher bandwidth, and improved device performance. Bonding the second integrated circuit die, 50B, to the backside interconnect structure 121 by solder bonding reduces costs.

[0045] In Fig. In step 8, an encapsulation material 130 is formed on the backside interconnect structure 121 and around the first integrated circuit die 50A, the second integrated circuit die 50B, the conductive connectors 128, the bond pads 126, and the interface die 111. After formation, the encapsulation material 130 encapsulates the first integrated circuit die 50A, the second integrated circuit die 50B, the conductive connectors 128, the bond pads 126, the backfill material (if present), and the interface die 111. The encapsulation material 130 can consist of a molding compound, an epoxy resin, or the like. The encapsulation material 130 can be deposited by compression molding, transfer molding, or the like. The encapsulation material 130 is formed over the interface die 111 such that the first integrated circuit die 50A, the second integrated circuit die 50B and the interface die 111 are buried or covered.The encapsulation material 130 is formed in gap regions between the first integrated circuit die 50A and the second integrated circuit die 50B. In embodiments where the underfill material is omitted, the encapsulation material 130 can be formed around the conductive connectors 128 and between the second integrated circuit die 50B and the backside interconnect structure 121. The encapsulation material 130 can be applied in liquid or semi-liquid form and subsequently cured.

[0046] The encapsulation material 130 is then thinned to expose the back surfaces of the first integrated circuit die 50A and the second integrated circuit die 50B. The thinning process can consist of grinding, CMP, back etching, combinations thereof, or the like. After the thinning process, the top surfaces of the first integrated circuit die 50A, the second integrated circuit die 50B, and the encapsulation material 130 are coplanar (within process variations). Thinning is performed until a desired amount of the first integrated circuit die 50A, the second integrated circuit die 50B, and the encapsulation material 130 has been removed.In particular, the thinning removes the sections of the encapsulation material 130 that cover the top surface of the first integrated circuit die 50A and the second integrated circuit die 50B, until no encapsulation material 130 remains over the first integrated circuit die 50A and the second integrated circuit die 50B.

[0047] In Fig. 9 will describe the structure of Fig. 8. The device is inverted; the encapsulation material 130, the first integrated circuit die 50A, and the second integrated circuit die 50B are attached to a support substrate 140; and the support substrate 100 and the separator layer 102 are removed. The device can be inverted so that the back sides of the first integrated circuit die 50A and the second integrated circuit die 50B are facing downwards. The support substrate 140 can be bonded to the encapsulation material 130, the first integrated circuit die 50A, and the second integrated circuit die 50B by means of a separator layer 142. The support substrate 140 can be made of a glass support substrate, a ceramic support substrate, or the like. The support substrate 140 can consist of a single wafer, allowing multiple packages to be processed simultaneously on the support substrate 140.The separating layer 142 can be made of a polymer-based material that, together with the support substrate 140, can be removed from the overlying structures formed in subsequent steps. In some embodiments, the separating layer 142 consists of a thermal release material based on epoxy resin that loses its adhesive properties when heated, for example, an LTHC release coating. In some embodiments, the separating layer 142 can consist of a UV adhesive that loses its adhesive properties when exposed to UV radiation, such as UV light. The separating layer 142 can be dispensed as a liquid and cured, can consist of a laminate film that is laminated onto the substrate 140, or the like. The top surface of the separating layer 142 can be flattened and exhibit a high degree of planarity.

[0048] A support substrate debonding process is performed to separate (or “debond”) the support substrate 100 from the interface die 111 and the encapsulation material 130. In some embodiments, the debonding process involves projecting light, such as laser light or UV light, onto the separating layer 102, so that the separating layer 102 decomposes under the heat of the light and the support substrate 100 can be removed. As shown in Fig. As shown in Figure 9, the surfaces of the encapsulation material 130, the conductive vias 114 and the dielectric layer 112 can be exposed after removal of the support substrate 100 and the separating layer 102.

[0049] In Fig. In step 10, a front-side interconnect structure 150 is formed on the interface die 111 and the encapsulation material 130 opposite the support substrate 140. The front-side interconnect structure 150 has dielectric layers 152 and metallization layers 154 (sometimes referred to as redistribution layers or redistribution lines) in the dielectric layers 152. For example, the front-side interconnect structure 150 can have multiple metallization layers 154 separated from each other by corresponding dielectric layers 152. The metallization layers 154 of the front-side interconnect structure 150 are electrically connected to the conductive vias 114 of the interface die 111.The metallization layers 154 are electrically connected to the first integrated circuit die 50A and the second integrated circuit die 50B via the conductive vias 114 and the rear interconnect structure 121. The first integrated circuit die 50A and the second integrated circuit die 50B can be electrically connected to each other via the metallization layers 118 of the rear interconnect structure 121 and / or the metallization layers 154 of the front interconnect structure 150.

[0050] In some embodiments, the dielectric layers 152 are formed from a polymer, which may consist of a photosensitive material such as PBO, polyimide, a BCB-based polymer, or the like, and which can be patterned using a lithography mask. In other embodiments, the dielectric layers 152 are formed from a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layers 152 can be formed by spin coating, lamination, CVD, or the like, or a combination thereof. After each dielectric layer 152 has been formed, it can be patterned to expose underlying conductive features, such as portions of the underlying conductive vias 114 or the underlying metallization layers 154. The patterning can be performed by any suitable process.In embodiments where the dielectric layers 152 contain a photosensitive material, the structuring process can include exposing the dielectric layers 152. The dielectric layers 152 can be developed after exposure. In some embodiments, the structuring of the dielectric layers 152 can include etching using anisotropic etching.

[0051] The metallization layers 154 each have conductive vias and / or conductor tracks. The conductive vias extend through a respective dielectric layer 152, and the conductor tracks extend along the respective dielectric layer 152, such as on a top surface of the respective dielectric layer 152. As an example of forming a metallization layer 154, a seed layer (not shown separately) is formed over the respective underlying features. For example, the seed layer can be formed on a respective dielectric layer 152, in openings extending through the respective dielectric layer 152, and on an underlying feature such as the conductive vias 114 or the metallization layers 154.In some embodiments, the seed layer is a metal layer that may consist of a single layer or a composite layer comprising several sublayers formed from different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using a deposition process such as PVD, CVD, or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and exposed to light for patterning. The pattern of the photoresist corresponds to the metallization layer 154. The patterning creates openings through the photoresist that expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer.The conductive material can be formed from the seed layer by plating, such as electroless plating or electroplating, or the like. The conductive material can be a metal or metal alloy such as copper, titanium, tungsten, aluminum, or the like, or combinations thereof. The photoresist and the portions of the seed layer where the conductive material is not formed are removed. The photoresist can be removed by a suitable ashing or peeling process, for example, using an oxygen plasma or the like. After the photoresist is removed, exposed portions of the seed layer are removed using a suitable etching process, such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the metallization layers 154.

[0052] The dielectric layers 152 and the metallization layers 154 of the front-side interconnect structure 150 are shown as an example. More or fewer dielectric layers 152 and metallization layers 154 than shown can be formed in the front-side interconnect structure 150 by repeating or omitting the steps described above.

[0053] Under-bump metallizations (UBMs) 156 are configured for external connection to the front-side interconnect structure 150. The UBMs 156 have bump sections on and along a top surface of the top dielectric layer 152 of the front-side interconnect structure 150 and have via sections extending through the top dielectric layer 152 of the front-side interconnect structure 150. The via sections can be physically and electrically connected to the top metallization layer 154 of the front-side interconnect structure 150. The UBMs 156 can be electrically connected to the conductive vias 114, the first integrated circuit die 50A, and the second integrated circuit die 50B.The UBMs 156 can be formed from materials and by processes that are the same as or similar to those used to form the metallization layers 154. In some embodiments, the UBMs 156 have a different size (are, for example, larger) than the metallization layers 154.

[0054] Conductive connectors 158 are formed on the UBMs 156. The conductive connectors 158 can consist of BGA connectors, solder balls, metal columns, C4 bumps, micro-bumps, bumps formed by ENEPIG, or the like. The conductive connectors 158 can contain a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 158 are formed by initially forming a solder layer by vapor deposition, electroplating, printing, solder transfer, ball placement, or the like. After a solder layer has formed on the structure, melting can be performed to shape the material into the desired bump shape.In another embodiment, the conductive connectors comprise 158 metal columns (e.g., copper columns) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal columns may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal columns. The metal cap layer may contain nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or a combination thereof, and may be formed by a plating process.

[0055] In Fig. Step 11 removes the support substrate 140 and optionally forms a heat dissipation layer 159 over the encapsulation material 130, the first integrated circuit die 50A, and the second integrated circuit die 50B. The heat dissipation layer 159, the encapsulation material 130, the first integrated circuit die 50A, the second integrated circuit die 50B, and the interface die 111 form a first packaged component 200. A support substrate debonding process is performed to separate the support substrate 140 from the encapsulation material 130, the first integrated circuit die 50A, and the second integrated circuit die 50B. In some embodiments, the debonding process involves projecting light, such as laser light or UV light, onto the separating layer 142, causing the separating layer 142 to decompose under the heat of the light and allowing the support substrate 140 to be removed. As in Fig. As shown in Figure 11, the surfaces of the encapsulation material 130, the first integrated circuit die 50A and the second integrated circuit die 50B can be exposed after removal of the support substrate 140 and the separating layer 142.

[0056] The heat dissipation layer 159 is formed over the encapsulation material 130, the first integrated circuit die 50A, and the second integrated circuit die 50B. The heat dissipation layer 159 is formed from a material with high thermal conductivity, such as a metal or a metal nitride. In some embodiments, the heat dissipation layer 159 may be formed from aluminum, titanium, titanium nitride, nickel, nickel vanadium, silver, gold, copper, combinations thereof, or the like. The heat dissipation layer 159 may be formed conformally by a PVD process such as sputtering or evaporation; a plating process such as electroless plating or electroplating; a printing process such as inkjet printing; or the like. In some embodiments, the heat dissipation layer 159 is formed from copper by a sputtering process.The heat dissipation layer 159 can be included to increase heat dissipation from the first integrated circuit die 50A and the second integrated circuit die 50B. In some embodiments, the heat dissipation layer 159 can be formed over the encapsulation material 130, the first integrated circuit die 50A, and the second integrated circuit die 50B before the encapsulation material 130, the first integrated circuit die 50A, and the second integrated circuit die 50B are mounted on the support substrate 140. In some embodiments, the heat dissipation layer 159 can be omitted.

[0057] The inclusion of both hybrid bonding and solder bonding for bonding the first integrated circuit die 50A and the second integrated circuit die 50B to an interface of the rear interconnect structure 121 allows for the benefits of both methods. For example, hybrid bonding of the first integrated circuit die 50A enables bonding of dies with small center-to-center distances to the rear interconnect structure 121, providing higher bandwidth and improved device performance. Solder bonding of the second integrated circuit die 50B reduces costs while still achieving sufficiently small bond center-to-center distances.

[0058] The Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10 to Fig. Figure 11 shows an example where the package has a front-side-back structure, with the front sides of the integrated circuit dies 50 facing the back side of the interface die 111. Fig. 12, Fig. 13, Fig. 14 to Fig. Figure 15 shows an example where a package has a front-front-front structure, with the front sides of the integrated circuit dies 50 facing the front side of the interface die 111. Fig. 12, Fig. 13, Fig. 14 to Fig. Figure 15 shows cross-sectional views of intermediate steps during a process for forming a second packaged component 300 (shown in Figure 15). Fig. 15) according to some examples.

[0059] In Fig. Interface die 111 is provided at position 12. Interface die 111 may be the same as or similar to the interface die 111 described above in relation to... Fig. 2 was described. As in Fig. As shown in Figure 12, the interface die 111 can have an interface substrate 110, a dielectric layer 112 on a front side of the interface substrate 110, active devices 113 formed in and / or on the front side of the interface substrate 110, and conductive vias 114 extending through the dielectric layer 112 and into the interface substrate 110.

[0060] In Fig. In section 13, a front-side interconnect structure 160 is formed over the interface die 111. The front-side interconnect structure 160 has dielectric layers 162, metallization layers 164 within the dielectric layers 162, a dielectric layer 166, and bond pads 168 within the dielectric layer 166. The front-side interconnect structure 160 can be formed from materials and using processes that are the same as or similar to those of the back-side interconnect structure 121, which was described above with respect to Fig. 4 described. In particular, the dielectric layers 162, the metallization layers 164, the dielectric layer 166 and the bond pads 168 can be formed from materials and using processes that are the same as or similar to those of the dielectric layers 116, the metallization layers 118, the dielectric layer 120 and the bond pads 122 respectively.

[0061] In Fig. In step 14, a first integrated circuit die 50A and a second integrated circuit die 50B are bonded to the front-side interconnect structure 160. An underfill material 129 is optionally formed between the second integrated circuit die 50B and the front-side interconnect structure 160, and an encapsulation material 130 is formed around the first integrated circuit die 50A and the second integrated circuit die 50B. The first integrated circuit die 50A can be bonded to the front-side interconnect structure 160 by hybrid bonding, as described above. Fig. 5 described. The second integrated circuit die 50B can be bonded to the front interconnect structure 160 by solder bonding through bond pads 126 and conductive connectors 128, as described above in relation to the Fig. 6 and Fig. 7 described. The underfill material 129 can be formed from materials and using processes that are the same as or similar to those of the underfill material 129 described above in relation to Fig. 7. The encapsulation material 130 can be formed from materials and using processes that are the same as or similar to those of the encapsulation material 130 described above in relation to Fig. 8 were described. Hybrid bonding of the first integrated circuit die, 50A, enables bonding of dies with small center-to-center distances using the front-facing interconnect structure 160, offering higher bandwidth and improved fixture performance. Solder bonding of the second integrated circuit die, 50B, reduces costs while still achieving sufficiently small bond center-to-center distances.

[0062] In Fig. 15 The back side of the interface substrate 110 is thinned, a backside interconnect structure 170 is formed on the back side of the interface substrate 110, and a heat dissipation layer 159 is optionally formed on the encapsulation material 130, the first integrated circuit die 50A, and the second integrated circuit die 50B. The heat dissipation layer 159, the encapsulation material 130, the first integrated circuit die 50A, the second integrated circuit die 50B, and the interface die 111 form a second packaged component 300. The interface substrate 110 can be thinned by a planarization process applied to the interface substrate 110 such that the conductive vias 114 are exposed. Once the conductive vias 114 are exposed, the conductive vias 114 extend through the interface substrate 110 and can be referred to as TSVs.Planarization can remove sections of the interface substrate 110 opposite the dielectric layer 112, exposing the conductive vias 114. Planarization can be achieved by any suitable process, such as CMP, grinding, etching, or a combination thereof. After planarization, the conductive vias 114 can extend completely through the interface substrate 110, providing a connection between opposite sides of the interface substrate 110.

[0063] The rear interconnect structure 170 can be formed from materials and using processes that are the same as or similar to those of the front interconnect structure 150 described above in relation to Fig. The rear interconnect structure 170 has dielectric layers 172 and metallization layers 174 within the dielectric layers 172. The dielectric layers 172 and the metallization layers 174 can be formed from materials and using processes that are the same as or similar to those of the dielectric layers 152 and the metallization layers 154, respectively.

[0064] UBMs 176 and conductive connectors 178 are designed for external connection to the rear interconnect structure 170. The UBMs 176 and the conductive connectors 178 can be formed from materials and using processes that are the same as or similar to those of the UBMs 156 and the conductive connectors 158 described above in relation to Fig. The UBMs 176 have hump sections on and along an upper surface of a top dielectric layer 172 of the backside interconnect structure 170 and have via sections extending through the top dielectric layer 172 of the backside interconnect structure 170. The via sections can be physically and electrically connected to a top metallization layer 174 of the backside interconnect structure 170. The UBMs 176 can be electrically connected to the conductive vias 114, the first integrated circuit die 50A, and the second integrated circuit die 50B.

[0065] The heat dissipation layer 159 is formed over the encapsulation material 130, the first integrated circuit die 50A, and the second integrated circuit die 50B. The heat dissipation layer 159 is formed from a material with high thermal conductivity, such as a metal or a metal nitride. In some embodiments, the heat dissipation layer 159 may be formed from aluminum, titanium, titanium nitride, nickel, nickel vanadium, silver, gold, copper, combinations thereof, or the like. The heat dissipation layer 159 may be formed conformally by a PVD process such as sputtering or evaporation; a plating process such as electroless plating or electroplating; a printing process such as inkjet printing; or the like. In some embodiments, the heat dissipation layer 159 is formed from copper by a sputtering process.The heat dissipation layer 159 can be included to increase heat dissipation from the first integrated circuit die 50A and the second integrated circuit die 50B. In some embodiments, the heat dissipation layer 159 can be formed over the encapsulation material 130, the first integrated circuit die 50A, and the second integrated circuit die 50B before the encapsulation material 130, the first integrated circuit die 50A, and the second integrated circuit die 50B are mounted on the support substrate 140. In some embodiments, the heat dissipation layer 159 can be omitted.

[0066] The inclusion of both hybrid bonding and solder bonding for bonding the first integrated circuit die 50A and the second integrated circuit die 50B to an interface of the front-side interconnect structure 160 allows for the benefits of both methods. For example, hybrid bonding of the first integrated circuit die 50A enables bonding of dies with small center-to-center distances to the front-side interconnect structure 160, providing higher bandwidth and improved device performance. Solder bonding of the second integrated circuit die 50B reduces costs while still achieving sufficiently small bond center-to-center distances.

[0067] The Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20 to Fig. Figure 21 shows an embodiment in which three integrated circuit dies 50 are bonded to two interface dies 111. As shown in Fig. As shown in Figure 19, in particular, a first integrated circuit die 50A is hybrid-bonded to a first interface die 111A, a second integrated circuit die 50B is solder-bonded to the first interface die 111A and a second interface die 111B, and a third integrated circuit die 50C is solder-bonded to the second interface die 111B. Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20 to Fig. Figure 21 shows an embodiment in which a package has a front-back structure, wherein the front sides of the integrated circuit dies 50 face the back sides of the interface dies 111. Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20 to Fig. Figure 21 shows cross-sectional views of intermediate steps during a process for forming a third packaged component 400 (shown in Figure 21). Fig. 21) according to some embodiments.

[0068] In Fig. Figure 16 shows a first interface die 111A and a second interface die 111B mounted on a support substrate 100. The front faces of the first interface die 111A and the second interface die 111B are attached to the support substrate 100 by a separating layer 102. The support substrate 100 and the separating layer 102 can be formed from materials and using processes similar to or identical to those of the support substrate 100 and the separating layer 102 described above with respect to Fig. 2 were described. The first interface die 111A and the second interface die 111B may be the same as or similar to the interface die 111 described above in relation to Fig. 2 as described. Both the first interface die 111A and the second interface die 111B can have an interface substrate 110, a dielectric layer 112 on a front face of the interface substrate 110, active devices 113 formed in and / or on the front face of the interface substrate 110, and conductive vias 114 extending through the dielectric layer 112 and into the interface substrate 110. The first interface die 111A and the second interface die 111B can be laterally adjacent to each other and can be separated by a gap.

[0069] A rear-side interconnect structure 121 is formed on the back side of both the first interface die 111A and the second interface die 111B. The rear-side interconnect structures 121 comprise dielectric layers 116, metallization layers 118 within the dielectric layers 116, dielectric layers 120, and bond pads 122 within the dielectric layers 120. The metallization layers 118 are electrically connected to the conductive vias 114 of the first interface die 111A and the second interface die 111B. The bond pads 122 are electrically connected to the metallization layers 118 and, via the metallization layers 118, to the conductive vias 114 of the first interface die 111A and the second interface die 111B.The rear interconnect structures 121 can be formed from materials and using processes that are the same as or similar to those of the rear interconnect structure 121 described above in relation to . Fig. 4 described. In particular, the dielectric layers 116, the metallization layers 118, the dielectric layers 120 and the bond pads 122 can be formed from materials and using processes that are the same as or similar to those of the dielectric layers 116, the metallization layers 118, the dielectric layer 120 and the bond pads 122 respectively.

[0070] In Fig. In step 17, a first encapsulation material 131 is formed on the separating layer 102 and around the first interface die 111A and the second interface die 111B. The first encapsulation material 131 is deposited on the separating layer 102 and around the first interface die 111A, the second interface die 111B, and the backside interconnect structures 121. After formation, the first encapsulation material 131 encapsulates the first interface die 111A, the second interface die 111B, and the backside interconnect structures 121. The first encapsulation material 131 can consist of a molding compound, an epoxy resin, or the like. The first encapsulation material 131 can be deposited by compression molding, transfer molding, or the like.The first encapsulation material 131 is formed above the separating layer 102 such that the first interface die 111A, the second interface die 111B, and the backside interconnect structures 121 are buried or covered. The first encapsulation material 131 is formed in gaps between the first interface die 111A and the second interface die 111B and between the backside interconnect structures 121. The first encapsulation material 131 can be applied in liquid or semi-liquid form and subsequently cured.

[0071] The first encapsulation material 131 is then thinned to expose the bond pads 122 of the backside interconnect structures 121. The thinning process can consist of a grinding process, CMP, back-etching, combinations thereof, or the like. After the thinning process, the top surfaces of the first encapsulation material 131, the bond pads 122, and the dielectric layers 120 are coplanar (within process variations). The thinning is carried out until the bond pads 122 are exposed. In some embodiments, the thinning removes the portions of the first encapsulation material 131 covering the backside interconnect structures 121 until nothing of the first encapsulation material 131 remains above the backside interconnect structures 121.

[0072] In Fig. In the embodiment shown, a first integrated circuit die 50A is bonded to the backside interconnect structure 121 via the first interface die 111A by hybrid bonding. A desired type and quantity of integrated circuit dies 50 can be bonded to the backside interconnect structure 121 by hybrid bonding, for example, one or more of the first integrated circuit dies 50A. In the embodiment shown, a single first integrated circuit die 50A is bonded to the backside interconnect structure 121. The first integrated circuit die 50A can consist of a logic device, for example, a CPU, a GPU, a SoC, a microcontroller, or the like.

[0073] The first integrated circuit die 50A is bonded to the rear interconnect structure 121 in a hybrid bond configuration. The first integrated circuit die 50A is oriented with the front facing down, so that the front of the first integrated circuit die 50A faces the rear interconnect structure 121 and the rear of the first integrated circuit die 50A faces away from the rear interconnect structure 121. This can be referred to as a front-to-back (F2B) configuration, since the front of the first integrated circuit die 50A faces the rear of the first interface die 111A. The dielectric layer 68 of the first integrated circuit die 50A can be directly bonded to the dielectric layer 120, and the die connectors 66 of the first integrated circuit die 50A can be directly bonded to the bond pads 122.

[0074] The first integrated circuit die 50A is bonded without the use of solder joints (e.g., micro-bumps or similar). Direct bonding of the first integrated circuit die 50A to the backside interconnect structure 121 offers advantages such as a narrower bump center-to-center distance; small form factor packages through the use of hybrid bonds; reduced bond center-to-center distance scalability for chip I / O to achieve high-density die-die interconnects; improved mechanical durability; improved electrical performance; fewer defects; and increased yield. Furthermore, smaller die-to-die distances between the first integrated circuit die 50A and subsequent integrated circuit dies can be achieved, resulting in the benefits of a smaller form factor, higher bandwidth, improved power integrity (PI), improved signal integrity (SI), and lower power consumption.

[0075] In Fig. 19. Bond pads 126 are formed on the rear interconnect structures 121 above the first interface die 111A and the second interface die 111B, a second integrated circuit die 50B is bonded to the rear interconnect structures 121 above the first interface die 111A and the second interface die 111B by solder bonding, and a third integrated circuit die 50C is bonded to the rear interconnect structure 121 above the second interface die 111B by solder bonding. The bond pads 126 and the conductive connectors 128 can be formed on the rear interconnect structures 121 from materials and using processes that are the same as or similar to those of the bond pads 126 and the conductive connectors 128 described above with respect to Fig. 6 were described.

[0076] A desired type and quantity of integrated circuit dies 50 can be bonded to the rear interconnect structure 121 by solder bonding, for example, one or more of the second integrated circuit dies 50B and one or more of the third integrated circuit dies 50C. In the embodiment shown, a single second integrated circuit die 50B is bonded to the rear interconnect structures 121 over the first interface die 111A and the second interface die 111B, and a single third integrated circuit die 50C is bonded to the rear interconnect structure 121 over the second interface die 111B. The second integrated circuit die 50B can consist of a bridge die, which may be a logic device or a passive device.In embodiments where the second integrated circuit die 50B consists of a logic device, the second integrated circuit die 50B can be a CPU, a GPU, a SoC, a microcontroller, or the like. In embodiments where the second integrated circuit die 50B consists of a passive device, the second integrated circuit die 50B can be an input-output die (I / O die), a SED die, or the like. The third integrated circuit die 50C can consist of a memory device, such as a DRAM die, an SRAM die, a NAND flash die, an HMC module, an HBM module, or the like. Although the third integrated circuit die 50C is shown as a single integrated circuit die, the third integrated circuit die 50C can have multiple stacked integrated circuit dies (also called die stacks).

[0077] The second integrated circuit die 50B and the third integrated circuit die 50C are attached to the rear interconnect structures 121 using solder bonds, for example, with the conductive connectors 128. The second integrated circuit die 50B and the third integrated circuit die 50C can be positioned on the rear interconnect structures 121 using, for example, a pick-and-place tool. Attaching the second integrated circuit die 50B and the third integrated circuit die 50C to the rear interconnect structures 121 can involve positioning the second integrated circuit die 50B and the third integrated circuit die 50C on the rear interconnect structures 121 and soldering the conductive connectors 128.The conductive connectors 128 form connections between the bond pads 126 on the rear interconnect structures 121 and the die connectors 66 of the second integrated circuit die 50B and the third integrated circuit die 50C, thereby electrically connecting the first interface die 111A and the second interface die 111B to the second integrated circuit die 50B and the third integrated circuit die 50C via the rear interconnect structures 121.

[0078] An underfill material 129 can be formed around the conductive connectors 128 and between the rear interconnect structures 121 and both the second integrated circuit die 50B and the third integrated circuit die 50C. As shown in Fig. As shown in Figure 19, the backing material 129 can consist of a continuous material or two separate, discontinuous materials. The backing material 129 can reduce stresses and protect the connections resulting from the melting of the conductive connectors 128. The backing material 129 can be formed from any suitable backing material, such as a molding compound, an epoxy, or the like. The backing material 129 can be formed by a capillary flow process after the second integrated circuit die 50B and the third integrated circuit die 50C have been attached to the rear interconnect structures 121, or it can be formed by a suitable deposition process before the second integrated circuit die 50B and the third integrated circuit die 50C have been attached to the rear interconnect structures 121.The underfill material 129 can be applied in liquid or semi-liquid form and subsequently cured. In some embodiments, the underfill material 129 is omitted, and the underfill material 129 is omitted in subsequent figures.

[0079] The first integrated circuit die 50A, the second integrated circuit die 50B, and the third integrated circuit die 50C can be formed by processes at the same technology node or by processes at different technology nodes. For example, the first integrated circuit die 50A can originate from a more advanced process node than the second integrated circuit die 50B and / or the third integrated circuit die 50C. The first integrated circuit die 50A, the second integrated circuit die 50B, and / or the third integrated circuit die 50C can have different dimensions (e.g., different heights and / or areas) or they can have the same dimensions (e.g., the same height and / or area). Other combinations of integrated circuit dies are also possible.In some embodiments, the first integrated circuit die 50A, the second integrated circuit die 50B and the third integrated circuit die 50C may have a thickness of more than approximately 100 µm.

[0080] The first integrated circuit die 50A and the third integrated circuit die 50C can be electrically connected to each other and to the second integrated circuit die 50B via the rear interconnect structures 121. The first integrated circuit die 50A is physically and electrically connected to the rear interconnect structure 121 on the first interface die 111A via hybrid bonds between the die connectors 66 and the bond pads 122. The second integrated circuit die 50B is physically and electrically connected to the rear interconnect structures 121 on the first interface die 111A and the second interface die 111B via solder bonds between the die connectors 66 and the bond pads 126. The third integrated circuit die 50C is physically and electrically connected to the rear interconnect structure 121 on the second interface die 111B by solder bonds between the die connectors 66 and the bond pads 126.In some embodiments, the first integrated circuit die 50A can consist of a logic die, the second integrated circuit die 50B can consist of a bridge die, and the third integrated circuit die 50C can consist of a memory die. The first integrated circuit die 50A has a relatively smaller die connector center-to-center spacing 66 and a higher circuit density, while the second integrated circuit die 50B and the third integrated circuit die 50C have relatively larger die connector center-to-center spacing 66 and a lower circuit density. Bonding the first integrated circuit die 50A to the rear interconnect structure 121 by hybrid bonding provides advantages such as a narrower hump center-to-center spacing, higher bandwidth, and improved device performance.Bonding the second integrated circuit die 50B and the third integrated circuit die 50C to the rear interconnect structures 121 by solder bonding reduces costs.

[0081] In Fig. 20 A second encapsulation material 133 is formed on the first interface die 111A, the second interface die 111B, and the first encapsulation material 131, and around the first integrated circuit die 50A, the second integrated circuit die 50B, and the third integrated circuit die 50C. The second encapsulation material 133 can be formed from materials and using processes that are the same as or similar to those of the encapsulation material 130 described above. Fig. 8 were described. The second encapsulation material 133 can be thinned to expose the back sides of the first integrated circuit die 50A, the second integrated circuit die 50B, and the third integrated circuit die 50C.

[0082] In Fig. 21 the support substrate 100 is removed; a front-side interconnect structure 150 is formed on front sides of the first interface die 111A and the second interface die 111B; and optionally a heat dissipation layer 159 is formed on the second encapsulation material 133, the first integrated circuit die 50A, the second integrated circuit die 50B and the third integrated circuit die 50C. The heat dissipation layer 159, the encapsulation material 130, the first integrated circuit die 50A, the second integrated circuit die 50B, the third integrated circuit die 50C, the first interface die 111A and the second interface die 111B form a third packaged component 400. A support substrate unbonding is performed to separate the support substrate 100 from the first interface die 111A, the second interface die 111B and the first encapsulation material 131.In some embodiments, the debonding process involves projecting light, such as laser light or UV light, onto the separating layer 102, causing the separating layer 102 to decompose under the heat of the light and allowing the support substrate 100 to be removed. As in . Fig. As shown in Figure 21, the surfaces of the first interface die 111A, the second interface die 111B and the first encapsulation material 131 can be exposed after the support substrate 100 and the separating layer 102 have been removed.

[0083] The front interconnect structure 150 can be formed from materials and using processes that are the same as or similar to those of the front interconnect structure 150 described above in relation to Fig. 10. The front-facing interconnect structure 150 has dielectric layers 152 and metallization layers 154 within the dielectric layers 152. The dielectric layers 152 and the metallization layers 154 can be formed from materials and using processes that are the same as or similar to those of the dielectric layers 152 and the metallization layers 154, respectively.

[0084] UBMs 156 and conductive connectors 158 are designed for external connection to the front interconnect structure 150. The UBMs 156 and the conductive connectors 158 can be formed from materials and using processes that are the same as or similar to those of the UBMs 156 and the conductive connectors 158 described above in relation to Fig. The UBMs 156 have hump sections on and along a top surface of the topmost dielectric layer 152 of the front interconnect structure 150 and have via sections extending through the topmost dielectric layer 152 of the front interconnect structure 150. The via sections can be physically and electrically connected to the topmost metallization layer 154 of the front interconnect structure 150. The UBMs 156 can be electrically connected to the conductive vias 114, the first integrated circuit die 50A, the second integrated circuit die 50B, and the third integrated circuit die 50C.

[0085] The heat dissipation layer 159 is formed over the second encapsulation material 133, the first integrated circuit die 50A, the second integrated circuit die 50B, and the third integrated circuit die 50C. The heat dissipation layer 159 is formed from a material with high thermal conductivity, such as a metal or a metal nitride. In some embodiments, the heat dissipation layer 159 may be formed from aluminum, titanium, titanium nitride, nickel, nickel vanadium, silver, gold, copper, combinations thereof, or the like. The heat dissipation layer 159 may be formed conformally by a PVD process such as sputtering or evaporation; a plating process such as electroless plating or electroplating; a printing process such as inkjet printing; or the like. In some embodiments, the heat dissipation layer 159 is formed from copper by a sputtering process.The heat dissipation layer 159 can be included to increase heat dissipation from the first integrated circuit die 50A, the second integrated circuit die 50B, and the third integrated circuit die 50C. In some embodiments, the heat dissipation layer 159 can be formed over the second encapsulation material 133, the first integrated circuit die 50A, the second integrated circuit die 50B, and the third integrated circuit die 50C before the removal of the support substrate 100. In some embodiments, the heat dissipation layer 159 can be omitted.

[0086] The inclusion of hybrid bonding of the first integrated circuit die 50A with the backside interconnect structure 121 over the first interface die 111A, as well as solder bonding of the second integrated circuit die 50B and the third integrated circuit die 50C with backside interconnect structures 121 over the first interface die 111A and the second interface die 111B, allows for the benefits of both hybrid bonding and solder bonding. For example, hybrid bonding of the first integrated circuit die 50A enables bonding of dies with small center-to-center distances using the backside interconnect structure 121, providing higher bandwidth and improved device performance. Solder bonding of the second integrated circuit die 50B and the third integrated circuit die 50C reduces costs while still ensuring sufficiently small bond center-to-center distances.

[0087] The Fig. 22, Fig. 23, Fig. 24, Fig. 25 to Fig. Figure 26 shows an embodiment in which three integrated circuit dies 50 are bonded to two interface dies 111. As shown in Fig. As shown in Figure 19, in particular, a first integrated circuit die 50A is hybrid-bonded to a first interface die 111A, a second integrated circuit die 50B is solder-bonded to the first interface die 111A and a second interface die 111B, and a third integrated circuit die 50C is solder-bonded to the second interface die 111B. Fig. 22, Fig. 23, Fig. 24, Fig. 25 to Fig. Figure 26 shows an embodiment in which a package has a front-to-front structure, wherein the front sides of the integrated circuit dies 50 face the front sides of the interface dies 111. Fig. 22, Fig. 23, Fig. 24, Fig. 25 to Fig. Figure 26 shows cross-sectional views of intermediate steps during a process for forming a fourth packaged component 500 (shown in Figure 26). Fig. 26) according to some embodiments.

[0088] In Fig. Figure 22 shows a first interface die 111A and a second interface die 111B attached to a support substrate 100. The back sides of the first interface die 111A and the second interface die 111B are attached to the support substrate 100 by a separating layer 102. The support substrate 100 and the separating layer 102 can be formed from materials and using processes similar to or identical to those of the support substrate 100 and the separating layer 102 described above with respect to Fig. 2 were described. The first interface die 111A and the second interface die 111B may be the same as or similar to the interface die 111 described above in relation to Fig. 2 as described. Both the first interface die 111A and the second interface die 111B can have an interface substrate 110, a dielectric layer 112 on a front face of the interface substrate 110, active devices 113 formed in and / or on the front face of the interface substrate 110, and conductive vias 114 extending through the dielectric layer 112 and into the interface substrate 110. The first interface die 111A and the second interface die 111B can be laterally adjacent to each other and can be separated by a gap.

[0089] A front-facing interconnect structure 160 is formed over the front face of both the first interface die 111A and the second interface die 111B. The front-facing interconnect structures 160 comprise dielectric layers 162, metallization layers 164 within the dielectric layers 162, dielectric layers 166, and bond pads 168 within the dielectric layers 166. The metallization layers 164 are electrically connected to the conductive vias 114 of the first interface die 111A and the second interface die 111B. The bond pads 168 are electrically connected to the metallization layers 164 and, via the metallization layers 164, to the conductive vias 114 of the first interface die 111A and the second interface die 111B.The front interconnect structure 160 can be formed from materials and using processes that are the same as or similar to those of the rear interconnect structure 121 described above in relation to . Fig. 4 described. In particular, the dielectric layers 162, the metallization layers 164, the dielectric layers 166 and the bond pads 168 can be formed from materials and using processes that are the same as or similar to those of the dielectric layers 116, the metallization layers 118, the dielectric layer 120 and the bond pads 122 respectively.

[0090] A first encapsulation material 131 is formed on the separating layer 102 and around the first interface die 111A and the second interface die 111B. The first encapsulation material 131 can be formed from materials and using processes that are the same as or similar to those of the first encapsulation material 131 described above. Fig. 17. The first encapsulation material 131 is thinned to expose the bond pads 168 of the front interconnect structure 160. After the thinning process, the top surfaces of the first encapsulation material 131, the bond pads 168, and the dielectric layers 166 are coplanar (within process variations). The thinning is carried out until the bond pads 168 are exposed. In some embodiments, the thinning removes portions of the first encapsulation material 131 covering the front interconnect structure 160 until nothing of the first encapsulation material 131 remains above the front interconnect structure 160.

[0091] In Fig. 23 A first integrated circuit die 50A is bonded to the front-side interconnect structure 160 over the first interface die 111A by hybrid bonding. A desired type and quantity of the integrated circuit dies 50 can be bonded to the front-side interconnect structure 160 by hybrid bonding, for example, one or more of the first integrated circuit dies 50A. In the embodiment shown, a single first integrated circuit die 50A is bonded to the front-side interconnect structure 160. The first integrated circuit die 50A can consist of a logic device, for example, a CPU, a GPU, a SoC, a microcontroller, or the like.

[0092] The first integrated circuit die 50A is bonded to the front-side interconnect structure 160 in a hybrid bond configuration. The first integrated circuit die 50A is oriented with its front side facing down, so that the front of the first integrated circuit die 50A faces the front-side interconnect structure 160 and the rear of the first integrated circuit die 50A faces away from the front-side interconnect structure 160. This can be referred to as a front-to-front (F2F) configuration, since the front of the first integrated circuit die 50A faces the front of the first interface die 111A. The dielectric layer 68 of the first integrated circuit die 50A can be directly bonded to the dielectric layer 166, and the die connectors 66 of the first integrated circuit die 50A can be directly bonded to the bond pads 168.

[0093] The first integrated circuit die 50A is bonded to the front-side interconnect structure 160 without the use of solder joints (e.g., micro-bumps or the like). Direct bonding of the first integrated circuit die 50A to the front-side interconnect structure 160 offers advantages such as a narrower bump center-to-center distance; small form factor packages through the use of hybrid bonds; reduced bond center-to-center distance scalability for chip I / O to achieve high-density die-die interconnects; improved mechanical durability; improved electrical performance; fewer defects; and increased yield.Furthermore, smaller die-die distances between the first integrated circuit die 50A and other integrated circuit dies can be achieved, which has the advantages of a smaller form factor, higher bandwidth, improved power integrity (PI), improved signal integrity (SI) and lower power consumption.

[0094] In Fig. 24. Bond pads 126 are formed on the front-side interconnect structures 160 over the first interface die 111A and the second interface die 111B, a second integrated circuit die 50B is bonded to the front-side interconnect structures 160 over the first interface die 111A and the second interface die 111B by solder bonding, and a third integrated circuit die 50C is bonded to the front-side interconnect structure 160 over the second interface die 111B by solder bonding. The bond pads 126 and the conductive connectors 128 can be formed over the front-side interconnect structures 160 from materials and using processes that are the same as or similar to those of the bond pads 126 and the conductive connectors 128 described above with respect to Fig. 6 were described.

[0095] A desired type and quantity of integrated circuit dies 50 can be bonded to the front-facing interconnect structure 160 by solder bonding, for example, one or more of the second integrated circuit dies 50B and one or more of the third integrated circuit dies 50C. In the embodiment shown, a single second integrated circuit die 50B is bonded to the front-facing interconnect structures 160 over the first interface die 111A and the second interface die 111B, and a single third integrated circuit die 50C is bonded to the front-facing interconnect structure 160 over the second interface die 111B. The second integrated circuit die 50B can consist of a bridge die, which may be a logic device or a passive device.In embodiments where the second integrated circuit die 50B consists of a logic device, the second integrated circuit die 50B can be a CPU, a GPU, a SoC, a microcontroller, or the like. In embodiments where the second integrated circuit die 50B consists of a passive device, the second integrated circuit die 50B can be an input-output die (I / O die), a SED die, or the like. The third integrated circuit die 50C can consist of a memory device, such as a DRAM die, an SRAM die, a NAND flash die, an HMC module, an HBM module, or the like. Although the third integrated circuit die 50C is shown as a single integrated circuit die, the third integrated circuit die 50C can have multiple stacked integrated circuit dies (also called die stacks).

[0096] The second integrated circuit die 50B and the third integrated circuit die 50C are attached to the front-facing interconnect structures 160 using solder bonds, for example, with the conductive connectors 128. The second integrated circuit die 50B and the third integrated circuit die 50C can be positioned on the front-facing interconnect structures 160 using, for example, a pick-and-place tool. Attaching the second integrated circuit die 50B and the third integrated circuit die 50C to the front-facing interconnect structures 160 can involve positioning the second integrated circuit die 50B and the third integrated circuit die 50C on the front-facing interconnect structures 160 and soldering the conductive connectors 128.The conductive connectors 128 form connections between the bond pads 126 on the front interconnect structures 160 and the die connectors 66 of the second integrated circuit die 50B and the third integrated circuit die 50C, thereby electrically connecting the first interface die 111A and the second interface die 111B to the second integrated circuit die 50B and the third integrated circuit die 50C via the front interconnect structures 160.

[0097] An underfill material 129 can be formed around the conductive connectors 128 and between the front-side interconnect structures 160 and both the second integrated circuit die 50B and the third integrated circuit die 50C. As shown in Fig. As shown in Figure 24, the backing material 129 can consist of a continuous material or two separate, discontinuous materials. The backing material 129 can reduce stresses and protect the connections resulting from the melting of the conductive connectors 128. The backing material 129 can be formed from any suitable backing material, such as a molding compound, an epoxy, or the like. The backing material 129 can be formed by a capillary flow process after the second integrated circuit die 50B and the third integrated circuit die 50C have been attached to the front interconnect structures 160, or it can be formed by a suitable deposition process before the second integrated circuit die 50B and the third integrated circuit die 50C have been attached to the front interconnect structures 160.The underfill material 129 can be applied in liquid or semi-liquid form and subsequently cured. In some embodiments, the underfill material 129 is omitted, and the underfill material 129 is omitted in subsequent figures.

[0098] The first integrated circuit die 50A, the second integrated circuit die 50B, and the third integrated circuit die 50C can be formed by processes at the same technology node or by processes at different technology nodes. For example, the first integrated circuit die 50A can originate from a more advanced process node than the second integrated circuit die 50B and / or the third integrated circuit die 50C. The first integrated circuit die 50A, the second integrated circuit die 50B, and / or the third integrated circuit die 50C can have different dimensions (e.g., different heights and / or areas) or they can have the same dimensions (e.g., the same height and / or area). Other combinations of integrated circuit dies are also possible.In some embodiments, the first integrated circuit die 50A, the second integrated circuit die 50B and the third integrated circuit die 50C may have a thickness of more than approximately 100 µm.

[0099] The first integrated circuit die 50A and the third integrated circuit die 50C can be electrically connected to each other and to the second integrated circuit die 50B via the front-side interconnect structures 160. The first integrated circuit die 50A is physically and electrically connected to the front-side interconnect structure 160 on the first interface die 111A via hybrid bonds between the die connectors 66 and the bond pads 168. The second integrated circuit die 50B is physically and electrically connected to the front-side interconnect structures 160 on the first interface die 111A and the second interface die 111B via solder bonds between the die connectors 66 and the bond pads 126. The third integrated circuit die 50C is physically and electrically connected to the front-side interconnect structure 160 on the second interface die 111B by solder bonds between the die connectors 66 and the bond pads 126.In some embodiments, the first integrated circuit die 50A can consist of a logic die, the second integrated circuit die 50B can consist of a bridge die, and the third integrated circuit die 50C can consist of a memory die. The first integrated circuit die 50A has a relatively smaller die connector center-to-center spacing 66 and a higher circuit density, while the second integrated circuit die 50B and the third integrated circuit die 50C have relatively larger die connector center-to-center spacing 66 and a lower circuit density. Bonding the first integrated circuit die 50A to the front-side interconnect structure 160 by hybrid bonding provides advantages such as a narrower hump center-to-center spacing, higher bandwidth, and improved device performance.Bonding the second integrated circuit die 50B and the third integrated circuit die 50C to the front-side interconnect structure 160 by solder bonding reduces costs.

[0100] In Fig. 25 A second encapsulation material 133 is formed on the first interface die 111A, the second interface die 111B, and the first encapsulation material 131, and around the first integrated circuit die 50A, the second integrated circuit die 50B, and the third integrated circuit die 50C. The second encapsulation material 133 can be formed from materials and using processes that are the same as or similar to those of the encapsulation material 130 described above. Fig. 8 were described. The second encapsulation material 133 can be thinned to expose the back sides of the first integrated circuit die 50A, the second integrated circuit die 50B, and the third integrated circuit die 50C.

[0101] In Fig. 26 The support substrate 100 is removed; the back surfaces of the interface substrates 110 and the first encapsulation material 131 are thinned; a backside interconnect structure 170 is formed on the back surfaces of the interface substrates 110 and the first encapsulation material 131; and optionally, a heat dissipation layer 159 is formed on the encapsulation material 130, the first integrated circuit die 50A, and the second integrated circuit die 50B. The heat dissipation layer 159, the encapsulation material 130, the first integrated circuit die 50A, the second integrated circuit die 50B, the third integrated circuit die 50C, the first interface die 111A, and the second integrated circuit die 111B form a fourth packaged component 500.A support substrate debonding process is performed to separate the support substrate 100 from the first interface die 111A, the second interface die 111B, and the first encapsulation material 131. In some embodiments, the debonding process involves projecting light, such as laser light or UV light, onto the separating layer 102, causing the separating layer 102 to decompose under the heat of the light and allowing the support substrate 100 to be removed. As shown in... Fig. As shown in Figure 26, surfaces of the first interface die 111A, the second interface die 111B and the first encapsulation material 131 can be exposed after the support substrate 100 and the separating layer 102 have been removed.

[0102] The interface substrates 110 and the first encapsulation material 131 can be thinned by a planarization process applied to them, exposing the conductive vias 114. Once exposed, the conductive vias 114 extend through the interface substrates 110 and can be referred to as TSVs. Planarization can remove sections of the interface substrates 110 relative to the dielectric layer 112, thus exposing the conductive vias 114. Planarization can be achieved by any suitable process, such as CMP, grinding, etching, or a combination thereof.After planarization, the conductive vias 114 can extend completely through the interface substrates 110 and provide a connection between opposite sides of the interface substrates 110.

[0103] The rear interconnect structure 170 can be formed from materials and using processes that are the same as or similar to those of the front interconnect structure 150 described above in relation to Fig. The rear interconnect structure 170 has dielectric layers 172 and metallization layers 174 within the dielectric layers 172. The dielectric layers 172 and the metallization layers 174 can be formed from materials and using processes that are the same as or similar to those of the dielectric layers 152 and the metallization layers 154, respectively.

[0104] UBMs 176 and conductive connectors 178 are designed for external connection to the rear interconnect structure 170. The UBMs 176 and the conductive connectors 178 can be formed from materials and using processes that are the same as or similar to those of the UBMs 156 and the conductive connectors 158 described above in relation to Fig.The UBMs 176 have hump sections on and along an upper surface of a top dielectric layer 172 of the backside interconnect structure 170 and have via sections extending through the top dielectric layer 172 of the backside interconnect structure 170. The via sections can be physically and electrically connected to a top metallization layer 174 of the backside interconnect structure 170. The UBMs 176 can be electrically connected to the conductive vias 114, the first integrated circuit die 50A, and the second integrated circuit die 50B.

[0105] The heat dissipation layer 159 is formed over the encapsulation material 130, the first integrated circuit die 50A, and the second integrated circuit die 50B. The heat dissipation layer 159 is formed from a material with high thermal conductivity, such as a metal or a metal nitride. In some embodiments, the heat dissipation layer 159 may be formed from aluminum, titanium, titanium nitride, nickel, nickel vanadium, silver, gold, copper, combinations thereof, or the like. The heat dissipation layer 159 may be formed conformally by a PVD process such as sputtering or evaporation; a plating process such as electroless plating or electroplating; a printing process such as inkjet printing; or the like. In some embodiments, the heat dissipation layer 159 is formed from copper by a sputtering process.The heat dissipation layer 159 can be included to increase heat dissipation from the first integrated circuit die 50A and the second integrated circuit die 50B. In some embodiments, the heat dissipation layer 159 can be formed over the encapsulation material 130, the first integrated circuit die 50A, and the second integrated circuit die 50B before the encapsulation material 130, the first integrated circuit die 50A, and the second integrated circuit die 50B are mounted on the support substrate 140. In some embodiments, the heat dissipation layer 159 can be omitted.

[0106] The inclusion of hybrid bonding of the first integrated circuit die (50A) with the front-side interconnect structure 160 over the first interface die (111A), as well as solder bonding of the second integrated circuit die (50B) and the third integrated circuit die (50C) with the front-side interconnect structures 160 over the first interface die (111A) and the second interface die (111B), allows for the benefits of both hybrid and solder bonding. For example, hybrid bonding of the first integrated circuit die (50A) enables bonding of dies with small center-to-center distances using the front-side interconnect structure 160, providing higher bandwidth and improved device performance. Solder bonding of the second integrated circuit die (50B) and the third integrated circuit die (50C) reduces costs while still ensuring sufficiently small bond center-to-center distances.

[0107] Certain embodiments can offer specific advantages. Bonding the first integrated circuit die 50A to the interface dies 111 via hybrid bonding allows for bonding dies with small center-to-center distances to the interface dies 111, providing higher bandwidth and improved device performance. Bonding the second integrated circuit die 50B and / or the third integrated circuit die 50C to the interface dies 111 via solder bonding reduces costs while still ensuring sufficiently small bond center-to-center distances.

[0108] The bonding processes described above are performed at the die level, where the integrated circuit dies 50 are bonded to the interface dies 111 after the interface dies 111, which are bonded to the integrated circuit dies 50, have been singulated into separate dies. Alternatively, bonding can be performed at the die-wafer or wafer-wafer level, and subsequent singulation processes can be carried out.

[0109] According to one embodiment, a package comprises a first interposer, wherein the first interposer includes a first redistribution structure; a first die bonded to a first surface of the first redistribution structure by a dielectric-dielectric bond and a metal-metal bond; a second die bonded to the first surface of the first redistribution structure by a first solder bond; an encapsulation material surrounding the first die and the second die; and multiple conductive connectors on a second side of the first redistribution structure opposite the first die and the second die. In one embodiment, the first die includes a logic die, and the second die includes a memory die.In one embodiment, the package further comprises a second interposer adjacent to the first interposer, wherein the second interposer has a second redistribution structure, the second die being bonded to a first surface of the second redistribution structure by a second solder bond. In another embodiment, the package further comprises a third die, which is bonded to the first surface of the second redistribution structure by a third solder bond. In another embodiment, the package further comprises a second encapsulation material extending from the first interposer to the second interposer. In another embodiment, an upper surface of the encapsulation material, an upper surface of the first die, and an upper surface of the second die are planar.In one embodiment, the package further features an under-bump metallization on the first surface of the first redistribution structure, wherein the second die is bonded to the first redistribution structure by the first solder bond on the under-bump metallization, and a surface of the under-bump metallization is planar with a surface of the first die.

[0110] According to a further embodiment, a semiconductor package comprises a first interface die; a second interface die adjacent to the first interface die; a first encapsulation material extending from the first interface die to the second interface die; a first integrated circuit die bonded to the first interface die by a dielectric-dielectric bond and a metal-metal bond; and a second integrated circuit die bonded to the second interface die by a first solder bond. In one embodiment, the second integrated circuit die is further bonded to the first interface die by a second solder bond. In another embodiment, the semiconductor package further comprises a third integrated circuit die bonded to the second interface die by a third solder bond.In one embodiment, the first integrated circuit die consists of a logic die, the second integrated circuit die consists of a bridge die, and the third integrated circuit die consists of a memory die. In another embodiment, the first interface die has a first interconnect structure, the first integrated circuit die is bonded to a first surface of the first interconnect structure, the second interface die has a second interconnect structure, the second integrated circuit die is bonded to a second surface of the second interconnect structure, and the first and second surfaces are planar.In one embodiment, the semiconductor package further comprises a second encapsulation material around the first integrated circuit die and the second integrated circuit die, wherein the second encapsulation material contacts the first integrated circuit die, the second integrated circuit die, the first interface die and the second interface die.

[0111] According to yet another embodiment, a method comprises providing a first interposer having a first interconnect structure on a first interposer substrate; bonding a first die to the first interconnect structure, wherein the bonding of the first die comprises direct bonding of a first insulating layer of the first die to a bonding layer of the first interconnect structure and direct bonding of a first die connector of the first die to a first bond pad of the first interconnect structure; bonding a second die to the first interconnect structure, wherein the bonding of the second die comprises solder bonding of a second die connector of the second die to a second bond pad of the first interconnect structure; and encapsulating the first die and the second die in a molding compound.In one embodiment, the method further comprises forming a first under-bump metallization on the second bond pad; forming a conductive connector on the first under-bump metallization; and melting the conductive connector to connect the second die to the first interconnect structure. In one embodiment, the method further comprises planarizing the molding compound, the first die, and the second die. In one embodiment, the method further comprises forming an underfill material between the second die and the first interconnect structure, wherein the underfill material surrounds solder joints formed between the second die and the first interconnect structure. In one embodiment, the molding compound is formed around solder joints formed between the second die and the first interconnect structure.In one embodiment, the method further comprises providing a second interposer adjacent to the first interposer, wherein the second interposer has a second interconnect structure on a second interposer substrate, bonding the second die to the first interconnect structure, and bonding the second die to the second interconnect structure by solder bonding. In another embodiment, the method further comprises bonding a third die to the second interconnect structure, wherein the bonding of the third die comprises solder bonding a third die connector of the third die to a third bond pad of the second interconnect structure.

Claims

[1] Package, containing: a first interposer (111A) wherein the first interposer (111A) has a first redistribution structure (160); a first die (50A) which is bonded to a first surface of the first redistribution structure (160) by a dielectric-dielectric bond and a metal-metal bond; a second interposer (111B) adjacent to the first interposer (111A), wherein the second interposer (111B) has a second redistribution structure (160); a second die (50B) which is bonded to a first surface of the second redistribution structure (160) by a first lot bond (128); an encapsulation material (133) around the first die (50A) and the second die (50B); and several conductive connectors (128) on a second side of the first redistribution structure (160) opposite the first die (50A) and the second die (50B). [2] Package according to claim 1, wherein the first die (50A) comprises a logic die, and wherein the second die (50B) comprises a memory die. [3] Package according to claim 1 or 2, wherein the second die (50B) is bonded to the first surface of the first redistribution structure (160) by a second lot bond (128). [4] Package according to claim 3, further comprising a third die (50C) which is bonded to the first surface of the second redistribution structure (160) by a third lot bond (128). [5] Package according to claim 3 or 4, further comprising a second encapsulation material (131) extending from the first interposer (111A) to the second interposer (111B). [6] Package according to any of the preceding claims, wherein an upper surface of the encapsulation material (133), an upper surface of the first die (50A) and an upper surface of the second die (50B) are planar. [7] Package according to one of the preceding claims, further comprising an under-bump metallization (126) on the first surface of the first redistribution structure (160), wherein the second die (50B) is bonded to the first redistribution structure (160) by the first solder bond (128) on the under-bump metallization (126), and wherein a surface of the under-bump metallization (126) is planar with a surface of the first die (50A). [8] Semiconductor package comprising: a first interface die (111A); a second interface die (111B) adjacent to the first interface die (111A); a first encapsulation material (131) extending from the first interface die (111A) to the second interface die (111B); a first integrated circuit die (50A) bonded to the first interface die (111A) by a dielectric-dielectric bond and a metal-metal bond; and a second integrated circuit die (50B) which is bonded to the second interface die (111B) by a first solder bond (128). [9] Semiconductor package according to claim 8, wherein the second integrated circuit die (50B) is further bonded to the first interface die (111A) by a second solder bond (128). [10] Semiconductor package according to claim 9, further comprising a third integrated circuit die (50C) which is bonded to the second interface die (111B) by a third solder bond (128). [11] Semiconductor package according to claim 10, wherein the first integrated circuit die (50A) consists of a logic die, wherein the second integrated circuit die (50B) consists of a bridge die and wherein the third integrated circuit die (50C) consists of a memory die. [12] Semiconductor package according to any one of claims 8 to 11, wherein the first interface die (111A) has a first interconnect structure (160), wherein the first integrated circuit die (50A) is bonded to a first surface of the first interconnect structure (160), wherein the second interface die (111B) has a second interconnect structure (160), wherein the second integrated circuit die (50B) is bonded to a second surface of the second interconnect structure (160), and wherein the first surface and the second surface are planar. [13] Semiconductor package according to one of claims 8 to 11, further comprising a second encapsulation material (133) around the first integrated circuit die (50A) and the second integrated circuit die (50B), wherein the second encapsulation material (133) contacts the first integrated circuit die (50A), the second integrated circuit die (50B), the first interface die (111A) and the second interface die (111B). [14] Procedures, including: Providing a first interposer (111A) having a first interconnect structure (160) on a first interposer substrate (110); Providing a second interposer (111B) adjacent to the first interposer (111A), wherein the second interposer has a second interconnect structure (160) on a second interposer substrate (110); Bonding a first die (50A) to the first interconnect structure (160), wherein the bonding of the first die (50A) comprises direct bonding of a first insulating layer of the first die (50A) to a bonding layer of the first interconnect structure (160) and direct bonding of a first die connector (66) of the first die (50A) to a first bond pad (168) of the first interconnect structure (160); Bonding a second die (50B) to the second interconnect structure (160), wherein the bonding of the second die (50B) comprises solder bonding a second die connector (66) of the second die (50B) to a second bond pad 168 of the second interconnect structure (160); and Encapsulation of the first die (50A) and the second die (50B) in a molding compound (133). [15] The method of claim 14, further comprising: Forming a first under-bump metallization (126) on the second bond pad (168); Forming a conductive connector (128) on the first under-bump metallization (126); and Melting the conductive connector (128) to connect the second die (50B) to the first interconnect structure (160). [16] Method according to claim 14 or 15, further comprising planarizing the molding compound (133), the first die (50A) and the second die (50B). [17] Method according to any one of claims 14 to 15, further comprising forming an underfill material (129) between the second die (50B) and the first interconnect structure (160), wherein the underfill material (129) surrounds solder connections formed between the second die (50B) and the first interconnect structure (160). [18] Method according to any one of claims 14 to 16, wherein the molding compound (133) is formed around solder joints formed between the second die (50B) and the first interconnect structure (160). [19] Method according to any one of claims 14 to 18, wherein bonding the second die (50B) to the second interconnect structure (160) also bonds the second die (50B) to the first interconnect structure (160) by solder bonding. [20] Method according to claim 19, further comprising bonding a third die (50C) to the second interconnect structure (160), wherein the bonding of the third die (50C) comprises solder bonding a third die connector (66) of the third die (50C) to a third bond pad (168) of the second interconnect structure (160).

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