External non-volatile storage with additional functionality

Abstract

External non-volatile storage device comprising: an overwritable non-volatile memory (140); and an interface (90), wherein the interface (90) has: a bidirectional data signal; and a clock input, wherein the clock input has a frequency greater than 1 GHz, uses an asymmetric CMOS signaling and is used to generate a memory Serdes clock (127) which is used to clock outgoing data sent on the bidirectional data signal.

Description

Area

[0001] The present disclosure describes systems for maximizing CPU performance using external non-volatile memory. background

[0002] System-on-a-Chip (SoC) and other similar devices are created by integrating a processing unit, its instructions, and other functions within a single die. In some cases, the processing unit may be an ARM-based processor, although other processors can be used. Furthermore, in some embodiments, the instructions are located within rewritable non-volatile memory (NVM), such as flash memory.

[0003] The miniaturization of NVM, however, has delayed transistor miniaturization. For example, transistor miniaturization has reached 22 nm, and further shrinkage to smaller geometries is planned. In contrast, NVM technology is currently limited to 40 nm or larger geometries. This leaves system designers with a dilemma. The SoC can be manufactured using an older technology to allow for the integration of flash memory. However, this approach limits the number of transistors in the device and also results in higher power consumption.

[0004] Alternatively, the SoC can be manufactured using the latest technology. In this configuration, the developer can choose to use a ROM-based architecture, which does not allow for future software updates. Alternatively, newer NVM technologies such as ReRAM or MRAM can be used. However, these memory technologies are not yet fully mature. Yet another alternative is to use external non-volatile memory.

[0005] Existing external non-volatile memory uses a Serial Peripheral Interface (SPI) interface. Unfortunately, this memory has long access times. For example, it can take more than 64 CPU cycles to fill a 4-word cache line at single data rate (SDR). Furthermore, the interface to this external non-volatile memory operates at 1.8 V, which consumes power.

[0006] Furthermore, there is no security associated with these external non-volatile storage devices. This can allow a hacker or other malicious actor to monitor the processing unit or inject code into it.

[0007] Therefore, it would be advantageous to have a configuration that allowed locally updatable code, for which a current manufacturing technology would be applied, which would be secure and consume little power.

[0008] US 2011 / 0 239 031 A1 concerns high-speed signaling in low-power applications.

[0009] US 6 775 328 B1 concerns a high-speed communication system with a feedback synchronization loop.

[0010] US 2019 / 0 122 007 A1 describes techniques for multiplexing between an Execute-in-Place (XIP) mode and a memory-mapped input / output (MMIO) mode for accessing external storage devices.

[0011] EP 3 842 976 A1 a method for secure access to at least one feature of a chip.

[0012] It is therefore an object of the present invention to provide an external non-volatile storage device which has reduced power consumption. Brief description

[0013] This problem is solved by a storage device with the features according to claim 1. Preferred embodiments are described in dependent claims 2 to 12.

[0014] An external non-volatile storage device is disclosed, comprising a rewritable non-volatile memory and a CMOS interface. The interface includes a clock signal that is input into the external non-volatile storage device. This clock signal is multiplied by an integer to generate a memory S-S-E clock, which is used to clock outgoing data. The memory S-S-E clock is also used to generate a clock that is used to clock data received from the main processing device. The external non-volatile storage device further includes an encryption / decryption block that encrypts data read from the non-volatile memory before it is sent via the interface and decrypts data received by the interface before it is stored in the non-volatile memory.A stream cipher can be used in the encryption / decryption block.

[0015] According to one embodiment, an external non-volatile storage device is disclosed. The external non-volatile storage device comprises a rewritable non-volatile memory; an interface, wherein the interface has a bidirectional data signal; and a clock input, wherein the clock input is used to generate a memory-Serdes clock, which is used to clock outgoing data transmitted on the bidirectional data signal. In certain embodiments, the clock input is multiplied by an integer to generate the memory-Serdes clock. In some embodiments, the integer is 2. In some embodiments, the clock input has a frequency greater than 1 GHz. In some embodiments, the data is transmitted at a rate greater than 2 Gbit / s.In some embodiments, the clock input is held in a disabled state when no data is being sent on the bidirectional data signal.

[0016] In some embodiments, the external non-volatile storage device includes an encryption / decryption block for encrypting data read from the rewritable non-volatile memory before the data is transmitted over the interface. In certain embodiments, a stream cipher is used in the encryption / decryption block. In some embodiments, the external non-volatile storage device includes a circuit system for appending a cyclic redundancy code (CRC) to the data transmitted over the interface. In some embodiments, the encryption / decryption block decrypts data received at the interface before the data is written to the rewritable non-volatile memory. In certain embodiments, CMOS signaling is used in the bidirectional data signal.In some embodiments, the external non-volatile storage device supports safe boot-up.

[0017] The above-mentioned problem is also solved by a system with the features according to claim 13.

[0018] In another embodiment, a system is disclosed. The system comprises the external non-volatile storage device described above and a main processing device, wherein the main processing device comprises the bidirectional data signal; an outgoing clock signal; and a radio circuit configured to send and receive packets at an RF frequency, wherein a frequency of the outgoing clock signal is selected such that the frequency or a harmonic oscillation thereof is within 10% of the RF frequency.

[0019] The aforementioned problem is also solved by a storage device with the features according to claim 14. Preferred embodiments are described in dependent claims 15 to 20.

[0020] In a further embodiment, an external non-volatile storage device is disclosed. The external non-volatile storage device comprises a rewritable non-volatile memory; an interface, wherein the interface has a bidirectional data signal; an interrupt signal and a clock input; and an encryption / decryption block for encrypting data read from the rewritable non-volatile memory before the data is transmitted via the interface. In certain embodiments, a stream cipher is used in the encryption / decryption block. In some embodiments, the external non-volatile storage device includes a circuit system for appending a cyclic redundancy code (CRC) to the data transmitted via the interface.In some embodiments, the encryption / decryption block decrypts data received at the interface before writing the data to the rewritable non-volatile memory. In some embodiments, the interrupt signal is activated when an error is detected by the encryption / decryption block. In some embodiments, the external non-volatile storage device includes a processing unit, and the interrupt signal is activated when the processing unit wishes to provide information to a device connected to the interface. In some embodiments, the external non-volatile storage device is reset when the interrupt signal is activated by another device. Brief description of the drawings

[0021] For a better understanding of the present revelation, reference is made to the accompanying drawings, in which similar elements are designated with similar reference numbers and in which: Fig. 1 shows a main processing device and an associated external non-volatile storage device; Fig. 2 a block diagram of the interface between the main processing device and the associated external non-volatile storage device; Fig. 3 shows a time diagram illustrating the operation of the interface; Fig. 4 is a block diagram of the external non-volatile storage device; and Fig. Figure 5 shows the performance spectrum of a random data structure compared to the wireless channel frequency. Detailed description

[0022] Fig. Figure 1 shows a block diagram with a main processing device 10 and an associated external non-volatile storage device 100. The main processing device 10 can include an embedded processing unit and a cache memory. In certain embodiments, the main processing device 10 can be fabricated using 22 nm technology. In some embodiments, a smaller geometry can be used. This selection allows for a maximum number of transistors while minimizing power consumption.

[0023] The external non-volatile storage device 100 can be manufactured using older technologies, such as 40 nm or 90 nm. These technologies are better suited for rewritable non-volatile storage devices like FLASH memory.

[0024] Furthermore, an interface 90, also known as the Serdes interface, can be used to exchange data between the two devices. The interface 90 can include one or more data signals. It can also include a clock signal. Using a clock signal allows for faster data exchange between the devices because clock reconstruction is not required. The interface 90 can use unbalanced CMOS signals, which consume less power than LVDS signals. In certain embodiments, the voltage used for the signals in the interface 90 can be less than 2 V. In some embodiments, the voltage can be less than 1 V.

[0025] In addition to data signals and a clock signal, the interface 90 may also include other signals. For example, in certain embodiments, the main processing device 10 may supply power to the external non-volatile storage device 100. In this way, the external non-volatile storage device 100 can utilize the DC-DC converter located in the main processing device 10. In certain embodiments, the interface 90 may include a reset signal. In certain embodiments, the interface 90 may include an interrupt signal (IRQ signal).

[0026] Fig. Figure 2 shows a block diagram of the interface between the main processing device 10 and the external non-volatile storage device 100. Each block within the main processing device 10 and within the external non-volatile storage device 100 can be an integrated circuit comprising several transistors configured to perform the described operation or function. Furthermore, as stated above, the non-volatile memory is overwritable.

[0027] The main processing unit 10 comprises an external oscillator 11, which may be a crystal. This external oscillator 11 communicates with a clock multiplier 12, which multiplies the clock signal from the external oscillator 11 to obtain signals with higher frequencies. An output of the clock multiplier 12, referred to as the Serdes clock, can be higher than 2 GHz, e.g., 2.4 GHz or more. The Serdes clock can then be provided as an input to the clock divider 13, which divides the high-frequency clock for use within other blocks of the main processing unit 10, e.g., to generate the clock for the processing unit 30, which may be an ARM processor.

[0028] The Serdes clock determines the data rate of interface 90. For example, if the Serdes clock 27 has a frequency of 2.5 GHz, then data can be sent at a rate of 2.5 Gbit / s. In certain embodiments, the Serdes clock is higher than 2 GHz, so that data can be sent at a rate of more than 2 Gbit / s.

[0029] The Serdes clock signal is also provided to a divider 15, which divides the high-frequency clock signal by an integer (N). This reduction in the frequency of the Serdes clock signal reduces the power consumption of the clock driver 25. In some embodiments, N can be 2. The reduced-frequency clock signal 26 is then sent to the external non-volatile memory device 100 using the clock driver 25. The reduced-frequency clock signal 26 can have a frequency greater than 1 GHz.

[0030] The Serdes clock is also provided to a clock phase alignment block 14. This block is used to align the phase of the clock used by the serial-to-parallel converter (S2P converter) 22 with the incoming data from the external non-volatile storage device 100.

[0031] The main processing device 10 also includes an incoming and an outgoing data path.

[0032] The outgoing data path includes a send FIFO 16 and a packetizer 17 for generating packets from the data to be sent. The packets can contain commands, data, and other control information. The output of the packetizer 17 is then provided to a parallel-to-serial converter (P2S converter) 18. The P2S converter 18 can be clocked using the Serdes clock. The output from the P2S converter 18, which is a serial bitstream, is then provided to the data output buffer 19.

[0033] The data input path includes a data input buffer 23. The output from the data input buffer 23 is then provided to a serial-to-parallel converter (S2P converter) 22. The S2P converter 22 is clocked by the output of the clock phase alignment block 14, which centers each incoming data bit around a rising clock edge. The output of the S2P converter 22, which is parallel data, is used by the depacketizer 21 to extract the necessary information from the incoming data, which is in packet form. The output of the depacketizer 21 is then provided to the receive FIFO 20.

[0034] The external non-volatile storage device 100 is configured to be connected to the main processing device 10. Therefore, it has a multiplier 115, which receives the reduced-frequency clock 26 sent by the clock driver 25. The multiplier 115 multiplies the received clock by a factor that is the same as the divisor by which the divider 15 performed the division. In this way, the output of the multiplier 115, which is called the storage Serdes clock 127, has the same frequency as the Serdes clock 27.

[0035] The external non-volatile storage device 100 also includes an incoming and an outgoing data path.

[0036] The outgoing data path includes a send FIFO 116 and a packetizer 117 for generating packets from the data to be sent. The output of the packetizer 117 is then provided to a parallel-to-serial converter (P2S converter) 118. The P2S converter 118 can be clocked using the memory-Serde clock 127. The output from the P2S converter 118 is then provided to the data output buffer 119.

[0037] The data input path includes a data input buffer 123. The output from the data input buffer 123 is then provided to a serial-to-parallel converter (S2P converter) 122. The S2P converter 122 is clocked by the output of the clock phase alignment block 114, which centers each incoming data bit around the rising clock edge. Specifically, the clock phase alignment block receives the memory S-EDE clock 127 as an input and generates a clock that has the same frequency as the memory S-EDE clock 127, but with a different phase aligned with the incoming data. The output of the S2P converter 122 is used by the depacket 121 to extract the necessary information from the incoming data. The output of the depacket 121 is then provided to the receive FIFO 120.

[0038] The transmit and receive FIFOs communicate with a non-volatile memory controller (NVM controller) 130, which is responsible for providing addresses to the non-volatile memory 140, which can be a flash memory or another rewritable non-volatile memory. The data is stored in the non-volatile memory 140.

[0039] Furthermore, the data paths can include security and error correction mechanisms. For example, packetizers can include a circuit system for appending a cyclic redundancy code (CRC) to the packet before transmission. Similarly, depackers can use a circuit system that utilizes the CRC appended by the packetizers to verify that there are no transmission errors.

[0040] Furthermore, additional security features can be incorporated into the main processing device 10 and the external non-volatile storage device 100. For example, a security module 50 can be incorporated into the main processing device 10, and a security module 150 can also be incorporated into the external non-volatile storage device 100. In certain embodiments, the security modules can be used to encrypt the transmitted data. For example, a Galois / Counter-Mode (GCM) algorithm can be used to encrypt the data. Of course, other algorithms can also be used. Although the security modules are represented as separate blocks, it is understood that these modules interact with the respective incoming and outgoing data paths.

[0041] Furthermore, the safety modules, as described in more detail below, enable a safe startup.

[0042] In certain embodiments, there can be separate external connections for outgoing data (i.e., data sent from the main processing device 10 to the external non-volatile storage device 100) and incoming data (i.e., data sent from the external non-volatile storage device 100 to the main processing device 10). Thus, in this mode, there are two (or more) unidirectional data signals between the main processing device 10 and the external non-volatile storage device 100. Furthermore, in this mode, the output of the data output buffer 19 is not connected to the input of the data input buffer 23, and the output of the data output buffer 119 is not connected to the input of the data input buffer 123.

[0043] In other embodiments, such as those in Fig. As shown in Figure 2, the data signals can be bidirectional and operate in half-duplex mode to minimize external connections. In this embodiment, the output of data output buffer 19 and the input of data input buffer 23 are connected by a single external connection. Similarly, the output of data output buffer 119 and the input of data input buffer 123 are connected by a single external connection. Furthermore, these two external connections are linked via a trace located on the printed circuit board.

[0044] Half-duplex connections are configured such that all data exchange is initiated by the main processing device 10. In other words, the external non-volatile storage device 100 never initiates a data exchange with the main processing device 10. Instead, it only responds to data exchanges initiated by the main processing device 10.

[0045] As an example, Fig. 3. A series of data exchange operations takes place between the main processing device 10 and the external non-volatile storage device 100. At time T0, the main processing device 10 initiates a data exchange by sending a packet to the external non-volatile storage device 100. This packet can be a command to read multiple locations, starting at a specified address. Because the main processing device 10 initiates each data exchange, it does not need to detect the data signal or wait before starting to send the packet at time T0. After sending the packet, both devices recognize that the response requires the external non-volatile storage device 100 to send data back to the main processing device 10. In response, at time T1, the main processing device 10 turns off its data output buffer 19 and turns on its data input buffer 23.Similarly, the external non-volatile storage device 100 turns on its data output buffer 119 and turns off its data input buffer 123. This process can take a certain amount of time, represented as T. wait Note that the duration T waitThe waiting time is shorter than the time required to read the contents of the FLASH memory, so there is no disadvantage to introducing this waiting time. At time T2, the external non-volatile storage device 100 sends an initial packet. This packet can contain data located at the specified address in the FLASH. If, at time T3, the external non-volatile storage device 100 needs to send a second packet, for example, to send more data from the FLASH, it simply begins sending it. No waiting is required because the previous packet was also sent by the external non-volatile storage device 100 to the main processing device 10. At time T4, the sending of the second packet is complete. Before the main processing device 10 can send another packet at time T5, a waiting period must be inserted to allow the data buffers to be reconfigured.

[0046] In certain embodiments, the main processing device 10 can direct all outputs in the interface 90 to the low state when there is no activity between the two devices. In certain embodiments, this includes the clock signal.

[0047] Fig. Figure 4 shows a block diagram of the external non-volatile storage device 100.

[0048] The Serdes module 125 and the Serdes controller 126 contain the logic for managing the transition between serial data sent on the external interface and parallel data used by the non-volatile memory 140. Therefore, the Serdes module 125 and the Serdes controller 126 include many of the functions described in Fig. The components described above include, for example, the data input buffer 123, the S2P converter 122, the depacketizer 121, the receive FIFO 120, the transmit FIFO 116, the packetizer 117, the P2S converter 118, the data output buffer 119, the clock phase alignment module 114, and the multiplier 115. These blocks perform the function described above. Furthermore, the Serdes module 125 and the Serdes controller 126 can also generate a clock signal based on the memory Serdes clock 127. For example, the memory Serdes clock 127 can be divided by a number such as 8, 16, or 32 to generate an internal clock.

[0049] As described above, the security module 150 can be used to encrypt the data sent to the main processing device 10. Part of the security module 150 can include an encryption / decryption block 151. This encryption / decryption block 151 can use a known algorithm such as AES or another algorithm such as a stream cipher. The encryption / decryption block 151 is used to encrypt data read from the NVM 140 before it is sent on interface 90. The encryption / decryption block 151 is also used to decrypt data received from the main processing device 10 before it is written to the NVM 140.

[0050] The NVM controller 130 is used to control access to the non-volatile memory 140. The NVM controller 130 comprises the state machine that reads and writes to the non-volatile memory 140. For example, writing to a flash memory is a multi-cycle process that takes many milliseconds with asynchronous timing of various signals to the non-volatile memory 140. The NVM controller 130 manages the control of these various signals.

[0051] In addition to the functions used for data transfers, the external non-volatile storage device 100 also includes other blocks. For example, the external non-volatile storage device 100 has a processing unit 160, which can be a RISC-V processor. Random access memory (RAM) 165 can be used to hold information used by the processing unit 160. This processing unit 160 performs various functions.

[0052] The processing unit 160 can be responsible for handling updates to the non-volatile memory 140. For example, the processing unit 160 can be responsible for executing instructions that supply data to the non-volatile memory 140 with the required timing. This can be done in support of write or read operations performed on the non-volatile memory 140.

[0053] Furthermore, the processing unit 160 can be used to warn the main processing device 10 of unexpected events. For example, the processing unit 160 can activate the interrupt signal (IRQ signal) when a fault is detected in the safety module 150. The interrupt signal (IRQ signal) can also be activated when the processing unit 160 wants to provide data or a status to the main processing device 10. In certain embodiments, the interrupt signal (IRQ signal) is also used by the main processing device 10 to reset the external non-volatile storage device 100. In other words, if the interrupt signal is directed low but not by the external non-volatile storage device 100, the external non-volatile storage device 100 assumes that the main processing device 10 has activated the signal.In response to activation of the interrupt signal (IRQ signal) by another device, the external non-volatile storage device 100 can be reset.

[0054] The Processing Unit 160 supports some of the safety functions and responds to and processes error conditions in software. The Processing Unit 160 is also used during startup to support the initial configuration of the device and safety operations such as safe startup. The Processing Unit 160 is also used to support the Power Management Unit (PMU) 180 during power state transitions.

[0055] The external non-volatile storage device 100 also includes a special RAM used for secure boot-up. This special RAM can be referred to as a Physically Unclonable Function RAM (PUF-RAM) 167. The purpose of the PUF-RAM 167 is to generate a device-unique key that cannot be easily replicated or extracted. With regard to the present disclosure, it is important to note that the PUF-RAM 167 is present to support the storage of keys necessary to support connection security, specifically the encryption of data exchange to and from the main processing device 10.

[0056] The external non-volatile storage device 100 also includes a serial wire debug block (SWD block) 170 and the associated interfaces required for this function. Serial wire debug blocks are well known and are not described in detail.

[0057] The external non-volatile storage device 100 also includes a power management unit (PMU) 180. The PMU 180 is responsible for switching the supply of voltage to the various blocks within the device on and off. For example, in low-current modes, the PMU 180 can switch off the entire device, with the exception of the PMU 180, the Serdes controller 126, and, if applicable, the RAM 165.

[0058] The external non-volatile storage device 100 further comprises an oscillator 190. The oscillator 190 can be an RC oscillator. The oscillator 190 is used to generate the clock signal used by the processing unit 160 and other functions. As described above, in certain embodiments, the clock signal at the interface 90 is switched off when there is no activity between the two devices. At these times, the external non-volatile storage device 100 can utilize the output of the oscillator 190 so that it can continue to operate. In certain embodiments, the external non-volatile storage device 100 can select either the output from the oscillator or the internal clock generated by the Serdes module 125.

[0059] The external non-volatile storage device 100 can also include a reset generator 195. In certain embodiments, the main processing device 10 can activate the clock signal for a specific duration. When the clock signal is activated for this duration, it indicates that the main processing device 10 wants to reset the external non-volatile storage device 100. Therefore, the reset generator 195 communicates with the clock signal from the interface 90 and activates the reset signal accordingly.

[0060] The present system offers many advantages. First, by separating the non-volatile memory from the processor, each can be manufactured using the technology best suited to that technology. For example, the processing unit and its associated logic can be manufactured using a 22 nm process (or smaller), while the non-volatile memory unit can be manufactured using a larger geometry, such as 40 nm or 90 nm.

[0061] Secondly, the present system incorporates a high-speed interface operating at up to 2.5 GHz. This enables data to be sent very quickly from the non-volatile memory to the main processing unit 10, minimizing latency and maximizing throughput. This speed supports execution in place (XIP), meaning that the contents of the non-volatile memory do not need to be replicated in their entirety in the main processing unit 10. Instead, the cache in the main processing unit 10 is sufficiently large to allow the processing unit 30 to operate at full speed while new data is being retrieved from the external non-volatile memory.

[0062] Furthermore, this interface is designed to utilize CMOS signaling to save quiescent current. Many other components use an LVDS interface, which has a much higher quiescent current. To further reduce the power consumed by the interface, the clock signal used by the interface is divided before being sent to the external non-volatile memory device 100. This reduces the power consumed by the clock output buffer. Thus, for example, data can be sent at 2.5 Gbit / s, but the clock signal sent to the external non-volatile memory device 100 can be 1.25 GHz or less.

[0063] Furthermore, in certain embodiments, the frequency of interface 90 can be controlled in such a way as to minimize interference between this interface and the wireless transceiver. Fig. Figure 5 shows a performance spectrum of the interface for a random bitstream, where the duration of each bit is denoted as T. b The power spectrum for a random data sequence, where the bits transition between +A and -A, is defined as follows: P = A 2 *T b *sinc 2 (f*T b ). By choosing T b such that f*T b If f is an integer and is close to the operating frequency of the wireless network, interference between interface 90 and the wireless channel can be minimized. Specifically, the power spectral density is defined as A 2 *T b * (BW) *sinc 2 (f*T b This can then be expressed as PSD = 2A 2 *Tb* (BW) sin 2 (n*f*T b ) / (n*f*T b ). n / T b (which represents the frequency of the Serdes clock and its harmonic frequency) can be expressed as f RF+ Δ. This can be rewritten as f RF *T b = n-ΔT b Thus, the bandwidth can be calculated close to the frequency of the radio circuit, denoted as f. RF , the power spectral density can be expressed as PSD = 2A 2 *Tb* (BW) sin 2 (π(n-ΔT s )) / (π 2 *f RF 2 *T b 2 ) or PSD = 2A 2 *Tb* (BW)sin 2 (π*ΔT b ) / (π 2 *f RF 2 *T b 2 For small values, sin(x) equals x, so this can be expressed as PSD = 2A 2 *Tb* (BW)*(π*ΔT b ) 2 / (π 2 *f RF 2 *T b 2 ), which can be simplified to PSD = 2A 2 *Tb* (BW) *(Δ) 2 / (f RF 2 ), as in Fig.Figure 5 illustrates this. By keeping Δ small, the power spectral density at the RF frequencies can be minimized. In this disclosure, a small Δ is defined as being within 10% of f. RF lying down. In other words, the frequency of the Serdes clock or its harmonic frequencies can be chosen so that they lie within 10% of the RF frequency at which the main processing unit transmits and receives.

[0064] Furthermore, the present system offers a level of security that cannot be achieved with commercially available SPI flash components. Specifically, the data transmitted via interface 90 includes a CRC and is also encrypted using a cryptographic algorithm such as AES-GCM or another appropriate algorithm. This allows the main processing device 10 not only to detect transmission errors but also to identify injected bits. Additionally, the external non-volatile storage device 100 supports secure booting. The external non-volatile storage device 100 can perform hashing and signature verification on disk and then transmit the result to the main processing device 10 via the secure interface.

[0065] This eliminates the need to send the contents of the non-volatile memory to the main processing unit 10 for hashing and acknowledgment. This, in turn, saves power and reduces the time required to start up the unit.

Claims

[1] External non-volatile storage device comprising: an overwritable non-volatile memory (140); and an interface (90), wherein the interface (90) has: a bidirectional data signal; and a clock input, wherein the clock input has a frequency greater than 1 GHz, uses an asymmetric CMOS signaling and is used to generate a memory Serdes clock (127) which is used to clock outgoing data sent on the bidirectional data signal. [2] External non-volatile storage device according to claim 1, wherein the clock input is multiplied by an integer to generate a storage-Serdes clock (127). [3] External non-volatile storage device according to claim 2, wherein the integer is 2. [4] External non-volatile storage device according to claim 1, wherein the clock input has a frequency of more than 1 GHz. [5] External non-volatile storage device according to claim 4, wherein the data is transmitted at a speed of more than 2 Gbit / s. [6] External non-volatile storage device according to claim 1, wherein the clock input is kept in a disabled state when no data is being sent on the bidirectional data signal. [7] External non-volatile storage device according to claim 1, wherein the data in the rewritable non-volatile memory (140) is not encrypted and which further comprises an encryption / decryption block (151) for encrypting data read from the overwritable non-volatile memory (140) before the data is sent via the interface (90). [8] External non-volatile storage device according to claim 7, wherein a stream cipher is used in the encryption / decryption block (151). [9] External non-volatile storage device according to claim 8, which further comprises a circuit system for appending a cyclic redundancy code (CRC) to the data transmitted via the interface (90). [10] External non-volatile storage device according to claim 7, wherein in the encryption / decryption block (151) data received on the interface (90) are decrypted before the data is written to the overwritable non-volatile memory (140). [11] External non-volatile storage device according to claim 1, wherein an asymmetric CMOS signaling is used for the bidirectional data signal. [12] External non-volatile storage device according to claim 1, wherein the external non-volatile storage device (100) supports safe startup. [13] System, comprising: the external non-volatile storage device (100) according to claim 1; and a main processing device (10), comprising: an interface (90) to the external non-volatile storage device (100) which includes the bidirectional data signal; an outgoing clock signal; and a radio circuit which is distinct from the interface (90) to the external non-volatile storage device (100) and is configured to send and receive packets on an RF frequency, wherein a frequency of the outgoing clock signal is chosen such that the frequency of a harmonic frequency thereof is within 10% of the RF frequency. [14] External non-volatile storage device comprising: a writable non-volatile memory (140) containing unencrypted data; an interface (90), wherein the interface (90) has: a bidirectional data signal; an interrupt signal; and a clock input; and an encryption / decryption block (151) for encrypting data read from the overwritable non-volatile memory (140) before the data is sent via the interface (90). [15] External non-volatile storage device according to claim 14, wherein a stream cipher is used in the encryption / decryption block (151). [16] External non-volatile storage device according to claim 14, which further comprises a circuit system for appending a cyclic redundancy code (CRC) to the data transmitted via the interface (90). [17] External non-volatile storage device according to claim 14, wherein in the encryption / decryption block (151) data received on the interface (90) are decrypted before the data is written to the overwritable non-volatile memory (140). [18] External non-volatile storage device according to claim 14, wherein the interrupt signal is activated when an error is detected in the encryption / decryption block (151). [19] External non-volatile storage device according to claim 14, which further comprises a processing unit (160) wherein the interrupt signal is activated when the processing unit (160) wants to provide information to a device (10) connected to the interface (90). [20] External non-volatile storage device according to claim 14, wherein when the interrupt signal is activated by another device (10), the external non-volatile storage device (100) is reset.

Images