Thin-layer transistor substrate and display device containing therein

Abstract

Thin-film transistor substrate comprising the following: a substrate (100); an active layer (130) on the substrate (100); a gate electrode (150) on the active layer (130); a source electrode (171) connected to a first side of the active layer (130); and a drain electrode (172) connected to a second side of the active layer (130), wherein the gate electrode (150) comprises a body part (151) and at least one first projection (152a) on a first side of the body part (151), wherein the at least one first projection (152a) overlaps the active layer (130) in a top view, the active layer (130) comprises: a channel section (131); a source region (132a) on a first side of the channel part (131), wherein the source region (132a) is conductive and is connected to the source electrode (171); and a drain area (132b) on a second side of the channel part (131), wherein the drain area (132b) is conductive and is connected to the drain electrode (172), where at least one first projection (152a) overlaps the source area (132a), wherein the channel part (131) has several first concave parts (131a) and the source region (132a) has several first convex parts (133a) in a region corresponding to the several first concave parts (131a).

Description

BACKGROUND Technical area

[0001] The disclosure relates to a thin-film transistor substrate and a display device containing it. Discussion of the state of the art

[0002] Because a thin-film transistor can be fabricated on a glass or plastic substrate, it is frequently used as a switching device or as a driver for a display device, such as a liquid crystal display or an organic light-emitting display. Various types of thin-film transistors, such as display area thin-film transistors for individual pixels emitting light, logic GIP thin-film transistors for controlling display area thin-film transistors, and buffer GIP thin-film transistors for controlling the entire power supply, can be used in display panels to drive an organic light-emitting device.

[0003] WO 2017 / 164904 A1 describes an N-type MOSFET transistor. The transistor includes a polysilicon tab that extends from the gate polysilicon structure into the source region and leads to a P+ region, the body contact region, created in the source region. Since the polysilicon tab is a structure adjacent to the gate polysilicon structure, a corresponding body tab is created beneath the polysilicon tab, which is of the same type (doping) as the P-body region beneath the gate polysilicon structure. This body tab connects the P-body region beneath the gate polysilicon structure to the body contact region formed within the source region.

[0004] US 2003 / 0222308 A1 describes a silicon-on-insulator (SOI) semiconductor device comprising a source, drain, and gate formed on a substrate. At least one p+ body contact region is located adjacent to the source and away from a channel of the SOI semiconductor device. At least one poly branch may be connected to the gate such that the poly branch passes through the p+ body contact region. The p+ body contact region and the source may be bonded together on the surface of a silicon film using a silicide, thereby forming the SOI semiconductor device.

[0005] US 2011 / 0057918 A1 concerns a display device.

[0006] IPRI AC et al., “The application of silicon-on-insulator (SOI) technology for the fabrication of fully scanned active matrix flat panel displays”, Proceedings, IEEE International SOI Conference, October 3-6, 1994, Nantucket, MA, USA, pp. 97-98, ISBN 0-7803-2406-4, mentions that SOI technology is used for the fabrication of both liquid crystal displays (LCDs) and electroluminescent displays (EL).

[0007] To implement a high-mobility device in a top-gate thin-film transistor, a conductivity enablement process (also known as a conductor formation process) of an oxide semiconductor layer can be performed using a gate electrode as a mask. However, during the conductivity enablement process in the oxide semiconductor layer, the channel area can become smaller than the specified area due to excessive penetration of the conductive region, thus reducing the channel length and shifting the threshold voltage Vth in the negative (-) direction. In particular, if the width of the oxide semiconductor layer is large, the degree of penetration of the conductive region increases, and therefore the channel length can be further reduced.

[0008] If the threshold voltage Vth is shifted in a negative (-) direction, a leakage current can be generated in the original circuit. As a result, a board containing a thin-film transistor may be driven incorrectly due to this leakage current, and the board may experience increased power consumption. SUMMARY

[0009] Accordingly, embodiments of the present disclosure relate to a thin-film transistor substrate and a display device containing it, which essentially avoid one or more of the problems due to limitations and disadvantages of the prior art.

[0010] One aspect of the present disclosure is to provide a thin-film transistor substrate and a display device containing it, which can suppress a negative shift of the threshold voltage Vth by preventing the channel length from decreasing when an oxide semiconductor layer is made conductive.

[0011] One or more of these problems are solved by the features of the independent claims. Further features and aspects are set out in the following description and are partly evident from the description or can be learned by implementing the inventive concepts provided here. Further features and aspects of the inventive concepts can be realized and achieved through the structure to which specific reference is made in the written description or which can be derived from it, and the claims thereto, as well as the accompanying drawings.

[0012] According to one aspect, a thin-film transistor substrate comprises a substrate; an active layer on the substrate; a gate electrode on the active layer; a source electrode connected to a first side of the active layer; and a drain electrode connected to a second side of the active layer, wherein the gate electrode comprises a body part and at least one first projection on a first side of the body part, the at least one first projection overlapping the active layer in a top view.

[0013] The active layer comprises: a channel portion; a source region on a first side of the channel portion, wherein the source region is conductive and connected to the source electrode; and a drain region on a second side of the channel portion, wherein the drain region is conductive and connected to the drain electrode. The at least one first projection overlaps the source region. The channel portion has several first concave portions. The source region has several first convex portions in a region corresponding to the several first concave portions.

[0014] The multiple first convex parts may not overlap the at least one first projection. The multiple first convex parts may have a rounded shape. The at least one first projection may comprise multiple first projections. Each of the multiple first projections may have the same shape. The at least one first projection may comprise multiple first projections. A gap between adjacent first projections may be 0.5 µm or more and 50 µm or less.

[0015] The length of the at least one first projection in a first direction can be 0.5 µm or more and 5 µm or less. The length of the at least one first projection in a second direction can be 0.5 µm or more and 20 µm or less. The first direction can be a direction in which the source electrode and the drain electrode face each other. The second direction can be perpendicular to the first direction. The at least one first projection may not overlap the source electrode and the drain electrode. The gate electrode may further include at least one second projection on a second side of the body part. The at least one second projection may overlap the active layer. The at least one first projection and the at least one second projection may be arranged symmetrically with respect to the body part.

[0016] The active layer can comprise: a channel portion; a source region on a first side of the channel portion, wherein the source region is conductive and connected to the source electrode; and a drain region on a second side of the channel portion, wherein the drain region is conductive and connected to the drain electrode. The at least one first projection can overlap the source region. The at least one second projection can overlap the drain region.

[0017] The channel portion can comprise multiple first concave portions and multiple second concave portions. The source region can comprise multiple first convex portions in a region corresponding to the multiple first concave portions. The drain region can comprise multiple second convex portions in a region corresponding to the multiple second concave portions. The multiple first convex portions and the multiple second convex portions can be arranged symmetrically with respect to the channel portion. The at least one first projection can overlap an edge in a longitudinal direction of the active layer. The longitudinal direction can be a direction between the source region and the drain region. The active layer can have at least one active hole. The at least one active hole may not overlap the at least one first projection. A portion of the at least one active hole can overlap the body portion.A remaining portion of the at least one active hole may not overlap the body part.

[0018] The thin-film transistor substrate can further comprise a gate insulating layer between the gate electrode and the active layer. The gate insulating layer can be located within the at least one active hole. The thin-film transistor substrate can further comprise an intermediate insulating layer between the source electrode and the active layer. The intermediate insulating layer can be located within the at least one active hole.

[0019] According to one aspect, an indicator device comprises: a thin-film transistor substrate comprising: a substrate; an active layer on the substrate; a gate electrode on the active layer; a source electrode on a first side of the active layer; and a drain electrode on a second side of the active layer, wherein the gate electrode comprises a body part and at least one first projection on a first side of the body part, the at least one first projection overlapping the active layer; and a gate driver and a data driver connected to the thin-film transistor substrate to supply gate signals and data signals, respectively, to the thin-film transistor substrate.

[0020] In another aspect, a display device comprises a thin-film transistor substrate, which includes: a substrate, an active layer on the substrate, a gate electrode on the active layer, a source electrode on a first side of the active layer, and a drain electrode on a second side of the active layer, wherein the gate electrode comprises a body part and at least one first projection on a first side of the body part, the at least one first projection overlapping the active layer; and a gate driver and a data driver connected to the thin-film transistor substrate to supply gate signals and data signals, respectively, to the thin-film transistor substrate.

[0021] It is understood that both the above general description and the following detailed description are exemplary and explanatory and are intended to further explain the claimed inventive concepts. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are included for a better understanding of the disclosure and form part of this application, illustrate embodiments of the disclosure and, together with the description, serve to explain various principles; they show: Fig. 1A and Fig. 1B Top views of a thin-film transistor substrate according to an embodiment of the present disclosure. Fig. 2 a cross-sectional view of a thin-film transistor substrate according to an embodiment of the present disclosure, which shows a cross-sectional view along line II' of Fig. 1B is. Fig. 3 a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure. Fig. 4 a Vgs-Ids diagram showing how Vth changes compared to a conventional thin-film transistor when a thin-film transistor is used according to an embodiment of the present disclosure. Fig. 5A a top view of a thin-film transistor substrate according to a further embodiment of the present disclosure. Fig. 5B a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure and Fig. 5B a cross-sectional view along line II-II' of Fig. 5A. Fig. 6 a top view of a thin-film transistor substrate according to a further embodiment of the present disclosure. Fig. 7 a top view of a thin-film transistor substrate according to a further embodiment of the present disclosure. Fig. 8 a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure, which shows a cross-sectional view along line III-III' of Fig. 7 is. Fig. 9 a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure, which shows a cross-sectional view along line III-III' of Fig. 7 is. Fig. 10 a cross-sectional view of a display device with a thin-film transistor substrate according to an embodiment of the present disclosure. Fig. 11 a schematic representation of a display device according to an embodiment of the present disclosure. Fig. 12 a circuit diagram of a shift register according to an embodiment of the present disclosure. Fig. 13 a circuit diagram of a pixel provided in a display device according to an embodiment of the present disclosure. Fig. 14 a circuit diagram of a pixel provided in a display device according to a further embodiment of the present disclosure. Fig. 15 a circuit diagram of a pixel provided in a display device according to a further embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] The advantages and features of the present disclosure and the implementation methods therefor are illustrated by the following embodiments, which are described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments set forth herein. Rather, these embodiments are provided to ensure that this disclosure is thorough and complete and to fully convey the scope of the present disclosure to those skilled in the art. Furthermore, the present disclosure is defined only by the scope of the claims.

[0024] The shapes, sizes, ratios, angles, and numbers disclosed in the drawings illustrating embodiments of the present disclosure are merely examples, and therefore the present disclosure is not limited to the details shown. The same reference numerals refer to the same elements throughout. If, in the following description, it is determined that a detailed description of a relevant known function or configuration would unnecessarily obscure the essential point of the present disclosure, the detailed description will be omitted.

[0025] In cases where the terms "comprise," "have," and "exhibit" are used in the present description, another part may also be present, unless "only" is used. Singular terms may include plural forms unless otherwise stated.

[0026] When constructing an element, it is assumed that the element contains an error area, even if there is no explicit description of it.

[0027] When describing a positional relationship, if the order of positions is described as, for example, "on", "above", "below", "below" and "next to", the case without contact in between may be included unless "immediately" or "directly" is used.

[0028] When it is mentioned that a first element is positioned "on" a second element, this does not mean that the first element is essentially positioned above the second element in the figure. Depending on the object's orientation, the top and bottom parts of an object can change. Consequently, the case in which a first element is positioned "on" a second element, in the figure or in an actual configuration, includes both the case in which the first element is positioned "below" the second element and the case in which the first element is positioned "above" the second element.

[0029] When describing a temporal relationship, if the temporal sequence is described as, for example, "after", "subsequently", "next", and "before", it may include a case that is not consecutive unless "immediately" or "directly" is used.

[0030] It is understood that the terms "first," "second," etc., can be used here to describe different elements, but these elements should not be restricted by these terms. These terms are only used to distinguish one element from another. For example, a first element could be called a second element, and likewise, a second element could be called a first element.

[0031] It is understood that the term "at least one" includes all combinations relating to any element. For example, "at least one of a first element, a second element, and a third element" can include all combinations of two or more elements selected from the first, second, and third elements, as well as each element of the first, second, and third elements.

[0032] Features of different embodiments of the present disclosure can be partially or completely coupled or combined and can interact and be controlled in various ways. The embodiments of the present disclosure can be implemented independently of one another or together in a dependent relationship.

[0033] In the drawings, identical or similar elements are designated with the same reference symbols, even if they are shown in different drawings.

[0034] In the embodiments of the present disclosure, a source electrode and a drain electrode are distinguished from one another for the sake of simplicity. However, the source electrode and drain electrode are used interchangeably. Thus, the source electrode can be the drain electrode and the drain electrode can be the source electrode. Furthermore, the source electrode in one embodiment of the present disclosure can be the drain electrode in another embodiment of the present disclosure, and the drain electrode in any embodiment of the present disclosure can be the source electrode in another embodiment of the present disclosure.

[0035] In one or more embodiments of the present disclosure, for the sake of simplicity, a source region is distinguished from a source electrode and a drain region from a drain electrode. However, embodiments of the present disclosure are not limited to this structure. For example, a source region can be a source electrode and a drain region can be a drain electrode. Furthermore, a source region can be a drain electrode and a drain region can be a source electrode.

[0036] Fig. 1A and Fig. Figure 1B shows top views of a thin-film transistor substrate according to an embodiment of the present disclosure. In this case, it shows Fig. 1A a state prior to performing a conduction capability process on the active layer 130 and Fig. Figure 1B shows a state in which the active layer 130 comprises a channel part 131, a first connection part 132a (or source area) and a second connection part 132b (or drain area) by performing a conductivity enablement process on the active layer 130.

[0037] As it is in Fig. 1A and Fig. As shown in Figure 1B, the thin-film transistor substrate according to one embodiment of the present disclosure comprises an active layer 130, a gate electrode 150 overlapping the active layer 130, a source electrode 171 provided on one side of the active layer 130, and a drain electrode 172 provided on the other side of the active layer 130. The active layer 130 may extend in a first direction, for example a horizontal direction, and the gate electrode 150 may extend in a second direction, for example a vertical direction, without being limited thereto.

[0038] The thin-film transistor according to the present disclosure can have a top-gate structure in which the gate electrode 150 is provided on the active layer 130, and in the top-gate structure a conductivity enablement process can be carried out on a sub-area of ​​the active layer 130 that is not covered by the gate electrode 150, the gate electrode 150 serving as a mask. Through the conductivity enablement process, the active layer 130 can comprise a channel part 131, a first interconnect part 132a, and a second interconnect part 132b.

[0039] The conductivity enhancement process (alternatively referred to as the conductor formation process) is a process for increasing the electron concentration in a sub-region of the active layer 130, which consists of an oxide semiconductor. Examples include plasma treatment or doping with dopant ions during the etching of a gate insulating layer. When the conductivity enhancement process is performed, the electron concentration of a section of the active layer 130 increases, thereby improving its conductivity properties and achieving conductor-like characteristics. If the conductivity enhancement process involves doping with dopant ions, the dopant ions can be boron (B), phosphorus (P), fluorine (F), and hydrogen (H).

[0040] According to one embodiment of the present disclosure, a conductivity enhancement process can be carried out using the gate electrode 150 as a mask, for example, a dopantion doping process. In this case, the active layer 130 can comprise a region that overlaps the gate electrode 150 and is not doped with a dopant, for example, a channel portion 131, and a region that does not overlap the gate electrode 150 and is doped with a dopant, for example, a first connecting portion 132a and a second connecting portion 132b. However, the conductivity enhancement process is not limited to a dopantion doping process and can include a conductivity enhancement process by plasma treatment.

[0041] When the conductivity enhancement process is performed, dopants can diffuse into the active layer 130 that overlaps the gate electrode 150. Therefore, a portion of the active layer 130 that does not overlap the gate electrode 150 is doped with dopants to form parts of the first interconnect 132a and the second interconnect 132b. Furthermore, dopants can be deposited onto a portion of the active layer 130 that overlaps the gate electrode 150 to form the remaining parts of the first interconnect 132a and the second interconnect 132b, for example, a first convex part 133a and a second convex part 133b.

[0042] If the thin-film transistor substrate only includes the body part 151 of the gate electrode 150 and not the first protrusion 152a, the size of the first convex part 133a can increase during the conductivity process due to the diffusion rate of dopants into the active layer 130 that overlaps the gate electrode 150. This can result in the channel part 131 becoming too short.

[0043] If the length of channel section 131 is too short, the threshold voltage Vth can be shifted in a negative (-) direction, and thus a leakage current can flow through the thin-film transistor substrate, including the active layer 130. If this leakage current flows, the switching function of the thin-film transistor may malfunction, and the quality of the original image may be impaired. Therefore, to prevent the threshold voltage Vth from being shifted in the negative (-) direction, the length of channel section 131 can be controlled to ensure it is not too short.

[0044] According to one embodiment of the present disclosure, the amount of dopant diffusing into the active layer 130 overlapping the gate electrode 150 can be reduced because the gate electrode 150 has the first projection 152a on one side of the body part 151. This prevents the first convex part 133a from becoming large by preventing the dopant from diffusing into the active layer 130 overlapping the gate electrode 150. Thus, according to one embodiment of the present disclosure, the size of the first convex part 133a can be reduced, thereby preventing the length of the channel part 131 from becoming excessively short.

[0045] In the following, configurations of the gate electrode 150 and the active layer 130 according to an embodiment of the present disclosure are described in more detail.

[0046] The body part 151 of the gate electrode 150 can overlap the active layer 130, in particular the channel part 131, and can extend in the second direction.

[0047] As an example of one side of body part 151, at least one first projection 152a is provided on one side of body part 151, for example on the left side facing a source electrode 171. The at least one first projection 152a extends from body part 151 in the first direction, in particular towards the source electrode 171. On the other side of body part 151, for example the right side facing a drain electrode 172, a separate projection may not be provided.

[0048] Accordingly, one side and the other side of the gate electrode 150 can be asymmetrically designed with respect to the body part 151. However, the structure of the gate electrode 150 is not limited to this and can be further specified in the embodiment shown. Fig. As shown in Figure 5A, a protrusion may be formed on the other side of body part 151.

[0049] The body part 151 and the at least one first projection 152a can be used as a mask in the process of enabling a sub-area of ​​the active layer 130. Since at least one first projection 152a is provided on one side of the body part 151 at this time, and the other side of the body part 151 is not provided with a separate projection, the conductive area of ​​the active layer 130 can be asymmetrically formed with respect to the channel part 131.

[0050] An area of ​​the active layer 130, not covered by the body part 151 and the first projection 152a, is conductive to form a first connecting part 132a and a second connecting part 132b. The first connecting part 132a is provided on the left side of the non-conductive channel part 131, and the second connecting part 132b is provided on the right side of the non-conductive channel part 131.

[0051] However, the active layer 130, which is covered by body part 151 and the first projection 152a, is not supposed to be conductive, but, for example, doped dopants diffuse into a part of the active layer 130 covered by body part 151 and the first projection 152a when the process is actually carried out. For example, the area of ​​the active layer 130 that overlaps the first projection 152a is conductive to form the first connecting part 132a.

[0052] Furthermore, a sub-area of ​​the active layer 130, which overlaps the body part 151, is conductive to form the first convex part 133a and the second convex part 133b of the active layer 130.

[0053] The first convex part 133a overlaps the left end of body part 151, and the second convex part 133b overlaps the right end of body part 151. Since several first projections 152a are provided on the left side at this time, several first convex parts 133a are formed on the side of body part 151 in an area that overlaps the left end of body part 151. Conversely, since the first projection 152a is not provided on the right side of body part 151, a second convex part 133b is formed in an area that overlaps the right end of body part 151.

[0054] The channel portion 131 of the active layer 130, with the exception of the first connecting portion 132a, the second connecting portion 132b, the first convex portion 133a, and the second convex portion 133b, corresponds to a non-conductive region. In this case, the horizontal length of the channel portion 131 is reduced by the first convex portion 133a and the second convex portion 133b. However, since, according to one embodiment of the present disclosure, the gate electrode 150 includes the first projection 152a, the horizontal length of the channel portion 131, which extends in the left-right direction in the region overlapping the first projection 152a, is relatively increased.

[0055] Since, for example, several first projections 152a are provided, the area to be made conductive, for example, an area in which dopants diffuse, is reduced in size, and thus the size of the first convex part 133a is relatively reduced. Accordingly, the size of the first convex part 133a is smaller than the size of the second convex part 133b. Consequently, the length of the channel part 131 is relatively increased in an area where the first convex part 133a is formed.

[0056] Furthermore, since the first projection 152a is provided, the active layer 130 may be non-conductive in the region between the several first convex parts 133a. Accordingly, the length of the channel part 131 is relatively increased in a region between the several first convex parts 133a.

[0057] Due to the multiple first projections 152a provided on one side, for example the left side of the body part 151, the multiple first convex parts 133a can as a result be spaced apart from each other by a predetermined gap and can be formed in the first connecting part 132a, and the horizontal length of the channel part 131 can be relatively increased.

[0058] If the length of channel part 131 is increased relatively, it prevents the length of channel part 131 from becoming too short, and thus it is possible to reduce the problem of the threshold voltage Vth of the thin-film transistor being shifted in the negative (-) direction.

[0059] The following sections refer to the enlarged drawing, which is indicated by an arrow in Fig. 1A describes conditions for generating an optimal effect of the thin-film transistor substrate according to an embodiment of the present invention with respect to the gap between the at least one first projection 152a and the lengths in the first and second directions of the at least one first projection 152a.

[0060] As shown in the enlarged drawing, indicated by arrows in Fig. As indicated in 1A, the at least one first projection 152a can be provided as several first projections 152a. Accordingly, the several first projections 152a can protrude from one side of the body part 151 in the first direction.

[0061] The multiple first projections 152a can have the same shape. However, the multiple first projections 152a can, for example, be provided as three first projections 152a. The number of multiple first projections 152a is not limited to this.

[0062] According to one embodiment of the present disclosure, the distance d between the multiple first projections 152a can be constant. The conductivity of the active layer 130 can be controlled by adjusting the distance d between the multiple first projections 152a. For example, if the distance d between the multiple first projections 152a is constant, the conductive active layer 130 can have uniform properties. However, the distance d between the multiple first projections 152a is not limited to this and can be configured differently.

[0063] The distance d between the multiple first projections 152a can be 0.5 µm or more to 50 µm or less, and the distance d between the multiple first projections 152a is preferably 2 µm or more and 20 µm or less.

[0064] If the distance d between the several first projections 152a is 50 µm or more, the size of the first convex part 133a increases and thus it is difficult to ensure the threshold voltage Vth in a positive (+) direction, and if the distance d between the several first projections 152a is 2 µm or less, the length of the channel part 131 can be excessively enlarged and the resistance can increase, thereby reducing the current flowing through the entire device.

[0065] Each of the several first projections 152a extends in the first direction by a predetermined length l. As shown in Fig. As shown in Figure 1A, the first projection 152a extends by a predetermined length l in one direction from one end, for example a left end, of the body part 151 towards the source electrode 171.

[0066] According to one embodiment of the present disclosure, several first convex parts 133a provided in the first connecting part 132a can be of the same size, since each of the several first projections 152a can protrude by the same length l. However, the length l of each of the several first projections 152a is not limited to the same length, and the length l of each of the several first projections 152a can be configured to have different lengths.

[0067] The lengths l of the multiple first projections 152a can be 0.5 µm or more and 5 µm or less. If the length l of the multiple first projections 152a is less than 0.5 µm, no multiple first convex parts 133a may be obtained, and if the length l of the multiple first projections 152a is more than 5 µm, the length of the channel part 131 may increase excessively. However, the first projection 152a does not overlap the source electrode 171, as it does not extend to a region where the source electrode 171 is located.

[0068] Each of the multiple first projections 152a is configured to have a predetermined width w in the second direction. According to one embodiment of the present disclosure, each of the multiple first projections 152a is configured to have the same width w. However, the present disclosure is not limited to this, and the width w of each of the multiple first projections 152a can be configured to have different widths.

[0069] The width w of the multiple first projections 152a is preferably 0.5 µm or more and 20 µm or less. If the width w of the multiple first projections 152a is less than 0.5 µm, the multiple first convex parts 133a may not be obtained, and if the width w of the multiple first projections 152a exceeds 20 µm, a parasitic capacitance generated by the gate electrode 150 may increase.

[0070] However, the distance d, the length l in the first direction and the width w in the second direction among the several first projections 152a are not limited to those described above, but can be optimized differently depending on expertise in order to adapt them according to the properties of the facility.

[0071] As it is in Fig. As shown in Figure 1B, a portion of the active layer 130, which overlaps the body part 151, is conductive to form the first convex part 133a. In this case, the first concave part 131a is formed in the channel part 131 corresponding to the first convex part 133a. Furthermore, the second convex part 133b is formed in another part of the active layer 130, which faces the first convex part 133a, and the second concave part 131b is formed in the channel part 131 corresponding to the second convex part 133b.

[0072] The first concave part 131a overlaps the left end of body part 151, and the second concave part 131b overlaps the right end of body part 151. Since, in this case, the multiple first projections 152a are provided on the left side, several first concave parts 131a are formed on the side of body part 151 in an area that overlaps the left end of body part 151. Conversely, since the first projection 152a is not provided on the right side of body part 151, a second concave part 131b is formed in an area that overlaps the right end of body part 151.

[0073] For example, if three first projections 152a are provided on one side of the body part 151, four first concave parts 131a can be provided on the left side of the channel part 131. However, the number of first projections 152a and first concave parts 131a is not limited to this.

[0074] The first concave part 131a and the second concave part 131b may be provided in a rounded shape and correspond to the first convex part 133a and the second convex part 133b, respectively.

[0075] The first connecting part 132a can be formed on one side of the channel part 131 and can be electrically connected to the source electrode 171. Furthermore, the second connecting part 132b can be formed on the other side of the channel part 131 and be electrically connected to the drain electrode 172. However, the method for connecting the first connecting part 132a and the second connecting part 132b to the source electrode 171 and the drain electrode 172, respectively, is not limited to these possibilities, and in some cases the first connecting part 132a can be electrically connected to the drain electrode 172, and in this case the second connecting part 132b can be electrically connected to the source electrode 171.

[0076] Since the thin-film transistor according to Fig. 1B where the first projection 152a has only on the left side of the body part 151 and does not have a separate projection on the right side of the body part 151, the first connecting part 132a and the second connecting part 132b are provided asymmetrically with respect to the channel part 131.

[0077] Since, according to one embodiment of the present disclosure, the first projection 152a is provided on one side of the body part 151, the first convex part 133a can, however, be formed from several first convex parts 133a. For example, if, as in Fig. As shown in Figure 1B, where three first projections 152a are provided on one side of the body part 151, four first convex parts 133a can be provided on the left side of the channel part 131, overlapping the body part 151. However, the number of first projections 152a and first convex parts 133a is not limited to this.

[0078] The multiple first convex parts 133a, which are formed as part of the active layer 130 where the multiple first projections 152a are not formed, become a conductor. Accordingly, the multiple first convex parts 133a do not overlap the multiple first projections 152a in the horizontal direction.

[0079] Furthermore, since the gap between the several first projections 152a is identical, the gap between the several first convex parts 133a can also be identical. For example, a gap between the several first convex parts 133a can be equal to the width w of the first projection 152a in the second direction.

[0080] The first convex part 133a and the second convex part 133b can be provided in a rounded shape and correspond to the first concave part 131a and the second concave part 131b, respectively.

[0081] Since in this case at least one first projection 152a is provided on one side of the body part 151 and no separate projection is provided on the other side of the body part 151, the first convex part 133a and the second convex part 133b can be asymmetrical with respect to the channel part 131. The second connecting part 132b can include a second convex part 133b, and the second convex part 133b can be relatively larger than the first convex part 133a.

[0082] Fig. Figure 2 is a cross-sectional view of a thin-film transistor substrate according to an embodiment of the present disclosure and Fig. 2 is a cross-sectional view along line II' of Fig. 1B. This corresponds to Fig. 2 a cross-section of an area in which the projection 152a of the gate electrode 150 is formed.

[0083] As it is in Fig. As shown in Figure 2, the thin-film transistor substrate according to an embodiment of the present disclosure can comprise a substrate 100, a light-blocking layer 110, a buffer layer 120, an active layer 130, a gate insulating layer 140, a gate electrode 150, an intermediate insulating layer 160, a source electrode 171, a drain electrode 172 and a planarization layer 180.

[0084] Substrate 100 can be made of glass or plastic. Specifically, substrate 100 can be made of a transparent, flexible plastic, such as polyimide. If polyimide is used as substrate 100, given that a high-temperature deposition process will be performed on it, a heat-resistant polyimide capable of withstanding high temperatures should be used.

[0085] The light-blocking layer 110 is formed on the substrate 100. In some cases, however, the light-blocking layer 110 can be omitted. Since the light-blocking layer 110 overlaps the channel portion 131 of the active layer 130, it can protect the channel portion 131 of the active layer 130 by blocking light penetrating from the lower part of the substrate 100.

[0086] The light-blocking layer 110 may contain an aluminum-based metal, such as aluminum Al or an aluminum alloy (Al alloy), a silver-based metal, such as silver Ag or a silver alloy (Ag alloy), a copper-based metal, such as copper Cu or a copper alloy (Cu alloy), a molybdenum-based metal, such as molybdenum Mo or a molybdenum alloy (Mo alloy), chromium Cr, tantalum Ta, neodymium Nd and / or titanium Ti.

[0087] The buffer layer 120 is formed on the light-blocking layer 110. Since the buffer layer 120 is formed on a portion of the substrate 100 and the light-blocking layer 110, the substrate 100 and the buffer layer 120 can be configured to surround the light-blocking layer 110. The buffer layer 120 can be formed from an inorganic insulating material such as silicon dioxide, silicon nitride, or metal oxide, but is not limited to this and can also be formed from an organic insulating material. The buffer layer 120 can consist of a single layer or multiple layers.

[0088] The active layer 130 is formed on the buffer layer 120. The active layer 130 comprises the channel part 131, the first connection part 132a, which is provided on one side of the channel part 131, and the second connection part 132b, which is provided on the other side of the channel part 131. The channel part 131 overlaps the gate electrode 150, in particular the body part 151.

[0089] The first connecting part 132a is connected to one side of the channel part 131. Part of the first connecting part 132a does not overlap the gate electrode 150, and the other part of the first connecting part 132a does overlap the gate electrode 150, for example, the first projection 152a. The first connecting part 132a does not extend to a lower section of the body part 151 of the gate electrode 150. Accordingly, in the area where the projection 152a of the gate electrode 150 is formed, the first convex part 133a is formed according to Fig. 1B not formed in the first connecting part 132a.

[0090] Since, as described above, the first convex part 133a is not formed in the first connecting part 132a, which overlaps the first projection 152a, the length of the channel part 131 can be relatively increased. Accordingly, it is possible to control the threshold voltage Vth of the thin-film transistor of the present disclosure by shifting it in a negative (-) direction.

[0091] The second connecting part 132b is connected to the other side of the channel part 131. Part of the second connecting part 132b does not overlap the gate electrode 150, and the other part of the second connecting part 132b does overlap the gate electrode 150, specifically the body part 151. The second connecting part 132a can extend into a lower part of the body part 151 and thus encompass the second convex part 133b. Furthermore, the second concave part 131b can be formed on the other side of the channel part 131 in response to the second convex part 133b, for example, at a point adjacent to the second connecting part 132b.

[0092] The active layer 130 forms a channel by applying a constant voltage to the gate electrode 150 and provides a space in which the charge carrier moves through the channel. When the charge carrier moves through the channel formed in the active layer 130, a current flows through the thin-film transistor according to one embodiment of the present disclosure. The active layer 130 overlaps the gate electrode 150 and applies a voltage higher than the threshold voltage Vth to the gate electrode 150, allowing the charge carrier to move through the active layer 130.

[0093] The active layer 130 can contain a semiconductor material, for example, an oxide semiconductor material. Examples of oxide semiconductor materials include an IZO-based (InZnO-based) oxide semiconductor material, an IGO-based (InGaO-based) oxide semiconductor material, an ITO-based (InSnO-based) oxide semiconductor material, an IGZO-based (InGaZnO-based) oxide semiconductor material, an IGZTO-based (InGaZnSnO-based) oxide semiconductor material, a GZTO-based (GaZnSnO-based) oxide semiconductor material, a GZO-based (GaZnO-based) semiconductor material, an IZTO-based (InZnSnO-based) oxide semiconductor material, and a FIZO-based (FeInZnO-based) oxide semiconductor material.

[0094] The gate insulating layer 140 can be formed on the active layer 130. As shown in Fig. As shown in Figure 2, the thin-film transistor substrate according to an embodiment of the present disclosure can be provided in a structure in which the gate insulating layer 140 is etched. An etched structure is understood to be a structure formed by structuring a portion of the gate insulating layer 140 provided on the substrate 100 using the gate electrode 150 as a mask, leaving only the remaining portion of the gate insulating layer 140, corresponding to the gate electrode 150.

[0095] The gate insulating layer 140 can comprise, but is not limited to, a silicon nitride layer (SiNx) or a silicon oxide layer (SiOx). The gate insulating layer 140 can have a single-layer or a multi-layer structure.

[0096] Plasma can be used to structure the gate insulating layer 140, and the first compound part 132a and the second compound part 132b can be formed by irradiating the exposed area of ​​the active layer 130. However, the present disclosure is not limited to this, and the first compound part 132a and the second compound part 132b can also be formed by performing a separate ion doping process after the structuring process of the gate insulating layer 140.

[0097] The gate electrode 150 can be formed on the gate insulating layer 140. The gate electrode 150 can contain an aluminum-based metal, such as aluminum (Al) or an aluminum alloy (Al alloy), a silver-based metal, such as silver (Ag) or a silver alloy (Ag alloy), a copper-based metal, such as copper (Cu) or a copper alloy (Cu alloy), a molybdenum-based metal, such as molybdenum (Mo) or a molybdenum alloy (Mo alloy), chromium (Cr), tantalum (Ta), neodymium (Nd), and / or titanium (Ti). The gate electrode 150 can have a multilayer structure comprising at least two conductor layers with different physical properties.

[0098] The gate electrode 150 is formed on and overlaps the active layer 130. The gate electrode 150 comprises the body part 151 and the first projection 152a. The first projection 152a is provided on one side, for example, on the left side of the body part 151. Since, however, there is no separate projection on the other side of the body part 151, for example, on the right side, the gate electrode 150 is asymmetrically formed with respect to the body part 151.

[0099] Since the first projection 152a may only be provided on one side of the body part 151, the first connecting part 132a and the second connecting part 132b of the active layer 130 may be asymmetrically formed with respect to the channel part 131.

[0100] The gate electrode 150 protects the channel part 131 in a process for enabling the conductivity of the active layer 130. For example, the body part 151 can protect the channel part 131.

[0101] The first projection 152a also protects part of the active layer 130. Meanwhile, the first projection 152a overlaps the first connecting part 132a, which is provided in the active layer 130.

[0102] The interlayer insulating layer 160 is provided on the gate electrode 150. For example, the interlayer insulating layer 160 can be provided on a section of the buffer layer 120, a section of the active layer 130, a section of the gate insulating layer 140, and the gate electrode 150.

[0103] The interlayer insulating layer 160 insulates the gate electrode 150 from the source electrode 171 and further insulates the gate electrode 150 from the drain electrode 172. The interlayer insulating layer 160 can comprise a single layer or multiple layers containing an inorganic insulating material and / or an organic insulating material.

[0104] The intermediate insulating layer 160 is provided with a first contact hole CH1 and a second contact hole CH2. Accordingly, the first connecting part 132a of the active layer 130 can be exposed through the first contact hole CH1 and the second connecting part 132b of the active layer 130 can be exposed through the second contact hole CH2.

[0105] The source electrode 171 and the drain electrode 172 can be formed on the intermediate insulating layer 160. The source electrode 171 is electrically connected to one side of the active layer 130, for example, the first connecting part 132a, and the drain electrode 172 is electrically connected to the other side of the active layer 130, for example, the second connecting part 132b.

[0106] For example, the source electrode 171 can be connected to the first connection part 132a via a first contact hole CHI provided in the interlayer insulating layer 160, and the drain electrode 172 can be connected to the second connection part 132b via a second contact hole CH2 provided in the interlayer insulating layer 160.

[0107] The planarization layer 180 is provided on the intermediate insulating layer 160, the source electrode 171, and the drain electrode 172. However, although not shown in the planarization layer 180, a third contact hole CH3 may be provided. This is explained with reference to Fig. 12 described.

[0108] Fig. Figure 3 is a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure. The description of Fig. The substrate shown in Figure 3 resembles the thin-film transistor substrate according to Figure 3. Fig. 2, with the exception that the gate insulating layer 140 is formed in an etch-free structure, and therefore mainly differing configurations are described below.

[0109] The gate insulating layer 140 is formed on the active layer 130. Since the gate insulating layer 140 can, for example, be formed on a section of the buffer layer 120 and the active layer 130, the active layer can be configured such that it is surrounded by the buffer layer 120 and the gate insulating layer 140.

[0110] However, as can be seen in Fig. Figure 3 shows that the gate insulating layer 140 has an etch-free structure. The etch-free structure refers to a structure in which the gate insulating layer 140 formed on the substrate 100 is provided throughout the entire substrate 100 using the gate insulating layer 140 without any special structuring.

[0111] Since the gate insulating layer 140 is formed in an etch-free structure, the first contact hole CH1 and the second contact hole CH2 are provided in the gate insulating layer 140; furthermore, the source electrode 171 is connected via the gate insulating layer 140 and the interlayer insulating layer 160 to one side of the active layer 130, for example, the first connection part 132a, and the interlayer insulating layer 160 and the drain electrode 172 are connected via the gate insulating layer 140 and the interlayer insulating layer 160 to the other side of the active layer 130, for example, the second connection part 132b. In the etch-free structure, a first connection part 132a and a second connection part 132b of the active layer 130 can be formed by performing a separate ion doping process.

[0112] Fig. Figure 4 is a Vgs-Ids diagram of a thin-film transistor substrate according to an embodiment of the present disclosure.

[0113] The Vgs-Ids diagram of Fig. Figure 4 shows a transfer curve according to the embodiment and a transfer curve according to the comparative example. In this case, the thin-film transistor according to one embodiment of the present disclosure has the first projection 152a on one side of the body part 151. In contrast, the thin-film transistor according to the comparative example does not have a separate projection on the gate electrode 150.

[0114] In the case of the transfer curve of the comparison example, a threshold voltage Vth is formed on the left side in comparison to the transfer curve of the embodiment, and the transfer curve of the embodiment has a threshold voltage Vth that is positive (+) in comparison to the transfer curve of the comparison example.

[0115] In the case of the thin-film transistor substrate according to the embodiment with the first projection 152a, the threshold voltage Vth can be shifted in a positive (+) direction compared to the thin-film transistor substrate according to the comparative example without the first projection 152a. The length of the channel portion 131 can be adjusted by the first projection 152a, and as a result, the length of the channel portion 131 is adjusted to shift the threshold voltage Vth of the thin-film transistor substrate of the present disclosure in a positive (+) direction.

[0116] Fig. Figure 5A is a top view of a thin-film transistor substrate according to a further embodiment of the present disclosure.

[0117] As opposed to Fig. 1B shows the thin-film transistor substrate according to Fig. 5A the second projection 152b on the other side of the body part 151 of the gate electrode 150 and thus the second convex part 133b is formed in the second connecting part 132b of the active layer 130. Since it is up to this point Fig. 1B is similar, only one of Fig. 1B differing configuration described below.

[0118] The gate electrode 150 comprises a body part 151, at least one first projection 152a and at least one second projection 152b, as shown in Fig. 5A are shown.

[0119] At least one first projection 152a is provided on one side, for example on the left side of body part 151, and at least one second projection 152b is provided on the other side, for example on the right side, of the body part. Accordingly, one side and the other side of the gate electrode 150 can be symmetrical with respect to body part 151.

[0120] Since in this case the at least one first projection 152a and the at least one second projection 152b are formed symmetrically around the body part 151, the first connecting part 132a and the second connecting part 132b, which are provided while the active layer 130 becomes conductive, can be formed symmetrically with respect to the channel part 131.

[0121] The description of at least one first projection 152a is similar to that in Fig. 1A and is therefore omitted.

[0122] The at least one second projection 152b can be provided on the other side of the body part 151, for example on the right side, and extend from the body part 151 in the first direction. As shown in Fig. As shown in Figure 5A, the at least one second projection 152b extends from the body part 151 towards the drain electrode 172. Furthermore, the at least one second projection 152b can be positioned such that it faces the at least one first projection 152a.

[0123] If, as described above, the gate electrode 150 comprises several first projections 152a and second projections 152b, the active layer 130 comprises several first convex parts 133a and second convex parts 133b, such that the horizontal length of the channel part 131 is relatively larger than in the Fig. The thin-film transistor substrate shown in 1B is shown.

[0124] Since the first protrusion 152a and the second protrusion 152b are also provided, the active layer 130 is non-conductive in the region between the multiple first convex parts 133a and in the region between the multiple second convex parts 133b. Accordingly, in the region between the multiple first convex parts 133a and the region between the multiple second convex parts 133b, the horizontal length of the channel part 131 is relatively larger than in the thin-film transistor substrate according to Fig. 1B.

[0125] As a result, the multiple first projections 152a provided on one side of the body part 151 and the multiple second projections 152b provided on the other side of the body part 151 can form the multiple first convex parts 133a in the first connecting part 132a and the multiple second convex parts 133b in the second connecting part 132b, and as a result, the horizontal length of the channel part 131 can be increased in comparison to the thin-film transistor substrate according to Fig. 1B will be relatively enlarged.

[0126] Since the second projection 152b is provided symmetrically to the first projection 152a around the body part 151, the number of first projections 152a, the distance d between the multiple first projections 152a, the length l in the first direction, and the width w of the at least one first projection 152a can also be applied under the same or similar conditions.

[0127] The channel part 131 can have a first concave part 131a on one side, for example a left side, and a second concave part 131b on the other side, for example a right side. Since the thin-film transistor according to Fig. Since the body part 151 has projections 152a and 152b on one side and the other side, the first concave part 131a and the second concave part 131b are provided symmetrically with respect to the channel part 131. Accordingly, the similar description of the first concave part 131a and the second concave part 131b is omitted.

[0128] In the case of the thin-film transistor according to Fig. 5A the horizontal length of the channel part 131 can be relatively longer, since the first concave part 131a and the second concave part 131b are provided symmetrically in the channel part 131.

[0129] The first connecting part 132a and the second connecting part 132b can be configured symmetrically with respect to the channel part 131. Here, the first convex part 133a is provided on one side of the first connecting part 132a, and the other side of the first connecting part 132a is electrically connected to the source electrode 171. Furthermore, the second convex part 133b is provided on one side of the second connecting part 132b, and the other side of the second connecting part 132b is electrically connected to the drain electrode 172.

[0130] The second connecting part 132b can comprise at least one second convex part 133b. The at least one second convex part 133b can be formed symmetrically to the at least one first convex part 133a around the channel part 131.

[0131] The thin-film transistor according to Fig. 5A has a first convex part 133a in the first connecting part 132a and a second convex part 133b in the second connecting part 132b symmetrically to the first convex part 133a, so that the length of the channel part 131 is relatively longer. Accordingly, the threshold voltage Vth of the thin-film transistor substrate according to the embodiment of Fig. 5A must be controlled so that it is not shifted in a negative (-) direction.

[0132] Fig. Figure 5B is a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure and Fig. 5B is a cross-sectional view along line II-II' of Fig. 5A.

[0133] The embodiment according to Fig. 5B is similar except for the configuration of the gate electrode 150 and the configuration of the second convex part 133b, which is provided in the active layer 130, and therefore only differing configurations are described below.

[0134] As it is in Fig. As shown in Figure 5B, the active layer 130 comprises the channel part 131, the first connecting part 132a, and the second connecting part 132b. The second connecting part 132b is connected to the other side of the channel part 131, for example, the right side of the channel part 131 in the figure.

[0135] One section of the second connecting part 132b does not overlap the gate electrode 150, and the remaining section of the second connecting part 132b does overlap the gate electrode 150, in particular the second projection 152b. The second connecting part 132b does not extend to a lower section of the body part 151 of the gate electrode 150. Accordingly, in a region where the second projection 152b of the gate electrode 150 is formed, the second convex part 133b is formed according to Fig. 5A is not formed in the second connecting part 132b.

[0136] Since, as described above, the second convex part 133b is not formed in the second connecting part 132b, which overlaps the second projection 152b, the length of the channel part 131 can be relatively increased. Accordingly, it is possible to control the threshold voltage Vth of the thin-film transistor of the present disclosure by shifting it in a negative (-) direction.

[0137] According to one embodiment of the present disclosure, the gate electrode 150 comprises the body part 151, the first projection 152a, and the second projection 152b. In this case, the first projection 152a and the second projection 152b can be symmetrical with respect to the body 151. The second projection 152b also protects a section of the active layer 130, just like the body part 151 and the first projection 152a. However, the second projection 152b overlaps the second connecting part 132b provided in the active layer 130.

[0138] Fig. Figure 6 is a top view of a thin-film transistor substrate according to a further embodiment of the present disclosure.

[0139] The thin-film transistor substrate according to Fig. 6 resembles Fig. 5A, except that the first protrusion 152a and the second protrusion 152b form one end or the other end of the active layer 130 in the thin-film transistor substrate according to Fig. 5A overlap, and therefore only one of them will be used. Fig. 5A different configuration. Described below.

[0140] In the thin-film transistor substrate according to a further embodiment of the present disclosure, as described in Fig. As shown in Figure 6, one of the several first projections 152a overlaps an end of the active layer 130. In this case, one end of the active layer 130 can overlap the gate electrode 150.

[0141] Furthermore, any one of the several first projections 152a overlaps the other end of the active layer 130. In this case, the other end of the active layer 130 can overlap the gate electrode 150 and be positioned in a direction facing one end of the active layer 130.

[0142] For example, any one of the several first projections 152a can coincide with one end of the active layer 130, and any other of the several first projections 152a can coincide with the other end of the active layer 130.

[0143] Since the first projection 152a and the second projection 152b are symmetrical with respect to body part 151, the description given above can also be applied to the second projection 152b. Therefore, a description of the second projection 152b is omitted.

[0144] Fig. Figure 7 is a top view of a thin-film transistor substrate according to a further embodiment of the present disclosure.

[0145] The thin-film transistor substrate according to Fig. 7 resembles Fig. 5A, except that the active layer 130 has a first active hole H1 and a second active hole H2, and therefore only one of Fig. 5A differing configuration described below.

[0146] According to a further embodiment of the present disclosure as it appears in Fig. As shown in Figure 7, the active layer 130 can have a channel part 131, a first connecting part 132a with at least one first convex part 133a, a second connecting part 132b with at least one second convex part 133b, at least one first active hole H1, and at least one second active hole H2. The at least one first active hole H1 is provided on one side of the active layer 130, and the at least one second active hole H2 is provided on the other side of the active layer 130.

[0147] According to one embodiment of this disclosure, the at least one first active hole H1 and the second active hole H2 can be formed by structuring a portion of the active layer 130. The active layer 130 may not be provided at the same locations as the first active hole H1 and the second active hole H2. However, the first active hole H1 and the second active hole H2 are not limited to these locations, and the active layer 130 may be partially present at a location where the first active hole H1 and the second active hole H2 are formed. Therefore, the thickness of a portion of the active layer 130 provided at the first active hole H1 and the second active hole H2 may be thinner than the thickness of the remaining portion of the active layer 130 that is not provided at the first active hole H1 and the second active hole H2.

[0148] The at least one first active hole H1 may be provided between the channel part 131 and the first connecting part 132a. Furthermore, a portion of the at least one first active hole H1 may not overlap the entire gate electrode 150, and the remaining portion of the at least one first active hole H1 may overlap the body part 151 of the gate electrode 150. The at least one first active hole H1 may not overlap the first projection 152a of the gate electrode 150.

[0149] Accordingly, the at least one first active hole H1 is formed in a region between several first projections 152a. Furthermore, the at least one first active hole H1 can be formed in a region between several first convex parts 133a.

[0150] The at least one first active hole H1 can be provided in the form of several first active holes H1, and the several first active holes H1 can be arranged in a line in the same shape. Furthermore, the gap between the several first active holes H1 can be identical. Since the first active holes H1 are configured to have the same gap, the entire first connecting part 132a can be uniformly configured.

[0151] Since the first active hole H1 is formed in this way, the degree of conductivity of the active layer 130 decreases during the conductivity process, and thus the size of the first convex part 133a decreases, and consequently the length of the channel part 131 is extended.

[0152] Similarly, the at least one second active hole H2 may be provided between the channel part 131 and the second connecting part 132b. Furthermore, a portion of the at least one second active hole H2 may not overlap the entire gate electrode 150, and the remaining portion of the at least one second active hole H2 may overlap the body part 151 of the gate electrode 150. However, the at least one second active hole H2 may not overlap the second projection 152b of the gate electrode 150.

[0153] Accordingly, the at least one second active hole H2 is formed in a region between several second projections 152b. Furthermore, the at least one second active hole H2 can be formed in a region between several second convex parts 133b.

[0154] The at least one second active hole H2 can be provided in the form of several second active holes H2, and the several second active holes H2 can be arranged in a line in the same shape. Furthermore, the gap between the several second active holes H2 can be identical. Since the second active holes H2 are configured to have the same gap, the entire second connecting part 132b can be uniformly configured.

[0155] Since the second active hole H2 is formed in this way, the conductivity of the active layer 130 is reduced during the conductivity process, thereby decreasing the size of the second convex part 133b and thus increasing the length of the channel part 131. Because the horizontal length of the channel part 131 becomes relatively long, the threshold voltage Vth of the thin-film transistor substrate is increased according to Fig. 7 may not be shifted in a negative (-) direction.

[0156] Fig. Figure 8 is a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure and Fig. Figure 8 is a cross-sectional view along line III-III' of Fig. 7. Fig. Figure 8 is a cross-sectional view including the first projection 152a and the second active hole H2 in a top view of the thin-film transistor substrate of Fig. 7. The thin-film transistor substrate according to Fig. 8 resembles the thin-film transistor substrate according to Fig. 2 with the exception that the second active hole H2 is provided in active layer 130, and therefore one of the following will be Fig. Two different configurations are described.

[0157] As it is in Fig. As shown in Figure 8, the active layer 130 can have a channel part 131, a first connecting part 132a, a second connecting part 132b, and a second active hole H2. In this case, the second active hole H2 can be formed between the channel part 131 and the second connecting part 132b.

[0158] Although not shown, the active layer 130 can be configured in a multilayer structure. For example, the active layer 130 can be configured in a bilayer structure. In this case, the active layer 130 can comprise a first active layer and a second active layer provided on top of the first active layer. The second active hole H2 can be configured in the first active layer 130, and the second active hole H2 may not be configured in the second active layer. In this case, a portion of the second active layer can contact the buffer layer 120 through the second active hole H2, which is only configured in the first active layer. However, the active layer 130 is not limited to the bilayer structure and can be configured in a three-layer or a four-layer structure.

[0159] A section of the gate insulating layer 140 formed on the active layer 130 and a section of the intermediate insulating layer 160 formed on the gate insulating layer 140 can be provided within the second active hole H2. Since the gate insulating layer 140 is structured using the gate electrode 150 as a mask during the etching process, only the portion of the gate insulating layer 140 that overlaps the gate electrode 150 remains, and the portion of the gate insulating layer 140 that does not overlap the gate electrode 150 is removed.

[0160] Since the interlayer insulating layer 160 is formed after the structuring of the gate insulating layer 140, a section of the interlayer insulating layer 160 can also be formed in the second active hole H2. Therefore, the gate insulating layer 140 can be provided in a region where the second active hole H2 and the gate electrode 150 overlap, but the gate insulating layer 140 is not provided in a region where the second active hole H2 and the gate electrode 150 do not overlap and a section of the interlayer insulating layer 160 is provided.

[0161] Fig. Figure 9 is a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure. Fig. Figure 9 is a cross-sectional view along line III-III' of Fig. 7. The description of Fig. 9 resembles the thin-film transistor substrate according to Fig. 8, with the exception that the gate insulating layer 140 is formed in an etch-free structure, and therefore mainly differing configurations are described below.

[0162] The gate insulating layer 140 is formed on the active layer 130. For example, the gate insulating layer 140 can be provided on a section of the buffer layer 120, the channel part 131, the first connection part 132a and the second connection part 132b, and the gate insulating layer 140 can also be provided in the second active hole H2, which is provided between the channel part 131 and the second connection part 132b.

[0163] The gate insulating layer 140 can be formed in an etch-free structure, as described in Fig. 3 is described, and the non-etching structure is similar to that in Fig. 3, so that it is not described. Since the gate insulating layer 140 can be formed in an etch-free structure, the second active hole H2 can be provided with the gate insulating layer 140, as shown in Fig. 8 is shown.

[0164] Fig. Figure 10 is a cross-sectional view of a display device with a thin-film transistor substrate according to an embodiment of the present disclosure.

[0165] As it is in Fig. As shown in Figure 10, the display device according to one embodiment of the present disclosure comprises a substrate 100, a light-blocking layer 110, a buffer layer 120, an active layer 130, a gate insulating layer 140, a gate electrode 150, an intermediate insulating layer 160, a source electrode 171, a drain electrode 172, a planarization layer 180, a first electrode 190, a bank layer 200, a light-emitting layer 210, and a second electrode 220. The substrate 100, the light-blocking layer 110, the buffer layer 120, the active layer 130, the gate insulating layer 140, the gate electrode 150, the intermediate insulating layer 160, the source electrode 171, the drain electrode 172, and the planarization layer 180 are similar to those described above, and repeated descriptions of them are omitted.

[0166] A third contact hole CH3 is provided on the planarization layer 180 such that the drain electrode 172 is exposed through the third contact hole CH3. In some cases, however, the source electrode 171 may also be exposed through the third contact hole CH3.

[0167] The first electrode 190 is formed on the planarization layer 180 and is connected to the source electrode 171 or the drain electrode 172 via the third contact hole CH3. The first electrode 190 can function as the anode.

[0168] The bench layer 200 is positioned to cover an edge of the first electrode 190, defining a light-emitting area. Accordingly, any upper surface area of ​​the first electrode 190 that is exposed, not covered by the bench layer 200, also becomes a light-emitting area.

[0169] The light-emitting layer 210 is provided on the first electrode 190. The light-emitting layer 210 can comprise a red, a green, and a blue light-emitting layer, each structured for a specific pixel, or it can consist of a single white light-emitting layer connected to all pixels. If the light-emitting layer 210 consists of a white light-emitting layer, it can, for example, include a first stack of a blue light-emitting layer, a second stack of a yellow-green light-emitting layer, and a charge-generating layer located between the first and second stacks, but this configuration is not limited to these components.

[0170] The second electrode 220 is provided on the light-emitting layer 210. The second electrode 220 can function as a cathode. Although not shown, an encapsulation layer can also be formed on the second electrode 220 to prevent the ingress of moisture or oxygen.

[0171] Fig. Figure 11 is a schematic representation of a display device according to an embodiment of the present disclosure.

[0172] As it is in Fig. As shown in Figure 11, the display device according to one embodiment of the present disclosure can comprise a display panel 310, a gate driver 320, a data driver 330, and a controller 340. The display panel 310 comprises gate lines GLs and data lines DLs, and pixels P are arranged in the respective intersection regions of the gate lines GLs and data lines DLs. An image is displayed by activating pixel P. The gate lines GLs, the data lines DLs, and the pixels P can be arranged on the substrate 100.

[0173] Controller 340 controls Gate Driver 320 and Data Driver 330. Controller 340 outputs a Gate Control Signal (GCS) to control Gate Driver 320 and a Data Control Signal (DCS) to control Data Driver 330 using a signal supplied by an external system (not shown). Additionally, Controller 340 samples input video data from the external system, rearranges the sampled input video data, and supplies the rearranged RGB digital video data to Data Driver 330.

[0174] The gate control signal GCS comprises a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. Furthermore, control signals for controlling a shift register can be included in the gate control signal GCS. The data control signal DCS comprises a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

[0175] The data driver 330 supplies a data voltage to the data lines DL of the display panel 310. The data driver 330 converts the RGB video data input from the controller 340 into an analog data voltage and supplies the data voltage to the data lines DL.

[0176] The gate driver 320 can be mounted on the display panel 310. As described above, a structure in which the gate driver 320 is mounted directly on the display panel 310 is called a gate-in-panel (GIP) structure. In the gate-in-panel (GIP) structure, the gate driver 320 can be arranged on the substrate 100.

[0177] The gate driver 320 can include a shift register 350. During a single frame, the shift register 350 sequentially supplies gate pulses to the gate lines GL using the start signal and gate clock sent from the controller 340. Here, a single frame refers to a period during which an image is displayed on the display panel 310. The gate pulse has a turn-on voltage capable of switching on a switching device (a thin-film transistor) located in pixel P.

[0178] Furthermore, during the remaining time of a single frame in which the gate pulse is not supplied, the shift register 350 delivers a gate-off signal to the gate line GL, which can switch off the switching device. Hereinafter, the gate pulse and the gate-off signal are collectively referred to as the sampling signal GS.

[0179] Fig. Figure 12 is a circuit diagram of a shift register according to an embodiment of the present disclosure.

[0180] As it is in Fig. As shown in Figure 12, the GIP circuit comprises a full-up node Q, a full-down node QB, a node controller NC, and a buffer unit Buffer. The buffer unit Buffer is connected to an output terminal and comprises a full-up transistor Tu, a full-down transistor Td, and a capacitor C.

[0181] The full-up transistor Tu is turned on to output the gate-on signal when the full-up node Q is charged with a gate high voltage. The full-down transistor Td is turned on to output the gate-off signal when the full-down node QB is charged with a gate low voltage.

[0182] The capacitor C serves to maintain the gate high voltage supplied to the full-up transistor Tu for a single frame and is provided between the gate terminal and the source terminal of the full-up transistor Tu.

[0183] The node controller NC controls the charging and discharging between the full-up node Q and the full-down node QB. The node controller NC can include a full-up node controller NC_Q for controlling the charging and discharging of the full-up node Q and a full-down node controller NC_QB for controlling the charging and discharging of the full-down node QB. The full-up node controller NC_Q includes at least one transistor TQ for controlling the full-up node Q, and the full-down node controller NC_QB includes at least one transistor TQB for controlling the full-down node QB.

[0184] The output of the gate signal Vout can be stably controlled by the node controller NC. Here, the node controller NC discharges the full-down node QB to a gate low voltage when the full-up node Q is charged with a gate high voltage, and discharges the full-down node Q to a gate low voltage when the full-down node QB is charged with a gate high voltage.

[0185] When the start signal Vst is applied, the operation of the multiple transistors TQ and TQB provided in the node controller NC charges the full-up node Q with a gate high voltage and discharges the full-down node QB with a gate low voltage, thus outputting the source high voltage VDD as the gate signal Vout. Similarly, when a discharge signal VQB is applied, the operation of the multiple transistors TQ and TQB provided in the node controller NC charges the full-up node Q with a gate low voltage and charges the full-down node QB with a gate high voltage, outputting a low-power voltage VSS as the gate signal Vout.

[0186] Fig. Figure 13 is a circuit diagram of a pixel provided in a display device according to an embodiment of the present disclosure.

[0187] As it is in Fig. As shown in Figure 13, the display device according to one embodiment of the present disclosure comprises a first and second thin-film transistor T1 and T2 and capacitors Cst. The first thin-film transistor T1 is a driver thin-film transistor and the second thin-film transistor T2 is a switching thin-film transistor. At least one of the first thin-film transistor T1 and the second thin-film transistor T2 can be formed from the various thin-film transistors described above.

[0188] The first thin-film transistor T1 is switched according to the data voltage Vdata supplied by the second thin-film transistor T2, generates a data stream from the drive voltage VDD supplied by the power line PL, and delivers it to the organic light-emitting diode OLED. The second thin-film transistor T2 is switched according to the gate signal GS supplied to the gate line GL and delivers the data voltage Vdata supplied by the data line DL to the first thin-film transistor T1.

[0189] The capacitor Cst serves to maintain the data voltage supplied to the first thin-film transistor T1 for a single frame and is located between the gate and source electrodes of the first thin-film transistor T1. The organic light-emitting diode (OLED) emits predefined light according to a data stream supplied by the first thin-film transistor T1.

[0190] Fig. Figure 14 is a circuit diagram of a pixel provided in a display device according to a further embodiment of the present disclosure.

[0191] As it is in Fig. As shown in Figure 14, the display device according to a further embodiment of the present disclosure comprises a first to third thin-film transistor T1, T2, T3 and a capacitor Cst. The first thin-film transistor T1 is a driver thin-film transistor, and the second and third thin-film transistors T2 to T3 are switching thin-film transistors. At least one of the first to third thin-film transistors T1, T2, and T3 can be formed from the various thin-film transistors described above.

[0192] The first thin-film transistor T1 is switched according to the data voltage Vdata supplied by the second thin-film transistor T2, generates a data current from the drive voltage VDD supplied by the power line PL, and delivers it to the organic light-emitting diode OLED. The second thin-film transistor T2 is switched according to the gate signal GS supplied to the gate line GL and delivers the data voltage Vdata supplied by the data line DL to the first thin-film transistor T1. The third thin-film transistor T3, in response to the sampling control signal SENSE supplied by the sampling line SCL, delivers the current of the first thin-film transistor T1 to the reference line RL. A reference voltage Vref is supplied to the reference line RL.

[0193] The capacitor Cst serves to maintain the data voltage supplied to the first thin-film transistor T1 for a single frame and is located between the gate and source electrodes of the first thin-film transistor T1. The organic light-emitting diode (OLED) emits predefined light according to a data stream supplied by the first thin-film transistor T1.

[0194] Fig. Figure 15 is a circuit diagram of a pixel provided in a display device according to a further embodiment of the present disclosure.

[0195] As it is in Fig. As shown in Figure 15, the display device according to a further embodiment of the present disclosure comprises a first to fourth thin-film transistor T1, T2, T3 and T4 and a capacitor Cst.

[0196] The first thin-film transistor, T1, is a driver transistor, and the second through fourth thin-film transistors, T2 through T4, are switching transistors. At least one of the first through fourth thin-film transistors, T1, T2, T3, and T4, can be composed of the different thin-film transistors described above.

[0197] The first thin-film transistor T1 is switched according to the data voltage Vdata supplied by the second thin-film transistor T2, generates a data current from the drive voltage VDD supplied by the power line PL, and delivers it to the organic light-emitting diode (OLED). The second thin-film transistor T2 is switched according to the gate signal GS supplied to the gate line GL and delivers the data voltage Vdata supplied by the data line DL to the first thin-film transistor T1. The third thin-film transistor T3, in response to the sampling control signal SENSE supplied by the sampling line SCL, delivers the current of the first thin-film transistor T1 to the reference line RL. A reference voltage Vref is applied to the reference line RL.The fourth thin-film transistor T4 is switched according to the light emission control signal EM, which is supplied to the light emission control line EML, and supplies the control voltage VDD supplied by the power line PL to the first thin-film transistor T1.

[0198] The capacitor Cst serves to maintain the data voltage supplied to the first thin-film transistor T1 for a single frame and is located between the gate and source electrodes of the first thin-film transistor T1. The organic light-emitting diode (OLED) emits predefined light according to a data stream supplied by the first thin-film transistor T1.

[0199] Accordingly, the present disclosure may, for example, have the following advantages.

[0200] According to one embodiment of the present disclosure, an area in which an active layer overlapping the gate electrode is conductive can be controlled in a process for enabling the conductivity of the active layer, since protrusions are provided on one side and the other side of the gate electrode in the top-gate thin-film transistor structure.

[0201] Since, according to one embodiment of the present disclosure, an area in which the active layer is conductive can be controlled even in the case of a thin-film transistor with a large-width active layer, a phenomenon in which the length of the channel becomes too short can be controlled.

[0202] Since, according to one embodiment of the present disclosure, a region in which the active layer is conductive can be controlled, a device with a sufficiently long channel length can be reliably implemented in a wide active layer. Because the channel length is not too short, for example, a thin-film transistor substrate can be created that implements the designed properties.

[0203] Since, according to one embodiment of the present disclosure, the top-gate thin-film transistor has projections on one side and the other side of the gate electrode, and the active layer has active holes such that they do not overlap the projections of the gate electrode, an area can be controlled in which the active layer overlaps the gate electrode.

[0204] According to one embodiment of the present disclosure, it is possible to prevent the threshold voltage Vth of the thin-film transistor with a wide channel from being shifted in the negative (-) direction, since the conductive area within the channel part is controlled by the projection of the gate electrode and the active hole of the active layer.

[0205] According to one embodiment of the present disclosure, since the threshold voltage Vth is prevented from shifting in the negative (-) direction, a leakage current of the thin-film transistor of the highly mobile device can be prevented and the power consumption of the board with the thin-film transistor can be reduced. This allows for the production of a low-power thin-film transistor substrate.

Claims

[1] Thin-film transistor substrate comprising the following: a substrate (100); an active layer (130) on the substrate (100); a gate electrode (150) on the active layer (130); a source electrode (171) connected to a first side of the active layer (130); and a drain electrode (172) connected to a second side of the active layer (130), wherein the gate electrode (150) comprises a body part (151) and at least one first projection (152a) on a first side of the body part (151), wherein the at least one first projection (152a) overlaps the active layer (130) in a top view, the active layer (130) comprises: a channel section (131); a source region (132a) on a first side of the channel part (131), wherein the source region (132a) is conductive and is connected to the source electrode (171); and a drain area (132b) on a second side of the channel part (131), wherein the drain area (132b) is conductive and is connected to the drain electrode (172), where at least one first projection (152a) overlaps the source area (132a), wherein the channel part (131) has several first concave parts (131a) and the source region (132a) has several first convex parts (133a) in a region corresponding to the several first concave parts (131a). [2] Thin-film transistor substrate according to claim 1, wherein the multiple first convex parts (133a) do not overlap the at least one first projection (152a). [3] Thin-film transistor substrate according to one of claims 1 and 2, wherein the several first convex parts (133a) have a round shape. [4] Thin-film transistor substrate according to one of the preceding claims, wherein the at least one first projection (152a) comprises several first projections (152a) and each of the several first projections (152a) has the same shape. [5] Thin-film transistor substrate according to any of the preceding claims, wherein the at least one first projection (152a) comprises several first projections (152a) and wherein a gap between adjacent first projections (152a) is 0.5 µm or more and 50 µm or less. [6] Thin-film transistor substrate according to any of the preceding claims, wherein the length of the at least one first projection (152a) in a first direction is 0.5 µm or more and 5 µm or less, a length of at least one first projection (152a) in a second direction is 0.5 µm or more and 20 µm or less, the first direction is a direction in which the source electrode (171) and the drain electrode (172) face each other, and the second direction is perpendicular to the first direction. [7] Thin-film transistor substrate according to one of the preceding claims, wherein the at least one first projection (152a) does not overlap the source electrode (171) and the drain electrode (172). [8] Thin-film transistor substrate according to claim 1, wherein the gate electrode (150) further comprises at least one second projection (152b) on a second side of the body part (151), wherein the at least one second projection (152b) overlaps the active layer (130). [9] Thin-film transistor substrate according to claim 8, wherein the at least one first projection (152a) and at least one second projection (152b) are arranged symmetrically with respect to the body part (151). [10] Thin-film transistor substrate according to one of claims 8 and 9, wherein the active layer (130) comprises: a channel section (131); a source region (132a) on a first side of the channel part (131), wherein the source region (132a) is conductive and is connected to the source electrode (171); and a drain area (132b) on a second side of the channel part (131), wherein the drain area (132b) is conductive and is connected to the drain electrode (172), wherein at least one first projection (152a) overlaps the source area (132a) and at least one second projection (152b) overlaps the drain area (132b). [11] Thin-film transistor substrate according to claim 10, wherein the channel part (131) has several first concave parts (131a) and several second concave parts (131b), the source region (132a) has several first convex parts (133a) in a region corresponding to the several first concave parts (131a), and the drain area (132b) has several second convex parts (133b) in an area corresponding to the several second concave parts (131b). [12] Thin-film transistor substrate according to claim 11, wherein the multiple first convex parts (133a) and the multiple second convex parts (133b) are arranged symmetrically with respect to the channel part (131). [13] Thin-film transistor substrate according to one of the preceding claims, wherein the at least one first projection (152a) overlaps an edge in a longitudinal direction of the active layer (130), wherein the longitudinal direction is a direction between the source region (132a) and the drain region (132b). [14] Thin-film transistor substrate according to any of the preceding claims, wherein the active layer (130) has at least one active hole (H1, H2) and the at least one active hole (H1, H2) does not overlap the at least one first projection (152a). [15] Thin-film transistor substrate according to claim 14, wherein a section of the at least one active hole (H1, H2) overlaps the body part (151) and a remaining section of the at least one active hole (H1, H2) does not overlap the body part (151). [16] Thin-film transistor substrate according to one of claims 14 and 15, further comprising a gate insulating layer (140) between the gate electrode (150) and the active layer (130), wherein the gate insulating layer (140) is located within the at least one active hole (H1, H2). [17] Thin-film transistor substrate according to one of claims 14 to 16, further comprising an interlayer insulating layer (160) between the source electrode (171) and the active layer (130), wherein the interlayer insulating layer (160) is located within the at least one active hole (H1, H2). [18] Display device comprising: a thin-film transistor substrate comprising the following: a substrate (100); an active layer (130) on the substrate (100); a gate electrode (150) on the active layer (130); a source electrode (171) on a first side of the active layer (130); and a drain electrode (172) on a second side of the active layer (130), wherein the gate electrode (150) comprises a body part (151) and at least one first projection (152a) on a first side of the body part (151), wherein the at least one first projection (152a) overlaps the active layer (130); a gate driver (320) connected to the thin-film transistor substrate to supply gate signals to the thin-film transistor substrate; and a data driver (330) connected to the thin-film transistor substrate to supply data signals to the thin-film transistor substrate, the active layer (130) comprises: a channel section (131); a source region (132a) on a first side of the channel part (131), wherein the source region (132a) is conductive and is connected to the source electrode (171); and a drain area (132b) on a second side of the channel part (131), wherein the drain area (132b) is conductive and is connected to the drain electrode (172), where at least one first projection (152a) overlaps the source area (132a), wherein the channel part (131) has several first concave parts (131a) and the source region (132a) has several first convex parts (133a) in a region corresponding to the several first concave parts (131a).

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