METHODS, SYSTEMS, EQUIPMENT AND MANUFACTURES FOR MANAGING NETWORK COMMUNICATIONS IN TIME-CRITICAL NETWORKS

Abstract

Systems, devices, manufactured articles, and processes are disclosed. An exemplary device disclosed herein is designed to determine, based on (a) the payload of the data packet and (b) historical information associated with the data stream, whether a data packet from a data stream should be discarded or forwarded. The exemplary device is also designed to perform actions on the data packet based on this determination.

Description

RELATED APPLICATION

[0001] This patent claims priority to Indian Provisional Patent Application No. 202341048353, filed on July 19, 2023. Indian Provisional Patent Application No. 202341048353 is hereby incorporated by reference in its entirety. AREA OF REVELATION

[0002] This disclosure relates generally to network communications and, more particularly, to methods, systems, apparatus, and articles of manufacture for managing network communications in time-critical networks. BACKGROUND

[0003] At a general level, edge computing refers to the transition of computing and storage resources closer to endpoint devices (e.g., consumer computing devices, user equipment, etc.) to optimize total cost of ownership, reduce application latency, improve service capabilities, and enhance compliance with security or privacy requirements. In some edge network environments, data is transferred between edge devices (e.g., edge computing devices) in the form of network packets. For example, data may be collected and packaged into a network packet (e.g., a data packet), which is then sent to a scheduler of a network interface controller (NIC), which is responsible for dispatching the network packet to a destination computing device.In recent years, time-sensitive networking (TSN) has been developed to reduce latency and / or jitter in the transmission of network packets between edge devices. Time-sensitive networks provide time synchronization and packet scheduling to ensure that latency targets are met for network packets sent between devices. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates an example representation of an edge cloud configuration for edge computing. Fig. Figure 2 illustrates operational layers between endpoints, an edge cloud, and cloud computing environments. Fig. Figure 3 illustrates an example approach for networking and services in an edge computing system. Fig. Figure 4 illustrates a computing and communication use case involving mobile access to applications in an edge computing system. Fig. Figure 5A provides an overview of example computational components deployed at a compute node in an edge computing system. Fig. Figure 5B provides a further overview of example components within a computing device in an edge computing system. Fig. 6 illustrates an example cluster of nodes in an example Time Sensitive Network (TSN) environment. Fig. 7 illustrates an example system including an example control node implementing example power mapping circuitry and an example edge node implementing example state management circuitry in accordance with teachings of this disclosure. Fig. Figure 8 illustrates exemplary implementations of the exemplary control node and the exemplary edge node of Fig. 7. Fig. 9 is a block diagram of the exemplary current mapping circuitry of Fig. 7 and / or 8. Fig. 10 is a table representing exemplary compression schemes implemented by the exemplary current mapping circuitry of Fig. 9 can be implemented. Fig. 11 illustrates an example process flow for implementing an example power allocation procedure according to teachings of this disclosure. Fig. 12 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed by example programmable circuitry to implement the example current mapping circuitry of Fig. 9 to be implemented. Fig. 13 illustrates an example system for managing data ingestion, the system including an example platform and an example network interface card implementing example utility evaluation circuitry in accordance with teachings of this disclosure. Fig. 14 is a block diagram of the exemplary utility evaluation circuitry of Fig. 13. Fig. 15 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed by example programmable circuitry to implement the example utility evaluation circuitry of Fig. 14 to register a new entropy function. Fig. 16 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed by example programmable circuitry to implement the example utility evaluation circuitry of Fig. 14 to determine whether an example data packet should be discarded or forwarded. Fig. 17 is a block diagram of an example processing platform including programmable circuitry configured to execute, instantiate, and / or perform the example machine-readable instructions and / or perform the example operations of Fig. 12 for implementing the exemplary current mapping circuitry of Fig. 9 is structured. Fig. 18 is a block diagram of an example processing platform including programmable circuitry configured to execute, instantiate, and / or perform the example machine-readable instructions and / or perform the example operations of Fig. 15 and / or 16 for implementing the utility evaluation circuitry of Fig. 14 is structured. Fig. 19 is a block diagram of an exemplary implementation of the programmable circuitry of Fig. 17 and / or 18. Fig. 20 is a block diagram of another exemplary implementation of the programmable circuitry of Fig. 17 and / or 18. Fig. 21 is a block diagram of an example software / firmware / instruction distribution platform (e.g., one or more servers) for distributing software, instructions, and / or firmware (e.g., corresponding to the example machine-readable instructions of Fig. 12, Fig. 15 and / or 16) to client devices associated with end users and / or consumers (e.g., for license, sale and / or use), retailers (e.g., for sale, resale, license and / or sublicense), and / or original equipment manufacturers (OEMs) (e.g., for inclusion in products to be distributed, for example, to retailers and / or other end users, such as direct purchase customers).

[0004] In general, the same reference numerals are used throughout the drawings and the accompanying written description to refer to the same or similar parts. The figures are not necessarily to scale. DETAILED DESCRIPTION

[0005] Methods, systems, devices, and articles of manufacture for managing network communications in time-critical networks are disclosed. In some network environments, real-time traffic may experience excessive latency and / or jitter when networks with multiple transmit and receive hosts are congested. In recent years, Time-Sensitive Networks (TSNs) have been developed to reduce latency and / or jitter in networks by synchronizing clocks, allocating resources (e.g., bandwidth and / or time) between nodes, and / or prioritizing real-time data streams across the network.

[0006] However, in some applications, bandwidth, latency, and / or other quality of service (QoS) requirements between nodes in a network may vary over time. For example, in some industrial applications, the expected QoS between nodes may vary based on a production phase on a factory floor. For example, for a first operation (e.g., an automated paint inspection operation) performed on a first assembly line using wirelessly connected cameras mounted on robots, uplink bandwidth utilization may increase when compute-intensive tasks (e.g., artificial intelligence (AI) inference, image processing, etc.) are performed at a network edge. In some cases, the network edge may also perform a second operation (e.g.,A robotic welding operation may control a second assembly line, such as a robotic welding operation, where the second operation may expect different QoS levels, for example, based on one or more distances between robot arms and one or more objects on the second assembly line. For such networks with time-varying QoS expectations (e.g., with respect to latency, bandwidth, etc.), examples disclosed herein provide techniques for managing and / or satisfying the changing QoS expectations across a network.

[0007] In some examples, overprovisioning a system is used to accommodate changing QoS expectations of the system. In a congested system, additional bandwidth and / or resources are allocated to corresponding communication links so that a portion (e.g., all) of the communication links meet a highest expected QoS level for the system. However, some applications may not require the highest QoS level and / or may not simultaneously utilize the highest QoS level, resulting in wasted and / or unused resources in the system. Therefore, while overprovisioning may be practical in small and / or dedicated wired networks (e.g., a network where links have a fixed and / or known capacity), overprovisioning and / or using the highest QoS level is not feasible for dynamic networks with links (e.g.,Wireless connections) with variable capacity and / or variable bandwidth limitations may not be desirable and / or efficient.

[0008] Furthermore, in recent years, increasing data volumes have been observed in some network environments (e.g., involving smart cities and / or analytics) where thousands of sensors and / or other sources send data streams to one or more servers (e.g., server platforms). In some cases, large amounts of data arriving at the server(s) at high transfer rates can create a number of challenges. For example, the server(s) often store the data in-memory for in-memory analytics (e.g., for cases where the data is expected to operate at memory speeds). However, the server(s) typically have limited memory to store such data, requiring prioritization of data processing.Furthermore, if the server(s) are required to process multiple parallel streams, it may be difficult to order and / or process incoming data while ensuring that the data stored in memory is representative of a monitored system.

[0009] Typically, servers receiving multiple data streams parse a portion (e.g., some or all) of the data to determine how to handle the data (e.g., whether to discard data and / or retain the data in memory for processing and / or storage) based on one or more rules and / or policies (e.g., user-defined and / or predetermined rules). For example, the rules may be based on data pattern type, time of day, carbon monoxide levels, indoor temperature, etc. In some examples, a server may monitor an incoming data stream for certain data patterns, and / or the server may average a portion (e.g., all) of the data within a certain range. In some such cases, the server stores and / or retains data that satisfies the one or more rules, and the server does not store (e.g., discard) data that does not satisfy the one or more rules.At scale, such determinations can be difficult and inefficient to perform, especially in cases where real-time analytics are to be performed on the data. Furthermore, to implement one or more such rules in software (e.g., at least temporarily), the server stores a portion (e.g., part or all) of the incoming data in memory. Such an approach may work for relatively few incoming streams, but can lead to a bottleneck when there are a large number (e.g., thousands, tens of thousands, etc.) of incoming streams.

[0010] In some examples, much of the incoming data has low (or no) utility (e.g., entropy) relative to a complete dataset (e.g., all collected information) for a system. As used herein, utility refers to a measure of the variability of data and / or information provided by the data relative to previously collected data for a given data stream. For example, for data that is relatively invariant (e.g., the variability between the data and previously collected data is relatively small and / or less than a threshold), the corresponding utility is relatively low. Conversely, for data that is highly variable and / or anomalous (e.g., the difference(s) between the data and previously collected data is greater than or equal to the threshold), the corresponding utility is relatively high.In other words, high-utility data provides a greater amount of new and / or useful information than low-utility data.

[0011] In some examples, low utility is common for discrete sensor data. For example, the variation of data over time for some sensors (e.g., temperature sensors, carbon monoxide sensors, and / or video cameras) implemented at remote locations may be relatively small (e.g., less than a threshold). Furthermore, in some examples, there may be a large number (e.g., thousands) of such sensors in physical proximity to one another, resulting in information redundancy (e.g., low utility) in the sensor data due to spatial overlap of the sensors. Because the sensors independently stream data to a server and / or set of servers, such information redundancy may not be detectable at the stream level.

[0012] Examples disclosed herein determine whether a data packet of a data stream should be discarded or forwarded based on an example utility value (e.g., an entropy value) corresponding to the data packet. Examples disclosed herein enable an example software stack to register one or more example utility functions (e.g., entropy functions) with an example network interface card (e.g., a network interface card (NIC), an infrastructure processing unit (IPU), etc.), where the utility functions can be mapped to respective example queues (e.g., network queues, processing queues, application device queues, etc.) on the network interface hardware. In some examples, the utility function(s) correspond to filters, custom sampling techniques, and / or other data shaping techniques that can be applied to incoming data.Examples disclosed herein perform the utility function(s) based on a payload of the data packet and / or based on historical information associated with the data stream. In some examples, examples disclosed herein determine the utility value corresponding to the data packet based on a result of executing the utility function(s) and determine whether to forward or discard the data packet based on the utility value. Advantageously, examples disclosed herein may reduce an amount of redundant and / or low-utility data to be ingested at a platform, thereby reducing an amount of computational resources and / or memory used to store and / or process incoming data.

[0013] Further examples disclosed herein preconfigure multiple proxy data streams for sending data between edge devices in a time-critical network environment. For example, examples disclosed herein preconfigure the proxy data streams to meet respective different communication metrics (e.g., bandwidth, latency, etc.) for data sent over the proxy data streams. In some examples, the proxy data streams are preconfigured based on expected QoS levels for one or more applications and / or operations associated with the edge device(s) and / or based on computing and / or communication resources available to the edge device(s). In some examples, the example circuitry disclosed herein may select one of the proxy data streams that meets a target communication metric (e.g., a target QoS level, a target bandwidth and / or latency, etc.).) for a first edge device, and may cause transmission of data from the first edge device to a second edge device based on the selected one of the proxy data streams. Furthermore, the example circuitry may dynamically switch between one of the proxy data streams to meet changing QoS requirements for data transmitted to the second edge device.

[0014] In some examples, communication resources are preconfigured and / or pre-allocated to the respective proxy data streams as part of a handshake procedure between the edge device(s) and a central node (e.g., a centralized user configuration (CUC) node) of the time-critical network environment. For example, the configuration of the proxy data streams may be performed once, and the configuration may be performed offline or in the background and prior to changes in QoS demand. Once configured, the example circuitry may switch between the proxy data streams without requiring reallocation of communication resources and / or recalculation of possible scheduling plans for data sent over the network.In some examples, because the proxy data streams and / or the scheduling plans are pre-computed, the circuitry can switch between one of the proxy data streams with little or no signaling overhead. Accordingly, examples disclosed herein can reduce the time and / or computational power used to adapt to changing QoS requirements in the network. Advantageously, examples disclosed herein can meet the changing QoS requirements without overprovisioning the network.

[0015] Fig. 1 is a block diagram 100 showing an overview of an edge computing configuration that includes a processing layer, referred to as an "edge cloud" in many of the following examples. As shown, the edge cloud 110 is co-located at an edge location, such as an access point or base station 140, a local processing hub 150, or a central office 120, and thus may include multiple entities, devices, and device instances. The edge cloud 110 is located much closer to endpoint (consumer and producer) data sources 160 (e.g., autonomous vehicles 161, user equipment 162, enterprise and industrial equipment 163, video capture devices 164, drones 165, smart city or building devices 166, sensors and IoT devices 167, etc.) than the cloud data center 130.Compute, memory, and storage resources offered at the edges in the edge cloud 110 are critical for providing ultra-low latency response times for services and functions used by the endpoint data sources 160, as well as for reducing network backhaul traffic from the edge cloud 110 to the cloud data center 130, thereby improving power consumption and overall network utilization, among other benefits.

[0016] Computing, memory, and storage are scarce resources and generally decrease depending on the edge location (with, for example, fewer processing resources available at consumer endpoint devices than at a base station than at a central office). However, the closer the edge location is to the endpoint (e.g., user equipment (UE)), the more space and power are often constrained. Therefore, edge computing attempts to reduce the amount of resources required for network services by distributing more resources that are closer both geographically and in terms of network access time. In this way, edge computing attempts to bring the compute resources to the workload data, where appropriate, or to bring the workload data to the compute resources.

[0017] The following describes aspects of an edge cloud architecture that covers several potential deployments and addresses limitations that some network operators or service providers may have in their own infrastructures. These include varying configurations based on the edge location (since edges at a base station level, for example, may have more limited performance and capabilities in a multi-tenant scenario); configurations based on the type of compute, memory, storage, fabric, acceleration, or similar resources available to edge locations, tiers of locations, or groups of locations; the service, security, and management and orchestration capabilities; and associated goals for achieving end-service usability and performance.These deployments can perform processing in network layers, which can be considered as “near edge,” “close edge,” “local edge,” “middle edge,” or “far edge” layers depending on latency, distance, and timing characteristics.

[0018] Edge computing is an emerging paradigm in which computing is performed at or closer to the "edge" of a network, typically through the use of a compute platform (e.g., x86 or ARM compute hardware architecture) implemented at base stations, gateways, network routers, or other devices located much closer to endpoint devices that generate and consume the data. For example, edge gateway servers can be equipped with pools of memory and storage resources to perform real-time computations for low-latency use cases (e.g., autonomous driving or video surveillance) for connected client devices. Or, as one example, base stations can be augmented with compute and acceleration resources to directly process service workloads for connected user equipment, without further communicating data across backhaul networks.Or, as another example, central office network management hardware can be replaced with standardized compute hardware that performs virtualized network functions and provides compute resources for running services and consumer applications for connected devices. Within edge computing networks, there may be scenarios in services where the compute resource is "offloaded" to the data, as well as scenarios where the data is "offloaded" to the compute resource. Or, as one example, compute, acceleration, and network resources at the base station can provide services to scale workload requirements as needed by activating unused capacity (subscription, Capacity on Demand) to manage corner cases, emergencies, or provide longevity for deployed resources over a significantly longer implemented lifecycle.

[0019] Fig. Figure 2 illustrates operational layers between endpoints, an edge cloud, and cloud computing environments. In particular, Fig. 2 illustrates examples of computing use cases 205 that utilize the edge cloud 110 under several illustrative layers of network computing. The layers begin at an endpoint (devices and things) layer 200 that accesses the edge cloud 110 to perform data creation, analysis, and data consumption activities. The edge cloud 110 may span multiple network layers, such as an edge device layer 210 with gateways, on-premises servers, or network devices (nodes 215) located in physically proximate edge systems; a network access layer 220 that encompasses base stations, radio processing units, network hubs, regional data centers (DCs), or local network equipment (equipment 225); and any equipment, devices, or nodes located in between (in layer 212, not illustrated in detail).Network communication within the edge cloud 110 and between the various layers may occur over any number of wired or wireless media, including connectivity architectures and technologies not shown.

[0020] Examples of latencies resulting from network communication distance and processing time constraints can range from less than one millisecond (ms) at the endpoint layer 200, to less than 5 ms at the edge device layer 210, to even between 10 and 40 ms when communicating with nodes at the network access layer 220. Beyond the edge cloud 110 are core network 230 and cloud data center 240 layers, each with increasing latency (e.g., between 50-60 ms at the core network layer 230 and up to 100 or more ms at the cloud data center layer). As a result, operations in a core network data center 235 or a cloud data center 245 with latencies of at least 50 to 100 ms or more will not be able to implement many time-critical functions of use cases 205.Each of these latency values ​​is provided for illustrative and contrast purposes; it is understood that the use of other access network media and technologies can further reduce latencies. In some examples, respective portions of the network may be categorized as "close edge," "local edge," "near edge," "middle edge," or "far edge" layers relative to a network source and destination.For example, from the perspective of the core network data center 235 or a cloud data center 245, a switch or content data network may be considered to be located within a "near edge" layer ("close" to the cloud, with high latency in communication with the devices and endpoints of the use cases 205), whereas an access point, base station, on-premises server, or network gateway may be considered to be located within a "far edge" layer ("far" from the cloud, with low latency in communication with the devices and endpoints of the use cases 205).It is understood that other categorizations of a particular network layer constituting a "near," "local," "proximity," "middle," or "far" edge may be based on latency, distance, number of network hops, or other measurable characteristics as measured by a source in any of the network layers 200 through 240.

[0021] The various use cases 205 may access resources under pressure from incoming flows due to multiple services utilizing the edge cloud. To achieve low-latency results, the services executing within the edge cloud 110 balance varying requirements in terms of: (a) priority (throughput or latency) and quality of service (QoS) (e.g., traffic for an autonomous car may have a higher priority than a temperature sensor in terms of response time requirement; or a performance sensitivity / bottleneck may exist at a compute / accelerator, memory, storage, or network resource depending on the application); (b) reliability and resilience (e.g.,some input streams must be processed and traffic routed with mission-critical reliability, whereas some other input streams can tolerate occasional failure depending on the application); and (c) physical constraints (e.g., power, cooling, and form factor).

[0022] The end-to-end service view for these use cases incorporates the concept of a service flow and is associated with a transaction. The transaction specifies the overall service requirement for the entity consuming the service, as well as the associated services for the resources, workloads, workflows, and business function and enterprise-level requirements. The services executed with the described "conditions" can be managed at each layer in a way that ensures real-time and runtime contract compliance for the transaction throughout the service lifecycle.If a component in the transaction misses its agreed SLA, the system as a whole (components in the transaction) can provide the capability to (1) understand the impact of the SLA violation and (2) augment other components in the system to resume the entire transaction SLA, and (3) implement operations to remedy the situation.

[0023] Accordingly, taking these variations and service characteristics into account, edge computing within edge cloud 110 can provide the ability to serve and respond to multiple applications of use cases 205 (e.g., object tracking, video surveillance, tethered vehicles, etc.) in real-time or near-real-time, and meet ultra-low latency requirements for these multiple applications. These benefits enable a whole new class of applications (virtual network functions (VNF), function-as-a-service (FaaS), edge-as-a-service (EaaS), standard processes, etc.) that cannot leverage traditional cloud computing due to latency or other limitations.

[0024] However, with the benefits of edge computing come the following caveats. Devices located at the edge are often resource-constrained, putting pressure on the utilization of edge resources. This is typically addressed by pooling memory and storage resources for use by multiple users (tenants) and devices. The edge may be power- and cooling-constrained, so the power consumption by the applications that consume the most power must be considered. There can be inherent performance and capability trade-offs with these pooled storage resources, as many are likely to use new storage technologies where increased performance requires greater memory bandwidth.Likewise, enhanced hardware security and trusted root-of-trust capabilities are required, as edge sites may be unmanned and even require authorized access (e.g., if located at a third-party site). Such problems are magnified in the edge cloud 110 in a multi-tenant, multi-owner, or multi-access situation where services and applications are requested by many users, especially as network usage fluctuates dynamically and the composition of the multiple stakeholders, use cases, and services changes.

[0025] At a more generic level, an edge computing system can be described as comprising any number of deployments at the previously discussed layers operating in the edge cloud 110 (network layers 200-240) that provide coordination of client and distributed computing devices. One or more edge gateway nodes, one or more edge aggregation nodes, and one or more core data centers may be distributed across layers of the network to provide an implementation of the edge computing system by or on behalf of a telecommunications service provider ("Telco" or "TSP"), Internet of Things service provider, cloud service provider (CSP), an enterprise entity, or any number of other entities. Different implementations and configurations of the edge computing system can be dynamically deployed, such as when orchestrated to meet service objectives.

[0026] Consistent with the examples provided herein, a client computing node may be embodied as any type of endpoint component, device, application, or other thing capable of communicating as a producer or consumer of data. Furthermore, the label "node" or "device" as used in the edge computing system does not necessarily imply that such node or device operates in a client or agent / minion / follower role; rather, any of the nodes or devices in the edge computing system refer to individual entities, nodes, or subsystems that include specific or associated hardware or software configurations to enable or utilize the edge cloud 110.

[0027] As such, edge cloud 110 is comprised of network components and features operated by and within edge gateway nodes, edge aggregation nodes, or other edge computing nodes between network layers 210-230. Edge cloud 110 may thus be embodied as any type of network that provides edge computing and / or storage resources located near radio access network (RAN)-enabled endpoint devices (e.g., mobile computing devices, IoT devices, smart devices, etc.) discussed herein.In other words, the edge cloud 110 may be envisioned as an "edge" connecting endpoint devices and traditional network access points, serving as an entry point into service provider core networks, including mobile carrier networks (e.g., Global System for Mobile Communications (GSM) networks, Long Term Evolution (LTE) networks, 5G / 6G networks, etc.), while also providing storage and / or computing capabilities. Other types and forms of network access (e.g., Wi-Fi, wireless, long-range wired networks, including optical networks) may also be used instead of or in combination with such 3GPP carrier networks.

[0028] The network components of edge cloud 110 may be servers, multi-tenant servers, single-unit computing devices, and / or any other type of computing device. For example, edge cloud 110 may include a device computing device, which is a standalone electronic device including an enclosure, chassis, case, or shell. In some circumstances, the enclosure may be sized for portability so that it can be carried and / or shipped by a human. Example enclosures may include materials forming one or more exterior surfaces that partially or fully protect the contents of the device, where the protection may include weather protection, protection in hazardous environments (e.g., EMI, vibration, extreme temperatures), and / or allow for submersibility.Example enclosures may include power circuitry to provide power to stationary and / or portable implementations, such as AC power inputs, DC power inputs, AC / DC or DC / AC converters, power regulators, transformers, charging circuitry, batteries, wired inputs, and / or wireless power inputs. Example enclosures and / or surfaces thereof may include or be connected to mounting hardware to enable attachment to structures such as buildings, telecommunications structures (e.g., masts, antenna structures, etc.), and / or racks (e.g., server racks, blade mounts, etc.). Example enclosures and / or their surfaces may support one or more sensors (e.g., temperature sensors, vibration sensors, light sensors, acoustic sensors, capacitive sensors, proximity sensors, etc.).One or more of these sensors may be contained within, supported by, or otherwise embedded in and / or mounted on the surface of the device. Example enclosures and / or surfaces thereof may support mechanical connectivity, such as propulsion hardware (e.g., wheels, propellers, etc.) and / or articulated hardware (e.g., robotic arms, pivoting appendages, etc.). In some circumstances, the sensors may include any type of input device, such as user interface hardware (e.g., buttons, switches, dials, sliders, etc.). In some circumstances, example enclosures include output devices contained within, supported by, embedded in, and / or attached to them. Output devices may include displays, touchscreens, lights, LEDs, speakers, I / O ports (e.g., USB), etc.In some circumstances, edge devices are devices that are presented on the network for a specific purpose (e.g., a traffic light), but may have processing and / or other capabilities that can be used for other purposes. Such edge devices may be independent of other networked devices and may be equipped with an enclosure that has a form factor suitable for their primary purpose; but is still available for other computing tasks that do not interfere with their primary task. Edge devices include Internet of Things devices. The device computing device may include hardware and software components to manage local factors such as device temperature, vibration, resource utilization, updates, power factors, physical and network security, etc. Example hardware for implementing a device computing device is described in connection with. Fig. 5B. The edge cloud 110 may also include one or more servers and / or one or more multi-tenant servers. Such a server may include an operating system and a virtual computing environment. A virtual computing environment may include a hypervisor that manages (creates, deploys, destroys, etc.) one or more virtual machines, one or more containers, etc. Such virtual computing environments provide an execution environment in which one or more applications and / or other software, code, or scripts may be executed while being isolated from one or more other applications, software, code, or scripts.

[0029] In Fig. 3, various client endpoints 310 (in the form of mobile devices, computers, autonomous vehicles, business computing equipment, industrial processing equipment) exchange requests and responses specific to the type of endpoint network aggregation. For example, client endpoints 310 may access the network via a wired broadband network by exchanging requests and responses 322 via a local area network system 332. Some client endpoints 310, such as mobile computing devices, may access the network via a wireless broadband network by exchanging requests and responses 324 via an access point (e.g., a cell tower) 334. Some client endpoints 310, such as autonomous vehicles, may access the network for requests and responses 326 via a wireless vehicular network through a road-based network system 336.Regardless of the type of network access, however, the TSP may deploy aggregation points 342, 344 within the edge cloud 110 to aggregate traffic and requests. Thus, the TSP may deploy various computing and storage resources within the edge cloud 110, such as at edge aggregation nodes 340, to deliver requested content. The edge aggregation nodes 340 and other systems of the edge cloud 110 are connected to a cloud or data center 360, which uses a backhaul network 350 to fulfill higher latency requests from a cloud / data center for websites, applications, database servers, etc. Additional or consolidated instances of the edge aggregation nodes 340 and the aggregation points 342, 344, including those deployed on a single server framework, may also exist within the edge cloud 110 or other areas of the TSP infrastructure.

[0030] It is understood that the edge computing systems and arrangements discussed herein may be applicable to various solutions, services, and / or use cases involving mobility. As an example, Fig. 4 illustrates a simplified vehicle computing and communications use case involving mobile access to applications in an edge computing system 400 implementing an edge cloud 110. In this use case, respective client computing nodes 410 may be implemented as in-vehicle computing systems (e.g., in-vehicle navigation and / or infotainment systems) located in respective vehicles that communicate with edge gateway nodes 420 while traveling along a roadway. For example, edge gateway nodes 420 may be located in a control cabinet or other enclosure incorporated into a structure having another, separate, mechanical utility and may be placed along the roadway, at roadway intersections, or other locations near the roadway.As respective vehicles travel along the road, the connection may propagate between their client compute node 410 and a dedicated edge gateway device 420 to maintain a consistent connection and context for the client compute node 410. Similarly, mobile edge nodes may aggregate services based on high priority or throughput or latency resolution requirements for the one or more underlying services (e.g., in the case of drones). The respective edge gateway devices 420 include a lot of processing and storage capabilities, and therefore, some processing and / or storage of data for the client compute nodes 410 may be performed on one or more of the edge gateway devices 420.

[0031] The edge gateway devices 420 may communicate with one or more edge resource nodes 440, illustratively implemented as computing servers, devices, or components located at or within a communications base station 442 (e.g., a base station of a cellular network). As discussed above, the respective edge resource nodes 440 include a lot of processing and storage capabilities, and thus, some processing and / or storage of data for the client computing nodes 410 may be performed on the edge resource node 440.For example, processing of data that is less urgent or important may be performed by the edge resource node 440, while processing of data that has a higher urgency or importance may be performed by the edge gateway devices 420 (depending, for example, on the capabilities of each component or information in the request indicating urgency or importance). Based on data access, data location, or latency, work may continue on edge resource nodes if processing priorities change during processing activity. Similarly, configurable systems or hardware resources themselves may be activated (e.g., by a local orchestrator) to provide additional resources to meet the new demand (e.g., adapting compute resources to the workload data).

[0032] The one or more edge resource nodes 440 also communicate with the core data center 450, which may include computing servers, devices, and / or other components located at a central location (e.g., a central office of a cellular communication network). The core data center 450 may provide a gateway to the global network cloud 460 (e.g., the Internet) for the operations of the edge cloud 110 formed by the one or more edge resource nodes 440 and the edge gateway devices 420. Additionally, in some examples, the core data center 450 may include a lot of processing and storage capabilities, and thus, some processing and / or storage of data for the client computing devices may be performed on the core data center 450 (e.g., low urgency or importance or high complexity processing).

[0033] The edge gateway nodes 420 or the edge resource nodes 440 may offer the use of stateful applications 432 and a geographically distributed database 434. Although the applications 432 and the database 434 are illustrated as being distributed horizontally across a layer of the edge cloud 110, it is understood that resources, services, or other components of the application may be distributed vertically across the edge cloud (including a portion of the application executing at the client compute node 410, other portions at the edge gateway node 420 or the edge resource node 440, etc.). Additionally, as previously stated, peer relationships may exist at any level to fulfill service objectives and commitments.Furthermore, data for a specific client or application can move from edge to edge based on changing conditions (e.g., based on acceleration resource availability, vehicle movement consequences, etc.). For example, a prediction can be made based on the "decay rate" of the access to identify the next owner to continue, or to identify when the data or computational access will no longer be viable. These and other services can be used to complete the work needed to keep the transaction compliant and lossless.

[0034] In further scenarios, container 436 (or a pod of containers) can be flexibly migrated from one edge node 420 to other edge nodes (e.g., 420, 640, etc.), so that the container with an application and workload does not need to be reconstituted, recompiled, or reinterpreted for the migration to work. However, in such settings, some workaround or "swizzling" translation operations may be applied. For example, the physical hardware at node 440 may differ from that of the edge gateway node 420, and therefore the hardware abstraction layer (HAL) that forms the lower edge of the container is remapped to the physical layer of the target edge node.This may involve some form of late-binding technique, such as binary translation of the HAL from the native container format to the physical hardware format, or may involve mapping interfaces and operations. Pod control can be used to drive interface mapping as part of the container lifecycle, which includes migration to / from different hardware environments.

[0035] The scenarios that Fig. 4 may utilize various types of mobile edge nodes, such as an edge node hosted in a vehicle (car / truck / tram / railway) or other mobile device, as the edge node will move to different geographic locations along the platform that hosts it. In vehicle-to-vehicle communications, individual vehicles may even act as network edge nodes for other cars (e.g., to perform caching, reporting, data aggregation, etc.). Thus, it is understood that the application components deployed in various edge nodes may be distributed in static or mobile settings, including coordination between some functions or operations at individual endpoint devices or the edge gateway node 420, some others at the edge resource node 440, and others in the core data center 450 or the global network cloud 460.

[0036] In further configurations, the edge computing system can implement FaaS computing capabilities through the use of respective executable applications and functions. In one example, a developer writes functional code (herein, for example, "computer code") representing one or more computer functions, and the functional code is uploaded to a FaaS platform, provided, for example, by an edge node or a data center. A trigger, such as a service use case or an edge processing event, initiates the execution of the functional code with the FaaS platform.

[0037] In one example of FaaS, a container is used to provide an environment in which functional code (e.g., an application that may be deployed by a third party) is executed. The container can be any entity with isolated execution, such as a process, a Docker or Kubernetes container, a virtual machine, etc. Within the edge computing system, various data center, edge, and endpoint devices (including mobile devices) are used to "spin up" functions (e.g., enable and / or assign function actions) that scale on demand. The functional code is executed on the physical infrastructure device (e.g., edge computing nodes) and underlying virtualized containers. Finally, the container is "spin down" (e.g., deactivated and / or released) on the infrastructure in response to the completion of execution.

[0038] Other aspects of FaaS may enable edge capabilities to be delivered in a service format, including support for specific features that support edge computing as a service (Edge-as-a-Service or “EaaS”).Additional features of FaaS may include: a granular billing component that allows customers (for example, computer code developers) to pay only when their code is executed; a shared data store for storing data for reuse by one or more functions; orchestration and management between individual functions; function execution management, concurrency, and consolidation; management of container and function memory spaces; coordination of acceleration resources available to functions; and distribution of functions between containers (including "warm" containers that are already deployed or running versus "cold" ones that require initialization, deployment, or configuration).

[0039] The edge computing system 400 may include or be in communication with an edge deployment node 444. The edge deployment node 444 may execute software, such as the example computer-readable instructions 582 of Fig. 5B, to various receiving participants for implementing any of the methods described herein. The example edge provisioning node 444 may be implemented by any computer server, home server, content delivery network, virtual server, software distribution system, central facility, storage device, storage node, data facility, cloud service, etc., capable of storing and / or transmitting software instructions (e.g., code, scripts, executable binaries, containers, packages, compressed files, and / or derivatives thereof) to other computing devices.One or more components of the example edge deployment node 644 may be located in a cloud, on a local network, on an edge network, on a wide area network, on the Internet, and / or at any other location communicatively coupled to the one or more recipients. The recipients may be customers, clients, partners, users, etc., of the entity that owns and / or operates the edge deployment node 444. For example, the entity that owns and / or operates the edge deployment node 444 may be a developer, vendor, and / or licensor (or a customer and / or consumer thereof) of software instructions such as the example computer-readable instructions 582 of FIG. Fig. 5B. The receiving parties may be consumers, service providers, users, retailers, OEMs, etc., who acquire and / or license the software instructions for use and / or resale and / or sublicense.

[0040] In one example, edge deployment node 444 includes one or more servers and one or more data storage devices. The storage devices host computer-readable instructions, such as the example computer-readable instructions 582 of Fig. 5B, as described below. Similar to the edge gateway devices 420 described above, the one or more servers of the edge deployment node 444 are in communication with a base station 442 or other network communication entity. In some examples, the one or more servers respond to requests to transfer the software instructions to a requesting party as part of a commercial transaction. Payment for the delivery, sale, and / or license of the software instructions may be handled by the one or more servers of the software distribution platform and / or via a third-party payment entity. The servers enable purchasers and / or licensors to download the computer-readable instructions 582 from the edge deployment node 444. For example, the software instructions corresponding to the example computer-readable instructions 582 of Fig. 5B, onto which one or more example processor platforms are downloaded that are to execute the computer-readable instructions 582 to implement the methods described herein.

[0041] In some examples, the processor platform(s) executing the computer-readable instructions 582 may be physically located in different geographic locations, different legal jurisdictions, etc. In some examples, one or more servers of the edge deployment node 444 periodically provide, transmit, and / or enforce updates to the software instructions (e.g., the example computer-readable instructions 582 of Fig. 5B) to ensure that enhancements, patches, updates, etc., are distributed and applied to the software instructions implemented on the end-user devices. In some examples, different components of the computer-readable instructions 582 may be distributed from different sources and / or to different processor platforms; for example, different libraries, plug-ins, components, and other types of computation modules, whether compiled or interpreted, may be distributed from different sources and / or to different processor platforms. For example, a portion of the software instructions (for example, a script that is not inherently executable) may be distributed from a first source, while an interpreter (capable of executing the script) may be distributed from a second source.

[0042] In further examples, any of the compute nodes or devices discussed with reference to the present edge computing systems and environment may be configured based on the components described in Fig. 5A and Fig. 5B. Respective edge computing nodes may be implemented as a type of device, appliance, computer, or other "thing" capable of communicating with other edge, networking, or endpoint components. For example, an edge computing device may be embodied as a personal computer, server, smartphone, mobile computing device, smart device, in-vehicle computing system (e.g., a navigation system), a standalone device with an outer casing, shell, etc., or any other device or system capable of performing the described functions.

[0043] In Fig. 5A, an edge compute node 500 includes a compute engine (also referred to herein as "compute circuitry") 502, an input / output (I / O) subsystem 508, data storage 510, a communication circuitry subsystem 512, and optionally one or more peripheral devices 514. In other examples, respective compute devices may include other or additional components, such as those commonly found in a computer (e.g., a display, peripheral devices, etc.). One or more of the illustrative components may additionally be incorporated into or otherwise form part of another component in some examples.

[0044] Compute node 500 may be embodied as any type of engine, device, or collection of devices capable of performing various computing functions. In some examples, compute node 500 may be embodied as a single device such as an integrated circuit, an embedded system, a field-programmable gate array (FPGA), a system-on-chip (SOC), or other integrated system or device. In the illustrative example, compute node 500 includes or is embodied as a processor 504 and a memory 506. Processor 504 may be embodied as any type of processor capable of performing the functions described herein (e.g., executing an application).The processor 504 may be implemented, for example, as one or more multi-core processors, a microcontroller, a processing unit, a special purpose or specialized processing unit, or another processor or other processing / control circuit.

[0045] In some examples, the processor 504 may be embodied as, including, or coupled to an FPGA, an application-specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other specialized hardware to enable performance of the functions described herein. In some examples, the processor 504 may also be embodied as a specialized x-processing unit (xPU), also known as a data processing unit (DPU), infrastructure processing unit (IPU), or network processing unit (NPU). Such an xPU may be embodied as a standalone circuit or circuit package, integrated within a SOC, or integrated with networking circuitry (e.g.,Such an xPU may be integrated with other processors (e.g., a SmartNIC or enhanced SmartNIC), acceleration circuitry, storage devices, or AI hardware (e.g., GPUs or programmed FPGAs). Such an xPU may be configured to receive programming to process one or more data streams and perform specific tasks and actions on the data streams (such as hosting microservices, performing service management or orchestration, organizing or managing server or data center hardware, managing service networks, or collecting and distributing telemetry) external to the CPU or general-purpose processing hardware. However, it should be understood that an xPU, a SOC, a CPU, and other variations of the processor 504 may work in coordination with one another to execute many types of operations and instructions within and on behalf of the compute node 500.

[0046] Memory 506 may be embodied as any type of volatile (e.g., Dynamic Random Access Memory - DRAM, etc.) or non-volatile memory or non-volatile data storage suitable for performing the functions described herein. Volatile memory may be any storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of Random Access Memory (RAM), such as DRAM or Static Random Access Memory (SRAM). One particular type of DRAM that may be used in a memory module is Synchronous Dynamic Random Access Memory (SDRAM).

[0047] In one embodiment, the memory device is a block-addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include a three-dimensional crosspoint memory device (e.g., Intel® 3D XPoint™ memory) or other byte-addressable write-in-place non-volatile memory devices. The memory device may refer to the die itself and / or to a packaged memory product. In some examples, the 3D crosspoint memory (e.g., Intel® 3D XPoint™ memory) may comprise a transistorless stackable crosspoint architecture where memory cells sit at the intersection of wordlines and bitlines and are individually addressable, and where bit storage is based on a change in bulk resistance. In some examples, all or a portion of the memory 506 may be integrated into the processor 504.The memory 506 may store various software and data used during operation, such as one or more applications, data manipulated by the one or more applications, libraries, and drivers.

[0048] Computing circuitry 502 is communicatively coupled to other components of compute node 500 via I / O subsystem 508, which may be implemented as circuitry and / or components, to enable input / output operations with computing circuitry 502 (e.g., with processor 504 and / or main memory 506) and other components of computing circuitry 502. I / O subsystem 508 may be implemented as, for example, or otherwise include memory control hubs, input / output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point connections, bus connections, wires, cables, optical fibers, traces, etc.), and / or other components and subsystems to facilitate input / output operations.In some examples, the I / O subsystem 508 may form a portion of a system-on-chip (SoC) and may be integrated into the computing circuitry 502 along with one or more of the processor 504, the memory 506, and other components of the computing circuitry 502.

[0049] The one or more illustrative data storage devices 510 may be implemented as any type of device configured for short-term or long-term storage of data, such as memory devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage devices. Individual data storage devices 510 may include a system partition that stores data and firmware code for the data storage device 510. Individual data storage devices 510 may also include one or more operating system partitions that store files and executables for operating systems, depending on, for example, the type of compute node 500.

[0050] The communication circuitry 512 may be embodied as any communication circuit, device, or collection thereof capable of enabling communications over a network between the computing circuitry 502 and another computing device (e.g., an edge gateway of an implementing edge computing system). The communication circuitry 512 may be configured to support any one or more communication technologies (e.g., wired or wireless communications) and associated protocols (e.g., a cellular network protocol such as a 3GPP 4G or 5G standard, a wireless local area network protocol such as IEEE 802.11 / Wi-Fi®, a wireless wide area network protocol, Ethernet, Bluetooth®, Bluetooth Low Energy, an IoT protocol such as IEEE 802.15.4 or ZigBee®, low-power wide area network (LPWAN) or low-power wide area (LPWA) protocols, etc.).) to effect such communication.

[0051] The illustrative communication circuitry 512 includes a network interface controller (NIC) 520, which may also be referred to as a host fabric interface (HFI). The NIC 520 may be embodied as one or more daughter boards, subordinate cards, network interface cards, control chips, chipsets, or other devices that may be used by the compute node 500 to interface with another computing device (e.g., an edge gateway node). In some examples, the NIC 520 may be implemented as part of a system-on-chip (SoC) that includes one or more processors or may be included in a multi-chip package that also includes one or more processors. In some examples, the NIC 520 may include a local processor (not shown) and / or local memory (not shown), both of which are local to the NIC 520.In such examples, the local processor of the NIC 520 may be capable of performing one or more of the functions of the computing circuitry 502 described herein. Additionally or alternatively, in such examples, the local memory of the NIC 520 may be integrated into one or more components of the client compute node at the board level, socket level, chip level, and / or other levels.

[0052] Additionally, in some examples, a respective compute node 500 may include one or more peripheral devices 514. Such peripheral devices 514 may include any type of peripheral device found in a computing device or server, such as audio input devices, a display, other input / output devices, interface devices, and / or other peripheral devices, depending on the particular type of compute node 500. In further examples, compute node 500 may be embodied by a respective edge compute node (whether a client, gateway, or aggregation node) in an edge computing system or similar forms of devices, computers, subsystems, circuitry, or other components.

[0053] In a more detailed example, Fig. 5B is a block diagram of an example of components that may be present in an edge computing node 550 for implementing the techniques (e.g., operations, processes, methods, and techniques) described herein. This edge computing node 550 provides a closer view of the respective components of node 500 when implemented as or as part of a computing device (e.g., as a mobile device, a base station, a server, a gateway, etc.). The edge computing node 550 may include any combination of the hardware or logical components referenced herein, and may include or be coupled to any device usable with an edge communications network or combination of such networks.The components may be implemented as integrated circuits (ICs), portions thereof, discrete electronic devices or other modules, instruction sets, programmable logic or algorithms, hardware, hardware accelerators, software, firmware, or a combination thereof adapted in the edge computing node 550, or as components otherwise integrated into a chassis of a larger system.

[0054] Edge computing device 550 may include processing circuitry in the form of a processor 552, which may be a microprocessor, a multi-core processor, a multi-threaded processor, an ultra-low-voltage processor, an embedded processor, an xPU / DPU / IPU / NPU, a special-purpose processing unit, a specialized processing unit, or other known processing elements. Processor 552 may be part of a system-on-chip (SoC) in which processor 552 and other components are formed in a single integrated circuit or package, such as the Edison™ or Galileo™ SoC boards from Intel Corporation, Santa Clara, California. As an example, the processor 552 may include an Intel® Core™ architecture-based CPU processor, such as a Quark™, ​​Atom™, i3, i5, i7, i9, or MCU class processor, or other such processor available from Intel®.However, any number of other processors may be used, such as those available from Advanced Micro Devices, Inc. (AMD®) of Sunnyvale, California, a MIPS-based design from MIPS Technologies, Inc. of Sunnyvale, California, an ARM-based design licensed from ARM Holdings, Ltd. or a customer thereof, or its licensee or user. The processors may include devices such as an A5-13 processor from Apple® Inc., a Snapdragon™ processor from Qualcomm® Technologies, Inc., or an OMAP™ processor from Texas Instruments, Inc. The processor 552 and accompanying circuitry may be provided in a single socket form factor, multiple socket form factors, or a variety of other formats, including in limited hardware configurations or configurations that include fewer than all of the features described in . Fig. 5B shown elements.

[0055] Processor 552 may communicate with system memory 554 via an interconnect 556 (e.g., a bus). Any number of memory devices may be used to provide a given amount of system memory. As examples, memory 754 may be random access memory (RAM) conforming to a JEDEC (Joint Electron Devices Engineering Council) design, such as the DDR or mobile DDDR standards (e.g., LPDDR, LPDDR2, LPDDR3, or LPDDR4). In certain examples, a memory component may conform to a standard published by JEDEC, such as ESD79F for DDR-SDRAM, JESD79-2F for DDR2-SDRAM, JESD79-3F for DDR3-SDRAM, JESD79-4A for DDR4-SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4.Such standards (and similar standards) may be referred to as DDR-based standards, and communication interfaces of the storage devices implementing such standards may be referred to as DDR-based interfaces. In various implementations, the individual memory devices may be any of a number of different package types, such as Single Die Package (SDP), Dual Die Package (DDP), or Quad Die Package (Q17P). These devices may, in some examples, be soldered directly to a motherboard to provide a lower-profile solution, while in other examples, the devices are configured as one or more memory modules that are in turn coupled to the motherboard through a given connector. Any number of other memory implementations may be used, such as other types of memory modules, e.g.,Dual Inline Memory Modules (DIMMs) of various variants, including microDIMMs or MiniDIMMs.

[0056] To provide persistent storage of information, such as data, applications, operating systems, and so on, storage 558 may also couple to processor 552 via interconnect 556. In one example, storage 558 may be implemented via a solid-state disk drive (SSDD). Other devices that may be used for storage 558 include flash memory cards, such as Secure Digital (SD) cards, microSD cards, Extreme Digital (XD) image cards, and the like, and Universal Serial Bus (USB) flash drives. In one example, the memory device may be a chalcogenide glass, a multi-threshold NAND flash memory, a NOR flash memory, a single-level or multi-level phase-change memory (PCM), a resistive memory, a nanowire memory, a ferroelectric transistor random access memory (FeTRAM), an antiferroelectric memory, a magnetoresistive random access memory (MRAM),that incorporates memristor technology, be or include resistive memory that incorporates the metal oxide base, the oxygen vacancy base, and the conductive bridge Random Access Memory (CB-RAM), or Spin-Transfer Torque (STT)-MRAM, a spintronic magnetic junction-based device, a magnetic tunnel junction (MTJ)-based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer)-based device, a thyristor-based memory device, or a combination of any of the above, or other memory.

[0057] In low-power implementations, storage 558 may be on-die memory or registers associated with processor 552. However, in some examples, storage 558 may be implemented using a micro hard disk drive (HDD). Furthermore, any number of new technologies for storage 558 may be used in addition to or in place of the described technologies, such as, but not limited to, resistive change memory, phase change memory, holographic memory, or chemical memory.

[0058] The components can communicate via interconnect 556. Interconnect 556 can include any number of technologies, including industry standard architecture (ISA), enhanced ISA (EISA), peripheral component interconnect (PCI), peripheral component interconnect extended (PCIx), PCI Express (PCIe), or any number of other technologies. Interconnect 556 can be a proprietary bus, such as used in an SoC-based system. Other bus systems can be included, such as an Inter-Integrated Circuit (I2C) interface, a Serial Peripheral Interface (SPI) interface, point-to-point interfaces, and a power bus, among others.

[0059] The interconnect 556 may couple the processor 552 to the transceiver 566 for communications with connected edge devices 562. The transceiver 566 may use any number of frequencies and protocols, such as, but not limited to, transmissions at 2.4 gigahertz (GHz) under the IEEE 802.15.4 standard using the Bluetooth® Low Energy (BLE) standard as defined by the Bluetooth® Special Interest Group, or the ZigBee® standard. Any number of radios configured for a particular wireless communication protocol may be used for the connections to the connected edge devices 562. For example, a WLAN (Wireless Local Area Network) unit may be used to implement Wi-Fi® communications according to the IEEE (Institute of Electrical and Electronics Engineers) 802.11 standard. In addition, long-distance radio network communications, e.g.,in accordance with a cellular or other wireless wide area network protocol over a wireless wide area network (WWAN) unit.

[0060] The wireless network transceiver 566 (or multiple transceivers) may communicate using multiple standards or radios for communications at a different range. For example, the edge computing node 550 may communicate with nearby devices, e.g., within about 10 meters, using a local transceiver based on Bluetooth Low Energy (BLE) or another low-power radio to conserve power. More distant connected edge devices 562, e.g., within about 50 meters, may be reached via ZigBee® or other medium-power radios. Both communication techniques may take place via a single radio with different power levels, or may take place via separate transceivers, e.g., a local transceiver using BLE and a separate mesh transceiver using ZigBee®.

[0061] A wireless network transceiver 566 (e.g., a radio transceiver) may be included to communicate with devices or services in a cloud (e.g., the edge cloud 595) using local or wide-area network protocols. The wireless network transceiver 566 may be, among other things, a Low-Power Wide-Area (LPWA) transceiver following the IEEE 802.15.4 or IEEE 802.15.4g standards. The edge computing node 550 may communicate over a wide area using LoRaWAN™ (Long Range Wide Area Network) developed by Semtech and the LoRa Alliance. The techniques described herein are not limited to these technologies but may be used with any number of other cloud transceivers implementing long-range, low-bandwidth communications, such as Sigfox, and other technologies.Furthermore, other communication techniques can be used, such as time slot channel hopping, which is described in the IEEE 802.15.4e specification.

[0062] Any number of other radio communications and protocols may be used in addition to the systems mentioned for the wireless network transceiver 566 as described herein. For example, the transceiver 566 may include a radio transceiver that uses spread spectrum (SPA / SAS) communications to implement high-speed communications. Furthermore, any number of other protocols may be used, such as Wi-Fi® networks for medium-speed communications and provisioning network communications. The transceiver 566 may include radios compatible with any number of 3GPP (Third Generation Partnership Project) specifications, such as Long Term Evolution (LTE) and fifth-generation (5G) communication systems, which are discussed in more detail at the end of the present disclosure.A network interface controller (NIC) 568 may be included to provide wired communication to nodes of the edge cloud 595 or to other devices, such as the connected edge devices 562 (e.g., operating in a mesh). The wired communication may provide an Ethernet connection or may be based on other types of networks, such as Controller Area Network (CAN), Local Interconnect Network (LIN), DeviceNet, ControlNet, Data Highway+, PROFIBUS, or PROFINET, among many others. An additional NIC 568 may be included to enable connection to a second network, for example, a first NIC 568 providing communications to the cloud over Ethernet and a second NIC 568 providing communications to other devices over a different network type.

[0063] Given the variety of types of applicable communications from the device to another component or network, applicable communication circuitry employed by the device may include or be implemented by one or more of components 564, 566, 568, or 570. Accordingly, in various examples, applicable means for communicating (e.g., receiving, transmitting, etc.) may be implemented by such communication circuitry.

[0064] Edge computing node 550 may include or be coupled to acceleration circuitry 564, which may be embodied by one or more artificial intelligence (AI) accelerators, a neural network, neuromorphic hardware, an FPGA, an array of GPUs, an array of xPUs / DPUs / IPUs / NPUs, one or more SoCs, one or more CPUs, one or more digital signal processors, dedicated ASICs, or other forms of specialized processors or circuitry designed to perform one or more specialized tasks. These tasks may include AI processing (including machine learning, training, inference, and classification operations), visual computing, network computing, object detection, rule analysis, or the like.These tasks may also include the specific edge computing tasks for service management and service operations discussed elsewhere in this document.

[0065] The interconnect 556 may couple the processor 552 to a sensor hub or external interface 570 used to connect additional devices or subsystems. The devices may include sensors 572, such as accelerometers, level sensors, flow sensors, optical light sensors, camera sensors, temperature sensors, global navigation system sensors (e.g., GPS), pressure sensors, barometric pressure sensors, and the like. The hub or interface 570 may further be used to connect the edge computing node 550 to actuators 574, such as power switches, valve actuators, an audible tone generator, a visual warning device, and the like.

[0066] In some optional examples, various input / output (I / O) devices may be present within or connected to the edge computing node 550. For example, a display or other output device 584 may be included to show information, such as sensor readings or actuator position. An input device 586, such as a touchscreen or keypad, may be included to accept input. An output device 584 may include any number of forms of audio or visual display, including simple visual outputs such as binary status indicators (e.g., light-emitting diodes (LEDs)) and multi-character visual outputs, or more complex outputs such as display screens (e.g., liquid crystal display (LCD) screens), where the output of characters, graphics, multimedia objects, and the like is generated or produced from the operation of the edge computing node 550.Display or console hardware may be used in the context of the present system to provide output and receive input of an edge computing system; manage components or services of an edge computing system; identify a state of an edge computing component or service; or perform any other number of management or administrative functions or service use cases.

[0067] A battery 576 may power the edge computing node 550, although in examples where the edge computing node 550 is mounted at a fixed location, it may include a power supply coupled to a power grid, or the battery may be used as a backup or for temporary capabilities. The battery 576 may be a lithium-ion battery or a metal-air battery, such as a zinc-air battery, an aluminum-air battery, a lithium-air battery, and the like.

[0068] A battery monitor / charger 578 may be included in the edge computing node 550 to track the state of charge (SoCh) of the battery 576, if included. The battery monitor / charger 578 may be used to monitor other parameters of the battery 576 to provide failure predictions, such as the state of health (SoH) and state of function (SoF) of the battery 576. The battery monitor / charger 578 may include a battery monitoring integrated circuit, such as an LTC4020 or an LTC2990 from Linear Technologies, an ADT7488A from ON Semiconductor of Phoenix, Arizona, USA, or an IC from the UCD90xxx family from Texas Instruments of Dallas, TX, USA. The battery monitor / charger 578 may communicate the information about the battery 576 to the processor 552 via the interconnect 556.The battery monitor / charger 578 may also include an analog-to-digital converter (ADC) that allows the processor 552 to directly monitor the voltage of the battery 576 or the current flow from the battery 576. The battery parameters may be used to determine actions that the edge computing node 550 may perform, such as transmission frequency, mesh network operation, sampling frequency, and the like.

[0069] A power block 580 or other power supply coupled to a power grid may be coupled to the battery monitor / charger 578 to charge the battery 576. In some examples, the power block 580 may be replaced with a wireless power receiver to receive power wirelessly, for example, via a loop antenna in the edge computing node 550. A wireless battery charging circuit, such as, but not limited to, an LTC4020 chip from Linear Technologies of Milpitas, California, may be included in the battery monitor / charger 578. The specific charging circuits may be selected based on the size of the battery 576 and thus the required current.Charging can be performed using, among others, the Airfuel standard published by the Airfuel Alliance, the Qi wireless charging standard published by the Wireless Power Consortium, or the Rezence charging standard published by the Alliance for Wireless Power.

[0070] Storage 558 may include instructions 582 in the form of software, firmware, or hardware commands for implementing the techniques described herein. Although such instructions 582 are shown as code blocks contained within memory 554 and storage 558, it should be understood that any of the code blocks may be replaced by hard-wired circuitry incorporated, for example, in an application-specific integrated circuit (ASIC).

[0071] In one example, the instructions 582 provided via memory 554, storage 558, or processor 552 may be embodied as a non-transitory machine-readable medium 560 that includes code to instruct processor 552 to perform electronic operations in edge computing node 550. Processor 552 may access non-transitory machine-readable medium 560 via interconnect 556. For example, non-transitory machine-readable medium 560 may be embodied by devices described for storage 558 or may include specific storage units, such as optical disks, flash drives, or any number of other hardware devices.The non-transitory, machine-readable medium 560 may include instructions for directing the processor 552 to perform a specific sequence or flow of actions, such as described with reference to the flowchart(s) and block diagram(s) of operations and functionality presented above. As used herein, the terms "machine-readable medium" and "computer-readable medium" are interchangeable.

[0072] Also in a specific example, the instructions 582 on the processor 552 (separately or in combination with the instructions 582 of the machine-readable medium 560) may configure the execution or operation of a trusted execution environment (TEE) 590. In one example, the TEE 590 operates as a protected area accessible to the processor 552 for secure execution of instructions and secure access to data. Various implementations of the TEE 590 and an accompanying secure area in the processor 552 or in the memory 554 may be provided, for example, using Intel® Software Guard Extensions (SGX) or ARM® TrustZone® hardware security extensions, Intel® Management Engine (ME), or Intel® Converged Security Manageability Engine (CSME).Other aspects of security hardening, hardware root of trust, and trusted or protected operations may be implemented in device 550 by TEE 590 and processor 552.

[0073] Fig. 6 illustrates an example cluster (e.g., a node cluster, a device cluster) 602 implemented in an example Time Sensitive Network (TSN) environment 600. In the illustrated example of Fig. 6, cluster 602 includes example devices (e.g., endpoint devices, user equipment) 604 communicatively coupled to an example bridge (e.g., a TSN bridge) 606. In this example, devices 604 include example robotic arms 608 (e.g., a first example robotic arm 608A, a second example robotic arm 608B, and a third example robotic arm 608C), an example camera 610, and an example conveyor belt 612, with devices 604 working together to perform an example assembly procedure. In the illustrated example, an example computing device (e.g., a TSN end device, an edge computing server, an edge computing node) 614 is communicatively coupled to one or more of the devices 604 via the bridge 606 to receive and / or send data from the one or more of the devices 604.Further, an example centralized network configuration (CNC) node (e.g., a CNC device, a central node) 616 is communicatively coupled to the bridge 606 and further coupled to an example centralized user configuration (CUC) node 618. In this example, each of the devices 604, the bridge 606, and the computing device 614 are time-synchronized (e.g., example clocks associated with each of the devices 604, the bridge 606, and / or the computing device 614 are synchronized).

[0074] In the illustrated example of Fig. 6, computing device 614 may control, receive data from, and / or provide data to one or more of devices 604 using an example TSN infrastructure of TSN environment 600. For example, example image data (e.g., video stream data) from camera 610 and / or example position data from one or more of robot arms 608 and / or conveyor belt 612 may be provided to computing device 614. In some examples, expected communication metrics (e.g., expected quality of service (QoS) metrics, expected QoS levels) for the data sent from the one or more of devices 604 may vary over time. In some examples, the communication metrics include bandwidth utilization, latency, video stream resolution, video compression scheme, etc.

[0075] In some examples during the exemplary assembly process of Fig. 6, an example object positioned on conveyor belt 612 may be moved along conveyor belt 612 relative to robot arms 608. In some examples, robot arms 608 perform respective example operations (e.g., picking up and / or rotating the object, adding and / or removing a component of the object, etc.) as the object passes the respective robot arms 608. In some examples, image data (e.g., video data) from camera 610 is sent to an example edge device (e.g., an edge computing device) communicatively coupled to example computing device 614 to enable one or more of robot arms 608 to perform the respective operation(s). For example, the edge device may process the image data to perform object recognition and / or adjust positions of one or more of robot arms 608 to perform the respective operation(s).In some examples, the edge device may return the result of the image data processing to the computing device 614 for use in controlling and / or adjusting the one or more of the robot arms 608.

[0076] In some examples, devices 604 may be in different exemplary states (e.g., operating states, usage states, use cases) based on the distances between the object and the respective robot arms 608, corresponding to different expected communication metrics. For example, the first one or more of the robot arms 608 that are within a threshold distance of the object may perform one or more operations on the objects, while the second one or more of the robot arms 608 that are farther away from the object (e.g., more than the threshold distance from the object) may remain in the idle state.In such examples, the expected communication metrics for the first of the robot arms 608 that are operational may be different (e.g., lower latency, greater bandwidth utilization, higher video resolution, etc.) compared to the expected communication metrics for the second of the robot arms 608 that are idle to enable efficient use of available communication resources while maintaining precise control of the robot arms 608. For example, the edge device may require lower latency and / or utilize full resolution video data from the camera 610 to perform object detection and / or control the first of the robot arms 608, while the edge device may have more lenient latency requirements for the video data and / or the video data may be more heavily compressed if the edge device is to control the second of the robot arms 608.

[0077] In some examples, the CNC node 616 receives one or more example requests from the CUC node 618 and / or from one or more other CUC nodes in the TSN environment 600. In some examples, the CNC node allocates computing resources to one or more example nodes (e.g., the CUC node, the computing device 614, etc.) in the TSN environment 600 based on the request(s). In some examples, to adjust and / or reassign the computing resources for one or more of the nodes (e.g., as a result of a state change of the one or more nodes), one or more additional requests are sent to the CNC node 616, for example, specifying a desired bandwidth for the one or more nodes. In some examples, the CNC node 616 reallocates and / or reconfigures the computing resources based on the desired bandwidth.However, such reconfiguration and / or remapping by the CNC node 616 may result in delays (e.g., up to several tenths of a second) that may reduce the speed and / or increase the latency of communication in the TSN environment 600.

[0078] Fig. 7 illustrates an exemplary system 700 operating in the exemplary TSN environment 600 of Fig. 6 can be implemented. In the illustrated example of Fig. 7, the system 700 includes an example control node (e.g., a control device) 702 communicatively coupled to an example edge node (e.g., an edge device, an edge computing device) 704, wherein the control node 702 implements example stream mapping circuitry 706, and the edge node 704 implements example state management circuitry 708 and example motion control circuitry 710 according to teachings of this disclosure. In some examples, the control node 702 corresponds to a router and / or an in-edge server of an example TSN environment. In some examples, the control node 702 corresponds to the example computing device 614 of Fig. 6. In some examples, edge node 704 corresponds to an edge server and / or an edge server system of the TSN environment. In the illustrated example, control node 702 is communicatively coupled to one of the example robot arms 608, a first example camera 610A, a second example camera 610B, and the conveyor belt 612.

[0079] In some examples, multiple instances of the control node 702 and / or the current mapping circuitry 706 may be used such that one or more of the devices 604 in Fig. 7 implement corresponding instances of the control node 702 and / or the stream mapping circuitry 706 therein. In the illustrated example, the state management circuitry 708 and the motion control circuitry 710 are implemented in the same edge node 704. However, the state management circuitry 708 and the motion control circuitry 710 may be implemented in different nodes in some examples.

[0080] In the illustrated example of Fig. 7, the control node 702 receives data streams from one or more of the devices 604 (e.g., the robot arm 608, the camera(s) 610, and / or the conveyor belt 612) and / or controls their operation. For example, the cameras 610A, 610B may provide the control node 702 with respective example image data streams (e.g., video streams) 712A, 712B, where the image data streams 712A, 712B include example frames (e.g., video frames, camera frames) representing a scene from respective viewpoints of the cameras 610A, 610B. In the illustrated example, the robot arm 608 provides the control node 702 with an example position data stream 712C, where the position data stream 712C represents example positions of the robot arm 608. In some examples, one or more additional data streams may be received from one or more of the devices 604 of Fig. 6 in addition to or alternatively to the exemplary control node 702 of Fig. 7 are provided.

[0081] Because the control node 702 is located closer to an endpoint (e.g., the devices 604) of the TSN environment 600 (e.g., compared to the edge node 704), in some examples, the control node 702 may have fewer processing and / or computational resources compared to the edge node 704. As a result, for some computationally intensive tasks (e.g., state estimation and / or motion control for one or more of the devices 604), the control node 702 provides one or more of the data streams 712 to the edge node 704 for processing. In the illustrated example of Fig. 7, the data streams 712 are provided to the edge node 704 using one or more example proxy data streams (e.g., proxy channels), where the proxy data streams are defined between example proxy talkers implemented at the control node 702 and corresponding listeners implemented at the edge node 704. In examples disclosed herein, proxy data streams correspond to reserved communication resources of the control node 702 and / or the edge node 704, where the reserved communication resources are preconfigured to meet respective different communication metrics (e.g., QoS metrics). In some examples, the communication resources reserved for different ones of the proxy data streams enable data to be sent at different bandwidths, latencies, speeds, etc.For example, a first proxy data stream may send data at a first exemplary QoS level (e.g., a first bandwidth, a first latency, and / or a first speed), while a second proxy data stream may send the data at a second exemplary QoS level (e.g., a second bandwidth, a second latency, a second speed, etc.) that is different from the first QoS level.

[0082] In the illustrated example of Fig. 7, the example stream mapping circuitry 706 selects one or more of the proxy data streams for sending data (e.g., data stream(s) 712) from the control node 702 to the edge node 704. For example, the stream mapping circuitry 706 maps and / or assigns the data stream(s) 712 received at the control node 702 to one or more of the proxy data streams. In some examples, the stream mapping circuitry 706 selects the proxy data stream(s) based on a default map (e.g., a default configuration) stored in the stream mapping circuitry 706.In some examples, the stream mapping circuitry 706 selects and / or adjusts the mapping of the one or more data streams 712 to one or more of the proxy data streams based on example state information from the example state management circuitry 708 of the edge node 704.

[0083] For example, state management circuitry 708 determines state information for control node 702 and / or for one or more of devices 604 based on data provided to edge node 704 via one or more of the proxy data streams. In some examples, state management circuitry 708 determines example distances between an object on conveyor belt 612 and robot arm 608 based on image data from image data streams 712A, 712B obtained via a first one or more of the proxy data streams. Additionally or alternatively, state management circuitry 708 may determine the current position(s) of robot arm 608 based on position data stream 712C obtained via a second one or more of the proxy data streams. In some examples, state management circuitry 708 provides thethe determined distance(s) and / or positions as state information to the current mapping circuitry 706.

[0084] In some examples, based on the data obtained via the proxy data stream(s) and / or based on the state information determined by the state management circuitry 708, the motion control circuitry 710 determines example control information for controlling one or more of the devices 604. For example, based on the current position of the robot arm 608 and / or based on the distance between the object and the robot arm 608, the motion control circuitry 710 determines one or more target positions and / or target movements for the robot arm 608 to perform an operation (e.g., grasping the object, adding and / or removing a component from the object, etc.).In some examples, the motion control circuitry 710 provides the control information to the control node 702 for use in controlling the one or more of the devices 604, wherein the control information includes the target positions and / or the target movements.

[0085] In some examples, based on the state information from the state management circuitry 708, the stream mapping circuitry 706 determines and / or selects target communication metrics (e.g., target QoS levels) for one or more of the data streams 712. For example, if the state information indicates that the distance between the object and the robot arm 608 is less than a threshold distance and / or the robot arm 608 is to perform a grasping operation, the stream mapping circuitry 706 adjusts the target communication metric(s) for the position data stream 712C (e.g., increases a target bandwidth for the position data stream 712C, reduces a target latency for the position data stream 712C, etc.).In such examples, stream mapping circuitry 706 adjusts the mapping between data streams 712 and the proxy data streams such that image data stream 712C is reassigned to one or more of the data streams that satisfy the target communication metric(s). In some examples, stream mapping circuitry 706 evaluates and / or adjusts the mapping periodically and / or in response to receiving new state information from state management circuitry 708.

[0086] Fig. 8 illustrates example implementations of the example control node 702 and the example edge node 704 of Fig. 7. In the illustrated example of Fig. 8, the control node 702 implements the example stream mapping circuitry 706 that receives an example data stream 712 (e.g., one or more of the image data streams 712A, 712B, and / or the position data stream 712C) from an example data generation application 802 that is connected to one or more of the devices 604 of Fig. 6 and / or 7. In the illustrated example of Fig. 8, the control node 702 implements a plurality of example proxy talkers 808 (e.g., including a first example proxy talker 808A, a second example proxy talker 808B, and a third example proxy talker 808C) communicatively coupled to respective example listeners 810 (e.g., a first example listener 810A, a second example listener 810B, and a third example listener 810C) implemented at the edge node 704. In this example, example proxy data streams (e.g., proxy data channels) 812 are defined between respective pairs of the proxy talkers 808 and the corresponding listeners 810.

[0087] In the illustrated example of Fig. 8, the proxy data streams 812 each correspond to different communication metrics (e.g., different QoS levels, respectively). For example, the first proxy data stream 812A corresponds to a first example latency (e.g., less than 1 millisecond latency), the second proxy data stream 812B corresponds to a second example latency (e.g., less than 20 milliseconds latency), and the third proxy data stream 812C corresponds to a third example latency (e.g., more than 20 milliseconds latency). While the communication metrics in this example correspond to latency (e.g., data transmission latency), additionally or alternatively, different communication metrics (e.g., related to bandwidth, speed, etc.) may be used along one or more of the proxy data streams 812.

[0088] In some examples, the proxy data streams 812 are provided by the example CNC node 616 of Fig. 6 as part of a handshake procedure (e.g., a connection handshake, an exchange of network communications) that establishes example communication connection(s) between the control node 702 and the CNC node 616. For example, the stream mapping circuitry 706 evaluates communication resources available to the control node 702 to determine possible QoS metrics (e.g., possible latencies and / or bandwidths, etc.) that may be provided and / or supported by the communication resources. In such examples, as part of the handshake with the CNC node 616, the stream mapping circuitry 706 generates an array (e.g., a list, a QoS array) of the possible QoS metrics corresponding to the communication resources and provides the array to the CNC node 616. In some examples, the CNC node 616 determines multiple (e.g.all) possible combinations and / or permutations of the QoS metrics represented in the array, and the CNC node 616 selects and / or determines the proxy data streams 812 corresponding to different combinations and / or permutations.

[0089] In some examples, the CNC node 616 provides example configuration information to the control node 702. In some examples, the configuration information specifies a number of preconfigured proxy streams 812, example indices (e.g., identifiers) corresponding to the proxy streams 812, latencies associated with one or more of the proxy streams 812, a bandwidth allocated to the one or more of the proxy streams 812, etc. In some examples, the stream mapping circuitry 706 allocates (e.g., reserves, allocates, etc.) the communication resources to one or more of the proxy streams 812, respectively, based on the configuration information.By preconfiguring and / or allocating communication resources to respective proxy data streams 812 that satisfy respective different QoS metrics, the stream mapping circuitry 706 can dynamically switch between one or more of the proxy data streams 812 to meet changing QoS requirements for data to be sent to the edge node 704. For example, the stream mapping circuitry 706 can switch between the preconfigured proxy data streams 812 without requiring reallocation of communication resources by the CNC node 616, thereby reducing the time and / or processing power used to adapt to different QoS levels.

[0090] In some examples, stream mapping circuitry 706 selects one or more of the proxy streams 812 and / or the associated proxy talkers 808 to provide data from the stream 712 to the edge node 704. For example, stream mapping circuitry 706 selects the one or more proxy streams 812 based on an expected QoS for the stream 712 and / or based on an example default mapping. In this example, based on the default mapping, stream mapping circuitry 706 selects the third proxy stream 812C (e.g., corresponding to a lowest QoS level and / or a highest latency among the proxy streams 812) to send data from the stream 712 to the edge node 704. In some examples, another one of the proxy streams 812 (e.g., the first proxy stream corresponding to the highest QoS level and / or the lowest latency among the proxy streams 812, etc.) based on the default mapping. In this example, in response to selecting the third proxy stream 812C, the stream mapping circuitry 706 utilizes communication resources allocated to the third proxy talker 808C to send the data about the third proxy stream 812C to the corresponding third listener 810C at the edge node 704. In such examples, the communication resources remaining corresponding to one or more of the proxy streams 812 (e.g., the first proxy stream 812A and / or the second proxy stream 812B) may be utilized for other network communications (e.g., other streams to be sent to the edge node 704).

[0091] In the illustrated example of Fig. 8, after being received by the third listener 810C, the data provided via the third proxy data stream 812C is provided to an exemplary processing workload 814 of the state management circuitry 708. In this example, the state management circuitry 708 generates exemplary state information 816 based on the data. In some examples, the state information 816 represents positions and / or orientations of the device(s) 604 associated with the data stream 712, distance(s) between the device(s) 604 and one or more objects, etc. For example, if the data includes one or more images captured by one or more of the cameras 610 of Fig. 7, the state management circuitry 708 performs image processing of the one or more images to detect the one or more objects that are on the conveyor belt 612 of Fig. 7 are positioned, and / or determines the distance(s) between the device(s) 604 and the object(s). In some examples, the state information 816 represents a use case (e.g., an operating state) of the device(s) 604 (e.g., whether the robot arm 608 is Fig. 7 is idle or performing a grasp operation, etc.). In some examples, state management circuitry 708 provides state information 816 to current mapping circuitry 706.

[0092] In some examples, the stream mapping circuitry 706 adjusts the mapping between the data stream 712 and the proxy data streams 812 based on the state information 816. For example, the stream mapping circuitry 706 determines a target communication metric (e.g., a target QoS level, a target bandwidth, a target latency, etc.) corresponding to the data stream 712 based on the state information 816. In this example, the stream mapping circuitry 706 may determine, based on the state information 816, that an object on the conveyor belt 612 is approaching the device(s) 604 generating the data stream 712 (e.g., a distance between the device(s) 604 and the object is decreasing and / or is less than a threshold distance). In some such examples, the stream mapping circuitry 706 determines that the target latency for the data stream 712 should decrease.As a result, the stream mapping circuitry 706 switches the mapping of the data stream 712 from the third proxy data stream 812C to one of the first proxy data stream 812A or the second proxy data stream 812B that has a reduced latency compared to the third proxy data stream 812C. In some such examples, the communication resources associated with the remaining proxy data streams 812 (e.g., the third proxy data stream 812C and the unselected one of the first proxy data stream 812A or the second proxy data stream 812B) may be used for other communication tasks and / or data streams, thereby enabling efficient use of the communication resources at the control node 702. Advantageously, the stream mapping circuitry 706 may adjust the mapping of the data stream 712 between one of the proxy data streams 812 without making a request to the CNC node 616 of . Fig. 6 to recalculate and / or reconfigure the allocation of resources at the control node 702, thereby reducing the time and / or computational power required to adjust the mapping.

[0093] Fig. 9 is a block diagram of an example implementation of the example current mapping circuitry 706 of Fig. 7 and / or 8. The current mapping circuitry 706 of Fig. 9 may be instantiated (e.g., create an instance of, bring into being for an arbitrary period of time, materialize, implement, etc.) by programmable circuitry, such as a central processing unit (CPU), that executes first instructions. Additionally or alternatively, the stream mapping circuitry 706 of Fig. 9 may be instantiated (e.g., creating an instance of, appearing for any period of time, materializing, implementing, etc.) by (i) an application-specific integrated circuit (ASIC) and / or (ii) a field-programmable gate array (FPGA) structured and / or configured in response to the execution of second instructions to perform operations corresponding to the first instructions. It is understood that some or all of the circuitry of Fig. 9 can thus be instantiated at the same or different times. Part or all of the circuitry of Fig. 9 may, for example, be instantiated in one or more threads executing concurrently on hardware and / or in series on hardware. Furthermore, in some examples, some or all of the circuitry of Fig. 9 may be implemented by microprocessor circuitry executing instructions and / or FPGA circuitry performing operations to implement one or more virtual machines and / or containers.

[0094] In the illustrated example of Fig. 9, the stream mapping circuitry 706 includes example data interface circuitry 902, example array generation circuitry 904, example state analysis circuitry 906, example mapping control circuitry 908, example compression control circuitry 910, and an example mapping database 912.

[0095] The exemplary mapping database 912 stores data used and / or obtained by the current mapping circuitry 706. The exemplary mapping database 912 of Fig. 9 is implemented by any memory, storage device, and / or storage disk for storing data, such as flash memory, magnetic media, optical media, solid-state storage, hard drive(s), USB drive(s), etc. Furthermore, the data stored in the example mapping database 912 may be in any data format, such as binary data, comma-separated data, tab-separated data, structured query language (SQL) structures, etc. While in the illustrated example, the example mapping database 912 is illustrated as a single device, the example mapping database 912 and / or any other data storage devices described herein may be implemented by any number and / or type(s) of memories.

[0096] The exemplary data interface circuitry 902 of Fig. 9 accesses and / or receives exemplary data to be used by the stream mapping circuitry 706. For example, the data interface circuitry 902 accesses one or more of the exemplary data streams 712 generated by one or more of the exemplary devices 604 of Fig. 6 and / or 7. In some examples, the data stream(s) 712 include one or more image data streams (e.g., the image data streams 712A, 712B of Fig. 7) from one or more of the cameras 610 and / or include one or more position data streams (e.g., the position data streams 712C of Fig. 7) by one or more of the robot arms 608 of Fig. 6 and / or 7. In the illustrated example of Fig. 9, the data interface circuitry 902 accesses and / or receives the exemplary state information 816 provided by the state management circuitry 708 of Fig. 7 and / or 8. In some examples, the state information 816 indicates an exemplary state of the device(s) 604 providing the data streams 712 to the data interface circuitry 902, where the state indicates position(s) of the device(s) 604 relative to an object, whether the device(s) 604 are idle and / or performing an operation, etc. In some examples, the data interface circuitry 902 provides the state information 816 to the mapping database 912 for storage therein. In some examples, the data interface circuitry 902 is instantiated by programmable circuitry that executes data interface circuit instructions and / or is configured to perform operations, such as those represented by the flowchart of Fig. 12 are shown.

[0097] The exemplary array generation circuitry 904 of Fig. 9 generates an example array (e.g., a QoS array, a list, etc.) of possible communication metrics (e.g., possible latencies and / or bandwidths) that may be provided and / or supported by the control node 702. For example, the array generation circuitry 904 determines the possible communication metrics based on communication resources available at the control node 702 and generates the array indicating the possible communication metrics. In some examples, the array generation circuitry 904 provides the array to the example CNC node 616 of Fig. 6 during a handshake with the CNC node 616. In some examples, the array generation circuitry 904 obtains and / or receives example configuration information determined by the CNC node 616 based on the array. For example, the configuration information may include a number of the preconfigured proxy streams 812, example indices (e.g., identifiers) corresponding to the proxy streams 812, latencies associated with one or more of the proxy streams 812, bandwidth allocated to the one or more of the proxy streams 812, etc. In some examples, the array generation circuitry 904 provides the configuration information to the mapping database 912 for storage therein.In some examples, array generation circuitry 904 is instantiated by programmable circuitry that executes array generation circuit instructions and / or is configured to perform operations such as those illustrated by the flowchart of FIG. Fig. 12 are shown.

[0098] The exemplary state analysis circuit arrangement 906 of Fig. 9 analyzes the state information 816 to determine one or more example target communication metrics (e.g., target bandwidth, target latency, etc.) corresponding to the data stream(s) 712 accessed by the stream mapping circuitry 706. In some examples, the state analysis circuitry 906 determines the target communication metric(s) based on a comparison between the state information 816 and one or more example thresholds. For example, the state analysis circuitry 906 determines that the target communication metric corresponds to a first example latency (e.g., low latency, less than 1 millisecond, less than 2 milliseconds, etc.) when the distance between the device(s) 604 and an object on the conveyor belt 612 is Fig. 6 and / or 7 is less than a first threshold distance. In some examples, the state analysis circuitry 906 determines that the target communication metric corresponds to a second example latency (e.g., greater than the first latency, less than 20 milliseconds, less than 30 milliseconds, etc.) when the distance between the device(s) 604 and the object is greater than or equal to the first threshold distance and less than a second threshold distance (e.g., greater than the first threshold distance). In some examples, the state analysis circuitry 906 determines that the target communication metric corresponds to a third example latency (e.g., greater than the first latency and the second latency, greater than 20 milliseconds, greater than 30 milliseconds, etc.) when the distance between the device(s) 604 and the object is greater than or equal to the second threshold distance.

[0099] In some examples, one or more different thresholds (e.g., related to positions of device(s) 604, time of day, etc.) may be used to determine the target communication metric(s) for data stream(s) 712. In this example, the target communication metric(s) correspond to latency. In some examples, one or more different communication metrics may be used instead (e.g., corresponding to bandwidth utilization, speed, etc.). In some examples, state analysis circuitry 906 provides the target communication metric(s) to mapping control circuitry 908 and / or mapping database 912 for storage therein.In some examples, state analysis circuitry 906 is instantiated by programmable circuitry that executes state analysis circuit instructions and / or is configured to perform operations such as those illustrated by the flowchart of FIG. Fig. 12 are shown.

[0100] The exemplary image control circuitry 908 of Fig. 9 maps the data stream(s) 712 to one or more of the proxy data streams 812 of Fig. 8 to enable sending data to the edge node 704 of Fig. 7. For example, mapping control circuitry 908 selects the proxy data stream(s) 812 based on the target communication metric(s) determined by state analysis circuitry 906. In some examples, mapping control circuitry 908 selects the first proxy data stream 812A in response to determining that the target communication metric corresponds to the first latency (e.g., less than 1 millisecond). In some examples, mapping control circuitry 908 selects the second proxy data stream 812B in response to determining that the target communication metric corresponds to the second latency (e.g., at least 1 millisecond and less than 20 milliseconds). In some examples, the mapping control circuitry 908 selects the third proxy data stream 812C in response to determining that the target communication metric corresponds to the third latency (e.g., greater than 20 milliseconds).In some examples, the mapping control circuitry 908 maps the data stream(s) 712 to the selected one of the proxy data streams 812 to cause transmission of data from the control node 702 to the edge node 704 via the selected one of the proxy data streams 812.

[0101] In some examples, the data stream 712 is mapped to the selected one of the proxy data streams 812 for a predetermined duration and / or until one or more new target communication metrics are determined by the state analysis circuitry 906. For example, the state analysis circuitry 906 may periodically re-evaluate the incoming state information 816 to determine the new target communication metric(s), and the mapping control circuitry 908 may adjust the mapping based on the new target communication metric(s). In some examples, the mapping control circuitry 908 generates and / or updates exemplary mapping information stored in the mapping database 912, wherein the mapping information indicates the mapping between the data stream 712 and the selected one of the proxy data streams 812 and / or the duration associated with the mapping.In some examples, the mapping control circuitry 908 is instantiated by programmable circuitry that executes mapping control circuitry instructions and / or is configured to perform operations such as those illustrated by the flowchart of FIG. Fig. 12 are shown.

[0102] The exemplary compression control circuitry 910 of Fig. 9 selects an exemplary compression scheme (e.g., a video compression scheme, a video compression level) for the data stream(s) 712 accessed and / or obtained by the stream mapping circuitry 706. For example, based on the available bandwidth associated with the selected proxy data stream(s) 812, the compression control circuitry 910 may select the compression scheme to adjust a volume of data transmitted from the data stream(s) 712 to the edge node 704. In some examples, the compression control circuitry 910 may select the compression scheme from a plurality of preset compression schemes, wherein each of the preset compression schemes is stored in association with corresponding identifiers (e.g., compression indices) stored in the mapping database 912.

[0103] In some examples, compression control circuitry 910 selects the compression scheme based on the bandwidth available for the selected proxy stream(s) 812 and / or based on state information 816. For example, compression control circuitry 910 may determine that full resolution video included in stream(s) 712 should be provided to edge node 704 when device(s) 406 are a first distance (e.g., less than the first threshold distance) away from the object on conveyor belt 612. Conversely, if the device(s) 406 are located a second distance (e.g., greater than the first threshold distance) away from the object, the compression control circuitry 910 may determine that the video should be compressed before sending the video over the selected proxy stream(s) 812.In some examples, compression control circuitry 910 provides the compression index corresponding to the selected compression scheme to the device(s) 604 generating data stream 712. In some examples, compression control circuitry 910 is instantiated by programmable circuitry that executes compression control circuit instructions and / or is configured to perform operations such as those illustrated by the flowchart of FIG. Fig. 12.

[0104] Fig. 10 is an example table 1000 representing example compression schemes (e.g., video compression schemes) implemented by the stream mapping circuitry 706 of Fig. 9. In the illustrated example of Fig. 10, table 1000 includes a second example column 1004 including the example compression schemes, a first example column 1002 including example compression indices (e.g., compression identifiers) corresponding to the compression schemes, and a third example column 1006 including example descriptions corresponding to the compression schemes. In this example, for a first example compression scheme (e.g., a regular compression scheme), video from the data stream(s) 712 is encoded into a regular H.264 stream. For a second example compression scheme (e.g., an edge emphasis compression scheme), video frames of the video are preprocessed to extract contract edges, and remaining details are removed from the video frames before the video frames are encoded into the H.264 stream. For a third example compression scheme (e.g.Color depth maps of the video frames are encoded into the H.264 stream using a depth-of-field compression scheme (DVS). In some examples, one or more different compression schemes may be used in addition to or instead of one or more of the compression schemes shown in the example table 1000 of FIG. Fig. 10 are included.

[0105] Fig. 11 illustrates an exemplary process flow 1100 for implementing an exemplary power allocation procedure according to teachings of this disclosure. In the illustrated example of Fig. 11, process flow 1100 begins when the example power mapping circuitry 706 creates and / or provides an example array (e.g., a QoS array) to the example CNC node 616. In some examples, the array includes possible QoS metrics and / or communication resources used by the example control node 702 of Fig. 7 and / or 8 may be supported. In this example, the CNC node 616 generates example configuration information (block 1102) based on the array, where the configuration information includes a number of the preconfigured proxy streams 812, example indices (e.g., identifiers) corresponding to the proxy streams 812, latencies associated with one or more of the proxy streams 812, bandwidth allocated to the one or more of the proxy streams 812, etc. In this example, the CNC node 616 provides the configuration information to the stream mapping circuitry 706 for use in allocating and / or preconfiguring the communication resources at the control node 702 for corresponding ones of the proxy streams 812.

[0106] In some examples, stream mapping circuitry 706 transitions to a first example mapping (block 1104) in which stream mapping circuitry 706 associates data stream(s) 712 (e.g., from robot arm 608 and / or camera 610) with one or more corresponding first ones of proxy data streams 812. If the first mapping is operational (block 1106), the data stream(s) 712 are provided via the first one of proxy data streams 812 to example state management circuitry 708 and / or example motion control circuitry 710. For example, one of a plurality of example camera frames is provided from camera 610 to stream mapping circuitry 706 along with an example compression index corresponding to a first example compression scheme applied to the camera frame(s).In this example, the one or more camera frames are further provided to state management circuitry 708 and motion control circuitry 710 via the one or more first proxy data streams 812. In this example, exemplary position data from robot arm 608 is provided to stream mapping circuitry 706, and the position data is further provided to motion control circuitry 710 via the first proxy data stream(s) 812. In some examples, state management circuitry 708 determines exemplary state information based on the camera frame(s) provided to state management circuitry 708 and / or based on the position data provided to motion control circuitry 710.The state information may, for example, indicate positions and / or orientations of the robot arm 608, distance(s) between the robot arm 608 and one or more objects, whether the robot arm 608 is at rest or performing one or more operations, etc.

[0107] In this example, stream mapping circuitry 706 selects a second exemplary map based on the state information (block 1108). For example, if the state information indicates that the distance between robot arm 608 and one or more objects is less than a threshold and / or robot arm 608 is configured to perform one or more operations, stream mapping circuitry 706 determines that data streams 712 from robot arm 608 and / or camera 610 should be transmitted with a reduced latency (e.g., compared to a first latency associated with the first one or more of proxy data streams 812). In such examples, the stream mapping circuitry 706 selects the second mapping in which the data stream(s) 712 are mapped to the second of the proxy data streams 812 corresponding to a second latency (e.g., less than the first latency).Additionally or alternatively, the stream mapping circuitry 706 selects and / or adapts a compression scheme for compressing the camera frame(s) from the camera 610 based on the state information and / or based on a bandwidth available for the second of the proxy data streams 812. In this example, the CNC node 616 notifies other nodes in a system (e.g., in the example TSN environment 600 of FIG. Fig. 6) the selected second image (block 1110).

[0108] In the illustrated example of Fig. 11, stream mapping circuitry 706 switches to the selected second mapping (block 1112). For example, stream mapping circuitry 706 reassigns data stream(s) 712 to the second of the proxy data streams 812 corresponding to the second latency, such that data from data stream(s) 712 is provided to state management circuitry 708 and / or motion control circuitry 710 via the second of the proxy data streams 812. Further, in this example, the stream mapping circuitry 706 indicates the selected compression scheme to the camera 610, including a corresponding exemplary compression index and / or one or more exemplary parameters (e.g., the exemplary description(s) from the third column 1006) associated with the selected compression scheme.In this example, the second map remains in operation for a preset duration (block 1114) and / or until the stream mapping circuitry 706 receives new state information indicating a change in the target latency for the data stream(s) 712.

[0109] Fig. 12 is a flowchart representing example machine-readable instructions and / or example operations 1200 that may be executed, instantiated, and / or performed by programmable circuitry to implement the example current mapping circuitry 706 of Fig. 9. The exemplary machine-readable instructions and / or the exemplary operations 1200 of Fig. 12 begins at block 1202, where the example stream mapping circuitry 706 identifies example communication metrics (e.g., QoS parameters) available to the example control node 702 of Fig. 7 and / or 8. For example, the exemplary array generation circuitry 904 of Fig. 9 available communication resources available to the control node 702 to determine the communication metrics (e.g., latencies, bandwidths, speed, etc.) that can be provided and / or supported by the control node 702. In some examples, the array generation circuitry 904 generates an example array (e.g., a list, a report) of the available communication metrics and provides the array to the example CNC node 616 of Fig. 6 ready.

[0110] At block 1204, the example stream mapping circuitry 706 determines and / or identifies a plurality of example proxy data streams 812 based on the available communication metrics. For example, the array generation circuitry 904 determines the proxy data streams 812 based on example configuration information generated by the CNC node 616 based on the array of available communication metrics. For example, the array generation circuitry 904 accesses and / or receives the configuration information from the CNC node 616, where the configuration information indicates a number of the preconfigured proxy streams 812, example indices (e.g., identifiers) corresponding to the proxy streams 812, latencies associated with one or more of the proxy streams 812, bandwidth allocated to the one or more of the proxy streams 812, etc.

[0111] At block 1206, the example stream mapping circuitry 706 selects a first example mapping (e.g., a first configuration) of one or more data streams 712 to one or more of the proxy data streams 812. For example, the example mapping control circuitry 908 of Fig. 9, selects the first mapping in which the data stream(s) 712 are to be mapped (e.g., assigned, associated) to the first of the proxy data streams 812. In some examples, the first mapping corresponds to a standard mapping stored in the example mapping database 912 of Fig. 9 is stored.

[0112] At block 1208, the example stream mapping circuitry 706 receives the data stream(s) 712 associated with a first example edge device (e.g., the example control node 702 of Fig. 7 and / or 8) of one or more of the exemplary devices 604 of Fig. 6 and / or 7. For example, the exemplary data interface circuitry 902 receives the data stream(s) 712 from one or more of the robot arm(s) 608 and / or the camera(s) 610 of Fig. 6 and / or 7. In some examples, the data stream(s) 712 include an image data stream(s) from the camera(s) 610 and / or position data stream(s) from the robot arm(s) 608.

[0113] At block 1210, the example stream mapping circuitry 706 causes the data stream(s) 712 to be transmitted to a second example edge device (e.g., the edge node 704 of Fig. 7 and / or 8) based on the selected mapping. For example, mapping control circuitry 908 causes data from data stream(s) 712 to be transmitted to edge node 704 via the first of the proxy data streams 812. In this example, the first of the proxy data corresponds to one or more first communication metrics (e.g., a first latency, a first bandwidth, a first speed, etc.).

[0114] At block 1212, the example stream mapping circuitry 706 obtains and / or accesses example state information 816 based on the data stream(s) 712. For example, the example state analysis circuitry 906 accesses the state information 816 generated by the example state management circuitry 708 implemented at the edge node 704. In some examples, the state information 816 represents positions and / or orientations of the device(s) 604 associated with the data stream(s) 712, distance(s) between the device(s) 604 and one or more objects, whether the device(s) 604 are idle and / or performing one or more operations, etc.

[0115] At block 1214, the example stream mapping circuitry 706 selects a target communication metric based on the state information 816. For example, the state analysis circuitry 906 selects a target latency, a target bandwidth, a target speed, etc., for the data stream(s) 712 based on the state information 816. In some examples, the state analysis circuitry 906 determines the target communication metric by evaluating the state information 816 based on one or more example thresholds. For example, the state analysis circuitry 906 selects a first target communication metric when the distance between the device(s) 604 and an object meets (e.g., is less than) an example distance threshold, and the state analysis circuitry 906 selects a second target communication metric (e.g.,from the first target communication metric) if the distance does not meet (e.g., is greater than or equal to) the distance threshold. In some examples, one or more different thresholds (e.g., related to the position(s) of the device(s) 604, related to the time of day, etc.) may be used instead.

[0116] At block 1216, the example stream mapping circuitry 706 determines whether to change the selected mapping. For example, the mapping control circuitry 908 determines that a new mapping should be selected if the target communication metric differs from (e.g., by a threshold amount) a communication metric associated with the selected mapping. In response to the mapping control circuitry 908 determining not to change the mapping (e.g., block 1216 returns a NO result), control returns to block 1208. Alternatively, in response to the mapping control circuitry 908 determining that a new mapping should be selected (e.g., block 1216 returns a YES result), control transfers to block 1218.

[0117] At block 1218, the example stream mapping circuitry 706 selects a second example mapping for the data stream(s) 712 to the proxy data streams 812 based on the target communication metric. For example, the mapping control circuitry 908 selects the second example mapping in which the data stream(s) 712 are mapped to the second one of the proxy data streams 812 that satisfy the target communication metric. In some examples, the mapping control circuitry 908 causes the data stream(s) 712 to be transmitted to the edge node 704 via the second one of the proxy data streams 812.

[0118] At block 1220, the example stream mapping circuitry 706 selects an example compression scheme (e.g., a compression level) for the data stream(s) 712. For example, the compression control circuitry 910 selects the compression scheme based on the bandwidth available for the selected proxy data stream(s) 812 and / or based on the state information 816.

[0119] At block 1222, the example stream mapping circuitry 706 determines whether to continue monitoring. For example, the data interface circuitry 902 determines to continue monitoring while data is streaming to the control node 702. In some examples, in response to the data interface circuitry 902 determining to continue monitoring (e.g., block 1222 returns a YES result), control returns to block 1208. Alternatively, control ends in response to the data interface circuitry 902 determining not to continue monitoring (e.g., block 1222 returns a NO result).

[0120] Fig. 13 illustrates an example system 1300 for managing data ingestion, where the system 1300 includes an example platform (e.g., a server platform, a computing platform, a processor platform) 1302 and an example network interface card (NIC) 1304 implementing example utility evaluation circuitry 1306 according to teachings of this disclosure. In some examples, the platform 1302 is implemented on one or more example devices (e.g., edge devices, computing devices, etc.) in an example network (e.g., a network environment), and the platform 1302 is configured to obtain, access, and / or receive data (e.g., data packets, network packets) sent over the network. In this example, the platform 1302 includes example memory 1308, example software stacks 1310, example cores (e.g.,CPU cores) 1312 and one or more example threads 1314 executed by one or more corresponding ones of the cores 1312. In this example, the NIC 1304 implements exemplary application device queue (ADQ) circuitry 1316. While the utility evaluation circuitry 1316 and the ADQ circuitry 1316 are implemented by the NIC 1304 in this example, the utility evaluation circuitry 1316 and / or the ADQ circuitry 1316 may be implemented by other network processing hardware (e.g., an infrastructure processing unit (IPU), an Ethernet controller (EC), a data processing unit (DPU), an intelligent NIC, an edge processing unit (EPU), a system-on-a-chip (SOC), a multi-chip module, a LAN on the motherboard (LOM), etc.).Furthermore, although ADQ circuitry is used in these examples, one or more different queue-based types of network technologies may be used additionally or alternatively.

[0121] In the illustrated example of Fig. 13, the platform 1302 stores and / or processes data received at the platform 1302 via the NIC 1304. In this example, the software stacks 1310 correspond to software components that enable different applications to execute on the platform 1302. For example, the software components may include one or more databases, one or more programming languages, one or more operating systems, etc. In some examples, the first software stack 1310A may correspond to a first application (e.g., an image processing application), and the second software stack 1310B may correspond to a second application (e.g., a sensor data processing application) that is different from the first application. In some examples, the software stacks 1310 may forward data to one or more corresponding threads 1314 to be executed by one or more corresponding ones of the cores 1312.In this example, the platform 1302 includes two of the software stacks 1310. In some examples, a different number of the software stacks 1310 may be used instead.

[0122] In the illustrated example of Fig. 13, the NIC 1304 accesses, obtains, and / or receives data sent over the network. In some examples, the NIC 1304 forwards the data to the platform 1302 for processing and / or storage. For example, data to be processed by the core(s) 1312 and / or processed data output by the core(s) 1312 may be stored (e.g., temporarily and / or permanently) in the memory 1308. In some examples, the NIC 1304 receives data from a large number (e.g., thousands, tens of thousands, etc.) of devices at a given time, and an amount of data received at the NIC 1304 may exceed a threshold amount of data that can be stored in the memory 1308 of the platform 1302. As such, in the illustrated example of Fig. 13, utility evaluation circuitry 1306 is implemented on NIC 1304 to identify data that may be discarded (e.g., instead of being forwarded to platform 1302). In some examples, utility evaluation circuitry 1306 reduces the amount of data to be forwarded to and / or ingested by platform 1302, thereby reducing the use of memory and / or computational resources on platform 1302.

[0123] In this example, utility evaluation circuitry 1306 evaluates whether one or more data packets received at NIC 1304 should be discarded or forwarded to platform 1302 based on the execution of one or more utility functions (e.g., processing functions, entropy functions, etc.) registered at utility evaluation circuitry 1306. For example, utility evaluation circuitry 1306 executes the utility function(s) based on a payload of the data packet(s) received at NIC 1304 and / or based on historical information associated with data ingested at the platform. As a result of the execution, utility evaluation circuitry 1306 determines an exemplary utility value (e.g., an entropy value, an entropy score) associated with the received data packet(s).In some examples, the utility value represents a set of new and / or useful (e.g., non-redundant) information included in the data packet(s). In some examples, utility evaluation circuitry 1306 forwards the first one or more of the data packets to platform 1302 if the corresponding utility value(s) meet one or more thresholds, and utility evaluation circuitry 1306 discards (e.g., does not forward) second one or more of the data packets if the corresponding utility value(s) do not meet the one or more thresholds. In some examples, utility evaluation circuitry 1316 may also map the utility function(s) to corresponding queues (e.g., ADQs) implemented by ADQ circuitry 1316.

[0124] Fig. 14 is a block diagram of an example implementation of the example utility evaluation circuitry 1306 of Fig. 13. The utility evaluation circuitry 1306 of Fig. 14 may be instantiated (e.g., by creating an instance of, appearing for an arbitrary period of time, materializing, implementing, etc.) by programmable circuitry, such as a central processing unit (CPU), that executes first instructions. Additionally or alternatively, the utility evaluation circuitry 1306 of Fig. 14 may be instantiated (e.g., by creating an instance of, appearing for any period of time, materializing, implementing, etc.) by (i) an application-specific integrated circuit (ASIC) and / or (ii) a field-programmable gate array (FPGA) structured and / or configured in response to the execution of second instructions to perform operations corresponding to the first instructions. It is understood that some or all of the circuitry of Fig. 14 can thus be instantiated at the same or different times. Part or all of the circuitry of Fig. 14 may, for example, be instantiated in one or more threads executing concurrently on hardware and / or in series on hardware. Furthermore, in some examples, some or all of the circuitry of Fig. 14 may be implemented by microprocessor circuitry executing instructions and / or FPGA circuitry performing operations to implement one or more virtual machines and / or containers.

[0125] In the illustrated example of Fig. 14, utility evaluation circuitry 1306 includes example input circuitry 1402, example registration circuitry 1404, example doorbell execution circuitry 1406, example ADQ mapping circuitry 1408, example traffic interception circuitry 1410, example historical processing circuitry 1412, example output circuitry 1414, example function execution circuitry 1416, an example function database 1418, and an example historical database 1420.

[0126] The exemplary input circuitry 1402 of Fig. 14 receives, accesses, and / or receives data from one or more exemplary platforms 1401. For example, one or more of the platforms 1401 may be Fig. 14 may be associated with different devices (e.g., temperature sensor(s), carbon monoxide sensor(s), camera(s), etc.) in a network, and the input circuitry 1402 receives the data (e.g., temperature data, image data, other sensor data, etc.) output by one or more of the devices. In some examples, the data may be provided to the input circuitry 1402 as one or more data packets (e.g., network packet(s)). Additionally or alternatively, the data may be provided to the input circuitry 1402 as one or more data streams. In some examples, the input circuitry 1402 is instantiated by programmable circuitry that executes input circuitry instructions and / or is configured to perform operations such as those illustrated by the flowchart(s) of Fig. 16 are shown.

[0127] The exemplary registration circuitry 1404 of Fig. 14 allows one or more of the software stacks 1310 of Fig. 13, to register one or more new utility functions with the NIC 1304. For example, the registration circuitry 1404 may register the new utility function(s) in response to a request from the software stack(s) 1310. In some examples, the request includes registration information associated with the software stack(s) 1310 and / or the utility function(s) to be registered. For example, the registration information may include a process address identifier (PASID) corresponding to the software stack(s) 1310, a queue identifier corresponding to one or more of the ADQs to which the utility function and / or the PASID is mapped, the utility function (and / or a location of the utility function) to be registered, a function identifier (e.g., a universally unique identifier) ​​corresponding to the utility function, and / or a threshold (e.g.,a utility threshold) associated with the utility function. In some examples, the function identifier is generated by registration circuitry 1404 and / or provided to registration circuitry 1404 from software stack(s) 1310.

[0128] In some examples, the utility function includes at least one of a pseudo-algorithm, a binary function, or an accelerated function (e.g., a function implemented in the FPGA logic). In some examples, the utility function includes a data shaping function. For example, the utility function may include one or more filters and / or implement one or more sampling techniques (e.g., simple random probability sampling, layered random probability sampling, etc.) applied to data received at the input circuitry 1402. In some examples, the utility function, when executed, outputs an exemplary utility value (e.g., a utility score, an entropy score) associated with a payload of a data packet, where the utility value may be used to determine whether the data packet should be discarded or passed to the platform 1302 of Fig. 13. Is forwarded. Additionally or alternatively, the utility function may output characterization data associated with the data packet as a result of execution, where the characterization data may specify data types that are and / or are not included in the data packet.

[0129] In some examples, the registration circuitry 1404 creates and / or updates an example registration table (e.g., a function registration table) 1422 based on the registration information, which is stored in the example function database 1418 of Fig. 14. The example functional database 1418 is implemented by any memory, storage device, and / or storage disk for storing data, such as, for example, flash memory, magnetic media, optical media, solid-state storage, hard drive(s), USB drive(s), etc. Furthermore, the data stored in the example functional database 1418 may be in any data format, such as binary data, comma-separated data, tab-separated data, structured query language (SQL) structures, etc. While in the illustrated example, the example functional database 1418 is illustrated as a single device, the example functional database 1418 and / or any other data storage devices described herein may be implemented by any number and / or type(s) of memories.

[0130] In the illustrated example of Fig. 14, the registration table 1422 includes information corresponding to one or more of the utility functions registered with the utility evaluation circuitry 1306. Example rows (e.g., entries) of the registration table 1422, for example, each correspond to a different one of the registered utility functions. In particular, the registration table 1422 includes a second example column 1426 representing the registered utility functions (e.g., including locations and / or function identifiers corresponding to the registered utility functions). The first example column 1424 of the registration table 1422 includes the example PASIDs corresponding to the software stack(s) 1310 to which the respective utility functions are mapped, and the third example column 1428 of the registration table 1422 includes example thresholds corresponding to the utility functions.In this example, the registration table 1422 includes a fourth example column 1430 that includes example quality of service (QoS) parameters associated with the corresponding utility functions in the second column 1426. In some examples, the QoS parameters correspond to data rates (e.g., minimum and / or maximum data rates), latency rates, priority rates, etc., for one or more of the utility functions. While the registration table 1422 includes four of the columns 1424, 1426, 1428, 1430 in the example of FIG. Fig. 14, the registration table 1422 may instead include one or more different columns (e.g., corresponding to the queue identifier(s), etc.).

[0131] In some examples, registration circuitry 1404 may add, delete, and / or modify one or more entries of registration table 1422. For example, registration circuitry 1404 may add one or more entries in response to receiving a request from one or more of software stacks 1310 to register one or more new utility functions. In some examples, registration circuitry 1404 may modify and / or reset one or more of the function identifiers, utility functions, thresholds, and / or QoS parameters included in registration table 1422. In some examples, registration table 1422 may be updated based on request(s) from platform 1302. Fig. 13 and / or modified based on user input(s). In some examples, registration circuitry 1404 is instantiated by programmable circuitry that executes registration circuit instructions and / or is configured to perform operations such as those illustrated by the flowchart(s) of Fig. 15 are shown.

[0132] The exemplary traffic interception circuitry 1410 intercepts network traffic from one or more of the platforms 1401 of Fig. 14 to the NIC 1304 of Fig. 13. For example, the traffic interception circuitry 1410 performs inline processing of data packets received from the NIC 1304, and the traffic interception circuitry 1410 presents one or more of the data packets to the function execution circuitry 1416 of Fig. 14 for further processing and / or analysis. In some examples, traffic interception circuitry 1410 intercepts one or more of the data packets for which a corresponding utility function is stored in function database 1418. In some examples, traffic interception circuitry 1410 intercepts a portion (e.g., all) of the data packets received at NIC 1304. In some examples, traffic interception circuitry 1410 selects the portion of the data packets to intercept based on a time of day, a source of the data packets, etc. In some examples, traffic interception circuitry 1410 intercepts one or more of the data packets periodically (e.g., at a preset frequency) and / or after a threshold number of data packets are received at NIC 1304.In some examples, traffic interception circuitry 1410 intercepts one or more of the data packets based on one or more sampling techniques implemented for one or more of the platforms 1401. In some examples, traffic interception circuitry 1410 is instantiated by programmable circuitry that executes traffic interception circuit instructions and / or is configured to perform operations such as those illustrated by the flowchart(s) of FIG. Fig. 16 are shown.

[0133] The exemplary function execution circuitry 1416 of Fig. 14 selects and / or identifies one or more utility functions to determine whether to discard or forward an intercepted data packet from an example data stream. For example, function execution circuitry 1416 accesses a payload of the data packet and, based on the payload, identifies one or more of the utility functions associated with the data packet. For example, the payload may include at least one of a PASID corresponding to one of the software stack(s) 1310, a function identifier corresponding to the one or more of the utility functions, a queue identifier associated with one of the ADQs to which the data packet is mapped, etc. In some examples, function execution circuitry 1416 accesses and / or obtains the identified utility function(s) from the function database 1418.

[0134] In some examples, the function execution circuitry 1416 accesses and / or obtains historical information corresponding to the data packet and / or the associated data stream. For example, the function execution circuitry 1416 accesses the historical information stored in the historical database 1420 of Fig. 14. The example historical database 1420 is implemented by any memory, storage device, and / or storage disk for storing data, such as, for example, flash memory, magnetic media, optical media, solid-state storage, hard drive(s), USB drive(s), etc. Furthermore, the data stored in the example historical database 1420 may be in any data format, such as binary data, comma-separated data, tab-separated data, structured query language (SQL) structures, etc. While in the illustrated example, the example historical database 1420 is illustrated as a single device, the example historical database 1420 and / or any other data storage devices described herein may be implemented by any number and / or type(s) of memories.

[0135] In some examples, the historical information includes results from a previous execution of the one or more utility functions. For example, the historical information may include example characteristics associated with one or more previous data packets previously evaluated by function execution circuitry 1416 based on the one or more utility functions, and / or may include indications of whether the previous data packets were discarded or forwarded. In some examples, the characteristic(s) may include first data types included in payloads of the previous data packets, second data types not included in the payloads of the previous data packets, data values ​​(e.g., for one or more corresponding ones of the data types) included in the payloads of the previous data packets, etc.

[0136] In the illustrated example of Fig. 14, to determine whether an intercepted data packet should be forwarded or discarded, function execution circuitry 1416 executes the selected utility function(s) based on a payload of the data packet and / or based on the historical information associated with one or more data streams received at NIC 1304. For example, function execution circuitry 1416 provides the payload of the data packet and / or the historical information as input(s) to the utility function(s), and as a result of execution, the utility function(s) output example utility value(s) corresponding to the data packet, example characterization data corresponding to the data packet, and / or an indication of whether the data packet should be forwarded or discarded.In some examples, function execution circuitry 1416 determines whether to forward or discard the data packet based on the indication output by the utility function(s). Additionally or alternatively, function execution circuitry 1416 determines whether to forward or discard the data packet based on a comparison of the utility value(s) to one or more example utility thresholds.

[0137] In some examples, the utility value(s) are based on an amount of variability and / or difference(s) between the payload of the data packet and the historical information from the data stream associated with the data packet. For example, if the data stream originates from a sensor (e.g., a temperature sensor, a carbon monoxide sensor, a video camera, etc.) operating in an environment, data from the data stream will have relatively low utility (e.g., low entropy, redundant information, etc.) if the data behaves relatively unchanged (e.g., there is little or no variation in the data over time). Conversely, the data from the data stream may have relatively high utility (e.g., high entropy) if the data is anomalous and / or if the data varies significantly over time (e.g., more than a threshold).In some examples, the utility value for the data packet is equal to the difference between the payload of the current data packet and the payload(s) of one or more previous data packets associated with the data stream.

[0138] Additionally or alternatively, the utility value(s) are based on an amount of variability and / or difference(s) between the data stream associated with the current data packet and one or more additional data streams received at the NIC 1304. For example, the data streams may originate from different sensors (e.g., temperature sensors, carbon monoxide sensors, video cameras, etc.) positioned at different locations in a physical environment, and one or more of the sensors may collect data corresponding to respective regions (e.g., geographic regions) of the physical environment. In some such examples, if any of the geographic regions overlap, corresponding ones of the data streams may contain redundant and / or repetitive information.In some such examples, the utility value for the current data stream corresponds to a set of non-repeating and / or unique information represented in the data packet (and, for example, not contained in the other data streams).

[0139] In some examples, if the utility value of the current data packet does not meet (e.g., is less than) the one or more utility value thresholds, the function execution circuitry 1416 determines that the current data packet does not include a threshold amount of new and / or useful information, and thus determines that the current data packet should be discarded. Conversely, if the utility value of the current data packet meets (e.g., is greater than) the utility threshold(s), the function execution circuitry 1416 determines that the current data packet includes a threshold amount of new and / or useful information, and thus determines that the current data packet should be passed to the software stack(s) 1310 of Fig. 13 should be forwarded.

[0140] In some examples, function execution circuitry 1416 may determine whether to discard or forward the data packet based on one or more preset and / or user-defined rules for one or more of the respective data streams. For example, as a result of executing the utility function(s), function execution circuitry 1416 may filter data from the data stream based on one or more example characteristics (e.g., based on time of day, temperature, carbon monoxide level, data pattern type, etc.) as defined by the example rule(s). In some examples, function execution circuitry 1416 identifies the filtered data (e.g., one or more of the data packets that satisfy the rule(s)) to be passed to the software stack(s) 1310 of Fig. 13. In some examples, in response to determining that one or more of the data packets should be discarded, the function execution circuitry 1416 marks the one or more of the data packets to be discarded. For example, the function execution circuitry 1416 may mark the one or more of the data packets by including an indication in the data packet(s) (e.g., in the payload(s) of the data packet(s)) to indicate that the data packet(s) should be discarded. In some examples, the function execution circuitry 1416 is instantiated by programmable circuitry that executes function execution circuitry instructions and / or is configured to perform operations such as those represented by the flowchart(s) of Fig. 16 are shown.

[0141] In the illustrated example of Fig. 14, the historical processing circuitry 1412 accesses and / or updates the historical information stored in the historical database 1420 of Fig. 14. For example, the historical processing circuitry 1412 may store characterization data for the data packet(s) (e.g., data types included and / or not included in the payload(s) of the data packet(s), utility value(s) of the data packet(s), etc.) in association with corresponding indication(s) of whether the data packet(s) were forwarded or discarded. In some examples, the historical processing circuitry 1412 may store the characterization data and / or indication(s) in association with the corresponding function identifier(s) of the utility function(s) performed on the data packet(s).In some examples, the historical processing circuitry 1412 may update the historical information to indicate a first number and / or percentage of data packets that were discarded, a second number and / or percentage of data packets forwarded, a rate at which the data packets were discarded (e.g., a number of data packets discarded per duration), sampling rate(s) corresponding to the data stream(s), etc.

[0142] In some examples, historical processing circuitry 1412 generates and / or updates statistical information (e.g., statistical models, graphs, traces, etc.) based on the historical information. For example, historical processing circuitry 1412 may generate and / or update one or more example histograms for the corresponding utility function(s), where the histograms may, for example, indicate a number of data packets per data type that were discarded (or forwarded) based on the utility function(s) in a given duration. In some examples, one or more different histograms and / or other graphs may be used instead.In some examples, historical processing circuitry 1412 may delete and / or modify the historical data based on available storage in the historical database and / or based on a duration of interest. For example, historical processing circuitry 1412 may retain the historical information corresponding to the duration of interest (e.g., the previous N time units), and historical processing circuitry 1412 may delete the historical information that does not correspond to the duration of interest. In some examples, historical processing circuitry 1412 deletes a portion of the historical information when the available storage in the historical database is less than a threshold.In some examples, historical processing circuitry 1412 is instantiated by programmable circuitry that executes historical processing circuit instructions and / or is configured to perform operations such as those illustrated by the flowchart(s) of FIG. Fig. 16 are shown.

[0143] The exemplary doorbell implementation circuitry 1406 of Fig. 14 generates and / or provides an example alert (e.g., a doorbell) to the one or more software stacks 1310 in response to detecting an event. For example, the event may include function execution circuitry 1416 marking at least a threshold number and / or percentage of the data packet(s) to be discarded (or forwarded), historical processing circuitry 1412 updating the historical information at least a threshold number of times, an amount of memory used to store the historical information for one or more of the utility functions being at or above a threshold amount, etc. In some examples, the event and / or the threshold(s) associated therewith may be preset and / or user-defined and / or modified.In some examples, in response to detecting an event associated with one or more of the utility functions, the doorbell execution circuitry 1406 generates and / or provides the alert(s) to one or more of the software stacks 1310 corresponding to the one or more of the utility functions. In some examples, the alert(s) may include historical and / or statistical information associated with the one or more of the utility functions. In some examples, the doorbell execution circuitry 1406 is instantiated by programmable circuitry that executes doorbell execution circuit instructions and / or is configured to perform operations such as those represented by the flowchart(s) of FIG. Fig. 16 are shown.

[0144] The exemplary ADQ mapping circuitry 1408 maps one or more of the data packets and / or associated utility functions to one or more corresponding ones of the ADQs provided by the ADQ circuitry 1316 of Fig. 13. For example, the ADQ mapping circuitry 1408 determines the mapping based on the queue identifiers stored in association with one or more of the utility functions in the function database 1418. In some examples, the ADQ mapping circuitry 1408 is instantiated by programmable circuitry that executes ADQ mapping circuit instructions and / or is configured to perform operations such as those described by the flowchart(s) of Fig. 16 are shown.

[0145] The exemplary output circuitry 1414 of Fig. 14 illustrates exemplary forwarded data packets 1432 to the exemplary platform 1302 of Fig. 13. For example, the output circuitry 1414 identifies the forwarded data packets 1432 corresponding to a first one or more of the data packets that were not marked as discarded (and / or marked as forwarded) by the function execution circuitry 1416. In some examples, the output circuitry 1414 provides the forwarded data packets 1432 to a corresponding one or more of the software stacks 1310, where the one or more of the software stacks 1310 may be identified based on the PASIDs stored in payloads of the data packets and / or based on the registration table 1422. In some examples, the output circuitry 1414 may store historical information and / or statistical information in one or more of the forwarded data packets 1432 to be forwarded to the software stacks 1310.In this example, output circuitry 1414 discards (e.g., deletes, does not forward) one or more of the second data packets marked as discarded by function execution circuitry 1416. In some examples, output circuitry 1414 is instantiated by programmable circuitry that executes output circuitry instructions and / or is configured to perform operations such as those illustrated by the flowchart(s) of FIG. Fig. 16 are shown.

[0146] Fig. 15 is a flowchart representing exemplary machine-readable instructions and / or exemplary operations 1500 that may be executed, instantiated, and / or performed by programmable circuitry to implement the utility evaluation circuitry 1306 of Fig. 13 and / or 14 to register a new utility function. The example machine-readable instructions and / or the example operations 1500 of Fig. 15 begin at block 1502, where the example utility evaluation circuitry 1306 receives one or more example requests from one of the software stacks 1310 of Fig. 13. For example, the example registration circuitry 1404 receives and / or accesses the request(s) from the software stack 1310, where the request(s) include registration information associated with the software stack 1310 and / or the new utility function to be registered.

[0147] At block 1504, the example utility evaluation circuitry 1306 determines an example identifier (e.g., a PASID) corresponding to the software stack 1310. For example, the registration circuitry 1404 determines and / or obtains the PASID from the registration information included in the request(s).

[0148] At block 1506, the example utility evaluation circuitry 1306 determines one or more example queues corresponding to the new utility function to be registered. For example, the registration circuitry 1404 determines and / or identifies the queue (e.g., ADQ) from the registration information included in the request(s) and / or identifies the queue based on the PASID.

[0149] At block 1508, the example utility evaluation circuitry 1306 determines one or more example thresholds (e.g., utility thresholds) corresponding to the new utility function to be registered. For example, the registration circuitry 1404 determines and / or identifies the threshold(s) from the registration information included in the request(s). In some examples, the threshold(s) indicate utility thresholds at which one or more data packets should be forwarded or discarded. In some examples, the threshold(s) are preset and / or user-defined, and the threshold(s) may be modified based on additional requirements from the software stack 1310.

[0150] At block 1510, the example utility evaluation circuitry 1306 determines a location (e.g., a location in the example feature database 1418 of Fig. 14) and / or a function identifier corresponding to the new utility function to be registered. For example, registration circuitry 1404 determines and / or identifies the location and / or function identifier from the registration information included in the request(s).

[0151] At block 1512, the example utility evaluation circuitry 1306 creates and / or updates one or more example entries in the example function database 1418 of Fig. 14. For example, the registration circuitry 1404 creates and / or updates an entry of the example registration table 1422 of Fig. 14 to include the new utility function, the PASID corresponding to the software stack 1310, the function identifier and / or location corresponding to the new utility function, the queue(s) corresponding to the new utility function, and / or the threshold(s) corresponding to the new utility function.

[0152] At block 1514, the example utility evaluation circuitry 1306 determines whether there are one or more additional requests to register in the function database 1418. For example, the registration circuitry 1404 determines that there are additional functions that need to be registered in response to obtaining and / or receiving one or more additional requests from one or more of the software stacks 1310. In response to the registration circuitry 1404 determining that there are additional functions to register (e.g., block 1514 returns a YES result), control returns to block 1502. Alternatively, control ends in response to the registration circuitry 1404 determining that no additional function(s) need to be registered (e.g., block 1514 returns a NO result).

[0153] Fig. 16 is a flowchart representing exemplary machine-readable instructions and / or exemplary operations 1600 that may be executed, instantiated, and / or performed by programmable circuitry to implement the utility evaluation circuitry 1306 of Fig. 13 and / or 14 to discard and / or forward example data packets. The example machine-readable instructions and / or the example operations 1600 of Fig. 16 begin at block 1602, where the example utility evaluation circuitry 1306 accesses an example data packet. For example, the example input circuitry 1402 of Fig. 14 to the data packet that is transmitted by one of the exemplary platforms 1401 of Fig. 14. In some examples, the data packet may be associated with an example data stream output from one or more sensors (e.g., temperature sensor(s), carbon monoxide sensor(s), camera(s), etc.) associated with platform 1401.

[0154] At block 1604, the example utility evaluation circuitry 1306 analyzes an example payload of the data packet. For example, the example traffic interception circuitry 1410 of Fig. 14 the payload to determine whether the data packet includes at least one identifier (e.g., a function identifier, a PASID, a queue identifier, etc.) that corresponds to one of the functions defined in the exemplary function database 1418 of Fig. 14 stored utility functions.

[0155] At block 1606, the example utility evaluation circuitry 1306 determines whether a utility function is associated with the data packet. For example, the traffic interception circuitry 1410 determines that a utility function is associated with the data packet if the payload includes the at least one identifier corresponding to one of the utility functions. In response to the traffic interception circuitry 1410 determining that a utility function is associated with the data packet (e.g., block 1606 returns a YES result), control transfers to block 1608. Alternatively, in response to the traffic interception circuitry 1410 determining that no utility function is associated with the data packet (e.g., block 1606 returns a NO result), control transfers to block 1624.

[0156] At block 1608, the exemplary utility evaluation circuitry 1306 accesses an exemplary utility function stored in the function database 1418. For example, the exemplary function execution circuitry 1416 evaluates Fig. 14, one or more entries of the example registration table 1422 based on the at least one identifier identified in the payload of the data packet (e.g., the function identifier, the PASID, the queue identifier, etc.). In some examples, the function execution circuitry 1416 accesses the utility function from one of the entries corresponding to the at least one identifier.

[0157] At block 1610, the example utility evaluation circuitry 1306 executes the utility function based on the payload of the data packet and / or based on historical information associated with the utility function. For example, the function execution circuitry 1416 provides the payload of the data packet and / or the historical information as input(s) to the utility function(s), and as a result of execution, the utility function(s) output example utility value(s) corresponding to the data packet, example characterization data corresponding to the data packet, and / or an indication of whether the data packet should be forwarded or discarded.

[0158] At block 1612, the example utility evaluation circuitry 1306 evaluates the utility value of the data packet based on a result of the execution. For example, the function execution circuitry 1416 determines whether to forward or discard the data packet based on a comparison of the one or more utility values ​​to one or more example utility thresholds. In some examples, the one or more utility values ​​are based on one or more differences between the payload of the data packet and the historical information from the data stream associated with the data packet. In some examples, the one or more utility values ​​are based on one or more differences between the data stream associated with the data packet and one or more additional data streams.

[0159] At block 1614, the example utility evaluation circuitry 1306 determines whether the utility value meets one or more example thresholds (e.g., utility thresholds). In response to the function execution circuitry 1416 determining that the utility value meets the threshold(s) (e.g., block 1614 returns a YES result), control transfers to block 1618. Alternatively, in response to the function execution circuitry 1416 determining that the utility value does not meet the threshold(s) (e.g., block 1614 returns a NO result), control transfers to block 1616.

[0160] At block 1616, the exemplary utility evaluation circuitry 1306 marks the data packet to be discarded. For example, the function execution circuitry 1416 may mark the data packet to be discarded by including an indication in the data packet (e.g., in the payload of the data packet).

[0161] At block 1618, the example utility evaluation circuitry 1306 updates the historical information stored in the example historical database 1420 of Fig. 14. For example, the exemplary historical processing circuitry 1412 of Fig. 14 the historical information to include the characterization data corresponding to the data packet, an indication of whether the data packet should be discarded or forwarded, a number and / or percentage of data packets that were discarded (or forwarded), etc.

[0162] At block 1620, the example utility evaluation circuitry 1306 determines whether the data packet is marked as discarded. For example, the example output circuitry 1414 determines that the data packet is marked as discarded if the payload of the data packet includes an indication that the data packet should be discarded. In response to the output circuitry 1414 determining that the data packet should be discarded (e.g., block 1620 returns a YES result), control transfers to block 1622. Alternatively, in response to the output circuitry 1414 determining that the data packet should not be discarded and / or forwarded (e.g., block 1620 returns a NO result), control transfers to block 1624.

[0163] At block 1622, the exemplary utility evaluation circuitry 1306 discards the data packet. For example, the output circuitry 1414 discards and / or deletes the data packet and / or otherwise does not deliver the data packet to the corresponding software stack(s) 1310 of Fig. 13.

[0164] At block 1624, the example utility evaluation circuitry 1306 forwards the data packet. For example, the output circuitry 1414 forwards the data packet and / or sends it to the appropriate software stack(s) 1310. In some examples, the output circuitry 1414 provides the data packet to one or more example queues (e.g., ADQs) that are mapped to the utility function and / or configured by the example ADQ mapping circuitry 1408 of Fig. 14 can be identified based on the payload of the data packet.

[0165] At block 1626, the example utility evaluation circuitry 1306 determines whether a doorbell event has been detected. For example, the example doorbell execution circuitry 1406 of Fig. 14 the doorbell event, wherein the doorbell event includes at least a threshold number and / or percentage of data packets being discarded, wherein the historical information is updated at least a threshold number of times, the amount of memory used to store the historical information is at or above a threshold amount, etc. In response to the doorbell execution circuitry 1406 detecting a doorbell event (e.g., block 1626 returns a YES result), control transfers to block 1628. Alternatively, in response to the doorbell execution circuitry 1406 not detecting a doorbell event (e.g., block 1626 returns a NO result), control transfers to block 1630.

[0166] At block 1628, the example utility evaluation circuitry 1306 generates and / or provides an example doorbell (e.g., an alert) to the software stack(s) 1310. For example, the doorbell execution circuitry 1406 generates the doorbell, including historical and / or statistical information associated with one or more of the utility functions, and provides (e.g., transmits, sends) the doorbell to the software stack(s) 1310.

[0167] At block 1630, the example utility evaluation circuitry 1306 determines whether one or more additional data packets should be received at the NIC 1304. In response to the input circuitry 1402 determining that one or more additional data packets should be received (e.g., block 1630 returns a YES result), control returns to block 1602. Alternatively, control ends in response to the input circuitry 1402 determining that no more additional data packets should be received (e.g., block 1630 returns a NO result).

[0168] In some examples, the current mapping circuitry 706 includes means for connecting. For example, the means for connecting may be implemented by the data interface circuitry 902. In some examples, the data interface circuitry 902 may be instantiated by programmable circuitry, such as the example programmable circuitry 1712 of Fig. 17. For example, the data interface circuitry 902 may be implemented by the exemplary microprocessor 1900 of Fig. 19 which executes machine-executable instructions such as those specified by at least blocks 1208, 1222 of Fig. 12. In some examples, the interface circuitry 902 may be instantiated by hardware logic circuitry implemented by an ASIC, an XPU, or the FPGA circuitry 2000 of Fig. 20 that is configured and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the data interface circuitry 902 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the data interface circuitry 902 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), logic circuitry, etc.).) that are configured and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are also suitable.

[0169] In some examples, current mapping circuitry 706 includes means for generating an array. For example, the means for generating an array may be implemented by array generation circuitry 904. In some examples, array generation circuitry 904 may be instantiated by programmable circuitry, such as the exemplary programmable circuitry 1712 of Fig. 17. For example, the array generation circuitry 904 may be implemented by the exemplary microprocessor 1900 of Fig. 19 which executes machine-executable instructions such as those specified by at least blocks 1202, 1204 of Fig. 12. In some examples, the array generation circuitry 904 may be instantiated by hardware logic circuitry implemented by an ASIC, an XPU, or the FPGA circuitry 2000 of Fig. 20 that is configured and / or structured to perform operations according to the machine-readable instructions. Additionally or alternatively, the array generation circuitry 904 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the array generation circuitry 904 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), logic circuitry, etc.) that are configured and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are also suitable.

[0170] In some examples, the current mapping circuitry 706 includes means for analyzing a state. For example, the means for analyzing a state may be implemented by the state analysis circuitry 906. In some examples, the state analysis circuitry 906 may be instantiated by programmable circuitry, such as the exemplary programmable circuitry 1712 of Fig. 17. For example, the state analysis circuitry 906 may be implemented by the exemplary microprocessor 1900 of Fig. 19 which executes machine-executable instructions such as those specified by at least blocks 1212, 1214 of Fig. 12. In some examples, the state analysis circuitry 906 may be instantiated by hardware logic circuitry implemented by an ASIC, XPU, or the FPGA circuitry 2000 of Fig. 20 configured and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the state analysis circuitry 906 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the state analysis circuitry 906 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), logic circuitry, etc.) configured and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are also suitable.

[0171] In some examples, the current mapping circuitry 706 includes means for mapping. For example, the means for mapping may be implemented by the mapping control circuitry 908. In some examples, the mapping control circuitry 908 may be instantiated by programmable circuitry, such as the exemplary programmable circuitry 1712 of Fig. 17. For example, the image control circuitry 908 may be implemented by the exemplary microprocessor 1900 of Fig. 19, which executes machine-executable instructions such as those specified by at least blocks 1206, 1210, 1216, 1218 of Fig. 12. In some examples, the mapping control circuitry 908 may be instantiated by hardware logic circuitry implemented by an ASIC, XPU, or the FPGA circuitry 2000 of Fig. 20 that are configured and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the mapping control circuitry 908 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the mapping control circuitry 908 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), logic circuitry, etc.) that are configured and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are also suitable.

[0172] In some examples, the stream mapping circuitry 706 includes means for selecting a compression scheme. For example, the means for selecting a compression scheme may be implemented by the compression control circuitry 910. In some examples, the compression control circuitry 910 may be instantiated by programmable circuitry, such as the exemplary programmable circuitry 1712 of Fig. 17. For example, the compression control circuitry 910 may be implemented by the exemplary microprocessor 1900 of Fig. 19, which executes machine-executable instructions such as those specified by at least block 1220 of Fig. 12. In some examples, the compression control circuitry 910 may be instantiated by hardware logic circuitry implemented by an ASIC, XPU, or the FPGA circuitry 2000 of Fig. 20 that are configured and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the compression control circuitry 910 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the compression control circuitry 910 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), logic circuitry, etc.).) that are configured and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are also suitable.

[0173] In some examples, utility evaluation circuitry 1306 includes means for receiving. For example, the means for receiving may be implemented by input circuitry 1402. In some examples, input circuitry 1402 may be instantiated by programmable circuitry, such as the exemplary programmable circuitry 1812 of Fig. 18. For example, the input circuitry 1402 may be implemented by the exemplary microprocessor 1900 of Fig. 19, which executes machine-executable instructions such as those specified by at least blocks 1602, 1630 of Fig. 16. In some examples, the input circuitry 1402 may be instantiated by hardware logic circuitry implemented by an ASIC, an XPU, or the FPGA circuitry 2000 of Fig. 20 configured and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the input circuitry 1402 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the input circuitry 1402 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), logic circuitry, etc.) configured and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are also suitable.

[0174] In some examples, the utility evaluation circuitry 1306 includes means for registering. For example, the means for registering may be implemented by registration circuitry 1404. In some examples, registration circuitry 1404 may be instantiated by programmable circuitry, such as the exemplary programmable circuitry 1812 of Fig. 18. For example, the registration circuitry 1404 may be implemented by the exemplary microprocessor 1900 of Fig. 19, which executes machine-executable instructions such as those specified by at least blocks 1502, 1504, 1506, 1508, 1510, 1512, 1514 of Fig. 15. In some examples, the registration circuitry 1404 may be instantiated by hardware logic circuitry implemented by an ASIC, an XPU, or the FPGA circuitry 2000 of Fig. 20 configured and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the registration circuitry 1404 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the registration circuitry 1404 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), logic circuitry, etc.) configured and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are also suitable.

[0175] In some examples, utility evaluation circuitry 1306 includes means for generating a doorbell. For example, the means for generating a doorbell may be implemented by doorbell execution circuitry 1406. In some examples, doorbell execution circuitry 1406 may be instantiated by programmable circuitry, such as the exemplary programmable circuitry 1812 of Fig. 18. For example, the doorbell execution circuitry 1406 may be implemented by the exemplary microprocessor 1900 of Fig. 19, which executes machine-executable instructions such as those specified by at least blocks 1626, 1628 of Fig. 16. In some examples, the doorbell execution circuitry 1406 may be instantiated by hardware logic circuitry implemented by an ASIC, XPU, or the FPGA circuitry 2000 of Fig. 20 that is configured and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the doorbell execution circuitry 1406 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the doorbell execution circuitry 1406 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), logic circuitry, etc.).) that are configured and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are also suitable.

[0176] In some examples, utility evaluation circuitry 1306 includes means for mapping to a queue. For example, the means for mapping to a queue may be implemented by ADQ mapping circuitry 1408. In some examples, ADQ mapping circuitry 1408 may be instantiated by programmable circuitry, such as the example programmable circuitry 1812 of Fig. 18. For example, the ADQ mapping circuitry 1408 may be implemented by the exemplary microprocessor 1900 of Fig. 19, which executes machine-executable instructions such as those specified by at least block 1624 of Fig. 16. In some examples, the ADQ mapping circuitry 1408 may be instantiated by hardware logic circuitry implemented by an ASIC, XPU, or the FPGA circuitry 2000 of Fig. 20 that is configured and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the ADQ mapping circuitry 1408 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the ADQ mapping circuitry 1408 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), logic circuitry, etc.) configured and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are also suitable.

[0177] In some examples, utility evaluation circuitry 1306 includes means for interception. For example, the means for interception may be implemented by traffic interception circuitry 1410. In some examples, traffic interception circuitry 1410 may be instantiated by programmable circuitry, such as the exemplary programmable circuitry 1812 of Fig. 18. For example, the traffic intercept circuit 1410 may be implemented by the exemplary microprocessor 1900 of Fig. 19, which executes machine-executable instructions such as those represented by at least blocks 1604, 1606 of Fig. 16. In some examples, the traffic interception circuitry 1410 may be instantiated by hardware logic circuitry implemented by an ASIC, XPU, or the FPGA circuitry 2000 of Fig. 20 that is configured and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the traffic interception circuitry 1410 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the traffic interception circuitry 1410 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), logic circuitry, etc.) that are configured and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are also suitable.

[0178] In some examples, utility evaluation circuitry 1306 includes means for processing historical information. For example, the means for processing historical information may be implemented by historical processing circuitry 1412. In some examples, historical processing circuitry 1412 may be instantiated by programmable circuitry, such as the exemplary programmable circuitry 1812 of Fig. 18. For example, the historical processing circuitry 1412 may be implemented by the exemplary microprocessor 1900 of Fig. 19, which executes machine-executable instructions such as those specified by at least block 1618 of Fig. 16. In some examples, the historical processing circuitry 1412 may be instantiated by hardware logic circuitry implemented by an ASIC, XPU, or the FPGA circuitry 2000 of Fig. 20 that is configured and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the historical processing circuitry 1412 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the processing circuitry 1412 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), logic circuitry, etc.) that are configured and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are also suitable.

[0179] In some examples, utility evaluation circuitry 1306 includes means for transmitting. For example, the means for transmitting may be implemented by output circuitry 1414. In some examples, output circuitry 1414 may be instantiated by programmable circuitry, such as the exemplary programmable circuitry 1812 of Fig. 18. For example, the output circuitry 1414 may be implemented by the exemplary microprocessor 1900 of Fig. 19, which executes machine-executable instructions such as those specified by at least blocks 1620, 1622, 1624 of Fig. 16. In some examples, the output circuitry 1414 may be instantiated by hardware logic circuitry implemented by an ASIC, an XPU, or the FPGA circuitry 2000 of Fig. 20 configured and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the output circuitry 1414 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the output circuitry 1414 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), logic circuitry, etc.) configured and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are also suitable.

[0180] In some examples, utility evaluation circuitry 1306 includes means for executing. For example, the means for executing may be implemented by function execution circuitry 1416. In some examples, function execution circuitry 1416 may be instantiated by programmable circuitry, such as the exemplary programmable circuitry 1812 of Fig. 18. For example, the function execution circuitry 1416 may be implemented by the exemplary microprocessor 1900 of Fig. 19, which executes machine-executable instructions such as those specified by at least blocks 1608, 1610, 1612, 1614, 1616 of Fig. 16. In some examples, the function execution circuitry 1416 may be instantiated by hardware logic circuitry implemented by an ASIC, XPU, or the FPGA circuitry 2000 of Fig. 20 that is configured and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the function execution circuitry 1416 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the function execution circuitry 1416 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), logic circuitry, etc.) that are configured and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are also suitable.

[0181] While an exemplary manner for implementing the current mapping circuitry 706 of Fig. 7 in Fig. 9, one or more of the elements, processes and / or devices shown in Fig. 9 may be combined, split, rearranged, omitted, eliminated, and / or implemented in any other manner. Furthermore, the exemplary data interface circuitry 902, the exemplary array generation circuitry 904, the exemplary state analysis circuitry 906, the exemplary mapping control circuitry 908, the exemplary compression control circuitry 910, the exemplary mapping database 912, and / or more generally, the exemplary stream mapping circuitry 706 of Fig. 9 may be implemented by hardware alone or by hardware in combination with software and / or firmware. Thus, for example, any of the example data interface circuitry 902, the example array generation circuitry 904, the example state analysis circuitry 906, the example mapping control circuitry 908, the example compression control circuitry 910, the example mapping database 912, and / or more generally, the example stream mapping circuitry 706 could be implemented by programmable circuitry in combination with machine-readable instructions (e.g.,Firmware or software), processor circuitry, analog circuit(s), digital circuit(s), logic circuit(s), programmable processor(s), programmable microcontroller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), ASIC(s), programmable logic device(s) (PLD(s)), and / or field programmable logic device(s) (FPLD(s)) such as FPGAs. Further, the example current mapping circuitry 706 of FIG. Fig. 9 one or more elements, processes and / or devices in addition to or instead of those described in Fig. 9 and / or may include more than one or all of the illustrated elements, processes and devices.

[0182] While an exemplary manner for implementing the utility evaluation circuitry 1306 of Fig. 13 in Fig. 14, one or more of the elements, processes and / or devices shown in Fig. 14 may be combined, split, rearranged, omitted, eliminated, and / or implemented in any other manner. Furthermore, the example input circuitry 1402, the example registration circuitry 1404, the example doorbell execution circuitry 1406, the example ADQ mapping circuitry 1408, the example traffic interception circuitry 1410, the example historical processing circuitry 1412, the example output circuitry 1414, the example function execution circuitry 1416, the example function database 1418, the example historical database 1420, and / or more generally, the example utility evaluation circuitry 1306 of Fig. 14 may be implemented by hardware alone or by hardware in combination with software and / or firmware. Thus, for example, any of the example input circuitry 1402, the example registration circuitry 1404, the example doorbell execution circuitry 1406, the example ADQ mapping circuitry 1408, the example traffic interception circuitry 1410, the example history processing circuitry 1412, the example output circuitry 1414, the example function execution circuitry 1416, the example function database 1418, the example history database 1420, and / or more generally, the example utility evaluation circuitry 1306 could be implemented by programmable circuitry in combination with machine-readable instructions (e.g.,Firmware or software), processor circuitry, analog circuitry, digital circuitry, logic circuitry, programmable processor(s), programmable microcontroller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), ASIC(s), programmable logic device(s) (PLD(s)), and / or field programmable logic device(s) (FPLD(s)), such as FPGAs. Furthermore, the example utility evaluation circuitry 1306 of FIG. Fig. 14 one or more elements, processes and / or devices in addition to or instead of those described in Fig. 14 and / or may include more than one or all of the illustrated elements, processes, and devices.

[0183] Flowchart(s) representing exemplary machine-readable instructions that may be executed by programmable circuitry to implement the current mapping circuitry 706 of Fig. 9 and / or the utility evaluation circuitry 1306 of Fig. 14, and / or represent exemplary operations that may be performed by programmable circuitry to implement and / or instantiate the current mapping circuitry 706 of Fig. 9 and / or the utility evaluation circuitry 1306 of Fig. 14 to implement and / or instantiate are in Fig. 12, Fig. 15 and / or 16. The machine-readable instructions may include one or more executable programs or portions of one or more executable programs for execution by programmable circuitry, such as the programmable circuitry 1712 shown in the exemplary processor platform 1700 described below in connection with Fig. 17, and / or the programmable circuitry 1812 shown in the exemplary processor platform 1800 described below in connection with Fig. 18, and / or may be one or more functions or one or more portions of function(s) to be performed by the exemplary programmable circuitry (e.g., an FPGA) described below in connection with Fig. 19 and / or 20. In some examples, the machine-readable instructions cause an operation, task, etc., to be performed and / or performed in an automated manner in the real world. As used herein, "automated" means without human intervention.

[0184] The program may be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as cache memory, a magnetic storage device or disk (e.g., a floppy disk, a hard disk drive (HDD), etc.), an optical storage device or disk (e.g., a Blu-ray disk, a compact disk (CD), a digital versatile disk (DVD), etc.), a redundant array of independent disks (RAID), a register, a ROM, a solid-state drive (SSD), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., random access memory (RAM) of any type, etc.), and / or any other storage device or disk.The instructions of the non-transitory, computer-readable and / or machine-readable medium may be programmed and / or executed by programmable circuitry residing in one or more hardware devices, but the entire program and / or portions thereof may alternatively be executed and / or instantiated by one or more hardware devices that are not part of the programmable circuitry and / or embodied in dedicated hardware. The machine-readable instructions may be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, the client hardware device may be implemented by an endpoint client hardware device (e.g.,a hardware device associated with a human and / or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that can facilitate communication between a server and an endpoint client hardware device. Likewise, the non-transitory computer-readable storage medium can include one or more media. Further, although the example program may be described with reference to the device(s) shown in . Fig. 12, Fig. 15 and / or 16, many other methods may alternatively be used to implement the example current mapping circuitry 706 and / or the utility evaluation circuitry 1306. For example, the order of execution of the blocks of the flowchart(s) may be changed, and / or some of the described blocks may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks of the flowchart may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, an FPGA, an ASIC, a comparator, an operational amplifier (OP-amp), logic circuitry, etc.) structured to perform the corresponding operation without executing software or firmware.The programmable circuitry may be distributed across different network locations and / or located locally on one or more hardware devices (e.g., a single-core processor (e.g., a single-core CPU), a multi-core processor (e.g., a multi-core CPU, an XPU, etc.)). The programmable circuitry may, for example, be a CPU and / or an FPGA located in the same package (e.g., in the same integrated circuit (IC) package or in two or more separate packages), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, etc., and / or any one or more combinations thereof.

[0185] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a fragmented format, a compiled format, an executable format, a packaged format, etc. Machine-readable instructions as described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bit stream (e.g., a computer-readable bit stream, a machine-readable bit stream, etc.), or a data structure (e.g., as portion(s) of instructions, code, representations of code, etc.) that can be used to generate, manufacture, and / or produce machine-executable instructions. For example, the machine-readable instructions may be fragmented and stored on one or more storage devices, hard disks, and / or computing devices (e.g.,Servers) located at the same or different locations of a network or collection of networks (e.g., in the cloud, at edge devices, etc.). The machine-readable instructions may require one or more of installation, modification, adaptation, updating, combining, addition, configuration, decryption, decompression, unpacking, distribution, remapping, compilation, etc., to make them directly readable, interpretable, and / or executable by a computing device and / or another machine.For example, the machine-readable instructions may be stored in multiple pieces that are individually compressed, encrypted, and / or stored on separate computing devices, which pieces, when decrypted, decompressed, and / or combined, form a set of computer-executable and / or machine-executable instructions that implement one or more functions and / or operations that together may form a program such as that described herein.

[0186] In another example, the machine-readable instructions may be stored in a state where they can be read by processor circuitry, but may require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., to execute the machine-readable instructions on a particular computing device or other device. In another example, the machine-readable instructions may require configuration (e.g., settings saved, data entered, network addresses recorded, etc.) before the machine-readable instructions and / or the one or more corresponding programs can be executed, in whole or in part.Thus, as used herein, machine-readable, computer-readable, and / or machine-readable media may include instructions and / or programs regardless of the particular format or state of the machine-readable instructions and / or programs.

[0187] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0188] As mentioned above, the example operations of Fig. 12, Fig. 15 and / or 16 may be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable and / or machine-readable media. As used herein, the terms non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium, and / or non-transitory machine-readable storage medium are expressly defined to include any type of computer-readable storage device and / or storage disk and exclude propagating signals and exclude transmission media.Examples of such a non-transitory computer-readable medium, a non-transitory computer-readable storage medium, a non-transitory machine-readable medium, and / or non-transitory machine-readable storage medium include optical storage devices, magnetic storage devices, an HDD, flash memory, read-only memory (ROM), a CD, a DVD, a cache, RAM of any type, a register, and / or any other storage device or storage disk in which information is stored for any duration (e.g., for extended periods of time, permanently, for short instances, for temporary buffering, and / or for caching the information).As used herein, the terms "non-transitory computer-readable storage medium" and "non-transitory machine-readable storage medium" are defined to include any physical (mechanical, magnetic, and / or electrical) hardware for storing information for a period of time, but exclude the propagation of signals and transmission media. Examples of non-transitory computer-readable storage devices and / or non-transitory machine-readable storage devices include random-access memory of any kind, read-only memory of any kind, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, and / or RAID (Redundant Array of Independent Disks) systems.As used herein, the term “apparatus” refers to a physical structure such as mechanical and / or electrical equipment, hardware and / or circuitry that may or may not be configured by computer-readable instructions, machine-readable instructions, etc. and / or made to execute computer-readable instructions, machine-readable instructions, etc.

[0189] "Including" and "comprising" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim uses any form of "include" or "comprise" (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within a claim recitation of any kind, it is understood that additional elements, expressions, etc. may be present without falling outside the scope of the corresponding claim or recitation. As used herein, the term "at least," when used as a transitional expression, for example, in a claim preamble, is open-ended in the same way that the terms "comprehensive" and "including" are open-ended.The term “and / or,” when used, for example, in a form such as A, B, and / or C, refers to any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used herein in the context of describing structures, components, elements, objects, and / or things, the phrase “at least one of A and B” is intended to refer to implementations that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, elements, objects, and / or things, the phrase “at least one of A or B” is intended to refer to implementations that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.As used herein in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A and B” shall refer to implementations that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” shall refer to implementations that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0190] As used herein, references to the singular (e.g., "a," "an," "one," "first," "second," etc.) do not exclude pluralities. The term "a," "an," or "an" object, as used herein, refers to one or more of such objects. The terms "a," "one or more," and "at least one" are used interchangeably herein. Further, although listed individually, multiple means, elements, or acts may be implemented by, for example, the same entity or object. In addition, although individual features may be included in different examples or claims, they may be combined, and inclusion in different examples or claims does not imply that a combination of features is not feasible and / or advantageous.

[0191] As used herein, connection references (e.g., attached, coupled, connected, and mated) may imply intermediaries between the elements referenced by the connection reference and / or relative movement between those elements, unless otherwise noted. Thus, connection references do not necessarily imply that two elements are directly connected and / or in a fixed relationship. As used herein, stating that any part is in "contact" with another part is defined to mean that there is no intermediary part between the two parts.

[0192] Unless specifically stated otherwise, descriptors such as "first," "second," "third," etc., are used herein without attributing or otherwise assigning any meaning of priority, physical order, arrangement in a list, and / or any arbitrary ordering, but are used merely as labels and / or arbitrary names to distinguish elements for easy understanding of the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor, such as "second" or "third." In such cases, it is understood that such descriptors are merely used to uniquely identify those elements within the discussion context (e.g.,within a claim) which might otherwise share the same name.

[0193] As used herein, "approximately" and "about" modify their subject / values ​​to account for the potential presence of variations that occur in real-world applications. For example, "approximately" and "about" may modify dimensions that may not be exact due to manufacturing tolerances and / or other real-world imperfections, as understood by those of ordinary skill in the art. For example, "approximately" and "about" may indicate that such dimensions may be within a tolerance range of + / - 10%, unless otherwise noted in the following description.

[0194] As used herein, "substantially real-time" refers to near-instantaneous occurrence, recognizing that in the real world there may be delays for computing time, transmission, etc. Therefore, unless otherwise noted, "substantially real-time" refers to real time + / - 1 second.

[0195] As used herein, the term "in communication," including variations thereof, includes direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or constant communication, but additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and / or one-time events.

[0196] As used herein, "programmable circuitry" is defined to include (i) one or more special-purpose electrical circuits (e.g., an application-specific integrated circuit (ASIC)) structured to perform one or more specific operations and to include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based electrical circuits programmable with instructions to perform one or more specific functions and / or operations and to include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuits include programmable microprocessors such as central processing units (CPUs) that can execute first instructions,to perform one or more operations and / or functions, as well as field-programmable gate arrays (FPGAs) that can be programmed with second instructions to configure and / or structure the FPGAs to instantiate one or more operations and / or functions according to the first instructions, graphics processing units (GPUs) that can execute first instructions to perform one or more operations and / or functions, digital signal processors (DSPs) that can execute first instructions to perform one or more operations and / or functions, XPUs, network processing units (NPUs), one or more microcontrollers that can execute first instructions to perform one or more operations and / or functions, and / or integrated circuits such as application-specific integrated circuits (ASICs). For example, an XPU can be implemented by a heterogeneous computing system,that includes multiple types of programmable circuits (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc.) and / or any combination thereof) and orchestration technology (e.g., application programming interface(s) (API(s)) that can assign computational task(s) to any of the multiple types of programmable circuits suitable and available to perform the computational task(s).

[0197] As used herein, an integrated circuit / circuitry is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, a programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system-on-chip (SoC), etc.

[0198] Fig. 17 is a block diagram of an example programmable circuitry platform 1700 structured to execute the example machine-readable instructions and / or the example operations of Fig. 12 for implementing the current mapping circuitry 706 of Fig. 9. The programmable circuitry platform 1700 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cellular phone, a smartphone, a tablet such as an iPad™), a personal digital assistant (PDA), an internet device, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a game console, a personal video recorder, a set-top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.), or other wearable device, or any other type of computing and / or electronic device.

[0199] The programmable circuitry platform 1700 of the illustrated example includes programmable circuitry 1712. The programmable circuitry 1712 of the illustrated example is hardware. For example, the programmable circuitry 1712 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers of any desired family or manufacturer. The programmable circuitry 1712 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices.In this example, the programmable circuitry 1712 implements the example data interface circuitry 902, the example array generation circuitry 904, the example state analysis circuitry 906, the example mapping control circuitry 908, the example compression control circuitry 910, and the example mapping database 912.

[0200] The programmable circuitry 1712 of the illustrated example includes a local memory 1713 (e.g., a cache, registers, etc.). The programmable circuitry 1712 of the illustrated example communicates via a bus 1718 with the main memory 1714, 1716, which includes a volatile memory 1714 and a non-volatile memory 1716. The volatile memory 1714 may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and / or any other type of RAM device. The non-volatile memory 1716 may be implemented by Flash memory and / or any other desired type of memory device. Access to the main memory 1714, 1716 of the illustrated example is controlled by a memory controller 1717.In some examples, the memory controller 1717 may be implemented by one or more integrated circuits, logic circuits, microcontrollers of any desired family, or any other type of circuitry to manage the flow of data to and from the main memory 1714, 1716.

[0201] The programmable circuitry platform 1700 of the illustrated example also includes interface circuitry 1720. The interface circuitry 1720 may be implemented in hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, a Bluetooth® interface, a Near Field Communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and / or a Peripheral Component Interconnect Express (PCIe) interface.

[0202] In the illustrated example, one or more input devices 1722 are connected to the interface circuitry 1720. The input device(s) 1722 enable a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the programmable circuitry 1712. The input device(s) 1722 may be implemented, for example, by an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a trackpad, a trackball, an isopoint device, and / or a speech recognition system.

[0203] One or more output devices 1724 are also connected to the interface circuitry 1720 of the illustrated example. The output device(s) 1724 may be implemented, for example, by display devices (e.g., a light-emitting diode (LED), an organic light-emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touchscreen, etc.), a tactile output device, a printer, and / or a speaker. The interface circuitry 1720 of the illustrated example thus typically includes a graphics driver card, a graphics driver chip, and / or graphics driver processor circuitry such as a GPU.

[0204] The interface circuitry 1720 of the illustrated example also includes a communication device, such as a transmitter, a receiver, a transceiver, a modem, a home gateway, a wireless access point, and / or a network interface, to enable the exchange of data with external machines (e.g., data processing devices of any type) through a network 1726. Communication may occur, for example, through an Ethernet connection, a DSL (Digital Subscriber Line) connection, a telephone line connection, a coaxial cable system, a satellite system, a beyond-line-of-sight wireless system, a line-of-sight wireless system, a cellular system, an optical connection, etc.

[0205] The programmable circuitry platform 1700 of the illustrated example also includes one or more mass storage disks or devices 1728 for storing firmware, software, and / or data. Examples of such mass storage disks or devices 1728 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices such as flash memory devices and / or SSDs.

[0206] The machine-readable instructions 1732, which are replaced by the machine-readable instructions of Fig. 12 may be stored in the mass storage device 1728, in the volatile memory 1714, in the non-volatile memory 1716, and / or on at least one non-transitory computer-readable storage medium, such as a CD or DVD, which may be removable.

[0207] Fig. 18 is a block diagram of an exemplary programmable circuitry platform 1800 structured to execute the exemplary machine-readable instructions and / or the exemplary operations of Fig. 15 and / or 16 for implementing the utility evaluation circuitry 1306 of Fig. 14. The programmable circuitry platform 1800 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cellular phone, a smartphone, a tablet such as an iPad™), a personal digital assistant (PDA), an internet device, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a game console, a personal video recorder, a set-top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.), or other wearable device, or any other type of computing and / or electronic device.

[0208] The programmable circuitry platform 1800 of the illustrated example includes programmable circuitry 1812. The programmable circuitry 1812 of the illustrated example is hardware. For example, the programmable circuitry 1812 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers of any desired family or manufacturer. The programmable circuitry 1812 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices.In this example, programmable circuitry 1812 implements example input circuitry 1402, example registration circuitry 1404, example doorbell execution circuitry 1406, example ADQ mapping circuitry 1408, example traffic interception circuitry 1410, example historical processing circuitry 1412, example output circuitry 1414, example function execution circuitry 1416, example function database 1418, and example historical database 1420.

[0209] The programmable circuitry 1812 of the illustrated example includes a local memory 1813 (e.g., a cache, registers, etc.). The programmable circuitry 1812 of the illustrated example communicates via a bus 1818 with the main memory 1814, 1816, which includes a volatile memory 1814 and a non-volatile memory 1816. The volatile memory 1814 may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and / or any other type of RAM device. The non-volatile memory 1816 may be implemented by Flash memory and / or any other desired type of memory device. Access to the main memory 1814, 1816 of the illustrated example is controlled by a memory controller 1817.In some examples, the memory controller 1817 may be implemented by one or more integrated circuits, logic circuits, microcontrollers of any desired family, or any other type of circuitry to manage the flow of data to and from the main memory 1814, 1816.

[0210] The programmable circuitry platform 1800 of the illustrated example also includes interface circuitry 1820. The interface circuitry 1820 may be implemented in hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, a Bluetooth® interface, a Near Field Communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and / or a Peripheral Component Interconnect Express (PCIe) interface.

[0211] In the illustrated example, one or more input devices 1822 are connected to the interface circuitry 1820. The input device(s) 1822 enable a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the programmable circuitry 1812. The input device(s) 1822 may be implemented, for example, by an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a trackpad, a trackball, an isopoint device, and / or a speech recognition system.

[0212] One or more output devices 1824 are also connected to the interface circuitry 1820 of the illustrated example. The output device(s) 1824 may be implemented, for example, by display devices (e.g., a light-emitting diode (LED), an organic light-emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touchscreen, etc.), a tactile output device, a printer, and / or a speaker. The interface circuitry 1820 of the illustrated example thus typically includes a graphics driver card, a graphics driver chip, and / or graphics driver processor circuitry such as a GPU.

[0213] The interface circuitry 1820 of the illustrated example also includes a communication device, such as a transmitter, a receiver, a transceiver, a modem, a home gateway, a wireless access point, and / or a network interface, to enable the exchange of data with external machines (e.g., data processing devices of any type) through a network 1826. Communication may occur, for example, through an Ethernet connection, a DSL (Digital Subscriber Line) connection, a telephone line connection, a coaxial cable system, a satellite system, a beyond-line-of-sight wireless system, a line-of-sight wireless system, a cellular system, an optical connection, etc.

[0214] The programmable circuitry platform 1800 of the illustrated example also includes one or more mass storage disks or devices 1828 for storing firmware, software, and / or data. Examples of such mass storage disks or devices 1828 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices such as flash memory devices and / or SSDs.

[0215] The machine-readable instructions 1832, which were replaced by the machine-readable instructions of Fig. 15 and / or 16 may be stored in the mass storage device 1828, in the volatile memory 1814, in the non-volatile memory 1816, and / or on at least one non-transitory computer-readable storage medium, such as a CD or DVD, which may be removable.

[0216] Fig. 19 is a block diagram of an exemplary implementation of the programmable circuitry 1712 of Fig. 17 and / or the programmable circuit arrangement 1812 of Fig. 18. In this example, the programmable circuit arrangement 1712 is Fig. 17 and / or the programmable circuit arrangement 1812 of Fig. 18 is implemented by a microprocessor 1900. For example, the microprocessor 1900 may be a general-purpose microprocessor (e.g., a general-purpose microprocessor circuitry). The microprocessor 1900 executes some or all of the machine-readable instructions of the flowcharts of Fig. 12, Fig. 15 and / or 16 for effectively instantiating the circuit arrangement of Fig. 9 and / or 14 as logic circuits for performing operations corresponding to these machine-readable instructions. In some such examples, the circuit arrangement of Fig. 9 and / or 14 are instantiated by the hardware circuitry of the microprocessor 1900 in combination with the machine-readable instructions. For example, the microprocessor 1900 may be implemented by multi-core hardware circuitry, such as a CPU, a DSP, a GPU, an XPU, etc. Although it may include any number of example cores 1902 (e.g., 1 core), the microprocessor 1900 of this example is a multi-core semiconductor device including N cores. The cores 1902 of the microprocessor 1900 may operate independently or cooperate to execute machine-readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the cores 1902, or it may be executed by multiple cores 1902 at the same time or at different times.In some example cases, the machine code corresponding to the firmware program, the embedded software program, or the software program is divided into threads and executed in parallel by two or more cores 1902. The software program may correspond to some or all of the machine-readable instructions and / or operations represented by the flowcharts of . Fig. 12, Fig. 15 and / or 16 are represented.

[0217] The cores 1902 may communicate via a first example bus 1904. In some examples, the first bus 1904 may be implemented by a communication bus to enable communication in association with one or more cores 1902. For example, the first bus 1904 may be implemented by at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 1904 may be implemented by any other type of computational or electrical bus. The cores 1902 may receive data, instructions, and / or signals from one or more external devices through example interface circuitry 1906. The cores 1902 may output data, instructions, and / or signals to the one or more external devices through the interface circuitry 1906.Although the cores 1902 of this example include an example local memory 1920 (e.g., Level 1 (L1) cache, which may be divided into an L1 data cache and an L1 instruction cache), the microprocessor 1900 also includes an example shared memory 1910 that may be shared between the cores (e.g., Level 2 (L2) cache) for high-speed access to data and / or instructions. Data and / or instructions may be transferred (e.g., shared) by writing to and / or reading from the shared memory 1910. The local memory 1920 of each of the cores 1902 and the shared memory 1910 may be part of a hierarchy of memory devices that may include multiple levels of cache memory and main memory (e.g., main memory 1714, 1716 of FIG. Fig. 17 and / or the main memory 1814, 1816 of Fig. 18). Typically, higher memory levels in the hierarchy have lower access times and smaller storage capacities than lower memory levels. Changes at the different levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherence policy.

[0218] Each core 1902 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuitry. Each core 1902 includes control unit circuitry 1914, arithmetic and logic (AL) circuitry (sometimes referred to as ALU) 1916, multiple registers 1918, local memory 1920, and a second example bus 1922. Other structures may be present. For example, each core 1902 may include vector unit circuitry, single instruction multiple data (SIMD) unit circuitry, load / store unit (LSU) circuitry, branch / jump unit circuitry, floating-point unit (FPU) circuitry, etc. The control unit circuitry 1914 includes semiconductor-based circuits structured to control (e.g., coordinate) data movement within the corresponding core 1902.The AL circuitry 1916 includes semiconductor-based circuitry structured to perform one or more mathematical and / or logical operations on the data within the corresponding core 1902. The AL circuitry 1916 of some examples performs integer-based operations. In other examples, the AL circuitry 1916 also performs floating-point operations. In still other examples, the AL circuitry 1916 may include first AL circuitry that performs integer-based operations and second AL circuitry that performs floating-point operations. In some examples, the AL circuitry 1916 may be referred to as an arithmetic logic unit (ALU).

[0219] The registers 1918 are semiconductor-based structures for storing data and / or instructions, such as results of one or more of the operations performed by the AL circuitry 1916 of the corresponding core 1902. The registers 1918 may include, for example, vector registers, SIMD registers, general-purpose registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. The registers 1918 may be arranged in a bank, as shown in Fig. 19. Alternatively, the registers 1918 may be organized in a different arrangement, format, or structure, e.g., by distributing them throughout the core 1902 to reduce access time. The second bus 1922 may be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0220] Each core 1902 and / or more generally, the microprocessor 1900 may include additional and / or alternative structures to those shown and described above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more converged / common mesh stops (CMSs), one or more shifters (e.g., barrel shifters), and / or other circuitry may be present. The microprocessor 1900 is a semiconductor device fabricated to include many transistors interconnected to implement the above-described structures in one or more integrated circuits (ICs) contained in one or more packages.

[0221] Microprocessor 1900 may include and / or cooperate with one or more accelerators (e.g., accelerator circuitry, hardware accelerators, etc.). In some examples, accelerators are implemented by logic circuitry to perform certain tasks faster and / or more efficiently than is possible with a general-purpose processor. Examples of accelerators include ASICs and FPGAs, such as those discussed herein. A GPU, a DSP, and / or another programmable device may also be an accelerator. Accelerators may be located onboard microprocessor 1900, in the same chip package as microprocessor 1900, and / or in one or more separate packages from microprocessor 1900.

[0222] Fig. 20 is a block diagram of another exemplary implementation of the programmable circuitry 1712 of Fig. 17 and / or the programmable circuit arrangement 1812 of Fig. 18. In this example, the programmable circuitry 1712 and / or the programmable circuitry 1812 is implemented by the FPGA circuitry 2000. For example, the FPGA circuitry 2000 may be implemented by an FPGA. The FPGA circuitry 2000 may, for example, be used to perform operations that would otherwise be performed by the exemplary microprocessor 1900 of Fig. 19 executing corresponding machine-readable instructions. However, once configured, the FPGA circuitry 2000 instantiates the operations and / or functions corresponding to the machine-readable instructions in hardware and can therefore often perform the operations / functions faster than they could be performed by a general-purpose microprocessor executing the corresponding software.

[0223] In particular, in contrast to the above-described microprocessor 1900 from Fig. 19 (which is a general-purpose device that can be programmed to carry out any or all of the machine-readable instructions represented by the flowchart(s) of Fig. 12, Fig. 15 and / or 16, but whose interconnections and logic circuitry are fixed after fabrication), the FPGA circuitry 2000 of the example of Fig. 20 Interconnections and logic circuitry that can be configured, structured, programmed and / or interconnected in different ways after manufacture, for example to instantiate some or all of the operations / functions corresponding to the machine-readable instructions represented by the flowchart(s) of Fig. 12, Fig. 15 and / or 16. In particular, the FPGA circuit 2000 can be viewed as an arrangement of logic gates, interconnections, and switches. The switches can be programmed to change the way the logic gates are connected to one another by the interconnections, effectively forming one or more dedicated logic circuits (unless and until the FPGA circuit 2000 is reprogrammed). The configured logic circuits enable the logic gates to cooperate in different ways to perform various operations on the data received from the input circuitry. These operations may correspond to some or all of the instructions (e.g., software and / or firmware) represented by the flowchart(s) of Fig. 12, Fig. 15 and / or 16. As such, the FPGA circuitry 2000 may be configured and / or structured to perform some or all of the operations / functions corresponding to the machine-readable instructions of the flowchart(s) of Fig. 12, Fig. 15 and / or 16, as dedicated logic circuits to perform the operations / functions corresponding to these software instructions in a dedicated manner analogous to an ASIC. Therefore, the FPGA circuitry 2000 may perform the operations / functions corresponding to some or all of the machine-readable instructions of Fig. 12, Fig. 15 and / or 16 faster than the general-purpose microprocessor can execute them.

[0224] In the example of Fig. 20, the FPGA circuitry 2000 is configured and / or structured in response to being programmed (and / or reprogrammed one or more times) based on a binary file. In some examples, the binary file may be compiled and / or generated based on instructions in a hardware description language (HDL) such as Lucid, Very High Speed ​​Integrated Circuits (VHSIC) Hardware Description Language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) may write code or a program corresponding to one or more operations / functions in an HDL; the code / program may be translated into a low-level language as needed; and the code / program (e.g., the code / program in the low-level language) may be converted (e.g., by a compiler, a software application, etc.) into the binary file. In some examples, the FPGA circuitry 2000 may be Fig. 20 access and / or load the binary file to the FPGA circuitry 2000 of Fig. 20 may be configured and / or structured to perform the one or more operations / functions. For example, the binary file may be implemented by a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions to which the FPGA circuitry 2000 of Fig. 20 to configure and / or structure the FPGA circuitry 2000 of Fig. 20 or section(s) thereof.

[0225] In some examples, the binary file is compiled, generated, transformed, and / or otherwise output by a unified software platform used to program FPGAs. For example, the unified software platform may translate first instructions (e.g., code or a program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into second instructions corresponding to the one or more operations / functions in an HDL. In some such examples, the binary file is compiled, generated, and / or otherwise output by the unified software platform based on the second instructions. In some examples, the FPGA circuitry 2000 may be comprised of Fig. 20 access and / or load the binary file to create the FPGA circuitry 2000 from Fig. 20 may be configured and / or structured to perform the one or more operations / functions. For example, the binary file may be implemented by a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions to which the FPGA circuitry 2000 of Fig. 20 to configure and / or structure the FPGA circuitry 2000 of Fig. 20 or section(s) thereof.

[0226] The FPGA circuit arrangement 2000 of Fig. 20 includes example input / output circuitry 2002 for receiving and / or outputting data to / from example configuration circuitry 2004 and / or external hardware 2006. For example, configuration circuitry 2004 may be implemented by interface circuitry that may receive a binary file implemented by a bit stream, data, and / or machine-readable instructions to configure FPGA circuitry 2000 or portions thereof. In some such examples, configuration circuitry 2004 may receive the binary file from a user, a machine (e.g., hardware circuitry (e.g., programmable or dedicated circuitry) that may implement an artificial intelligence / machine learning (AI / ML) model to generate the binary file), etc., and / or any combination thereof.In some examples, the external hardware 2006 may be implemented by external hardware circuitry. For example, the external hardware 2006 may be implemented by the microprocessor 1900 of [the text]. Fig. 19 must be implemented.

[0227] The FPGA circuitry 2000 also includes an array of exemplary logic gate circuitry 2008, a plurality of configurable exemplary interconnects 2010, and exemplary memory circuitry 2012. The logic gate circuitry 2008 and the configurable interconnects 2010 are configurable to instantiate one or more operations / functions corresponding to at least some of the machine-readable instructions of Fig. 12, Fig. 15 and / or 16 and / or other desired operations. The logic gate circuit arrangement 2008 shown in Fig. 20 is fabricated in blocks or groups. Each block includes semiconductor-based electrical structures that are configurable into logic circuits. In some examples, the electrical structures include logic gates (e.g., AND gates, OR gates, NOR gates, etc.) that provide basic building blocks for logic circuits. Electrically controllable switches (e.g., transistors) are present within each of the logic gate circuitry 2008 to enable configuration of the electrical structures and / or the logic gates to form circuits to perform desired operations / functions. The logic gate circuitry 2008 may include other electrical structures, such as look-up tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

[0228] The configurable connections 2010 of the example shown are conductive paths, traces, vias, or the like, which may include electrically controllable switches (e.g., transistors) whose state may be changed by programming (e.g., using an HDL instruction language) to enable or disable one or more connections between one or more of the logic gate circuitry 2008 to program desired logic circuits.

[0229] The storage circuitry 2012 of the illustrated example is configured to store the result(s) of one or more of the operations performed by the corresponding logic gates. The storage circuitry 2012 can be implemented using registers or the like. In the illustrated example, the storage circuitry 2012 is distributed among the logic gate circuitry 2008 to facilitate access and increase execution speed.

[0230] The exemplary FPGA circuit arrangement 2000 of Fig. 20 also includes exemplary dedicated operations circuitry 2014. In this example, the dedicated operations circuitry 2014 includes special-purpose circuitry 2016 that can be called to implement commonly used functions to avoid having to program those functions in the field. Examples of such special-purpose circuitry 2016 include memory (e.g., DRAM) control circuitry, PCIe control circuitry, clock circuitry, transceiver circuitry, memory, and multiplier-accumulator circuitry. Other types of special-purpose circuitry may also be present. In some examples, the FPGA circuitry 2000 may also include exemplary general-purpose programmable circuitry 2018, such as an exemplary CPU 2020 and / or an exemplary DSP 2022.Additionally or alternatively, there may also be another programmable general-purpose circuit arrangement 2018, such as a GPU, an XPU, etc., which may be programmed to perform further operations.

[0231] Although Fig. 19 and Fig. 20 two exemplary implementations of the programmable circuit arrangement 1712 of Fig. 17 and / or the programmable circuit arrangement 1812 of Fig. 18, many other approaches are contemplated. For example, the FPGA circuitry may include an on-board CPU, such as one or more of the exemplary CPU 2020 of Fig. 19. Therefore, the programmable circuit arrangement 1712 of Fig. 17 and / or the programmable circuit arrangement 1812 of Fig. 18 additionally by combining at least the exemplary microprocessor 1900 of Fig. 19 and the exemplary FPGA circuit arrangement 2000 of Fig. 20. In some such hybrid examples, one or more cores 1902 of Fig. 19 execute a first portion of the machine-readable instructions represented by the flowchart(s) of Fig. 12, Fig. 15 and / or 16 to perform one or more first operations / functions, the FPGA circuitry 2000 of Fig. 20 may be configured and / or structured to perform one or more second operations / functions corresponding to a second portion of the machine-readable instructions represented by the flowcharts of Fig. 12, Fig. 15 and / or 16, and / or an ASIC may be configured and / or structured to perform one or more third operations / functions corresponding to a third portion of the machine-readable instructions represented by the flowcharts of Fig. 12, Fig. 15 and / or 16 are shown.

[0232] It is understood that part or all of the circuit arrangement of Fig. 9 and / or 14 can thus be instantiated at the same or different times. For example, the same and / or different parts of the microprocessor 1900 can Fig. 19 may be programmed to execute portions of machine-readable instructions at the same and / or different times. In some examples, the same and / or different portions of the FPGA circuitry 2000 may be Fig. 20 be configured and / or structured to perform operations / functions corresponding to portions of machine-readable instructions at the same and / or different times.

[0233] In some examples, some or all of the circuitry may be Fig. 9 and / or 14, for example, may be instantiated in one or more threads that execute concurrently and / or in series. For example, the microprocessor 1900 may be Fig. 19 machine-readable instructions in one or more threads that execute concurrently and / or sequentially. In some examples, the FPGA circuitry 2000 may be Fig. 20 may be configured and / or structured to perform operations / functions simultaneously and / or sequentially. Furthermore, in some examples, part or all of the circuitry of Fig. 9 and / or 14 may be implemented within one or more virtual machines and / or containers running on the microprocessor 1900 of Fig. 19 are executed.

[0234] In some examples, the programmable circuitry 1712 may be Fig. 17 and / or the programmable circuit arrangement 1812 of Fig. 18 in one or more housings. For example, the microprocessor 1900 of Fig. 19 and / or the FPGA circuit arrangement 2000 of Fig. 20 may be housed in one or more packages. In some examples, an XPU may be implemented by the programmable circuitry 1712 of Fig. 17 and / or the programmable circuit arrangement 1812 of Fig. 18, which can be located in one or more packages. For example, the XPU can integrate a CPU (e.g., the 1900 microprocessor from Fig. 19, the CPU 2020 from Fig. 20 etc.) in one housing, a DSP (e.g. the DSP 2022 from Fig. 20) in another package, a GPU in another package and an FPGA (e.g. the FPGA circuitry 2000 of Fig. 20) contained in yet another housing.

[0235] A block diagram illustrating an example software distribution platform 2105 for distributing software, such as the example machine-readable instructions 1732 of Fig. 17 and / or the exemplary machine-readable instructions 1832 of Fig. 18 for other hardware devices (e.g. hardware devices owned and / or operated by third parties of the owner and / or operator of the software distribution platform) is in Fig. 21. The exemplary software distribution platform 2105 may be implemented by any computer server, data facility, cloud service, etc., capable of storing and transmitting software to other devices. The third parties may be customers of the entity that owns and / or operates the software distribution platform 2105. For example, the entity that owns and / or operates the software distribution platform 2105 may be a developer, a vendor, and / or a licensor of software, such as the exemplary machine-readable instructions 1732 of Fig. 17 and / or the exemplary machine-readable instructions 1832 of Fig. 18. The third parties may be consumers, users, retailers, OEMs, etc., who purchase the software for use and / or license and / or resell and / or sublicense it. In the illustrated example, the software distribution platform 2105 includes one or more servers and one or more storage devices. The storage devices store the machine-readable instructions 1732 and / or the machine-readable instructions 1832 corresponding to the example machine-readable instructions of Fig. 12, Fig. 15 and / or 16, as described above. The one or more servers of the example software distribution platform 2105 are in communication with an example network 2110, which may correspond to any one or more of the Internet and / or any of the example networks described above. In some examples, the one or more servers respond to requests to send the software to a requesting party as part of a commercial transaction. Payment for the delivery, sale, and / or license of the software may be handled by the one or more servers of the software distribution platform and / or by a third-party payment entity. The servers enable purchasers and / or licensors to download the machine-readable instructions 1732 and / or the machine-readable instructions 1832 from the software distribution platform 2105.For example, the software that conforms to the exemplary machine-readable instructions of . Fig. 12, Fig. 15 and / or 16, may be downloaded to the example programmable circuitry platform 1700, which is to execute the machine-readable instructions 1732 to implement the current mapping circuitry 706, and / or may be downloaded to the example programmable circuitry platform 1800, which is to execute the machine-readable instructions 1832 to implement the utility evaluation circuitry 1306. In some examples, one or more servers of the software distribution platform 2105 periodically provide updates to the software (e.g., the example machine-readable instructions 1732 of Fig. 17 and / or the exemplary machine-readable instructions 1832 of Fig.18) to ensure that improvements, patches, updates, etc., are distributed and applied to the software on the end-user devices. Although referred to as software above, the distributed "software" could alternatively be firmware.

[0236] From the foregoing, it should be appreciated that exemplary systems, devices, articles of manufacture, and methods have been disclosed that manage network communications in time-critical networks. Examples disclosed herein perform one or more exemplary utility functions based on a payload of a data packet from a data stream and / or based on exemplary historical information associated with the data stream. As a result of execution, examples disclosed herein determine an exemplary utility value of the data packet to determine whether to discard or forward the data packet to an exemplary platform (e.g., a server platform) and / or one or more exemplary software stacks implemented thereon.Advantageously, examples disclosed herein may reduce the amount of redundant and / or low-usage data to be ingested at the platform, thereby reducing computational power and / or memory usage for storing and / or processing incoming data. Further examples disclosed herein dynamically switch between multiple example proxy data streams to transfer data between edge devices in a time-critical network, where the proxy data streams are preconfigured to meet respective different communication metrics (e.g., bandwidth, latency, etc.).In some examples, examples disclosed herein may adapt to changing QoS requirements of a network by switching between preconfigured proxy data streams without overloading the network and / or without requiring reallocation of communication resources and / or recalculation of possible scheduling plans for data sent over the network. Thus, disclosed systems, devices, articles of manufacture, and methods improve the efficiency of using a computing device by reducing an amount of computing resources and / or memory used to transmit and / or receive data (e.g., data packets and / or data streams) over a network. The presented systems, devices, articles of manufacture, and methods accordingly target one or more improvements in the operation of a machine such as a computer or other electronic and / or mechanical device.

[0237] Exemplary methods, devices, systems, and articles of manufacture for managing network communications in time-critical networks are disclosed herein. Further examples and combinations include the following:

[0238] Example 1 includes a device comprising network interface circuitry and platform interface circuitry configured to be programmed by instructions to determine whether to discard a data packet of a data stream or forward the data packet based on (a) a payload of the data packet and (b) historical information associated with the data stream, and to operate on the data packet based on the determination.

[0239] Example 2 includes the apparatus of Example 1, wherein the platform interface circuitry is configured to execute a utility function based on the payload and the historical information, wherein a result of the execution includes a utility value corresponding to the data packet, the utility value based on a variability between the payload and the historical information, and to determine whether to discard the data packet or forward the data packet based on the result of the execution.

[0240] Example 3 includes the setup of Example 2, wherein the data stream is a first data stream and the utility value is based on a set of non-repetitive information included in the payload and not included in one or more second data streams.

[0241] Example 4 includes the device of Example 2, wherein the platform interface circuitry is configured to discard the data packet if the utility value does not satisfy a utility threshold and to forward the data packet if the utility value satisfies the utility threshold.

[0242] Example 5 includes the apparatus of Example 2, wherein the platform interface circuitry is configured to register the utility function by storing the utility function in association with at least one of a process address identifier corresponding to a software stack, a queue identifier corresponding to a network queue, or a universally unique identifier corresponding to the utility function.

[0243] Example 6 includes the apparatus of Example 1, wherein the historical information includes at least one of a first number of discarded data packets associated with the data stream and a second number of forwarded data packets associated with the data stream, or characteristics corresponding to at least one of the discarded data packets or the forwarded data packets.

[0244] Example 7 includes the apparatus of Example 1, wherein the platform interface circuitry is configured to generate an alert to a software stack in response to detecting an event, wherein the event is to include at least a threshold number of data packets of the data stream being discarded, the historical information being updated at least a threshold number of times, or an amount of memory used to store the historical information being at or above a threshold amount.

[0245] Example 8 includes a device comprising network interface circuitry and programmable circuitry configured to be programmed by instructions to select, based on state information for a first edge device, a first of a plurality of proxy data streams available to the first edge device in a time-critical network environment, wherein the plurality of proxy data streams are preconfigured in the time-critical network environment to satisfy respective different communication metrics and to cause transmission of data from the first edge device to a second edge device based on the first of the plurality of proxy data streams.

[0246] Example 9 includes the setup of Example 8, wherein the communication metrics correspond to at least one of a bandwidth or latency of data transmitted over respective ones of the plurality of proxy data streams.

[0247] Example 10 includes the setup of Example 8, wherein the plurality of proxy data streams are preconfigured in a handshake procedure between the first edge device and a centralized network configuration node of the time-critical network environment, wherein the plurality of proxy data streams are preconfigured based on communication resources available to the first edge device.

[0248] Example 11 includes the apparatus of Example 8, wherein the state information includes at least one of a position of an endpoint device associated with the first edge device, an orientation of the endpoint device, a distance between the endpoint device and an object, or an indication of whether the endpoint device is idle or performing an operation.

[0249] Example 12 includes the setup of Example 11, wherein the state information is based on a data stream from the endpoint device.

[0250] Example 13 includes the apparatus of Example 12, wherein the endpoint device is a camera, the data stream is a video data stream, and the programmable circuitry is configured to select a compression scheme for the video data stream based on the state information.

[0251] Example 14 includes the apparatus of Example 8, wherein the programmable circuitry is configured to determine a target communication metric based on updated state information, select a second of the plurality of proxy data streams corresponding to the target communication metric, pause a transmission of the data based on the first of the plurality of proxy data streams, and initiate a transmission of data from the first edge device to the second edge device based on the second of the plurality of proxy data streams.

[0252] Example 15 includes an apparatus comprising network interface circuitry and programmable circuitry configured to be programmed by instructions to determine at a first edge device whether to (a) discard a data packet of a data stream received at the first edge device or (b) forward the data packet to a second edge device, wherein the determination is based on a payload of the data packet and historical information associated with the data stream, wherein the determination is based on forwarding the data packet to the second edge device based on state information for the first edge device, selecting a first of a plurality of proxy data streams available to the first edge device in a time-critical network environment, wherein the plurality of proxy data streams are preconfigured in the time-critical network environment,to satisfy respective different communication metrics, and to initiate transmission of the data packet to the second edge device based on the first of the plurality of proxy data streams and to update the historical information based on the determination.

[0253] Example 16 includes the apparatus of Example 15, wherein the programmable circuitry is configured to execute a utility function based on the payload and the historical information, wherein a result of the execution includes a utility value corresponding to the data packet, the utility value being based on at least one of (a) an amount of variability between the payload and the historical information or (b) an amount of non-repetitive information included in the payload and not included in one or more second data streams received at the second edge device, and determine whether to discard the data packet or forward the data packet based on the result of the execution.

[0254] Example 17 includes the device of Example 16, wherein the programmable circuitry is configured to discard the data packet if the utility value does not satisfy a utility threshold and to forward the data packet if the utility value satisfies the utility threshold.

[0255] Example 18 includes the setup of Example 15, wherein the communication metrics correspond to at least one of a bandwidth or latency of data transmitted over respective ones of the plurality of proxy data streams.

[0256] Example 19 includes the apparatus of Example 15, wherein the programmable circuitry is configured to select a compression scheme for the data stream based on the state information.

[0257] Example 20 includes the apparatus of Example 15, wherein the state information includes at least one of a position of an endpoint device associated with the first edge device, an orientation of the endpoint device, a distance between the endpoint device and an object, or an indication of whether the endpoint device is idle or performing an operation.

[0258] Example 21 includes a non-transitory computer-readable medium comprising instructions that, when executed, cause programmable circuitry to determine whether to discard a data packet of a data stream or to forward the data packet based at least on (a) a payload of the data packet and (b) historical information associated with the data stream, and to operate on the data packet based on the determination.

[0259] Example 22 includes the non-transitory computer-readable medium of Example 21, wherein the instructions cause the programmable circuitry to perform a utility function based on the payload and the historical information, wherein a result of the execution includes a utility value corresponding to the data packet, the utility value is based on a variability between the payload and the historical information, and determines whether to discard the data packet or forward the data packet based on the result of the execution.

[0260] Example 23 includes the non-transitory computer-readable medium of Example 22, wherein the data stream is a first data stream and the utility value is based on a set of non-repeating information included in the payload and not included in one or more second data streams.

[0261] Example 24 includes the non-transitory computer-readable medium of Example 22, wherein the instructions cause the programmable circuitry to discard the data packet if the utility value does not satisfy a utility threshold and to forward the data packet if the utility value satisfies the utility threshold.

[0262] Example 25 includes the non-transitory computer-readable medium of Example 22, wherein the instructions cause the programmable circuitry to register the utility function by storing the utility function in association with at least one of a process address identifier corresponding to a software stack, a queue identifier corresponding to a network queue, or a universally unique identifier corresponding to the utility function.

[0263] Example 26 includes the non-transitory computer-readable medium of Example 21, wherein the historical information includes at least one of a first number of discarded data packets associated with the data stream and a second number of forwarded data packets associated with the data stream, or characteristics corresponding to at least one of the discarded data packets or the forwarded data packets.

[0264] Example 27 includes the non-transitory computer-readable medium of Example 21, wherein the instructions cause the programmable circuitry to generate an alert to a software stack in response to detecting an event, the event including at least a threshold number of data packets of the data stream being discarded, the historical information being updated at least a threshold number of times, or an amount of memory used to store the historical information being at or above a threshold amount.

[0265] Example 28 includes a non-transitory computer-readable medium comprising instructions that, when executed, cause programmable circuitry to select, based at least on state information for a first edge device, a first of a plurality of proxy data streams available to the first edge device in a time-critical network environment, wherein the plurality of proxy data streams are preconfigured in the time-critical network environment to satisfy respective different communication metrics, and to cause a transfer of data from the first edge device to a second edge device based on the first of the plurality of proxy data streams.

[0266] Example 29 includes the non-transitory computer-readable medium of Example 28, wherein the communication metrics correspond to at least one of a bandwidth or latency of data transmitted over respective ones of the plurality of proxy data streams.

[0267] Example 30 includes the non-transitory computer-readable medium of Example 28, wherein the plurality of proxy data streams are pre-configured in a handshake procedure between the first edge device and a centralized network configuration node of the time-critical network environment, the plurality of proxy data streams being pre-configured based on communication resources available to the first edge device.

[0268] Example 31 includes the non-transitory computer-readable medium of Example 28, wherein the state information includes at least one of a position of an endpoint device associated with the first edge device, an orientation of the endpoint device, a distance between the endpoint device and an object, or an indication of whether the endpoint device is idle or performing an operation.

[0269] Example 32 includes the non-transitory computer-readable medium of Example 31, wherein the state information is based on a data stream from the endpoint device.

[0270] Example 33 includes the non-transitory computer-readable medium of Example 32, wherein the endpoint device is a camera, the data stream is a video data stream, and the programmable circuitry is configured to select a compression scheme for the video data stream based on the state information.

[0271] Example 34 includes the non-transitory computer-readable medium of Example 28, wherein the instructions cause the programmable circuitry to determine a target communication metric based on updated state information, select a second of the plurality of proxy data streams that corresponds to the target communication metric, stop transmitting the data based on the first of the plurality of proxy data streams, and cause a transmission of data from the first edge device to the second edge device based on the second of the plurality of proxy data streams.

[0272] Example 35 includes a non-transitory computer-readable medium comprising instructions that, when executed, cause programmable circuitry to at least determine, at a first edge device, whether to (a) discard a data packet of a data stream received at the first edge device or (b) forward the data packet to a second edge device, the determination being based on a payload of the data packet and historical information associated with the data stream, based on the determination being to forward the data packet to the second edge device, selecting a first of a plurality of proxy data streams available to the first edge device in a time-critical network environment, the plurality of proxy data streams preconfigured in the time-critical network environment,to satisfy respective different communication metrics and to initiate transmission of the data packet to the second edge device based on the first of the plurality of proxy data streams and to update the historical information based on the determination.

[0273] Example 36 includes the non-transitory computer-readable medium of Example 35, wherein the instructions cause the programmable circuitry to perform a utility function based on the payload and the historical information, wherein a result of the execution includes a utility value corresponding to the data packet, the utility value being based on at least one of (a) an amount of variability between the payload and the historical information or (b) an amount of non-repetitive information included in the payload that is not included in one or more second data streams received at the second edge device, and determine whether to discard the data packet or forward the data packet based on the result of the execution.

[0274] Example 37 includes the non-transitory computer-readable medium of Example 36, wherein the instructions cause the programmable circuitry to discard the data packet if the utility value does not satisfy a utility threshold and to forward the data packet if the utility value satisfies the utility threshold.

[0275] Example 38 includes the non-transitory computer-readable medium of Example 35, wherein the communication metrics correspond to at least one of a bandwidth or latency of data transmitted over respective ones of the plurality of proxy data streams.

[0276] Example 39 includes the non-transitory computer-readable medium of Example 35, wherein the instructions cause the programmable circuitry to select a compression scheme for the data stream based on the state information.

[0277] Example 40 includes the non-transitory computer-readable medium of Example 35, wherein the state information includes at least one of a position of an endpoint device associated with the first edge device, an orientation of the endpoint device, a distance between the endpoint device and an object, or an indication of whether the endpoint device is idle or performing an operation.

[0278] Example 41 includes a method comprising determining whether to discard a data packet of a data stream or to forward the data packet based on (a) a payload of the data packet and (b) historical information associated with the data stream, and operating on the data packet based on the determination.

[0279] Example 42 includes the method of Example 41, further comprising executing a utility function based on the payload and the historical information, wherein a result of the execution includes a utility value corresponding to the data packet, the utility value based on an amount of variability between the payload and the historical information, and determining whether to discard the data packet or forward the data packet based on the result of the execution.

[0280] Example 43 includes the method of Example 42, wherein the data stream is a first data stream and the utility value is based on a set of non-repetitive information included in the payload and not included in one or more second data streams.

[0281] Example 44 includes the method of Example 42, further including discarding the data packet if the utility value does not satisfy a utility threshold and forwarding the data packet if the utility value satisfies the utility threshold.

[0282] Example 45 includes the method of Example 42, further including registering the utility function by storing the utility function in association with at least one of a process address identifier corresponding to a software stack, a queue identifier corresponding to a network queue, or a universally unique identifier corresponding to the utility function.

[0283] Example 46 includes the method of Example 41, wherein the historical information includes at least one of a first number of discarded data packets associated with the data stream and a second number of forwarded data packets associated with the data stream, or characteristics corresponding to at least one of the discarded data packets or the forwarded data packets.

[0284] Example 47 includes the method of Example 41, further including generating an alert to a software stack in response to detecting an event, wherein the event is to include at least a threshold number of data packets of the data stream being discarded, the historical information being updated at least a threshold number of times, or an amount of memory used to store the historical information being at or above a threshold amount.

[0285] Example 48 includes a method comprising selecting, based on state information for a first edge device, a first of a plurality of proxy data streams available to the first edge device in a time-critical network environment, wherein the plurality of proxy data streams are preconfigured in the time-critical network environment to satisfy respective different communication metrics and causing a transmission of data from the first edge device to a second edge device based on the first of the plurality of proxy data streams.

[0286] Example 49 includes the method of Example 48, wherein the communication metrics correspond to at least one of a bandwidth or latency of data transmitted over respective ones of the plurality of proxy data streams.

[0287] Example 50 includes the method of Example 48, wherein the plurality of proxy data streams are preconfigured in a handshake procedure between the first edge device and a centralized network configuration node of the time-critical network environment, wherein the plurality of proxy data streams are preconfigured based on communication resources available to the first edge device.

[0288] Example 51 includes the method of Example 48, wherein the state information includes at least one of a position of an endpoint device associated with the first edge device, an orientation of the endpoint device, a distance between the endpoint device and an object, or an indication of whether the endpoint device is idle or performing an operation.

[0289] Example 52 includes the method of Example 51, wherein the state information is based on a data stream from the endpoint device.

[0290] Example 53 includes the method of Example 52, wherein the endpoint device is a camera, the data stream is a video data stream, and further includes selecting a compression scheme for the video data stream based on the state information.

[0291] Example 54 includes the method of Example 48, further comprising determining a target communication metric based on updated state information, selecting a second of the plurality of proxy data streams that corresponds to the target communication metric, pausing transmission of the data based on the first of the plurality of proxy data streams, and causing transmission of data from the first edge device to the second edge device based on the second of the plurality of proxy data streams.

[0292] Example 55 includes a method comprising determining, at a first edge device, whether to (a) discard a data packet of a data stream received at the first edge device or (b) forward the data packet to a second edge device, the determination being based on a payload of the data packet and historical information associated with the data stream, based on the determination being to forward the data packet to the second edge device, selecting, based on state information for the first edge device, a first of a plurality of proxy data streams available to the first edge device in a time-critical network environment, the plurality of proxy data streams being preconfigured in the time-critical network environment to meet respective different communication metrics,and causing a transmission of the data packet to the second edge device based on the first of the plurality of proxy data streams and updating the historical information based on the determination.

[0293] Example 56 includes the method of Example 55, further including executing a utility function based on the payload and the historical information, wherein a result of the execution includes a utility value corresponding to the data packet, the utility value based on at least one of (a) an amount of variability between the payload and the historical information or (b) an amount of non-repetitive information included in the payload and not included in one or more second data streams received at the second edge device, and determining whether to discard the data packet or forward the data packet based on the result of the execution.

[0294] Example 57 includes the method of Example 56, further including discarding the data packet if the utility value does not satisfy a utility threshold and forwarding the data packet if the utility value satisfies the utility threshold.

[0295] Example 58 includes the method of Example 55, wherein the communication metrics correspond to at least one of a bandwidth or latency of data transmitted over respective ones of the plurality of proxy data streams.

[0296] Example 59 includes the method of Example 55, further including selecting a compression scheme for the data stream based on the state information.

[0297] Example 60 includes the method of Example 55, wherein the state information includes at least one of a position of an endpoint device associated with the first edge device, an orientation of the endpoint device, a distance between the endpoint device and an object, or an indication of whether the endpoint device is idle or performing an operation.

[0298] The following claims are hereby incorporated by reference into this Detailed Description. Although certain exemplary systems, devices, articles of manufacture, and methods have been disclosed herein, the scope of this patent is not so limited. On the contrary, this patent covers all systems, devices, articles of manufacture, and methods falling within the scope of the claims of this patent. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] IN 202341048353

[0001]

Claims

[1] Facility comprising: a network interface circuit arrangement; and Platform interface circuitry to be programmed by instructions to: Determining whether to discard a data packet of a data stream or to forward the data packet based on (a) a payload of the data packet and (b) historical information associated with the data stream; and Working on the data package based on the determination. [2] The device of claim 1, wherein the platform interface circuitry is configured to: Executing a utility function based on the payload and the historical information, wherein a result of the execution includes a utility value corresponding to the data packet, the utility value based on a variability between the payload and the historical information; and Determine whether to discard the data packet or forward the data packet based on the result of the execution. [3] The device of claim 2, wherein the data stream is a first data stream and the utility value is based on a set of non-repetitive information included in the payload and not included in one or more second data streams. [4] Device according to one of claims 2 or 3, wherein the platform interface circuitry is arranged to: Discarding the data packet if the utility value does not meet a utility threshold, and Forward the data packet if the utility value meets the utility threshold. [5] The device of claim 2 or 3, wherein the platform interface circuitry is configured to register the utility function by storing the utility function in association with at least one of a process address identifier corresponding to a software stack and a queue identifier corresponding to a network queue or a universally unique identifier corresponding to the utility function. [6] The device according to any one of claims 1 to 5, wherein the historical information includes at least one of a first number of discarded data packets associated with the data stream and a second number of forwarded data packets associated with the data stream, or characteristics corresponding to at least one of the discarded data packets or the forwarded data packets. [7] The device of any one of claims 1 to 5, wherein the platform interface circuitry is configured to generate an alert to a software stack in response to detecting an event, the event to include at least a threshold number of data packets of the data stream being discarded, the historical information being updated at least a threshold number of times, or an amount of memory used to store the historical information being at or above a threshold amount. [8] Facility comprising: a network interface circuit arrangement; and a programmable circuit arrangement designed to be programmed by instructions to: Selecting, based on state information for a first edge device, a first of a plurality of proxy data streams available to the first edge device in a time-critical network environment, wherein the plurality of proxy data streams are preconfigured in the time-critical network environment to satisfy respective different communication metrics; and Initiating a transmission of data from the first edge device to a second edge device based on the first of the plurality of proxy data streams. [9] The device of claim 8, wherein the communication metrics correspond to at least one of a bandwidth or latency of data transmitted over respective ones of the plurality of proxy data streams. [10] The device of claim 8 or 9, wherein the plurality of proxy data streams are preconfigured in a handshake procedure between the first edge device and a centralized network configuration node of the time-critical network environment, the plurality of proxy data streams being preconfigured based on communication resources available to the first edge device. [11] The device of any one of claims 8 to 10, wherein the state information includes at least one of a position of an endpoint device associated with the first edge device, an orientation of the endpoint device, a distance between the endpoint device and an object, or an indication of whether the endpoint device is idle or performing an operation. [12] The device of claim 11, wherein the state information is based on a data stream from the endpoint device. [13] The apparatus of claim 12, wherein the endpoint device is a camera, the data stream is a video data stream, and the programmable circuitry is configured to select a compression scheme for the video data stream based on the state information. [14] Device according to one of claims 8 to 13, wherein the programmable circuit arrangement is designed to: Determining a target communication metric based on updated state information; selecting a second of the plurality of proxy data streams that corresponds to the target communication metric; Stopping the transmission of the data based on the first of the plurality of proxy data streams; and Initiating a transmission of data from the first edge device to the second edge device based on the second of the plurality of proxy data streams. [15] Facility comprising: a network interface circuit arrangement; and a programmable circuit arrangement designed to be programmed by instructions to: Determining, at a first edge device, whether to (a) discard a data packet of a data stream received at the first edge device or (b) forward the data packet to a second edge device, the determination based on a payload of the data packet and historical information associated with the data stream; based on the determination to forward the data packet to the second edge device: Selecting, based on state information for the first edge device, a first of a plurality of proxy data streams available to the first edge device in a time-critical network environment, wherein the plurality of proxy data streams are preconfigured in the time-critical network environment to meet respective different communication metrics, and Initiating transmission of the data packet to the second edge device based on the first of the plurality of proxy data streams; and updating the historical information based on the determination. [16] The device of claim 15, wherein the programmable circuit arrangement is configured to: Executing a utility function based on the payload and the historical information, wherein a result of the execution includes a utility value corresponding to the data packet, the utility value being based on at least one of (a) an amount of variability between the payload and the historical information or (b) an amount of non-repetitive information included in the payload and not included in one or more second data streams received at the second edge device; and Determine whether to discard the data packet or forward the data packet based on the result of the execution. [17] Device according to claim 16, wherein the programmable circuit arrangement is designed to: Discarding the data packet if the utility value does not meet a utility threshold, and Forward the data packet if the utility value meets the utility threshold. [18] The device of any of claims 15 to 17, wherein the communication metrics correspond to at least one of a bandwidth or latency of data transmitted over respective ones of the plurality of proxy data streams. [19] Device according to one of claims 15 to 18, wherein the programmable circuit arrangement is designed to select a compression scheme for the data stream based on the state information. [20] The device of any of claims 15 to 18, wherein the state information includes at least one of a position of an endpoint device associated with the first edge device, an orientation of the endpoint device, a distance between the endpoint device and an object, or an indication of whether the endpoint device is idle or performing an operation. [21] A computer-readable medium comprising instructions which, when executed, cause a programmable circuit arrangement to at least: Determining, at a first edge device, whether to (a) discard a data packet of a data stream received at the first edge device or (b) forward the data packet to a second edge device, the determination based on a payload of the data packet and historical information associated with the data stream; based on the determination to forward the data packet to the second edge device: Selecting, based on state information for the first edge device, a first of a plurality of proxy data streams available to the first edge device in a time-critical network environment, wherein the plurality of proxy data streams are preconfigured in the time-critical network environment to meet respective different communication metrics; and initiating transmission of the data packet to the second edge device based on the first of the plurality of proxy data streams; and Updating historical information based on the determination. [22] The computer-readable medium of claim 21, wherein the instructions cause the programmable circuitry to: Executing a utility function based on the payload and the historical information, wherein a result of the execution includes a utility value corresponding to the data packet, the utility value being based on at least one of (a) an amount of variability between the payload and the historical information or (b) an amount of non-repetitive information included in the payload and not included in one or more second data streams received at the second edge device; and Determine whether to discard the data packet or forward the data packet based on the result of the execution. [23] The computer-readable medium of claim 22, wherein the instructions cause the programmable circuitry to: Discarding the data packet if the utility value does not meet a utility threshold, and Forward the data packet if the utility value meets the utility threshold. [24] The computer-readable medium of any of claims 21 to 23, wherein the communication metrics correspond to at least one of a bandwidth or latency of data transmitted over respective ones of the plurality of proxy data streams. [25] The computer-readable medium of any of claims 21 to 24, wherein the instructions cause the programmable circuitry to select a compression scheme for the data stream based on the state information.

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