Semiconductor package and electronic power module with several such semiconductor packages

Abstract

Semiconductor package (212, 215, 220) for an electronic power module (202), comprising a ceramic substrate (600) having a ceramic layer (800) between a lower copper layer (805) and an upper copper layer (810), two first load terminals (300, 305) each with a leadframe (615, 620), wherein one of the first load terminals (300) is associated with at least one first power semiconductor (335) and the other first load terminal (305) is associated with at least one second power semiconductor (350), and wherein the respective power semiconductor (335, 350) is arranged between the upper copper layer (810) of the ceramic substrate (600) and the leadframe (615, 620) of the associated first load terminal (300, 305) and is electrically connected to them, a second load terminal (310) which is electrically connected to the upper copper layer (810). connected, two third load connections (315, 320),which have the same potential as the second load terminal (310) and which are each electrically connected to the upper copper layer (810) of the ceramic substrate (600), a control terminal (605) which is electrically connected to signal pins (325, 330) for controlling the semiconductor package (212, 215, 220) and via connecting elements (610) to the power semiconductors (335, 350), wherein the ceramic substrate (600) is rectangular, and wherein a first load terminal (300, 305) is assigned to each of the longer sides and the second load terminal (310) to each of the shorter sides of the ceramic substrate (600), and a third load terminal (315, 320) is assigned to each of the longer sides of the ceramic substrate (600).

Description

[0001] The present invention relates to a semiconductor package for an electronic power module and an electronic power module for a motor control unit comprising several such semiconductor packages. The invention further relates to an electric drive axle comprising such a power module and to a motor vehicle.

[0002] For example, DE 10 2009 044 659 A1 discloses a power semiconductor module comprising a conductor frame, a power semiconductor element, and a cylindrical conductor. A portion of the conductor frame, the power semiconductor element, and the cylindrical conductor are each sealed by a compression-molded resin, with connection sections of the conductor frame protruding from circumferential side sections of the power semiconductor module, and an opening of the cylindrical conductor exposed on an upper surface of the power semiconductor module. Further power modules are disclosed in DE 10 2017 203 846 A1 and DE 10 2022 207 922 B3.

[0003] One object of the invention is to provide a compact semiconductor package that can achieve improved performance within a given installation space. The invention solves this object by means of the subject matter of the independent claims. Dependent claims describe preferred embodiments.

[0004] A semiconductor package according to the invention for an electronic power module comprises a rectangular ceramic substrate having a ceramic layer between a lower copper layer and an upper copper layer, two first load terminals each with a leadframe, wherein one of the first load terminals is associated with at least one first power semiconductor and the other first load terminal is associated with at least one second power semiconductor, and wherein the respective power semiconductor is arranged between the upper copper layer of the ceramic substrate and the leadframe of the associated first load terminal and is electrically connected to them, a second load terminal which is electrically connected to the upper copper layer, two third load terminals which have the same potential as the second load terminal and which are each electrically connected to the upper copper layer of the ceramic substrate, and a control terminal.which is electrically connected to the power semiconductors via signal pins for controlling the semiconductor package and via connecting elements, wherein a first load connection is assigned to one of the longer sides and the second load connection to one of the shorter sides of the ceramic substrate, characterized in that a third load connection is assigned to one of the longer sides of the ceramic substrate.

[0005] To further improve current symmetry within the upper copper layer of the ceramic substrate, the semiconductor package also includes two third load terminals that have the same potential as the second load terminal and are each electrically connected to the upper copper layer of the ceramic substrate. These third load terminals are for current balancing. For this purpose, the third load terminals are preferably located at opposite ends of the ceramic substrate with respect to the second load terminal and have the same potential. The third load terminals also form the drain side of the semiconductor package. On the side of the upper copper layer facing away from the ceramic layer, a first sintered layer can be arranged between each third load terminal and the upper copper layer of the ceramic substrate to improve contact.

[0006] In this configuration, a third load connection is assigned to each of the longer sides of the ceramic substrate. In other words, the third load connections are arranged on opposite sides of the semiconductor package and extend in opposite directions, analogous to the first load connections. The third load connections are spaced transversely from the first load connections, preferably at a distance sufficient to prevent any interaction during operation. Thus, a first load connection and a third load connection are arranged on each of the longer sides of the semiconductor package. The third load connections can also have a contact surface that lies in the same plane as the contact surfaces of the first load connections and the second load connection, respectively, on the top side of the semiconductor package.In a non-inventive embodiment of the power module, the third load connections can be arranged on the short side of the ceramic substrate opposite the second load connection.

[0007] The semiconductor package is a discrete, single-unit electronic power module. It can be used in a half-bridge of a motor controller, with two semiconductor packages forming one half-bridge. Multiple half-bridges, preferably three, can be individually controllable to operate an electric motor of a motor vehicle. The semiconductor package is used for switching current, particularly for loads in the tens of kilowatts range, especially for electric motors, such as those in a motor vehicle.

[0008] By providing two first load terminals and assigning at least one power semiconductor or chip to each first load terminal, the number of power semiconductors on a given area of ​​the ceramic substrate can be increased. In other words, the packing density of the semiconductor package is maximized. Furthermore, current symmetry can be achieved through a suitable arrangement of the first load terminals, the second load terminal, and the power semiconductors—that is, by choosing an appropriate topology for the semiconductor package. The semiconductor package is current-symmetrical when the current flow within it is evenly distributed. This means that the current in different paths or branches of a circuit is always the same. Current symmetry ensures that the circuit functions correctly and that no undesirable effects occur.Furthermore, the semiconductor package described herein improves electrical testability, thereby increasing the yield. Additionally, the heat dissipation of the power semiconductors can be optimized, particularly through heat spreading.

[0009] The ceramic substrate can be an AMB substrate (Active Metal Brazing), a DBC substrate (Direct Copper Bonding), or a DPC substrate (Direct Plated Copper). The ceramic layer is an electrical insulating layer. The ceramic layer is made, for example, of aluminum oxide or silicon nitride.

[0010] The lower copper layer of the ceramic substrate is designed to be connected to a heat sink. In other words, the lower copper layer is configured for cooling. The lower copper layer can be understood as the back or underside of the package, which is, for example, bonded to a heat sink. The heat sink is preferably part of a power module.

[0011] The load connections can be formed from a single sheet of metal and shaped into a stamped grid by punching and forming. After punching and forming the sheet, bonding it to the ceramic substrate, and subsequent encapsulation, a remaining frame, which may be fixed during manufacturing, can be separated from the load connections.

[0012] The first load connections are designed to electrically connect a busbar to the power semiconductors of the semiconductor package. These first load connections together form the AC connection, or "source" side, of the semiconductor package. By providing two first load connections, the power supply can be divided and directed into the semiconductor package. This allows for a more compact semiconductor package design and, due to the identical number of corresponding power semiconductors per first load connection, enables current symmetry. This increases the power density while maintaining a compact form factor. The second load connection forms the DC Plus connection, or "drain" side, of the semiconductor package.

[0013] The load terminals can have multiple monolithically connected legs, connectors, and / or arms. One leg of each load terminal, i.e., a leg that serves as a connection element for the external connection of the semiconductor package and has a contact surface, can be arranged three-dimensionally in space such that the contact surfaces of all load terminals are located in a common plane, particularly on a top surface of the semiconductor package. This improves the connection to the semiconductor package.

[0014] The first load connections comprise leadframes, i.e., connecting or guide frames, which are shaped such that a busbar connected to the first load connections is at least indirectly linked to the respective power semiconductor. The respective leadframe carries the electrical energy present at the first load connection to the associated power semiconductor. If multiple first or second power semiconductors are provided, the respective leadframe can be designed such that the electrical energy is distributed evenly to all first or second power semiconductors via cross-connectors or branches.

[0015] The control terminal acts as the gate rotor of the semiconductor package. It comprises a signal substrate with a ceramic layer sandwiched between a lower copper layer (facing the ceramic substrate) and an upper copper layer. The lower copper layer of the signal substrate is at the same potential as the upper copper layer of the ceramic substrate. The upper copper layer of the control terminal is electrically connected to the signal pins and the connecting elements. For information regarding the substrate material, please refer to the description of the ceramic substrate.

[0016] The connecting elements are preferably designed as bond wires. Two bond wires electrically connect the upper copper layer of the control terminal to one of the power semiconductors. The bond wires are made, for example, of aluminum or another electrically conductive material.

[0017] The power semiconductor is a current valve with an input, an output, and a control connection. The input and output are connected to the upper copper layer or the leadframe, respectively. The power semiconductor can be electrically insulated by encapsulation, particularly by injection molding, preferably by transfer molding. Current scaling can be achieved by adjusting the number and size of the parallel-connected power semiconductors.

[0018] Furthermore, the ceramic substrate is essentially rectangular, with a first load connection assigned to one of the longer sides and a second load connection to one of the shorter sides of the ceramic substrate. In other words, the first load connections are arranged on opposite sides of the semiconductor package and can extend in opposite directions. This allows the semiconductor package to be symmetrical. Furthermore, the semiconductor package can be used flexibly. The second load connection is preferably arranged centrally on one of the shorter sides of the semiconductor package.

[0019] The upper copper layer of the ceramic substrate is at least electrically connected to other components of the semiconductor package. Preferably, first sintered layers are applied to the upper copper layer to connect it at least electrically to the second load terminal and the power semiconductors. Due to the large number of components connected to the upper copper layer, a large number of separate first sintered layers are also arranged on its surface. In addition to the electrical connection, a thermal connection is preferably established between the upper copper layer of the ceramic substrate and the second load terminal, the control terminal, and the power semiconductors.

[0020] The first sintered layers can be designed as receptacles, particularly for the power semiconductors, with the power semiconductors arranged in these receptacles being electrically connected in parallel between the upper copper layer and the leadframe. A sintered layer is intended to establish or fix an electrical connection between two components of the semiconductor package. Furthermore, the sintered layer improves the thermal properties in the contact area. The sintered layer enables a reliable and durable connection between two components. The sintered layer is produced by a sintering process in which powder particles, a sintering paste, or a sintering film are melted by heat and pressure, thus creating a dense and homogeneous layer that, in particular, enables efficient heat transfer.The sintered layer can consist of various materials that are electrically conductive on the one hand and have good thermal properties on the other.

[0021] Preferably, a second sintered layer, a bond buffer layer, and a solder layer are arranged between the respective leadframe and the associated power semiconductor, extending from the respective power semiconductor. In other words, the bond buffer layer is arranged between the solder layer and the second sintered layer, with the solder layer being associated with the leadframe and the second sintered layer with the respective power semiconductor. The second sintered layer forms a dense, homogeneous bonding layer between the power semiconductor and the bond buffer. The bond buffer can be a copper layer. The solder layer forms a dense, homogeneous bonding layer between the bond buffer layer and the leadframe. Alternatively, the solder layer can be a sintered layer. Reference is made to the above descriptions, which are applicable analogously.

[0022] The bond buffer is a layer that reduces mechanical stress on the power semiconductor. It compensates for differing coefficients of thermal expansion between the leadframe and the power semiconductor. Furthermore, the bond buffer improves heat dissipation from the power semiconductor. This prevents temperature hotspots, thereby reducing stress on the power semiconductor and extending its lifespan. Consequently, the bond buffer layer further enhances the performance of the semiconductor package.

[0023] A solder layer is "softer" than a sintered layer and can therefore compensate for forces that can arise from so-called "thermal mismatch." Thermal mismatch refers to the situation where two components or materials have different coefficients of thermal expansion and therefore expand or contract differently with temperature changes. This can lead to stresses and deformations, especially when the materials or components are joined together. The thermal discrepancy can lead to cracks, delamination, or other damage. The solder layer is designed to compensate for this discrepancy. The solder layer can be designed according to the leadframe's configuration, particularly any cross-connectors or arm segments. The solder layer can be segmented and, in principle, have any surface geometry.

[0024] Preferably, exactly two signal pins are connected to the control terminal. In other words, exactly two signal pins are connected to the upper copper layer of the control terminal or the signal substrate. If only two signal pins are provided, these pins are used for gate control of the semiconductor package. The power semiconductors are controlled via the two signal pins, the upper copper layer of the signal substrate, and the connecting elements. The signal pins are connected to the power semiconductors for signal transmission.

[0025] In a further development of the invention, the control terminal is electrically connected to additional signal pins, which are electrically connected via additional connecting elements to a temperature sensor arranged on the upper copper layer of the ceramic substrate. When bond wires are used as connecting elements, two further bond wires are electrically connected between the upper copper layer of the signal substrate of the control terminal and the temperature sensor. The additional signal pins are connected to control the temperature sensor. The additional signal pins are connected to the temperature sensor for signal transmission. The temperature sensor can be connected to the upper copper layer of the ceramic substrate via a further first sintered layer in order to measure the temperature of the ceramic substrate.To simplify the design and / or if the temperature of the power semiconductors or other elements of the semiconductor package can be obtained by other means, the temperature sensor and the associated additional components can be omitted.

[0026] The semiconductor package preferably comprises two or more first power semiconductors and an identical number of second power semiconductors. In other words, the semiconductor package has the same number of first power semiconductors as second power semiconductors. One first load terminal is thus electrically connected to two or more first power semiconductors via the associated leadframe, while the other first load terminal is electrically connected to two or more second power semiconductors via the associated leadframe. Current scaling can be achieved by adjusting the number of chips. Preferably, six power semiconductors are provided, of which three are assigned to one of the first load terminals and the remaining three to the other first load terminal. The size or area of ​​the power semiconductors can also be adjusted to achieve current scaling.A surface area of ​​20, 25 or 32 mm is conceivable. 2 However, for reasons of current symmetry, it is advantageous if all power semiconductors have the same size or area, i.e., the same properties.

[0027] To further improve current symmetry, the first two power semiconductors are arranged in series and spaced apart, while the second two power semiconductors are arranged in series, with identical spacing between them and parallel to the first power semiconductors. Along the longitudinal direction of the semiconductor package, i.e., along the longer side of the rectangular ceramic substrate, the first and second power semiconductors maintain essentially constant distances from each other. Similarly, the first and second power semiconductors maintain a constant distance from each other in the transverse direction. With three first and three second power semiconductors, they are thus arranged in a 2x3 configuration on the upper ceramic layer of the ceramic substrate. The control terminal can be elongated and oriented essentially parallel to the two rows of power semiconductors.The control connection is located specifically between the two power semiconductor rows.

[0028] In the case of multiple first or second power semiconductors, the respective leadframe preferably has at least one cross-connector that connects the first load terminal to two first or two second power semiconductors, respectively. In other words, the leadframe of one first load terminal has at least one first cross-connector that connects two first power semiconductors to each other, and the leadframe of the other first load terminal has at least one second cross-connector that connects two second power semiconductors to each other.

[0029] Furthermore, the respective cross-connector preferably comprises one or more arm segments that are at least partially attached to the solder layer. Accordingly, the first cross-connector of the leadframe for one of the first load terminals has at least one first arm segment for electrically connecting the respective first load terminal to one of the first power semiconductors, and at least one second arm segment for electrically connecting the same first load terminal to another first power semiconductor. For each additional first power semiconductor, the first cross-connector of the leadframe can comprise at least one further arm segment to establish an electrical connection with the additional first power semiconductor. Two or more cross-connectors can also be provided to electrically connect the respective first load terminal to one or more power semiconductors.Everything said so far and below regarding one first load connection applies equally and analogously to the other first load connection, and vice versa. The first load connections are mirror images of each other.

[0030] To minimize the contact area between the leadframe and the power semiconductor, it is advantageous for the respective arm segment to be divided into several sections, with contact sections and connecting sections for linking two contact sections. In other words, the respective leadframe can be connected to the associated power semiconductor via several smaller areas. The connecting section acts as a bridge, thereby reducing the contact area with the chip and thus the stresses within the system. Preferably, the respective arm segment has at least two contact sections that make contact with the solder layer, with the two contact sections being connected to each other via the connecting section, which does not make contact with the solder layer.One of the implant sections is connected to the respective leadframe, while the other implant section forms a distal end of the respective arm segment.

[0031] To insulate the components of the semiconductor package, the package is encapsulated using injection molding. In other words, the semiconductor package is encapsulated in a so-called molding process. Molding is a process in which a plastic housing, consisting of insulating material, is formed around one or more power semiconductors. This encapsulation protects the power semiconductors from external influences such as moisture and dust. The molding process involves injecting liquid plastic as insulating material into a mold in which the components of the semiconductor package are placed. After the plastic has cured, the mold or tool is removed, thus protecting the semiconductor package. The semiconductor package is encapsulated, for example, using transfer or compression molding.

[0032] In transfer molding, a defined quantity of a molding material, typically a thermoset or thermoplastic, is poured through a sprue into a mold cavity. During transfer molding, the mold walls are typically heated to a temperature above the melting point of the molding material to ensure good flow properties within the cavity. A wide variety of thermoplastics and thermosets are suitable for transfer molding.

[0033] If the semiconductor package includes third load terminals, which are also assigned to the longer sides of the ceramic substrate and spaced apart from the first load terminals, at least one recess is formed in the insulating material between the first and third load terminals on the same side of the semiconductor package. The recess can be a bead, a step, or the like, formed or molded in the insulating material (also called the "mold") and is intended to create the necessary air and creepage distances. The respective recess is therefore advantageous for a compact design of the semiconductor package, as it allows the first and third load terminals on each side of the ceramic substrate to be positioned closer together without the load terminals negatively affecting each other.

[0034] In a further aspect of the invention, an electronic power module according to the invention comprises a heat sink on which several semiconductor packages according to one of the preceding claims are arranged. The lower copper layer of the ceramic layer of the respective semiconductor package can be connected to the heat sink, for example, by so-called nanowire technology, by sintering, soldering, or compression with an organic insulator. The lower copper layer can be directly connected to the heat sink. Alternatively, an insulating layer can be arranged between the lower copper layer and the heat sink.

[0035] Preferably, six semiconductor packages are arranged on the heat sink, with two semiconductor packages grouped together to form a half-bridge and connected in series. In an alternative embodiment, twelve semiconductor packages are arranged on the heat sink, with four semiconductor packages grouped together to form a half-bridge. The resulting half-bridges are preferably connected electrically in parallel. With six semiconductor packages, one semiconductor package is provided for each switching position. With twelve semiconductor packages, two semiconductor packages are provided for each switching position. Regardless of the number of semiconductor packages, all semiconductor packages can be arranged and cooled on a common heat sink, for example, a cooling plate or the like.

[0036] In another aspect of the invention, an electric drive axle, also called an e-axle, according to the invention comprises an electric machine and an electronic power module proposed therein. The electric machine is a three-phase electric machine. The power module is provided in a motor controller, which controls the electric machine. In addition to the electric machine, the electric drive axle can optionally include a transmission to provide torque and speed for driving a drive wheel of the motor vehicle. A motor controller can also be included in addition to the electric machine. The electric machine is supplied with electrical energy from an energy storage device.

[0037] In a further aspect of the invention, a motor vehicle according to the invention comprises an electric drive axle or an electronic power module according to the invention. The motor vehicle can, in particular, be a motorcycle, a passenger car, a truck, or a bus. The motor vehicle comprises at least two axles. Preferably, two axles are provided, wherein at least one of the axles is an electric drive axle and can be driven by at least one electric motor.

[0038] The above definitions and explanations regarding technical effects, advantages and advantageous embodiments of the semiconductor package according to the invention also apply mutatis mutandis to the power module according to the second aspect of the invention, to the electric drive axle according to the third aspect of the invention and to the motor vehicle according to the fourth aspect of the invention, and vice versa.

[0039] Where elements are designated by means of a number, for example "first component," "second component," and "third component," this numbering is solely for differentiation purposes and does not imply any dependency between the elements or a mandatory sequence. This means, in particular, that a device does not need to have a "first component" to be able to have a "second component." The device can also include a "first component" and a "third component" without necessarily having a "second component."

[0040] The invention will now be described in more detail with reference to the attached figures, in which: Fig. 1 a highly schematic view of a motor vehicle with an electric drive axle; Fig. 2 an exemplary motor control of the drive axle, comprising an electronic power module with half-bridges according to the invention; Fig. 3 a circuit diagram to illustrate the circuit of the electronic power module according to the invention Fig. 2; Fig. 4 a schematic view of the electronic power module according to the invention Fig. 2 and Fig. 3 with several semiconductor packages according to the invention; Fig. 5 a schematic perspective representation of an exemplary semiconductor package according to Fig. 4 according to a first embodiment; Fig. 6 a schematic exploded view of the semiconductor package according to Fig. 5; Fig. 7 a schematic perspective view of the semiconductor package according to Fig. 5 and Fig. 6 without showing the insulation material; Fig. 8 a schematic side view of the semiconductor package according to Fig. 5 to Fig. 7 without showing the insulation material; Fig. 9 a detailed cross-sectional view of the semiconductor package according to Fig. 8 to illustrate the electronic connection of a power semiconductor; Fig. 10 a detailed perspective view of the semiconductor package according to Fig. 5 to Fig. 9 to illustrate the electronic connection of a leadframe with power semiconductors; Fig. 11 a schematic top view of the semiconductor package according to a second embodiment without showing the insulating material; and Fig. 12 shows a schematic top view of the semiconductor package according to a third embodiment without showing the insulating material; wherein identical or similar components are provided with the same reference numeral.

[0041] Fig. Figure 1 shows an electric drive axle 100 in a motor vehicle 105. The motor vehicle 105 may additionally include an internal combustion engine 110, which is connected via a transmission 115 to a drive wheel 120 of the motor vehicle 105. In this case, the motor vehicle 105 would be a hybrid vehicle.

[0042] The electric drive axle 110 comprises an electric machine 125, which can also act on the drive wheel 120, preferably by means of the gearbox 115. Furthermore, a power converter 130 can be provided, which can be supplied with electrical energy from an electrical energy storage device 135. The electrical energy storage device 135 is preferably electrochemically constructed, but a fuel cell or another power source can also be used, for example. The power converter 130 is preferably configured to provide phase-shifted alternating currents to the electric machine 125. The electric machine 125 is implemented as a permanent magnet synchronous machine by way of example, but other embodiments are also possible. The supplied voltages and frequencies of the alternating currents can be determined such that the electric machine 125 converts a predetermined torque or rotates at a predetermined speed.A field-oriented control system can be implemented to control the direction and speed of rotation. The nominal voltage of the electrical energy storage device 135 is typically several hundred to over 1000 V. The current through the electric drive motor 125 can be several hundred A.

[0043] Fig. Figure 2 shows a motor controller 200 with a power module 202, comprising three half-bridges 205, which can be controlled by means of a common control device 210. The motor controller 200 is designed to control the rotational behavior of the electric machine 125 and typically operated digitally by means of a microcomputer.

[0044] Each half-bridge 205 comprises two semiconductor packages 212 according to the invention, divided into an upper semiconductor package 215 and a lower semiconductor package 220, wherein the semiconductor packages 212, 215, 220 are connected in series between DC potentials of the energy storage device 135 as shown. A DC link capacitor 225 is preferably provided between the potentials. A center tap 230 between the semiconductor packages 212, 215, 220 is connected to a corresponding phase of the electric machine 125. The upper semiconductor package 215 is located between a high potential of the energy storage device 135 and the center tap 230, and the lower semiconductor package 220 is located between the center tap 230 and a low potential of the energy storage device 135.

[0045] The semiconductor packages 212, 215, and 220 can be controlled independently, each acting like an electrical switch to close or open. The control unit 210 is configured to alternately close and open the semiconductor packages 212, 215, and 220, so that at no time are both semiconductor packages 215 and 220 of a half-bridge 205 closed. The voltage at the center tap 230 of the respective half-bridge 205 depends on the ratio of the on-times of the upper semiconductor package 215 and the lower semiconductor package 220. In normal operation of the electric machine 125, predetermined currents through the semiconductor packages 212, 215, and 220 can thus be controlled.

[0046] Fig. Figure 3 shows a circuit diagram of the semiconductor package 212, 215, 220 of the power module 202. Each semiconductor package 212, 215, 220 has two first load connections 300, 305, which are combined here into one connection called "Source" for simplicity, a second load connection 310, and two third load connections 315, 320, which are combined here into one connection called "Drain" for simplicity. The semiconductor package 212, 215, 220 also has two signal pins 325, 330 as control connections, which are intended for gate control. The "Gate" is the electrode between "Drain", i.e., the second and third load terminals 310, 315, 320, and "Source", i.e., the first load terminals 300, 305, and serves to control the switching behavior of the half-bridge 205. It enables the activation and deactivation of the semiconductor package 212, 215, 220 in the half-bridge 205.Between the load terminals 300 - 320, six parallel-connected power semiconductors 335, 340, 345, 350, 355, 360 are arranged, which can be controlled via the signal pins 325, 330.

[0047] In Fig. 4 is the electronic power module 202 according to Fig. Figure 2 shows a top view. The power module 202 comprises a heat sink 400 on which the six semiconductor packages 212, 215, 220 or the three half-bridges 205, each consisting of two semiconductor packages 215, 220 connected in series, are arranged. Each semiconductor package 212, 215, 220 is assigned as a discrete single package to a switching position of the power module 202. Alternatively, the power module 202 can also be arranged with twelve semiconductor packages 212, 215, 220 or six half-bridges 205 on the heat sink 400, with each pair of semiconductor packages 212, 215, 220 being assigned as discrete single packages to a switching position of the power module 202.

[0048] The semiconductor packages 212, 215, and 220 are identical regardless of their number; therefore, only an exemplary semiconductor package 212 is shown below. Fig. 5 ff. is shown and described. The other semiconductor packages 212, 215, 220 are designed analogously.

[0049] Fig. Figure 5 shows the semiconductor package 212 in its manufactured state as a separately handleable unit. Shown here are the aforementioned load connections 300-320, as well as, in addition to the previously mentioned signal pins 325 and 330 for gate control, two further signal pins 500 and 505, which will be discussed in more detail below.

[0050] The semiconductor package 212 is encapsulated by injection molding, with an insulating material 510 forming a housing for the semiconductor package 212 to protect the parts described below, where necessary, from interaction with each other and from external influences, in particular dirt and moisture. Fig. Figure 5 shows that a recess 515 in the form of a bead is formed in the insulating material 510 between each first load connection 300, 305 and a third load connection 315, 320 on the same longer side of the semiconductor package 212, which has a T-shaped cross-section and a rectangular top view, in order to provide the necessary air and creepage distance. This allows the distance between the load connections 300, 305, 315, 320 on the same side to be smaller, thus enabling a more compact design of the semiconductor package 212. In this sense, one of the third load connections 315, together with one of the first load connections 300, is assigned to one of the longer sides of the semiconductor package 212, with the other third load connection 320, together with the other first load connection 305, being assigned to the opposite side of the semiconductor package 212.The second load terminal 310 is assigned to the shorter side of the semiconductor package 212 that is farther away from the third load terminals 315 and 320, in order to achieve current symmetry within the semiconductor package 212. The two third load terminals 315 and 320 have the same potential as the second load terminal 310.

[0051] The load connections 300 - 320 each have a surface that lies in a plane with a surface of the insulating material 510, whereby the in Fig. The flat top surface of the semiconductor package 212 is formed as shown in Figure 5. The semiconductor packages 212, 215, and 220 of a half-bridge 205 are connected to each other, to a busbar arrangement (not shown here), and externally via the load connections 300-320.

[0052] According to Fig. 6 and Fig. 7 The semiconductor package 212 comprises a ceramic substrate 600 that is essentially rectangular in plan view, which, like Fig. As can be seen more clearly in Figure 8, a ceramic layer 800 is located between a lower copper layer 805 and an upper copper layer 810. Furthermore, the semiconductor package 212 includes a control terminal 605, which is electrically connected to signal pins 325 and 330 for controlling the semiconductor package 212, signal pins 500 and 505 for signal transmission to a temperature sensor (not shown here), and to the power semiconductors 335–360 via bond wires 610.

[0053] Each of the following is assigned to one of the longer sides of the ceramic substrate 600: a first load connection 300, 305 and a third load connection 315, 320. The second load connection 310 is assigned to one of the shorter sides of the ceramic substrate 600. On the upper copper layer 810, according to Fig. 7 Several first sintered layers 700 are applied to directly electrically connect the upper copper layer 810 of the ceramic substrate 600 to the second load terminal 310, the third load terminals 315, 320, the control terminal 605, and the power semiconductors 335-360. The load terminals 300-320 can be stamped from a sheet of metal as a grid and formed into the desired shape.

[0054] In this context, the power semiconductors 335, 340, 345 of the row of three arranged to the left of the control terminal 605 are to be understood as the first power semiconductors, which are assigned to the left first load terminal 300. The power semiconductors 350, 355, 360 of the row of three arranged to the right of the control terminal 605 are to be understood as the second power semiconductors, which are assigned to the right first load terminal 305. Thus, the semiconductor package 212 comprises three first power semiconductors 335, 340, 345 and an identical number of second power semiconductors 350, 355, 360. The three first power semiconductors 335, 340, 345 are arranged in series and spaced apart from each other, with the three second power semiconductors 350, 355, 360 arranged in series and at identical distances from each other and in parallel to the first power semiconductors. Therefore, the power semiconductors 335 - 360 are arranged in a 2x3 arrangement on the ceramic substrate 600.The power semiconductors 335-360 are identical in design and have the same size and area. The proposed design of the semiconductor package 212 allows for current symmetry, ensuring that all power semiconductors 335-360 are supplied with essentially uniform current, thereby optimizing the performance of the semiconductor package 212.

[0055] Each first load connection 300, 305 comprises a leadframe 615, 620, which is designed as a connecting arm to electrically connect the respective first load connection 300, 305 at least indirectly to the upper copper layer 810. Fig. Figure 9, which exemplifies the layer structure between the leadframe 615 of the first load terminal 300 and one of the associated first power semiconductors 335, shows, starting from the upper copper layer 810 of the ceramic substrate 600, i.e., from bottom to top, a first sintered layer 700, then the first power semiconductor 335, then a second sintered layer 900, then a bond buffer layer 905 (formed as a copper layer), then a solder layer 910, and finally the leadframe 615. Thus, the leadframe 615 is soldered onto the first power semiconductor 335. The connection between the leadframes 615, 620, and the other power semiconductors 340–360 is implemented analogously.

[0056] The design of the leadframes 615 and 620 is described below. Fig. 7 and Fig. As described in Figure 10, the leadframe 615 of the left first load terminal 300 has two cross-connectors 705 and 710 to connect the left first load terminal 300 to the three first power semiconductors 335, 340, and 345 to the left of the control terminal 605. The leadframe 620 of the right first load terminal 305, mirroring the leadframe 615 of the left first load terminal 300, also has two cross-connectors 705 and 710 to connect the right first load terminal 305 to the three second power semiconductors 350, 355, and 360 to the right of the control terminal 605.

[0057] Each cross connector 705, 710 has three arm segments 715, 720, 725, which are attached section by section to an associated, in Fig. The solder layer 910 of the respective power semiconductor 335-360 shown in Figure 9 is applied to the system. The solder layers 910 are formed here in parallel strips. The solder layers 910 are adapted to the design of the arm segments 715, 720, and 725. The solder layers 910 can be formed segmentally, i.e., with interruptions. To achieve or improve the desired current symmetry, they extend according to Fig. 7. Using the example of the power semiconductor array arranged to the left of the control terminal 605, two arm segments 715, 720 of the first cross-connector 705 extend to the first (335) of the three first power semiconductors, and another arm segment 725 extends to the second (340) of the three first power semiconductors. Two arm segments 715, 720 of the second cross-connector 710 extend to the third (345) of the three first power semiconductors, and another arm segment 725 also extends to the second (340) of the three first power semiconductors. Thus, the same area of ​​the left first load terminal 300 is present at each first power semiconductor 335, 340, 345, and the power semiconductors 335, 340, 345 can be energized evenly.

[0058] Fig. Figure 10 further illustrates the design of the respective arm segment 715, 720, 725, using the example of the second cross-connector 710 of the leadframe 615 of the left first load connection 300. Each arm segment 715, 720, 725 is divided into several sections: two assembly sections 1000, 1005 for contacting the leadframe 615 with the solder layer 910, and a connecting section 1010 that joins the two assembly sections 1000, 1005 in one piece. This connecting section 1010 does not contact the solder layer 910 and is designed as a bridge. This minimizes the contact area between the leadframe 615 and the first power semiconductors 335, 340, 345, thereby reducing the stress on the first power semiconductors 335, 340, 345.

[0059] To avoid unnecessary repetition, it is expressly pointed out that the first load connection 305, located to the right of the control connection 605, with the leadframe 620 formed thereon and the cross connectors 705, 710 and arm segments 715, 720, 725 encompassed therein, is essentially a mirror image of the previously described left first load connection 300. Therefore, what has been said about the left first load connection 300 applies analogously to the right first load connection 310.

[0060] Out of Fig. Figure 8 shows that the control terminal 605 has a multi-layered structure. The control terminal 605 can be understood as a gate rotor or signal substrate that forwards signals, which are fed into the semiconductor package 212 via the signal pins 325 and 330, to the power semiconductors 335–360 via the connecting elements 610. The control terminal 605 has a ceramic layer 815, which is arranged between a further lower copper layer 820 and a further upper copper layer 825. The lower copper layer 820 is electrically connected to the upper copper layer 810 of the ceramic substrate 600 via a first sintered layer 700. The aforementioned connecting elements 610 are directly electrically connected to the upper copper layer 825 of the control terminal 605, with each pair of connecting elements 610 contacting one of the power semiconductors 335–360.

[0061] The upper copper layer 825 of the control terminal 605 is according to Fig. 7. The upper copper layer 825 of the control terminal 605 is segmented. In other words, the upper copper layer 825 of the control terminal 605 consists of several segments. The design of the segments depends on the requirements of the control terminal 605. As already indicated, the control terminal 605 is also electrically connected to two further signal pins 500, 505, which are electrically connected via connecting elements (not shown here) – which, analogous to the other connecting elements 610, can be designed as bond wires – to a temperature sensor arranged on the upper copper layer 810 of the ceramic substrate 600. The temperature sensor is also not shown here. Fig. Figure 7 shows a further first sintered layer 700 in the upper right corner of the ceramic substrate 600 in the area of ​​the second load connection 310, on which the temperature sensor can be arranged. The connecting elements 610 for connecting the control connection 605 to this first sintered layer 700 are shown in Fig. 12 indicated.

[0062] Fig. Figure 11 shows an alternative implementation of the semiconductor package described above. Fig. 5 to Fig. 10, whereby only the differences in this regard will be discussed below. As in Fig. As can be seen in Figure 11, the temperature sensor, and consequently the associated control pins 500 and 505, the connecting elements, and the additional first sintered layer 700, can be omitted if the temperature of the semiconductor package 212 is determined or measured by other means. This simplifies the design of the semiconductor package 212.

[0063] Fig. Figure 12 shows another possible implementation of the semiconductor package described above. Fig. 5 to Fig. 10, whereby only the differences in this regard will be discussed below. In the present case, the semiconductor package 212 has only four power semiconductors 335, 345, of which two are assigned to one first load terminal 300 and the other two first load terminals 350, 360 are each assigned to the other first load terminal 305. Depending on the requirements of the semiconductor package 212, according to Fig.12, therefore, individual power semiconductors can be omitted. For reasons of current symmetry, the number of first power semiconductors must always be identical to the number of second power semiconductors. The semiconductor package 212 can be adapted to the given requirements using simple means. In this example, one first or second power semiconductor 340, 355, is omitted, in this case the middle one. This also simplifies the design of the leadframes 615, 620. Likewise, the number of first or second power semiconductors can be increased equally, so that, for example, eight, ten, or more power semiconductors are arranged on the upper copper layer 810 of the ceramic substrate 600 and connected to the control terminal 605. Reference sign 100 electric drive axle 105 motor vehicles 110 internal combustion engine 115 gearbox 120 drive wheel 125 electric machine 130 power converters 135 energy storage 200 engine control 202 Power Module 205 Half-bridge 210 Control device 212 Semiconductor package 215 upper semiconductor package 220 lower semiconductor package 225 Intermediate circuit capacitor 230 Center tap 300 First load connection 305 First load connection 310 Second load connection 315 Third load connection 320 Third load connection 325 Signal pin for gate control 330 Signal pin for gate control 335 First power semiconductor 340 First power semiconductor 345 First power semiconductor 350 Second power semiconductor 355 Second power semiconductor 360 Second power semiconductor 400 heat sinks 500 signal pin for temperature sensor 505 Signal pin for temperature sensor 510 Insulation material 515 Recess 600 ceramic substrate 605 Control connection 610 Connecting element 615 Leadframe 620 Leadframe 700 First sintered layer 705 First cross connector 710 Second cross connector 715 First arm segment 720 Second arm segment 725 Third arm segment 800 ceramic layer of the ceramic substrate 805 Lower copper layer of the ceramic substrate 810 Upper copper layer of the ceramic substrate 815 Ceramic layer of the control port 820 Lower copper layer of the control terminal 825 Upper copper layer of the control terminal 900 Second sintered layer 905 Bond buffer layer 910 solder layer 1000 First section of the arm segment 1005 Second section of the arm segment 1010 Connecting section of the arm segment

Claims

[1] Semiconductor package (212, 215, 220) for an electronic power module (202), comprising a ceramic substrate (600) having a ceramic layer (800) between a lower copper layer (805) and an upper copper layer (810), two first load terminals (300, 305) each with a leadframe (615, 620), wherein one of the first load terminals (300) is associated with at least one first power semiconductor (335) and the other first load terminal (305) is associated with at least one second power semiconductor (350), and wherein the respective power semiconductor (335, 350) is arranged between the upper copper layer (810) of the ceramic substrate (600) and the leadframe (615, 620) of the associated first load terminal (300, 305) and is electrically connected to them, a second load terminal (310) which is connected to the upper copper layer (810) is electrically connected, two third load connections (315, 320),which have the same potential as the second load terminal (310) and which are each electrically connected to the upper copper layer (810) of the ceramic substrate (600), a control terminal (605) which is electrically connected to signal pins (325, 330) for controlling the semiconductor package (212, 215, 220) and via connecting elements (610) to the power semiconductors (335, 350), wherein the ceramic substrate (600) is rectangular, and wherein a first load terminal (300, 305) is assigned to each of the longer sides and the second load terminal (310) to each of the shorter sides of the ceramic substrate (600), and a third load terminal (315, 320) is assigned to each of the longer sides of the ceramic substrate (600). [2] Semiconductor package (212, 215, 220) according to claim 1, wherein first sintered layers (700) are applied to the upper copper layer (810) of the ceramic substrate (600) to at least electrically connect the upper copper layer (810) to the second load terminal (310), to the control terminal (605) and to the power semiconductors (335, 350). [3] Semiconductor package (212, 215, 220) according to one of the preceding claims, wherein a second sintered layer (900), a bond buffer layer (905) and a solder layer (910) are arranged between the respective leadframe (615, 620) and the associated power semiconductor (335, 350) starting from the respective power semiconductor (335, 350). [4] Semiconductor package (212, 215, 220) according to one of the preceding claims, wherein the control terminal (605) is electrically connected to further signal pins (500, 505) which are electrically connected via connecting elements to a temperature sensor arranged on the upper copper layer (810). [5] Semiconductor package (212, 215, 220) according to any of the preceding claims, comprising two or more first power semiconductors (335, 340, 345) and an identical number of second power semiconductors (350, 355, 360). [6] Semiconductor package (212, 215, 220) according to one of the preceding claims, wherein the at least two first power semiconductors (335, 340, 345) are arranged in series and spaced apart from each other, and wherein the at least two second power semiconductors (350, 355, 360) are arranged in series and with identical distances from each other and parallel to the first power semiconductors (335, 340, 345). [7] Semiconductor package (212, 215, 220) according to claim 5 or claim 6, wherein the respective leadframe (615, 620) comprises at least one cross-connector (705) connecting the first load terminal (300, 305) to two first or two second power semiconductors (335, 340, 345, 350, 355, 360). [8] Semiconductor package (212, 215, 220) according to claim 7 in conjunction with claim 3, wherein the respective cross connector (705) comprises one or more arm segments (715) which come into contact with the solder layer (900) at least section by section. [9] Semiconductor package (212, 215, 220) according to any of the preceding claims, wherein the semiconductor package (212, 215, 220) is encapsulated by injection molding. [10] Semiconductor package (212, 215, 220) according to claim 9, wherein at least one recess (515) is formed spatially between the first and third load terminals (300, 305, 315, 320) of the same side of the semiconductor package (212, 215, 220) in the insulating material (510). [11] Electronic power module (202) for a motor control (200), comprising a heat sink (400) on which several semiconductor packages (212, 215, 220) are arranged according to one of the preceding claims. [12] Electronic power module (202) according to claim 11, wherein six semiconductor packages (212, 215, 220) are arranged on the heat sink (400), wherein two semiconductor packages (212, 215, 220) are combined to form a half bridge (205) and are connected in series. [13] Electronic power module (202) according to claim 11, wherein twelve semiconductor packages (212, 215, 220) are arranged on the heat sink (400), wherein four semiconductor packages (212, 215, 220) are combined to form a half bridge (205). [14] Electric drive axle (100) comprising an electric machine (125) and an electronic power module (202) according to one of claims 11-13. [15] Motor vehicle (105) comprising an electric drive axle (100) according to claim 14.

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