ELECTRONIC SYSTEM WITH AN INTEGRATED MASTER CIRCUIT AND AN INTEGRATED SLAVE CIRCUIT

Abstract

The present disclosure relates to an electronic system (200) comprising a master IC (110), a slave IC (120), and a serial communication interface (230) having a bidirectional data line and a clock line, wherein the communication interface (230) is configured to transmit data between the master IC (110) and the slave IC (120). The master IC (110) is configured to send a data request command (140; 144) to the slave IC (120) via the data line. The slave IC (120) is configured to begin providing requested data (160) in response to the data request command (140; 144). The master IC (110) is designed to send a data read command (150; 152) for reading the requested data (160) to the slave IC (120) via the data line after the data request command (140; 144).The slave IC (120) is configured to deactivate the clock line upon receipt of the data read command (150; 152) until the slave IC (120) can provide the requested data (160). The master IC (110) is configured to measure a time duration for which the clock line is deactivated. The master IC (110) is configured to set a waiting time between a next data request command (140; 144) and a next data read command (150; 152) according to the measured time duration.

Description

Technical FieldThe present disclosure relates to electronic systems including a master integrated circuit (master IC) and a slave IC. A serial communication interface having a bidirectional data line and a clock line is configured to transfer data between the master IC and the slave IC. The serial communication interface may be I 2 C (Inter-Integrated Circuit).BackgroundI 2 C denotes a serial data bus which has developed into a widely accepted industry standard. It can be used internally in the device for communication between various circuit parts, for example within a television set or between a controller and peripheral ICs.I 2 C is designed as a master-slave bus. A data transfer can be initiated by a master (controller); a slave (target) addressed via an address responds to this. Multiple controllers are possible (multi-controller operation). In multi-controller operation, if a controller package also operates as a target, another controller may communicate directly with it by responding to it as a target.One property of I 2 C is that a microcontroller can control an entire network of integrated circuits with only two I / O pins and simple software. Buses of this type have been realized because a considerable part of the cost of an integrated circuit and a printed circuit board used depends on a size of the package and a number of pins. A large IC package has more pins, requires more space on the circuit board, and has more connections that can fail. All this increases production and test costs.Although slower than newer bus systems, I 2 C may be advantageous for peripherals that do not need to be fast because of the low cost. I 2 C can be used for transmission of control and configuration data. Examples are volume regulators, low-sampling-rate analog-to-digital or digital-to-analog converters, real-time clocks, small, non-volatile memories or bidirectional switches and multiplexers. Electronic sensors can also have an analog-to-digital converter with an I 2 C interface integrated.When I 2 C is used, opposite requirements may arise. For example, there may be a need to immediately read data (e.g., measurement data) when available on the sensor side. There may be a need for lower power consumption of the system. There may be a need for inexpensive I 2 C-slave ICs without additional interrupt pins. Further, there may be a need for increased I 2 C bandwidth.SummaryOne or more of the above needs is addressed by apparatus and methods according to the independent claims. Advantageous further developments are addressed by the dependent claims.According to a first aspect, an electronic system is proposed. The electronic system includes a master integrated circuit (master IC) and a slave IC. The electronic system further includes a serial communication interface having a bidirectional data line and a clock line. The communication interface is configured to transmit data between the master IC and the slave IC. The master IC is designed to send a data request command to the slave IC via the data line. The slave IC is configured to start providing requested data in response to the data request command. The master IC is configured to send a data read command for reading out the requested data to the slave IC via the data line after the data request command. The slave IC is configured to deactivate the clock line after receiving the data read command until the slave IC can provide the requested data. The master IC is designed to measure a time duration of the deactivation of the clock line. The master IC is configured to set a waiting time between a next data request command and a next data read command according to the measured time duration.According to some exemplary embodiments, the master IC is designed to send the data read command to the slave IC after a specified minimum data provision time has elapsed since the data request command. If the requested data is not yet completely available after the specified minimum data provision time, the slave IC is designed to deactivate the clock line until the slave IC can provide the requested data. The master IC is configured to measure the time period of deactivation of the clock line and set the waiting time between the next data request command and the next data read command according to the minimum data provision time and the measured time period.According to some embodiments, the master IC is configured to maintain the wait time for a plurality of next data request commands and next data read commands, and thereafter determine an updated wait time according to one of the described embodiments.According to some exemplary embodiments, the master IC is designed to use the set waiting time for a data request command and the subsequent data read command and, after that, to successively reduce the waiting time between the data request command and the data read command until renewed deactivation of the clock line is detected by the slave IC in order to be able to provide the requested data on the data line.According to some embodiments, the master IC is configured to measure the time period of re-deactivation of the clock line and set a re-updated wait time between the next data providing command and the subsequent data read command according to the measured time period.According to some embodiments, the master IC comprises a microcontroller.According to some embodiments, the slave IC includes a sensor IC, such as a magnetic field sensor IC. The magnetic field sensor IC can comprise a 3D Hall sensor IC.According to some embodiments, the serial communication interface includes an I 2 C communication interface.According to a second aspect, a communication method for an electronic system is proposed, which comprises a master IC and a slave IC. The electronic system further includes a serial communication interface having a bidirectional data line and a clock line for transferring data between the master IC and the slave IC. The communication method includes sensing a data request command from the master IC to the slave IC via the data line. The communication method includes starting to provide requested data from the slave IC in response to the data request command. The communication method includes, after the data request command from the master IC to send a data read command to the slave IC via the data line to read out the requested data. The communication method includes, after receiving the data read command, disabling the clock line from the slave IC until the slave IC can provide the requested data. The communication method from the master IC to measure a time period of deactivation of the clock line. The communication method includes setting, from the master IC, a waiting time between a next data request command and a next data read command according to the measured time duration.According to another aspect, an integrated circuit (IC) is proposed. The IC includes a serial communication interface having a bidirectional data line and a clock line. The communication interface is configured to transmit data between the IC and another IC via the data line. The IC also includes a processor configured to transmit a data request command to the further IC via the data line, to transmit a data read command to the further IC via the data line after a wait time after the data request command, to measure a time duration of deactivation of the clock line by the further IC after the data read command, and to update the wait time between a next data request command and a subsequent data read command according to the measured time duration.According to some embodiments, the processor is configured to send the data read command to the further IC after a specified minimum data provision time has elapsed since the data request command.According to some embodiments, the processor is configured to maintain the updated wait time for a plurality of next data request commands and data read commands, and thereafter determine a re-updated wait time.According to some embodiments, the processor is configured to use the updated wait time for the next data request command and the next data read command and thereafter to successively reduce the wait time between the data request command and the data read command until a renewed deactivation of the clock line is detected by the further IC.According to some exemplary embodiments, the IC is designed as a microcontroller.According to some embodiments, the data provision command includes a command to measure sensor data to a sensor IC.Brief Description of the FiguresSome examples of devices and / or methods are explained in more detail below with reference to the attached figures, merely by way of example. The following are shown: FIG. 1A shows an example of an electronic system with a master IC and a slave IC; FIG. 1B shows an example of a data request command and a data read command; FIG. 2A shows another example of an electronic system having a master IC and a slave IC; FIG. 2B illustrates another example of a data request command and a data read command with clock stretching; FIG. 3 shows another example of a data request command and a data read command having a long wait time; FIG. 4 shows an exemplary embodiment of a communication between master IC and slave IC; FIG. 5 shows a further exemplary embodiment of a communication between master IC and slave IC; FIG. 6 shows a further exemplary embodiment of a communication between master IC and slave IC; FIG. 7 shows a further exemplary embodiment of a communication between master IC and slave IC; and FIG. 8 shows a communication method between a master IC and a slave IC according to an embodiment.DESCRIPTION OF THE INVENTIONSome examples will now be described in more detail with reference to the accompanying figures. However, other possible examples are not limited to the features of these embodiments described in detail. These may include modifications of the features, as well as equivalents and alternatives to the features. Further, the terminology used herein to describe certain examples is not intended to be limiting of other possible examples.The same or similar reference numerals refer to the same or similar elements or features throughout the description of the figures, which can each be implemented identically or in modified form, while providing the same or a similar function. In the figures, the thicknesses of lines, layers, and / or regions may be exaggerated for clarity.When two elements A and B are combined using one "or", it is to be understood that all possible combinations are disclosed, i.e., only A, only B, and A and B, unless expressly defined otherwise in the individual case. As an alternative formulation for the same combinations, "at least one of A and B" or "A and / or B" may be used. This applies equivalently to combinations of more than two elements.Where a singular form, e.g., "a," and "the," is used and the use of only a single element is not expressly or implicitly defined as obligatory, further examples may also use multiple elements to implement the same function. When a function is described below as being implemented using multiple elements, further examples may implement the same function using a single element or a single processing entity. It will be further understood that the terms "comprises," "comprising," "comprises," and / or "comprising," when used, describe the presence of stated features, integers, steps, operations, processes, elements, components, and / or a group thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, processes, elements, components, and / or a group thereof.FIG. 1A shows an electronic system 100 having a master IC 110 and a slave IC 120. The master IC 110 is designed as a microcontroller (μC), the slave IC 120 is designed as a sensor IC in the example shown. Other implementations of the slave IC 120, such as a display module, real time clock (RTC), etc., are also possible.Master IC 110 and slave IC 120 are connected to each other via a serial communication interface 130. The serial communication interface 130 may be an I 2 C-bus communication interface. The I 2 C-bus communication interface 130 includes a bidirectional data line (SDA) and a clock line (SCL) between the master IC 110 and the slave IC 120. In the example shown, an interrupt line (INTN) is additionally present between master IC 110 and slave IC 120.The master IC or microcontroller 110 is an electronic component which acts as a host or master device in an I 2 C-bus system. Microcontroller 110 provides control and coordination of communication between various I 2 C-enabled components, referred to as slaves. The tasks of microcontroller 110 in the I 2 C system may include, for example:Initiate communication: Microcontroller 110 starts communication by selecting the desired slave device, e.g., slave IC 120, on the I 2 C bus and beginning communication.Sending commands and data: Microcontroller 110 sends commands or data to the selected slaves, e.g., slave IC 120, to perform certain actions or to retrieve information.Receiving data: Microcontroller 110 may receive data from the slaves, e.g., slave IC 120, to collect information or monitor the status of the slaves.Handling errors and conflicts: Microcontroller 110 may be able to detect collisions or conflicts on the I 2 C bus and take appropriate action to ensure that communication can continue.Stopping communication: At the end of communication, microcontroller 110 may stop transmission and enable the I 2 C bus for other devices.The microcontroller 110 may thus play a central role in controlling and coordinating I 2 C communication in the electronic system 100 and may enable the connection and interaction of various components, such as sensors, displays, memory chips, and other peripheral devices.The microcontroller 110 can start communication in the I 2 C protocol by generating a so-called "start condition" (S) 141 on the I 2 C bus. This is shown in FIG. 1B. The "start condition" (S) 141 may be part of a command 140 the first step to establish a connection to one or more I 2 C slave devices, e.g., slave IC 120. The start condition 141 may signal the beginning of a new transmission. The microcontroller 110 can start communication as follows:Transmit a start condition (start condition) 141: Microcontroller 110 may for this purpose pull data line (SDA), for example, from HIGH to LOW, while clock line (SCL) remains, for example, at HIGH. This generates a start condition that is recognized by all I 2 C devices, e.g., slave IC 120, on the bus.Address Transfer 142: After the start condition is generated, the microcontroller 110 may, for example, send a 7-bit address of the slave device, e.g., slave IC 120, with which it wishes to communicate. The eighth bit of the address byte may indicate whether microcontroller 110 wishes to send data to slave device 120 (0) or to receive data 160 from slave device 120 (1). In the latter case and in the case of the absence of the data, the command 140 can be understood, for example, as a data request command to the slave device 120.Wait for Acknowledgement (ACK / NACK): After transmitting the address 142, the microcontroller 110 may expect an acknowledgement (ACK) from the slave IC 120. An ACK may be a short LOW level on the data line (SDA) signaling that the slave IC 120 is reachable. If the slave IC 120 is unavailable, it sends a NACK (Not Acknowledge) instead of the ACK, and the microcontroller 110 may take appropriate action, e.g., abort communication.Continuing communication: After the ACK is received, microcontroller 110 may either send data 143 to slave device 120 or receive data from slave device 120, depending on the purpose of the communication.Ending communication: At the end of communication, microcontroller 110 may send a stop condition (STOP CONDITION) 144 by pulling data line (SDA) from low to high, for example, while the clock line remains high, for example. This signals the end of the transmission.An exact sequence of these steps may vary depending on the requirements of the communication. Microcontroller 110 may be responsible for controlling these steps and ensure that communication is correct and reliable.In the example shown in FIG. 1B, the stop condition 144 of the data request command 140 triggers a measurement of the sensor IC 120. Thus, the stop condition (possibly together with the eighth bit of the address byte) can also be understood as a data request command to the sensor IC 120. In response to the data request command 140, the sensor IC 120 may begin measuring the required data 160. This may include the acquisition of information such as temperature, pressure, humidity, light intensity, or other physical parameters. For example, the sensor IC 120 can be designed as a 3D magnetic field sensor and measure x-, y- and z-coordinates. If necessary, the sensor IC 120 may also have a temperature sensor and provide a temperature measurement value.In the example shown in FIGS. 1A and 1B, an interrupt line (INTN) is provided between master IC 110 and slave IC 120, which interrupt line can be pulled from HIGH to LOW (or vice versa), for example, by sensor IC 120 as soon as measured data 160 are available in sensor IC 120. After signaling the interrupt from the sensor IC 120, the sensor IC 120 can transmit the measured data on request from the microcontroller 110. Data 160 may be sent back to microcontroller 110 via the I 2 C bus.Microcontroller 110 may read data 160 from sensor IC 120 as follows:After the interrupt, microcontroller 110 may again send a start condition (start condition) 151 as part of a command 150. For this purpose, microcontroller 110 may pull data line (SDA) from HIGH to LOW, for example, while clock line (SCL) remains at HIGH, for example. This generates a start condition that is recognized by all I 2 C devices, e.g., slave IC 120, on the bus.Address Transfer 152: After generating the start condition, microcontroller 110 may send the slave device's 7-bit address, e.g., slave IC 120, from which it wants to read the data. The eighth bit of the address byte indicates whether the microcontroller wishes to receive data from the slave device (1). In the latter case and in the case of the presence of the data 160, the command 150 can be understood, for example, as a data read command to the slave device 120.Wait for Acknowledgement (ACK / NACK): After sending address 152, microcontroller 110 awaits an acknowledgement (ACK) from slave IC 120. An ACK is a short LOW level on the data line (SDA) signaling that the slave IC 120 is reachable. If the slave IC 120 is unavailable, it sends a NACK instead of the ACK, and the microcontroller 110 may take appropriate action, e.g., abort communication.Continuing communication: After the ACK is received, the microcontroller 110 may receive the data 160 from the slave device 120.Ending communication: At the end of communication, microcontroller 110 sends a stop condition 154 by pulling data line (SDA) from LOW to HIGH, for example, while the clock line remains at HIGH, for example. This signals the end of the transmission.The stop condition 154, like the stop condition 144, can trigger the measurement of new sensor data 160 so that the stop conditions 144, 154 can also be understood as a data request command and the eighth bit of the address byte 142, 152 as a data read command.In the example described with reference to FIGS. 1A and 1B, the data 160 can be read by the slave device 120 in a time-optimized manner on account of the interrupt as soon as they are available. This means a comparatively high communication bandwidth and a low power consumption. However, the disadvantage of this is the additional hardware outlay for the interrupt line (INTN) between master IC 110 and slave IC 120.A possible implementation of the data exchange via the I 2 C bus 130 between master IC 110 and slave IC 120 without the interrupt line (INTN) is shown in FIGS. 2A and 2B. FIG. 2A shows an electronic system 200 having a master IC 110 and a slave IC 120. In contrast to the example of FIGS. 1A and 1B, there is no interrupt line between master IC 110 and slave IC 120 here.As in the example of FIGS. 1A and 1B, the master IC 110 is designed to send a data request command 140 or 144 to the slave IC 120 via the data line (SDA). The slave IC 120 is designed to begin the provision (measurement) of the requested data 160 in response to the data request command 140 or its stop condition 144. Immediately after the data request command 140 or its stop condition 144, the slave IC 120 starts providing or measuring the requested data 160. In this example, master IC 110 is configured to send data read commands 150 and 152 to sensor IC 120 for reading out the requested data while measuring data 160 (i.e., before they are ready). The slave IC 120 is configured to deactivate the clock line (SCL) after receiving the eighth bit of the address byte (data read command) 152 until the slave IC 120 can provide the requested data 160. This concept is known as "clock stretching" (clock expansion). The I 2 C communication protocol is a technique in which the slave device 120 may temporarily "stretch" the clock line (SCL) to slow or stop transmission when it is not ready to pass data 160."Clock Stretching" can function as follows:Normal clock cycle: In the I 2 C protocol, there is the master IC 110 that controls the clock (SCL) and data (SDA), as well as one or more slave ICs 120 that respond to requests from the master IC 110. The clock cycle is normally controlled by the master IC 110 and communication occurs synchronously with this clock.Clock cycle with clock stretching: If the slave IC 120 is not ready to send (or receive) data 160, it may temporarily "stretch" the clock cycle by pulling the clock line (SCL) low, for example. This signals the master IC 110 that the slave IC 120 requires more time to prepare or process the data 160. Master IC 110 detects the clock stretching signal of slave IC 120 and waits until the clock line (SCL) returns high. During clock stretching, the master IC 110 remains inactive and gives the slave IC 120 the time required to complete its tasks. Once the slave IC 120 is ready, it resets the clock line (SCL) back to HIGH and communication may continue. The master IC 110 continues the clock cycle and data transfer can be done as usual."Clock Stretching" is a function in the I 2 C protocol because it allows the slave devices 120 to slow or stop communication if they are unable to process data in real time. This is particularly useful in applications where the slave devices 120 may not operate as fast as the master 110, or when there are unpredictable delays. Clock stretching allows the I 2 C communication to be more reliable and robust with respect to delays.In the examples described with reference to FIGS. 2A and 2B, the data 160 may also be read by the slave device 120 once ready. This means a comparatively high communication bandwidth. However, a disadvantage of this is a high current consumption, since current can flow from the supply VDD to ground during clock stretching through the clock line (SCL) pulled to LOW in the manner shown in FIG. 2A. Furthermore, parallel communication between master 110 and other slaves is also not possible.FIG. 3 shows a further communication possibility between master 110 and slave 120, in which neither the interrupt line (INTN) nor "clock stretching" is required.As in previous examples, the master IC 110 is configured here to send a data request command 140, 144 to the slave IC 220 via the data line (SDA). The slave IC 220 is configured to immediately begin the provision (measurement) of the requested data 160 in response to the data request command 140, 144. In this example, however, the master IC 110 is designed to send the data read command 150, 152 for reading out the requested data to the sensor IC 220 after a longer, permanently defined waiting time T. In this case, the waiting time T between data request command 140 and data read command 150 can be selected to be so long that it overcomes the data provision time (measurement time) and also takes into account possible oscillator variations on the clock line (SCL). This can lead to long waiting times and thus to a comparatively low communication bandwidth.In view of the disadvantages of the examples described above, the present disclosure proposes an electronic system 200 having master IC 110 and at least one slave IC 120. The electronic system 200 further includes a serial communication interface 230 having a bidirectional data line (SDA) and a clock line (SCL). The communication interface 230 is configured to transmit data between the master IC 110 and the slave IC 120. The master IC 110 is configured to send a data request command 140, 144 to the slave IC 120 via the data line (SDA). The slave IC 120 is configured to begin providing (e.g., measuring) requested data 160 in response to the data request command 140, 144. The master IC 110 is configured to send a data read command 150, 152 for reading out the requested data 160 via the data line (SDA) to the slave IC 120 after the data request command 140, 144. After receiving the data read command 150, 152, the slave IC 120 is configured to deactivate the clock line (SCL) by means of clock stretching until the slave IC 120 can provide the requested data 160. According to proposed exemplary embodiments, the master IC 110 is designed to measure a time duration of the deactivation of the clock line or a time duration of the clock stretching. According to proposed embodiments, the master IC 110 is configured to set a waiting time between at least a next data request command 154 and a next data read command according to the measured time duration. This is illustrated in FIG. 4.The proposed procedure therefore corresponds to a combination of the approaches that were described with reference to FIGS. 2B and 3.The master IC 110 is configured to transmit the data request command 144 to the slave IC 120 via the data line (SDA). The slave IC 120 is configured to start providing (measuring) the requested data 160 in response to the data request command 144. Immediately after the data request command 144, the slave IC 120 starts to provide the data 160. Master IC 110 is configured to send data read command 152 to sensor IC 120 for reading out the requested data during the measurement or immediately after data request command 144. A time between data request command 144 and data read command 152 is therefore less than a measurement duration to be expected. The slave IC 120 is configured to deactivate (clock stretching) the clock line (SCL) after receiving the data read command 152 until the slave IC 120 can provide the requested data 160 (after the measurement duration). The master IC 110 is configured to measure the time duration of the clock stretching and to set the waiting time between the next or subsequent data request command 144, 154 and a next data read command 142, 152 based on the measured time duration of the clock stretching. Clock stretching is then no longer necessary between subsequent data request commands 144, 154 and subsequent data read commands 142, 152 on account of the set suitable waiting time.The step marked (1) in FIG. 4 refers to clock stretching (Clock Stretching) and immediate readout start after the data request command 144. At (2), the microcontroller 110 measures the clock expansion time and, based thereon, calculates the optimized readout start time (wait time) after subsequent data request commands 144, 154. This may also result in immediate readout of the data 160 when available. Furthermore, a lower power consumption of the system 200 than in FIG. 2B is possible. Favorable I 2 C slaves 120 without an interrupt pin are possible. In addition, an increased I 2 C bandwidth is possible.In the exemplary embodiment shown in FIG. 5, the master IC 110 is designed to send the data read command 150, 152 to the slave IC 120 after a minimum data provision time T min specified in a data sheet has elapsed since the data request command 144. If the requested data 160 is not yet completely available after the specified minimum data provision time T min the slave IC 120 is configured to deactivate (clock stretching) the clock line (SCL) until the slave IC 120 can provide the requested data 160. The master IC 110 is configured to measure the clock line deactivation time period T (clock expansion time) and set the waiting time between the next data request command 144, 154 and the next data read command 142, 152 based on the minimum data provision time and the measured clock expansion time. In essence, the wait time between the next data request command 144, 154 and the next data read command 142, 152 may correspond to a sum of the minimum data provisioning time and the measured clock expansion time.In the exemplary embodiment shown in FIG. 5, the reading out of the data 160 begins with clock stretching (clock stretching) in accordance with the minimum measurement time T min. specified in the data sheet (of the sensor IC 120). The microcontroller 110 measures the clock expansion time. The microcontroller 110 calculates the optimized readout start time based thereon. This optimized readout start time can then be used, for example, for all subsequent measurements and communications.In the exemplary embodiment shown in FIG. 6, the master IC 110 is designed to maintain the waiting time between the data request command and the data read command determined according to FIG. 4 or FIG. 5 for a plurality of next data request commands and next data read commands, and then to determine an updated waiting time according to FIG. 4 or FIG. 5 again.The embodiments according to FIG. 4 or 5 can thus be combined with the embodiment according to FIG. 6. (1) The reading out of the data 160 with clock stretching (clock stretching) correspondingly begins directly or after the minimum measurement time indicated in the data sheet. (2) The microcontroller 110 measures the clock expansion time. (3) The microcontroller 110 calculates the optimized readout start time. (4) Use of this optimized readout start time without clock expansion for a predetermined number of x measurements. (5) Thereafter, return to (1) to update the clock extension time and repeat steps (2) to (5).In the exemplary embodiment illustrated in FIG. 7, the master IC 110 is designed to use the waiting time set according to one of the exemplary embodiments of FIGS. 4 to 6 for a data request command 144 and the subsequent data read command 150, 152 and then to successively reduce the waiting time between further data request commands 144 and data read commands 150, 152 until a new clock stretching (clock stretching) is detected by the slave IC 120, in order to be able to provide the requested data 160 on the data line (SDA). The master IC 110 is configured to measure clock stretching (clock stretching) and set a newly updated wait time between the next data request command 144 and the subsequent data read command 150, 152 based on the measured clock stretching (clock stretching).The embodiments according to FIGS. 4 to 6 can therefore be combined with the embodiment according to FIG. 7 (1) The reading out of the data with clock stretching (clock stretching) begins directly or after the minimum measurement time indicated in the data sheet. (2) The microcontroller 110 measures the clock expansion time. (3) The microcontroller 110 calculates the optimized readout start time and uses this optimized readout start time for measurement. (4) The microcontroller 110 reduces the readout start time for each subsequent measurement slightly from the previous readout start time (wait time) until a clock expansion gap is detectable. Return to (2).FIG. 8 collectively shows a flow diagram of a communication method 800 between the master IC 110 and the slave IC 120.At 802, the master IC 110 sends a data request command 140; 144 to the slave IC 120 via the data line (SDA). At 804, the slave IC 120 begins providing requested data 160 in response to the data request command 140; 144. At 806, after the data request command 140; 144, the master IC 110 sends a data read command 150; 152 to the slave IC 120 via the data line to read out the requested data 160. In step 808, upon receipt of the data read command 150; 152, the slave IC 120 disables the clock line (SCL) until the slave IC 120 can provide the requested data 160. In step 810, the master IC 110 measures a time period of deactivation of the clock line. In step 812, the master IC 110 sets a waiting time between a next data request command 140; 144 and a next data read command 150; 152 based on the measured time duration.The aspects and features described in connection with a particular one of the preceding examples can also be combined with one or more of the further examples in order to replace an identical or similar feature of this further example or in order to additionally introduce the feature into the further example.Examples can furthermore be or relate to a (computer) program having a program code for executing one or more of the above methods when the program is executed on a computer, a processor or another programmable hardware component. Steps, operations, or processes of various of the methods described above may also be performed by programmed computers, processors, or other programmable hardware components. Examples may also cover program storage devices, e.g., digital data storage media, that are machine, processor, or computer readable and encode or contain machine-executable, processor-executable, or computer-executable programs and instructions. The program storage devices may include or be, for example, digital storage, magnetic storage media such as magnetic disks and magnetic tapes, hard disk drives, or optically readable digital data storage media. Further examples may also cover computers, processors, controllers, field programmable logic arrays ((F)PLAs=(field) programmable logic arrays), field programmable gate arrays ((F)PGA=(field) programmable gate arrays), graphics processors (GPU= Graph Processor Unit), application specific integrated circuits (ASIC=application-specific integrated circuit), integrated circuits (IC= Integr Circuit), or system-on-a-chip systems (SoC=System-on-a-chip) programmed to perform the steps of the methods described above.It is further understood that the disclosure of a plurality of steps, processes, operations or functions disclosed in the description or the claims should not be construed as necessarily in the described order, provided that this is not explicitly stated in the individual case or is absolutely necessary for technical reasons. Therefore, the foregoing description does not limit the execution of multiple steps or functions to a particular order. Further, in further examples, a single step, function, process, or operation may include and / or be broken into multiple substeps, functions, processes, or operations.Where some aspects have been described in the preceding paragraphs in the context of an apparatus or a system, these aspects should also be understood as a description of the corresponding method. In this case, for example, a block, a device or a functional aspect of the device or of the system can correspond to a feature, for example a method step, of the corresponding method. Accordingly, aspects described in connection with a method are also to be understood as a description of a corresponding block, a corresponding element, a property or a functional feature of a corresponding device or a corresponding system.The following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate example. It is further to be noted that although a dependent claim refers in the claims to a particular combination with one or more other claims, other examples may also comprise a combination of the dependent claim with the subject matter of any other dependent or independent claim. Such combinations are hereby explicitly proposed, unless it is stated in the individual case that a specific combination is not intended. Further, features of a claim are intended to be included for any other independent claim even if that claim is not defined directly as dependent on that other independent claim.

Claims

An electronic system (200) comprising a master integrated circuit, master IC (110); a slave IC (120); a serial communication interface (230) having a bidirectional data line and a clock line, wherein the communication interface (230) is configured to transmit data between the master IC (110) and the slave IC (120), wherein the master IC (110) is configured to transmit a data request command (140; 144) to the slave IC (120) via the data line, wherein the slave IC (120) is configured to start providing requested data (160) in response to the data request command (140; 144), wherein the master IC (110) is configured to start providing requested data (160) after the data request command (140; 144 ) to the slave IC (120) via the data line to transmit a data read command (150; 152) for reading out the requested data (160), wherein the slave IC (120) is configured to deactivate the clock line after receiving the data read command (150; 152) until the slave IC (120) can provide the requested data (160), wherein the master IC (110) is configured to measure a period of deactivation of the clock line, and wherein the master IC (110) is configured to set a waiting time between a next data request command (140; 144) and a next data read command (150; 152) according to the measured period of time.The electronic system (200) of claim 1, wherein the master IC is configured to send the data read command to the slave IC after a specified minimum data provision time has elapsed since the data request command, wherein the slave IC is configured to, if the requested data is not yet fully available after the specified minimum data provision time, deactivate the clock line until the slave IC can provide the requested data, wherein the master IC is configured to measure the time duration of deactivation of the clock line, and wherein the master IC is configured to set the waiting time between the next data request command and the next data read command according to the minimum data provision time and the measured time duration.The electronic system (200) according to any one of the preceding claims, wherein the master IC is configured to maintain the waiting time for a plurality of next data request commands and next data read commands, and thereafter determine an updated waiting time according to any one of the preceding claims.The electronic system (200) according to any one of the preceding claims, wherein the master IC is configured to use the set wait time for a data request command and the subsequent data read command and thereafter to successively decrease the wait time between the data request command and the data read command until a renewed deactivation of the clock line is detected by the slave IC in order to be able to provide the requested data on the data line.The electronic system (200) according to claim 4, wherein the master IC is configured to measure the time period of re-deactivation of the clock line, and set a re-updated waiting time between the next data providing command and the subsequent data reading command according to the measured time period.The electronic system (200) according to any one of the preceding claims, wherein the master IC comprises a microcontroller.The electronic system (200) according to any one of the preceding claims, wherein the slave IC comprises a sensor IC.The electronic system (200) according to any one of the preceding claims, wherein the slave IC comprises a magnetic field sensor IC.The electronic system (200) of any preceding claim, wherein the slave IC comprises a 3D Hall sensor IC.The electronic system (200) of any preceding claim, wherein the serial communication interface comprises an I 2 C communication interface.An integrated circuit, IC (110), comprising a serial communication interface (230) having a bidirectional data line and a clock line, wherein the communication interface (230) is configured to transmit data between the IC (110) and another IC (120) via the data line; and a processor configured to transmit a data request command (140; 144) to the another IC (120) via the data line, to transmit a data read command (150; 152) to the another IC via the data line after a wait time after the data request command (140; 144), to measure a duration of deactivation of the clock line by the another IC (120) after the data read command (150; 152), and to measure the wait time between a next data request command (140; 144) and a subsequent data read command (150; 152) according to the measured time period.The IC (110) of claim 11, wherein the processor is configured to send the data read command (150; 152) to the further IC (120) after a specified minimum data provisioning time has elapsed since the data request command (140; 144).The IC (110) of claim 11 or 12, wherein the processor is configured to maintain the updated wait time for a plurality of next data request commands (140; 144) and data read commands (150; 152), and thereafter determine a re-updated wait time.The IC (110) of any of claims 11 to 13, wherein the processor is configured to use the updated wait time for the next data request command (140; 144) and the next data read command (150; 152), and thereafter to successively decrease the wait time between the data request command (140; 144) and the data read command (150; 152) until a re-deactivation of the clock line is detected by the further IC (120).The IC (110) according to any one of claims 11 to 14, wherein the IC (110) is configured as a microcontroller.The IC (110) of any of claims 11 to 15, wherein the data request command (140; 144) comprises a command (144) for measuring sensor data to a sensor IC (120).

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