TREATMENT FOR TUNING THRESHOLD VOLTAGES OF TRANSISTORS

Abstract

Method (200) comprising the following steps: Forming a first source / drain region (48) based on a first part of a first semiconductor region (60-ND, 60-PD); Forming a first high-k dielectric layer (62B) based on a second part of the first semiconductor region (60-ND, 60-PD); forming a first dipole layer (64, 74) on the first high-k dielectric layer (62B); performing a first treatment process (67, 78) on the first dipole layer (64, 74) using a process gas comprising nitrogen and hydrogen; Performing a first drive-in process (70, 82) to drive a first dipole dopant in the first dipole layer (64, 74) into the first high-k dielectric layer (62B); and Depositing a first work function layer (84) on the first high-k dielectric layer (62B), the method (200) further comprising: prior to the first drive-in process (70, 82), trimming back (65, 76) the first dipole layer (64, 74).

Description

BACKGROUND

[0001] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers over a semiconductor substrate. The various material layers are patterned by lithography to create circuit components and elements on the substrate.

[0002] The semiconductor industry is continually improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, allowing more components to be integrated into a given area. However, reducing the minimum feature size creates additional problems that need to be addressed.

[0003] Methods for forming dipole interfaces are known, for example, from US 2021 / 0 134 597 A1, US 2015 / 0 123 167 A1 and US 2022 / 0 344 355 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. The Fig. 1-4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 11A, 11B, 12A, 12B, 13A, 13B, 14-24, 25A, 25B, 26A, 26B, 27A, 27B, 28A, and 28B illustrate the intermediate stages in the fabrication of gate-all-around (GAA) transistors according to some embodiments. Fig. 29 shows a process flow for fabricating multi-Vt devices according to some embodiments. DETAILED DESCRIPTION

[0005] The present invention provides methods having the features of claims 1, 12 and 16, respectively. Exemplary embodiments are set out in the dependent claims. The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact.Furthermore, reference numbers and / or letters may be repeated throughout the various examples in the present disclosure. This repetition is for simplicity and clarity and does not, in itself, dictate any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0007] A method for tuning the threshold voltages (Vts) of transistors is provided. According to some embodiments of the present disclosure, a dipole layer is deposited that can be trimmed back to reduce its thickness. A treatment process is performed using a process gas comprising a mixture of nitrogen (N2) and hydrogen (H2). With the treatment, the bonds of dipole atoms to their interconnects can be broken and the adverse effect caused by thermal processes can be reduced, making the dipole drive-in process more effective.Although gate-all-around transistors (GAA transistors) are used here as an example, it should be understood that the concept of the present disclosure may be applied to other types of transistors, such as planar transistors, fin field-effect transistors (FinFETs), complementary field-effect transistors (CFETs), and the like.

[0008] Embodiments discussed herein are intended to provide examples for making or using the subject matter of the present invention, and one of ordinary skill in the art should readily recognize modifications that may be made without departing from the intended scope of other embodiments. Throughout the illustrations and illustrative embodiments, similar reference numerals are used to refer to similar components. While method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0009] The Fig. 1-4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 11A, 11B, 12A, 12B, 13A, 13B, 14-24, 25A, 25B, 26A, 26B, 27A, 27B, 28A, and 28B illustrate the intermediate stages in the fabrication of GAA transistors according to some embodiments. The respective processes are illustrated in process flow 200, which is shown in Fig. 29 is shown.

[0010] In Fig. 1 shows a perspective view of a wafer 10. The wafer 10 has a multilayer structure including a multilayer stack 22 on a substrate 20. According to some embodiments, the substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, or the like, although other substrates and / or structures, such as a semiconductor-on-insulator (SOI), a strained SOI, a silicon germanium-on-insulator, or the like, could also be used. The substrate 20 may be doped as a p-type semiconductor, although in other embodiments, it may also be doped as an n-type semiconductor.

[0011] According to some embodiments, the multilayer stack 22 is formed by a series of deposition processes for depositing alternating materials. The respective process is illustrated as a process 202 in the process flow 200 shown in Fig. 29. According to some embodiments, the multilayer stack 22 includes first layers 22A made of a first semiconductor material and second layers 22B made of a second semiconductor material different from the first semiconductor material.

[0012] According to some embodiments, the first semiconductor material of a first layer 22A is made of or comprises SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or the like. According to some embodiments, the deposition of the first layers 22A (e.g., SiGe) is performed by epitaxial growth, and the corresponding deposition method may be vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), ultra-high vacuum chemical vapor deposition (UHVCVD), reduced-pressure chemical vapor deposition (RPCVD), or the like.According to some embodiments, the first layer 22A is formed with a first thickness in the range between about 3 nm and about 30 nm. However, any suitable thickness may be used without departing from the scope of the embodiments.

[0013] Once the first layer 22A has been deposited over the substrate 20, a second layer 22B is deposited over the first layer 22A. According to some embodiments, the second layers 22B are made of or comprise a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, or the like, wherein the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments where the first layer 22A is silicon germanium, the second layer 22B may be made of silicon, or vice versa. It is understood that any suitable combination of materials may be used for the first layers 22A and the second layers 22B.

[0014] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition process similar to the process used to form the first layer 22A. According to some embodiments, the second layer 22B is formed with a thickness similar to the thickness of the first layer 22A. The second layer 22B may also be formed with a thickness different from the thickness of the first layer 22A. According to some embodiments, the second layer 22B may be formed, for example, with a second thickness in the range between about 1 nm and about 50 nm.

[0015] Once the second layer 22B has been formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until a desired topmost layer of the multilayer stack 22 has been formed. According to some embodiments, the first layers 22A have thicknesses that are equal to or similar to each other, and the second layers 22B have thicknesses that are equal to or similar to each other. The first layers 22A may also have the same thicknesses as or different thicknesses than the second layers 22B. According to some embodiments, the first layers 22A are removed in subsequent processes and are alternatively referred to as sacrificial layers 22A in this description. According to alternative embodiments, the second layers 22B are sacrificial layers and are removed in subsequent processes.

[0016] According to some embodiments, there are one or more pad oxide layers and one or more hard mask layers (not shown) formed over the multilayer stack 22. These layers are patterned and are used for subsequent patterning of the multilayer stack 22.

[0017] In Fig. 2, the multilayer stack 22 and a part of the underlying substrate 20 are structured in one or more etching processes so that trenches 23 are formed. The respective process is illustrated as a process 204 in the process flow 200, which is shown in Fig. 29. The trenches 23 extend into the substrate 20. The remaining parts of the multilayer stacks are hereinafter referred to as multilayer stacks 22'. Below the multilayer stacks 22', some parts of the substrate 20 remain, which are hereinafter referred to as substrate strips 20'. The multilayer stacks 22' comprise semiconductor layers 22A and 22B. Hereinafter, the semiconductor layers 22A are alternatively referred to as sacrificial layers, and the semiconductor layers 22B are alternatively referred to as nanostructures. The parts of the multilayer stacks 22' and the underlying substrate strips 20' are collectively referred to as semiconductor strips 24.

[0018] In the embodiments illustrated above, the GAA transistor structures may be patterned using any suitable method. For example, the structures may be patterned using one or more photolithographic processes, such as double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithographic and self-aligned processes that can create structures having, for example, pitches smaller than those otherwise achievable with a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate, which is then patterned using a photolithographic process. Spacers are formed along the patterned sacrificial layer using a self-aligned process.The sacrificial layer is then removed and the remaining spacers can then be used to pattern the GAA structure.

[0019] Fig. Figure 3 shows the fabrication of isolation regions 26, which are also referred to in this description as shallow trench isolation (STI) regions. The respective process is illustrated as a process 206 in the process flow 200, which is shown in Fig. 29. The STI regions 26 may include a deposit oxide (not shown), which may be a thermal oxide formed by the thermal oxidation of a surface layer of the substrate 20. The deposit oxide may also be a deposited silicon oxide layer formed, for example, using ALD, high-density plasma chemical vapor deposition (HDPCVD), CVD, or the like. The STI regions 26 may also include a dielectric material over the deposit oxide, where the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, HDPCVD, or the like.Subsequently, a planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process may be performed to flatten the top surface of the dielectric material, and the remaining parts of the dielectric material are the STI regions 26.

[0020] The STI regions 26 are then recessed such that the upper portions of the semiconductor stripes 24 protrude higher than the top surfaces 26T of the remaining portions of the STI regions 26 to form protruding fins 28. The protruding fins 28 comprise the multilayer stacks 22' and the upper portions of the substrate stripes 20'. The recessing of the STI regions 26 may be performed using a dry etching process, for example, using NF3 and NH3 as the etching gases. A plasma may be generated during the etching process. Argon may also be included. According to alternative embodiments of the present disclosure, the recessing of the STI regions 26 is performed using a wet etching process. The etching chemical may, for example, comprise HF.

[0021] In Fig. 4, dummy gate stacks 30 and gate spacers 38 are fabricated on the top surfaces and side walls of the (overhanging) fins 28. The respective process is illustrated as a process 208 in the process flow 200, which is shown in Fig. 29. The dummy gate stacks 30 may include dummy gate dielectrics 32 and dummy gate electrodes 34 over the dummy gate dielectrics 32. The dummy gate dielectrics 32 may be formed by oxidizing the surface portions of the protruding fins 28 to form oxide layers or by depositing a dielectric layer, such as a silicon oxide layer. The dummy gate electrodes 34 may be formed using, for example, polysilicon or amorphous silicon, and other materials, such as amorphous carbon, may also be used.

[0022] Each of the dummy gate stacks 30 may also include one (or a plurality of) hard mask layers 36 over the dummy gate electrode 34. The hard mask layers 36 may be formed from silicon nitride, silicon oxide, silicon carbonitride, silicon oxide carbonitride, or multiple layers thereof. The dummy gate stacks 30 may traverse a single or a plurality of protruding fins 28 and the STI regions 26 between the protruding fins 28. The dummy gate stacks 30 may also have longitudinal directions perpendicular to the longitudinal directions of the protruding fins 28. Fabrication of the dummy gate stacks 30 includes fabricating a dummy gate dielectric layer, depositing a dummy gate electrode layer over the dummy gate dielectric layer, depositing one or more hard mask layers, and then patterning the fabricated layers using one or more patterning processes.

[0023] Gate spacers 38 are then formed on the sidewalls of the dummy gate stacks 30. According to some embodiments of the present disclosure, the gate spacers 38 are formed from a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or the like, and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers. The process for forming the gate spacers 38 may include depositing one or more dielectric layers and subsequently performing one or more anisotropic etching processes on the one or more dielectric layers. The remaining portions of the one or more dielectric layers are the gate spacers 38.

[0024] The Fig. 5A and Fig. 5B show the sectional views of the structure shown in Fig. 4 is shown. Fig. 5A shows the reference cross section A1-A1 in Fig. 4, wherein the cross-section cuts through the portions of the protruding fins 28 not covered by the gate stacks 30 and the gate spacers 38 and is perpendicular to the gate longitudinal direction. Fin spacers 39 are also shown, which are arranged on the sidewalls of the protruding fins 28. Fig. 5B shows the reference cross section BB in Fig. 4, where the reference cross-section is parallel to the longitudinal directions of the projecting fins 28. The fin spacers 39 are also shown.

[0025] In the Fig. 6A and Fig. 6B, the parts of the protruding fins 28 that are not directly below the dummy gate stacks 30 and the gate spacers 38 are recessed with an etching process to form recesses 42. The respective process is illustrated as a process 210 in the process flow 200 shown in Fig. 29. For example, a dry etching process using C2F6, CF4, SO2, the mixture of HBr, Cl2, and O2, the mixture of HBr, Cl2, O2, and CH2F2, or the like may be performed to etch the multilayer semiconductor stacks 22' and the underlying substrate strips 20'. The bottom surfaces of the recesses 42 are at least level with the bottom surfaces of the multilayer semiconductor stacks 22' or they may be lower than them (as shown in Fig. 6B). The etching may be anisotropic, so that the sidewalls of the multilayer semiconductor stacks 22' facing the recesses 42 are vertical and straight, as shown in Fig. 6B is shown.

[0026] In the Fig. 7A and Fig. 7B, the sacrificial semiconductor layers 22A are laterally recessed to form lateral recesses 41, which are recessed relative to the edges of the respective overlying and underlying nanostructures 22B. The respective process is illustrated as a process 212 in the process flow 200, which is shown in Fig. 29. The lateral recessing of the sacrificial semiconductor layers 22A may be achieved with a wet etch process using an etchant that is more selective for the material (e.g., silicon germanium (SiGe)) of the sacrificial semiconductor layers 22A than for the material (e.g., silicon (Si)) of the nanostructures 22B and the substrate 20. For example, in an embodiment where the sacrificial semiconductor layers 22A are made of silicon germanium and the nanostructures 22B are made of silicon, the wet etch process may be performed using an etchant such as hydrochloric acid (HCl). The wet etch process may be performed using a dipping process, a spraying process, or the like, and may be performed at any suitable process temperature (e.g., between about 400°C and about 600°C) and a suitable process time (e.g., between about 100 seconds and about 1,000 seconds).According to alternative embodiments, the lateral recessing of the sacrificial semiconductor layers 22A is performed using an isotropic dry etching process or a combination of a dry etching process and a wet etching process.

[0027] The Fig. 8A and Fig. 8B show the manufacture of inner spacers 44. The respective process is shown as a process 214 in the process flow 200, which in Fig. 29. The manufacturing process includes depositing a spacer layer extending into the recesses 41 and performing an etching process to remove the portions of the inner spacer layer outside the recesses 41, leaving the inner spacers 44 in the recesses 41. The inner spacers 44 may be made of or comprise SiOCN, SiON, SiOC, SiCN, or the like. The inner spacers 44 may also be porous, such that they have a lower k-value, for example, lower than about 3.5. According to some embodiments, the etching of the spacer layer may be performed using a wet etching process, where the etching chemical may comprise H2SO4, dilute HF, ammonia solution (NH4OH, ammonia in water), or the like, or combinations thereof.

[0028] In the Fig. 9A and Fig. 9B, epitaxial source / drain regions 48 are formed in the recesses 42. The respective process is shown as a process 216 in the process flow 200, which is shown in Fig. 29. According to some embodiments, the source / drain regions 48 may apply mechanical stress to the nanostructures 22B used as the channels of the corresponding GAA transistors, thereby improving performance. According to some embodiments, the corresponding transistor is an n-type transistor, and the epitaxial source / drain regions 48 are accordingly fabricated as n-type source / drain regions by doping with an n-type dopant. For example, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like may be grown to form the epitaxial source / drain regions 48. After the recesses 42 have been filled with the epitaxial regions 48, further epitaxial growth of the epitaxial regions 48 causes the epitaxial regions 48 to expand horizontally, and facets may be formed.The further growth of the epitaxial regions 48 can also cause adjacent epitaxial regions 48 to merge with one another.

[0029] The Fig. 10A, Fig. 10B and Fig. 10C show the sectional views of the structure after the formation of a contact etch stop layer (CESL) 50 and an inter-layer dielectric (ILD) 52. The Fig. 10A, Fig. 10B and Fig. 10C are made from the same cross-section as the cross-sections A2-A2, BB and A1-A1 respectively in Fig. 4. The respective process is represented as a process 218 in the process flow 200, which is Fig. 29. The CESL 50 may be made of silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed using CVD, ALD, or the like. The ILD 52 may include a dielectric material formed, for example, using FCVD, spin coating, CVD, or another suitable deposition method. The ILD 52 may be made of an oxygen-containing dielectric material, which may be a silicon oxide-based material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.

[0030] In subsequent processes, replacement gate stacks are manufactured to replace the dummy gate stacks 30. In the Fig. 11A and Fig. 11B, a planarization process, such as a CMP process or a mechanical grinding process, is performed to flatten the top surface of the ILD 52. The respective process is illustrated as a process 220 in the process flow 200 shown in Fig. 29. According to some embodiments, the planarization process may remove the hard masks 36 to expose the dummy gate electrodes 34, as shown in Fig. 11B. According to alternative embodiments, the planarization process may expose and stop at the hard masks 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrodes 34 (or the hard masks 36), the gate spacers 38, and the ILD 52 are flush with each other within the process variations.

[0031] Then, the dummy gate electrodes 34 (and hard masks 36, if they remain) are removed in one or more etching processes, so that recesses 58 are formed, as shown in the Fig. 12A and Fig. 12B. The respective process is shown as a process 222 in the process flow 200, which is shown in Fig. 29. The portions of the dummy gate dielectrics 32 in the recesses 58 are also removed. According to some embodiments, the dummy gate electrodes 34 and the dummy gate dielectrics 32 are removed by dry etching processes. For example, the etching process may be performed using one or more reactant gases that selectively etch the dummy gate electrodes 34 at a faster rate than the ILD 52. Each recess 58 exposes and / or is located above portions of the multilayer stacks 22' that will form the future channel regions in subsequently completed nano-FETs. The corresponding portions of the multilayer stacks 22' are located between adjacent pairs of the epitaxial source / drain regions 48.

[0032] The sacrificial layers 22A are then removed to widen the recesses 58 between the nanostructures 22B, and the resulting structure is shown in the Fig. 13A and Fig. 13B. The respective process is shown as a process 224 in the process flow 200, which in Fig. 29. The sacrificial layers 22A may be removed by performing an isotropic etching process, such as a wet etching process with etchants selective for the materials of the sacrificial layers 22A. The nanostructures 22B, the substrate 20, the STI regions 26 remain relatively unetched compared to the sacrificial layers 22A. According to some embodiments, where the sacrificial layers 22A comprise, for example, SiGe, and the nanostructures 22B comprise, for example, Si or SiC, an etching chemical, such as tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like, may be used to remove the sacrificial layers 22A.

[0033] The preceding processes can be used to fabricate multiple GAA transistors with different Vts. In the following discussion, four device regions are presented, in each of which a transistor is to be fabricated. For example, Fig. Fourteen device regions 60-PC, 60-PD, 60-NC, and 60-ND, and the structures shown therein, are fabricated using the processes discussed in the previous paragraphs. Device region 60-PD is a p-type transistor region, which is a region in which a p-dipole drive process is to be performed. Device region 60-PC is a counterpart p-type transistor region in which no p-dipole drive process is to be performed. Device region 60-ND is an n-type transistor region, which is a region in which an n-dipole drive process is to be performed. Device region 60-NC is a counterpart n-type transistor region in which no n-dipole drive process is to be performed.

[0034] In Fig. 14, gate dielectrics 62 are fabricated to enclose the semiconductor nanostructures 22B. The respective process is illustrated as a process 226 in the process flow 200, which is shown in Fig. 29. According to some embodiments, each of the gate dielectrics 62 includes an interface layer 62A and a high-k dielectric layer 62B on the interface layer 62A. The interface layer 62A may be formed from or include silicon oxide, which may be deposited using a conformal deposition process such as ALD or CVD. According to alternative embodiments, the interface layer 62A is formed by thermal oxidation. When formed by thermal oxidation, the portions of the interface layer 62A on top of the STI regions 26 are not formed. According to some embodiments, the high-k dielectric layers 62B include one or more dielectric layers.For example, the one or more high-k dielectric layers 62B may comprise a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, combinations thereof, and / or multilayers thereof. The high-k dielectric layer 62B is deposited using a conformal deposition process, such as ALD or CVD.

[0035] The Fig. 14-17 show the dipole doping of an n-dipole dopant in the device region 60-ND according to some embodiments. In Fig. 14, a dipole layer 64 is deposited on the gate dielectric 62 using a conformal deposition process, such as CVD, ALD, or the like. The respective process is illustrated as a process 228 in the process flow 200, which is shown in Fig. 29. The dipole layer 64 is deposited in the device regions 60-PC, 60-PD, 60-NC, and 60-ND. The dipole layer 64 may comprise an n-dopant, such as La, Sr, Y, Er, Sc, Mg, or the like, or combinations thereof. The n-dopant, when incorporated into the gate dielectrics of n-type transistors, may reduce the effective work function and consequently reduce the threshold voltages of the corresponding n-type transistors.

[0036] The dipole layer 64 may be deposited as the oxide and / or the nitride of the one or more n-dopants. According to some embodiments, the dipole layer 64 deposited on the upper nanostructures 22B may be fused to the dipole layer 64 deposited on the respective lower nanostructures 22B. According to alternative embodiments, once deposition is complete, the dipole layer 64 deposited on the upper nanostructures 22B may be physically separated from the dipole layer 64 deposited on the respective lower nanostructures 22B.

[0037] According to some embodiments, the dipole layer 64 is trimmed back in a trim-back process 65. The trim-back process 65 may be performed using an isotropic etching process to isotropically etch the dipole layer 64 so that its thickness is reduced to a desirable value, such as in the range between about 1.7 nm and about 2.0 nm. According to alternative embodiments, the trim-back process 65 is omitted. The trim-back process 65 may make the subsequent treatment process more efficient due to the thinner dipole layer 64, and the bonds of more dipole dopants close to the high-k dielectric layer 62B may be released, and the subsequent drive-in process is more efficient.

[0038] According to some embodiments, after the trim-back process 65, a treatment process 67 using N2 and H2 is performed to treat the dipole layer 64. The treatment process 67 may improve the efficiency of the drive-in process, and consequently, the atomic percentage (and concentration) of the dipole dopant diffused into the high-k dielectric layer 62B becomes greater than if the treatment is not performed. The details of the treatment process 67, such as the process gases, the treatment method, the wafer temperature, and the like, may substantially correspond to the details of a treatment process 78 ( Fig. 19) are the same.

[0039] According to alternative embodiments, no treatment process using N2 and H2 is performed to treat the dipole layer 64 during an entire period beginning with the initial deposition of the dipole layer 64 and ending with the completion of the drive-in process 70. By not treating the dipole layer 64, the dipole doping efficiency is lower, thereby producing a different Vt tuning level.

[0040] According to alternative embodiments, the treatment process 67 is selectively performed on the dipole layer 64 of some transistors, while not performed on the dipole layer 64 of some other transistors. For example, according to some embodiments, the dipole layer 64 is to remain in both the device region 60-NC and the device region 60-ND. In the treatment process 67, the dipole layer 64 in the device region 60-ND is selectively treated. On the other hand, the dipole layer 64 in the device region 60-NC is protected by a mask (not shown) and is not treated. As a result, the high-k dielectric layer 62B in the device region 60-ND (after dopant drive-in) has a higher dipole dopant concentration than the high-k dielectric layer 62B in the device region 60-NC due to the higher drive-in efficiency.The threshold voltage of the transistor in device region 60-ND is thus lower than the threshold voltage of the transistor in device region 60-ND, thus producing two Vt tuning levels.

[0041] In Fig. 15, after the trim-back process 65 and the treatment process 67 (if performed), a patterned etch mask 66 is formed. According to some embodiments, the patterned etch mask 66 includes a bottom anti-reflective coating (BARC) layer patterned using a top layer, which may include a patterned photoresist. The top layer is used to etch the BARC such that the BARC has a portion remaining in the device region 60-ND, and the portions of the BARC in the device regions 60-PC, 60-PD, and 60-NC are removed. The etch mask 66 is then removed.

[0042] Further with reference to Fig. 15, an etching / structuring process 68 is performed to etch the dipole layer 64. The respective process is shown as a process 230 in the process flow 200, which is shown in Fig. 29. The etching process 68 can be performed before or after the treatment process 67 (if performed). In the etching process 68, the etch mask 66 protects the portion of the dipole layer 64 in the device region 60-ND, while the portions of the dipole layer 64 in the device regions 60-PC, 60-PD, and 60-NC are removed. After the etching process 68, the etch mask 66 is removed.

[0043] Fig. 16 shows a drive-in process 70, which is performed with an annealing process so that the dipole dopant in the dipole layer 64 is driven into the high-k dielectric layer 62B. The respective process is shown as a process 232 in the process flow 200, which is shown in Fig. 29. The drive-in process 70 may be performed in a process gas, such as N2, He, NH3, Ar, or the like, or mixtures thereof. According to some embodiments, the drive-in process 70 is performed by a soak anneal process, a rapid thermal spike anneal process, or the like.

[0044] With the drive-in process 70, the n-type dipole dopant (such as La) in the dipole layer 64 is driven into the respective underlying high-k dielectric layers 62B in the device region 60-ND. The circles represent the dipole dopants. The threshold voltage of the resulting transistor is thus tuned, for example, reduced.

[0045] According to some embodiments, the process conditions, such as annealing time and temperature, are controlled such that the peak concentration of the dipole dopant (in the finished transistors used in the Fig. 28A and Fig. 28B) is present in the high-k dielectric layer 62B, and may be closer to the interface between the high-k dielectric layer 62B and the interface layer 62A than to the outside of the high-k dielectric layer 62B. When the soak anneal process is used, the annealing time may be in the range between about 5 seconds and about 5 minutes. The annealing temperature may be in the range between about 550°C and about 900°C.

[0046] According to some embodiments, after the drive-in process 70, the dipole layer 64 formed in Fig. 16, in an etching process. The respective process is shown as a process 234 in the process flow 200, which is shown in Fig. 29. According to some embodiments, after the drive-in process 70, the dipole layer 64 shown in Fig. 16 is not removed, and consequently the subsequently deposited dipole layer 74 ( Fig. 18) is deposited on the dipole layer 64. According to still other embodiments, after the drive-in process 70, the dipole layer 64, which is Fig. 16, but not completely removed. The subsequently deposited dipole layer 74 ( Fig. 18) is also deposited on the thinned dipole layer 64. Accordingly, Fig. 17, the dipole layer 64 is shown with dashed lines to indicate that it can be removed, thinned, or neither removed nor thinned.

[0047] The Fig. 18 to 24 show the dipole doping of a p-dipole dopant in the device region 60-PD according to some embodiments. In Fig. 18, the dipole layer 74 is deposited on the gate dielectric 62 by a conformal deposition process, such as CVD, ALD, or the like. The respective process is illustrated as a process 236 in the process flow 200, which is shown in Fig. 29. The dipole layer 74 is deposited in the device regions 60-PC, 60-PD, 60-NC, and 60-ND.

[0048] The dipole layer 74 may include a p-dopant, which, when incorporated into the gate dielectrics of p-type transistors, may increase the effective work function and consequently reduce the threshold voltages of the corresponding p-type transistors. According to some embodiments, the p-dopant may include aluminum (Al), zinc (Zn), and / or the like. The dipole layer 74 may be the oxide and / or nitride of the dipole dopants. For example, the dipole layer 74 may be AlO x , AlO x , AlN x , TiAl x N y or the like or combinations thereof.

[0049] According to some embodiments, the deposition of the dipole layer 74 may be performed using a conformal deposition process, such as CVD, ALD, or the like. According to some embodiments where the dipole layer 64 includes portions remaining in the device region 60-ND, the dipole layer 74 is formed on top of and in contact with the remaining dipole layer 64. Otherwise, the dipole layer 74 is formed in the device region 60-ND above and in contact with the high-k dielectric layer 62B.

[0050] According to some embodiments, the dipole layer 74 deposited on the upper nanostructures 22B may be fused to the dipole layer 74 deposited on the corresponding lower nanostructures 22B. According to alternative embodiments, upon completion of deposition, the dipole layer 74 deposited on the upper nanostructures 22B may be physically separated from the dipole layer 74 deposited on the respective lower nanostructures 22B.

[0051] According to some embodiments, as in Fig. 18, the dipole layer 74 is trimmed back in a trimming process 76, for example, by an isotropic etching process. The resulting structure is shown in Fig. 19. The respective process is shown as a process 238 in the process flow 200, which in Fig. 29. Through the trimming process, the thickness of the dipole layer 74 can be reduced from a thickness T1 ( Fig. 18) to a thickness T2 ( Fig. 19). The thickness T2 of the dipole layer 74 may range between about 1.7 nm and about 2.0 nm. According to alternative embodiments, the trimming process 76 is omitted.

[0052] According to some embodiments, as in Fig. 19, a treatment process 78 is carried out. The respective process is shown as a process 240 in the process flow 200, which is shown in Fig. 29. The treatment may be performed using a mixture of N2 and H2 as a process gas. According to some embodiments, the treatment process 78 may be performed in a process chamber that may be used for stripping processes according to some embodiments. According to some embodiments, the treatment process 78 is performed with N2 at a flow rate in the range between about 1,000 sccm (standard cubic centimeters per minute) and about 4,000 sccm, and H2 at a flow rate in the range between about 1,500 sccm and about 4,500 sccm.

[0053] The treatment process 78 may also be a plasma treatment process, wherein the wafer 10 is treated with the plasma generated from treatment gas. According to some embodiments, the treatment process 78 may be performed without heating the wafer 10 in order to minimize the thermal budget and threshold voltage drift due to the thermal budget. According to alternative embodiments, the treatment process may be a thermal treatment process in which the respective wafer 10 is heated to a temperature in a range between about 245°C and about 260°C. The duration of the thermal treatment may be in the range between about 0.3 minutes and about 15 minutes. Furthermore, the treatment process may be both a thermal treatment process and a plasma treatment process. The duration of the plasma treatment may be in the range between about 0.3 minutes and about 1.5 minutes.

[0054] According to some embodiments, the process conditions (such as the source power for generating the plasma, the partial pressure and / or the flow rate of N2 and H2) of the treatment process 78 are similar to those of the treatment process 67 ( Fig. 14) for treating the dipole layer 64. According to alternative embodiments, the process conditions of the treatment process 78 may differ from those of the treatment process 67 for treating the dipole layer 64.

[0055] According to some embodiments, the treatment process 78 may result in radicals and / or ions of hydrogen and nitrogen being generated and incorporated into the high-k dielectric layer 62B. Furthermore, the treatment process 78 may break the bonds of the dipole layer 64, forming bonds between the dipole dopant atoms and oxygen and / or nitrogen atoms. Consequently, the dipole dopant is easier to drive into the high-k dielectric layer 62B. The concentration and atomic percentage of the dipole dopant in the high-k dielectric layer 62B may thus be higher than if the treatment process 78 is not performed. The threshold voltage tuning (the reduction in the threshold voltage) resulting from the incorporation of the dipole dopant is thus more significant.

[0056] The treatment process 78 may be performed on all dipole layers 74 in all device regions, or may be performed selectively on some but not all device regions. For example, the treatment process 78 may be performed on the dipole layer 74 in the device region 60-PD, but not on the dipole layer 74 in the device region 60-PC. According to these embodiments, when the selective treatment process is performed, the dipole layer 74 in both the device region 60-PC and the device region 60-PD may not be removed, and the drive-in process 82 ( Fig. 21), the dipole dopant is driven into the respective high-k dielectric layers 62B in both the device region 60-PC and the device region 60-PD. As a result of the selective treatment process, the high-k dielectric layer 62B in the device region 60-PD (which is selectively treated) will have a higher dipole dopant percentage (and a higher dipole dopant concentration) than the high-k dielectric layer 62B in the device region 60-PC (which is not subjected to the selective treatment process 78). Accordingly, the threshold voltage of the transistor in the device region 60-PD will be lower than the threshold voltage of the transistor in the device region 60-PC.

[0057] In Fig. 20, a patterned etch mask 79 is formed. According to some embodiments, the patterned etch mask 79 comprises a BARC patterned using a top layer, which may comprise a patterned photoresist. The top layer is used to etch the BARC such that the BARC has a portion remaining in the device region 60-PD, and the portions of the etch mask in the device regions 60-PC, 60-NC, and 60-ND are removed.

[0058] Further with reference to Fig. 20, one or more etching / patterning processes 80 are performed to etch some parts of the dipole layer 74. The respective process is represented as a process 242 in the process flow 200, which in Fig. 29. In the etching process, the etch mask 79 protects the dipole layer 74 in the device region 60-PD, while the dipole layer 74 is removed in the device regions 60-PC, 60-NC, and 60-ND. After the etching process 80, the etch mask 79 is removed. According to some embodiments in which the dipole layer 64 remains in the device region 60-ND (as shown in Fig. 17), the dipole layer 64 remains in the device region 60-ND and is not removed.

[0059] According to some embodiments, the treatment process 78 is performed before the dipole layer 74 is patterned. According to alternative embodiments, the treatment process 78 is performed after the dipole layer 74 has been patterned.

[0060] Fig. Figure 21 shows the drive-in process 82 by means of a tempering process. The respective process is represented as a process 244 in the process flow 200, which is shown in Fig. 29. The drive-in process 82 may be performed in a process gas, such as N2, He, NH3, Ar, or the like, or the mixture thereof. According to some embodiments, the drive-in process 82 is performed by a soak anneal process, a rapid thermal spike anneal process, or the like. According to some embodiments, the process conditions, such as the anneal time and temperature, are controlled such that the peak concentration of the dipole dopant is in the high-k dielectric layer 62B and may be close to the interface between the high-k dielectric layer 62B and the interface layer 62A. When the soak anneal process is used, the anneal time may be in the range between about 5 seconds and about 5 minutes. The anneal temperature may be in the range between about 550°C and about 900°C.

[0061] According to some embodiments, the process conditions (such as duration, method, and / or temperature) of the driving process 82 differ from the process conditions of the driving process 70 ( Fig. 16) to match the different diffusion rate of other dipole dopants.

[0062] With the drive-in process 82, the p-type dipole dopant (such as Al) in the dipole layer 74 is driven into the respective underlying high-k dielectric layers 62B in the device region 60-PD. The circles represent the dipole dopants. The threshold voltage of the resulting transistor is thus tuned, for example, reduced.

[0063] According to some embodiments where the dipole layer 64 has some portions remaining in the device region 60-ND, when the drive-in process 82 is performed, more n-type dipole dopant in the device region 60-ND is also driven into the respective portion of the high-k dielectric layers 62B in the device region 60-ND by the drive-in process 82. The concentration of the n-type dipole dopant in the high-k dielectric layers 62B in the device region 60-ND is thus further increased, and the threshold voltage of the transistor in the device region 60-ND is further reduced, thereby creating a further Vt tuning level.

[0064] According to some embodiments, after the drive-in process 82, the dipole layer 74 is formed as shown in Fig. 21, is removed in an etching process. The respective process is shown as a process 246 in the process flow 200, which is shown in Fig. 29. The dipole layer 64, if remaining, is also removed. The resulting structure is shown in Fig. 22 shown.

[0065] The Fig. 23 and Fig. 24 illustrate the fabrication of the remaining portions of the gate stacks and the corresponding transistors according to some embodiments. The respective process is illustrated as a process 248 in the process flow 200 shown in Fig. 29 is shown. In Fig. 23, a second high-k dielectric layer 62C is deposited to form further gate dielectrics 62. The material of the second high-k dielectric layer 62C may be the same as or different from the material of the high-k dielectric layer 62B. According to alternative embodiments, no further high-k dielectric layer is deposited on the high-k dielectric layer 62B, and the subsequently deposited conductive layers (such as one or more adhesion layers, barrier layers, and / or capping layers) are in contact with the high-k dielectric layer 62B. Accordingly, the high-k dielectric layer 62C is shown with dashed lines to illustrate that it may or may not be fabricated.

[0066] Then, as in Fig. 24, conductive layers 84 and fill metal 86 are formed. According to some embodiments, the conductive layers 84 and fill metal 86 in device regions 60-PC and 60-PD are formed in common processes using common materials or in different processes using different materials. The conductive layers 84 and fill metal 86 in device regions 60-NC and 60-ND may be formed in common processes using common materials or in different processes using different materials. For example, the transistors formed in device regions 60-PC and 60-PD have conductivity types that are opposite to the conductivity types of the transistors formed in device regions 60-NC and 60-ND.Accordingly, the work function layers in the device regions 60-PC and 60-PD can be made of different materials than the work function layers of the transistors in 60-NC and 60-ND.

[0067] According to some embodiments, the conductive layers 84 in the device regions 60-PC and 60-PD may include a p-type work function layer, which may include TiN, TaN, TiSiN, WCN, MOCN, or combinations thereof. The conductive layers 84 in the device regions 60-NC and 60-ND may include a work function layer, which may include TiAlC, TiAlN, TaAlC, TaAlN, or the like, or combinations thereof.

[0068] The filler metal 86 can be manufactured to fill the remaining recesses 58 ( Fig. 13A and Fig. 13B) if they are not yet completely filled. The fill metal 86 may comprise a metal-containing material, such as cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multilayers thereof. Transistors 100-PC, 100-PD, 100-NC, and 100-ND are thus fabricated in the device regions 60-PC, 60-PD, 60-NC, and 60-ND, respectively, as shown in Fig. 24 is shown.

[0069] The Fig. 25A and 25B to 28A and 28B illustrate the fabrication of remaining gate stacks and contact plugs according to some embodiments. The following figure numbers in the Fig. 25A and 25B to 28A and 28B may have the corresponding numbers followed by the letter A or B. The letter A indicates that the corresponding figure shows a cross-section equal to the cross-section A2-A2 in Fig. 4, and the letter B indicates that the corresponding figure shows a reference cross-section equal to the reference cross-section BB in Fig. 4. Each of the structures in the device areas 60-PC, 60-PD, 60-NC and 60-ND ( Fig. 22) can be caused by the processes in the Fig. 25A and 25B to 28A and 28B to complete the fabrication of transistors, wherein the transistors have a tuned or untuned threshold voltage. Accordingly, the fabrication process described in the Fig. 25A and 25B to 28A and 28B, the fabrication of each of the transistors in Fig. 24 represent.

[0070] In the Fig. 25A and Fig. 25B, stacked conductive layers 84 and filler metal 86 are fabricated. The processes are described with reference to the Fig. 23 and Fig. 24. In the Fig. 25A and Fig. 25B, the high-k dielectric layer 62C is not shown, although it may also be present.

[0071] In the Fig. 26A and Fig. 26B, after filling the recesses 58, a planarization process, such as a CMP process or a mechanical grinding process, is performed to remove the excess portions of the gate dielectrics and the material of the stacked conductive layers 84 and fill metal 86, which excess portions are located above the top surface of the ILD 52. The remaining portions of the conductive layers 84 and fill metal 86 form gate electrodes 88. The gate electrodes 88 and the gate dielectrics 62 are collectively referred to as the gate stack 90.

[0072] Then, as in the Fig. 27A and Fig. 27B, the gate stacks 90 are recessed to form recesses directly above the gate stacks 90 and between opposing portions of the gate spacers 38. Gate masks 92 comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, are filled into the recesses, followed by a planarization process to remove excess portions of the dielectric material extending beyond the ILD 52.

[0073] As further confirmed by the Fig. 27A and Fig. As shown in Figure 27B, an ILD 96 is deposited over the ILD 52 and over the gate masks 92. An etch stop layer (not shown) may or may not be deposited prior to the formation of the ILD 96. According to some embodiments, the ILD 96 is formed using FCVD, CVD, PECVD, or the like. The ILD 96 is formed from a dielectric material that may be selected from silicon oxide, PSG, BSG, BPSG, USG, or the like.

[0074] In the Fig. 28A and Fig. 28B, the ILD 96, the ILD 52, the CESL 50, and the gate masks 92 are etched to form recesses (occupied by contact plugs 102A and 102B) through which the surfaces of the epitaxial source / drain regions 48 and / or the gate stacks 90 are exposed. The recesses are formed by etching using an anisotropic etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or the like.

[0075] After the recesses have been made, silicide areas 98 ( Fig. 28B) are formed over the epitaxial source / drain regions 48. Source / drain contact plugs 102B are then formed over the silicide regions 98. Additionally, gate contacts 102A are formed in the recesses and are located over and in contact with the gate electrodes 88. Fig. Although Figure 28B shows that contact plugs 102A and 102B have the same cross-section, in various embodiments, contact plugs 102A and 102B may be fabricated with different cross-sections, thereby reducing the risk of a short circuit between them. GAA transistors 100-PC, 100-PD, 100-NC, and 100-ND, represented by GAA transistor 100, are thus formed in device regions 60-PC, 60-PD, 60-NC, and 60-ND, respectively ( Fig. 24) were manufactured.

[0076] By performing the treatment process on the dipole layer, more dipole dopant can be doped into the high-k dielectric layer. For example, if aluminum is used as the p-type dipole dopant and energy dispersive spectroscopy (EDS) is used to detect the signal of aluminum in a high-k dielectric layer, the signal strength is 1.7 (normalized value) when no treatment is performed. If a treatment process is performed on the respective dipole layer for about 20 seconds to about 30 seconds, the signal strength can be increased to about 1.9, indicating that the aluminum concentration in the high-k dielectric layer has increased.

[0077] The embodiments of the present disclosure have several advantageous features. By performing the treatment process, more dipole dopant can be doped into the high-k dielectric layers of transistors, and the ability to tune the threshold voltage is improved.

[0078] According to some embodiments of the present disclosure, a method comprises: forming a first source / drain region based on a first portion of a first semiconductor region; forming a first high-k dielectric layer based on a second portion of the first semiconductor region; forming a first dipole layer on the first high-k dielectric layer; performing a first treatment process on the first dipole layer using a process gas comprising nitrogen and hydrogen; performing a first drive-in process to drive a first dipole dopant in the first dipole layer into the first high-k dielectric layer; and depositing a first work function layer on the first high-k dielectric layer. Prior to the first drive-in process, the first dipole layer is trimmed back.

[0079] In one embodiment, the method further comprises: removing the first dipole layer after the first drive-in process. In one embodiment, the method further comprises: after removing the first dipole layer, depositing a second high-k dielectric layer over the first high-k dielectric layer. In one embodiment, the first treatment process comprises a plasma treatment process. In one embodiment, the first treatment process is performed without heating a wafer having the first dipole layer.

[0080] In one embodiment, the first source / drain region is a p-type source / drain region, and the method further comprises: forming a second source / drain region based on a first portion of a second semiconductor region, wherein the second source / drain region is an n-type source / drain region; forming a second high-k dielectric layer based on a second portion of the second semiconductor region; forming a second dipole layer on the second high-k dielectric layer, the second dipole layer comprising a second dipole dopant that is different from the first dipole dopant; performing a second drive-in process to drive the second dipole dopant into the second high-k dielectric layer; and depositing a second work function layer on the second high-k dielectric layer.

[0081] In one embodiment, the method further comprises performing a second treatment process on the second dipole layer using another process gas comprising nitrogen and hydrogen, wherein the first treatment process and the second treatment process are separate processes. In one embodiment, the first treatment process and the second treatment process are performed using different process conditions. In one embodiment, the first dipole dopant comprises lanthanum.

[0082] In one embodiment, the first semiconductor region comprises a semiconductor nanostructure. In one embodiment, the method further comprises: forming a further high-k dielectric layer on a further semiconductor region, wherein the first dipole layer further comprises a further portion formed on the further high-k dielectric layer; and prior to the first drive-in process, removing the further portion of the first dipole layer.

[0083] According to some embodiments of the present disclosure, a method comprises: forming an interface layer on a first semiconductor region and a second semiconductor region; forming a first high-k dielectric layer on the interface layer and on the first semiconductor region and the second semiconductor region; depositing a dipole layer on the first high-k dielectric layer, the dipole layer having a first portion overlapping the first semiconductor region and a second portion overlapping the second semiconductor region; trimming the dipole layer; performing a plasma treatment process on the dipole layer; removing the second portion of the dipole layer; performing a drive-in process to drive a dipole dopant in the dipole layer into the first high-k dielectric layer;and forming a first gate electrode and a second gate electrode on the first high-k dielectric layer, wherein the first gate electrode and the second gate electrode are on the first semiconductor region and the second semiconductor region, respectively;

[0084] In one embodiment, the plasma treatment process is performed using a process gas comprising nitrogen and hydrogen. In one embodiment, the first semiconductor region and the second semiconductor region are semiconductor nanostructures, and the first part and the second part of the dipole layer enclose the first semiconductor region and the second semiconductor region, respectively. In one embodiment, the method further comprises: removing the dipole layer after the drive-in process; and depositing a second high-k dielectric layer on the first high-k dielectric layer.

[0085] According to some embodiments of the present disclosure, a method comprises: depositing a high-k dielectric layer enclosing a semiconductor nanostructure; depositing a dipole layer enclosing the high-k dielectric layer; trimming the dipole layer; performing a treatment process on the dipole layer using nitrogen (N2) and hydrogen (H2); performing an annealing process on the dipole layer that has been treated; removing the dipole layer; depositing a second high-k dielectric layer on the high-k dielectric layer; and forming a gate electrode on the second high-k dielectric layer. In one embodiment, the treatment process is performed by a plasma treatment process. In one embodiment, depositing the dipole layer comprises depositing aluminum oxide. In one embodiment, depositing the dipole layer comprises depositing lanthanum oxide.

Claims

[1] Method (200) comprising the following steps: Forming a first source / drain region (48) based on a first part of a first semiconductor region (60-ND, 60-PD); Forming a first high-k dielectric layer (62B) based on a second part of the first semiconductor region (60-ND, 60-PD); forming a first dipole layer (64, 74) on the first high-k dielectric layer (62B); performing a first treatment process (67, 78) on the first dipole layer (64, 74) using a process gas comprising nitrogen and hydrogen; Performing a first drive-in process (70, 82) to drive a first dipole dopant in the first dipole layer (64, 74) into the first high-k dielectric layer (62B); and Depositing a first work function layer (84) on the first high-k dielectric layer (62B), the method (200) further comprising: prior to the first drive-in process (70, 82), trimming back (65, 76) the first dipole layer (64, 74). [2] The method (200) of claim 1, further comprising removing the first dipole layer (64, 74) after the first drive-in process (70, 82). [3] The method (200) of claim 1 or 2, further comprising: after performing the first drive-in process (70, 82), depositing a second high-k dielectric layer (62C) over the first high-k dielectric layer (62B). [4] The method (200) of any preceding claim, wherein the first treatment process (67, 78) comprises a plasma treatment process. [5] The method (200) of any preceding claim, wherein the first treatment process (67, 78) is performed without heating a wafer (10) having the first dipole layer (64, 74). [6] The method (200) of any preceding claim, wherein the first source / drain region (48) is a p-type source / drain region, and the method (200) further comprises: forming a second source / drain region (48) based on a first part of a second semiconductor region (60-ND), wherein the second source / drain region (48) is an n-source / drain region; Forming a third high-k dielectric layer (62B) based on a second part of the second semiconductor region (60-ND); forming a second dipole layer (64) on the third high-k dielectric layer (62C), the second dipole layer (64) comprising a second dipole dopant different from the first dipole dopant; Performing a second drive-in process (70) to drive the second dipole dopant into the third high-k dielectric layer (62C); and Depositing a second work function layer (84) on the third high-k dielectric layer (62C). [7] The method (200) of claim 6, further comprising: performing a second treatment process (67) on the second dipole layer (64) using another process gas comprising nitrogen and hydrogen, wherein the first treatment process (78) and the second treatment process (67) are separate processes. [8] The method (200) of claim 7, wherein the first treatment process (78) and the second treatment process (67) are performed using different process conditions. [9] The method (200) of any preceding claim, wherein the first dipole dopant comprises lanthanum. [10] The method (200) according to any one of the preceding claims, wherein the first semiconductor region (60-ND, 60-PD) comprises a semiconductor nanostructure. [11] Method (200) according to one of the preceding claims, further comprising: Producing a further high-k dielectric layer (62B) on a further semiconductor region (60-PC, 60-NC), wherein the first dipole layer (64, 74) has a further part produced on the further high-k dielectric layer (62B); and before the first drive-in process (70, 82), removing the further part of the first dipole layer (64, 74). [12] Method (200) comprising the following steps: Forming an interface layer (62A) on a first semiconductor region (60-PD) and a second semiconductor region (60-ND); Forming a first high-k dielectric layer (62B) on the interface layer (62A) and on the first semiconductor region (60-PD) and the second semiconductor region (60-ND); Depositing a dipole layer (74) on the first high-k dielectric layer (62B), the dipole layer (74) having a first portion overlapping the first semiconductor region (60-PD) and a second portion overlapping the second semiconductor region (60-ND); Trimming the dipole layer (64, 74); performing a plasma treatment process (78) on the dipole layer (74); Removing the second part of the dipole layer (74); Performing a drive-in process (82) to drive a dipole dopant in the dipole layer (74) into the first high-k dielectric layer (62B); and Producing a first gate electrode (88) and a second gate electrode (88) on the first high-k dielectric layer (62B), wherein the first gate electrode (88) and the second gate electrode (88) lie on the first semiconductor region (60-PD) and the second semiconductor region (60-ND), respectively. [13] The method (200) of claim 12, wherein the plasma treatment process (78) is performed using a process gas comprising nitrogen and hydrogen. [14] The method (200) of claim 12 or 13, wherein the first semiconductor region (60-PD) and the second semiconductor region (60-ND) are semiconductor nanostructures (22B), and wherein the first part and the second part of the dipole layer (74) enclose the first semiconductor region (60-PD) and the second semiconductor region (60-ND), respectively. [15] The method (200) of any one of claims 12 to 14, further comprising: Removing the dipole layer (74) after the drive-in process (82); and Depositing a second high-k dielectric layer (62C) on the first high-k dielectric layer (62B). [16] Method (200) comprising the following steps: Depositing a high-k dielectric layer (62B) enclosing a semiconductor nanostructure (22B); depositing a dipole layer (64, 74) surrounding the high-k dielectric layer (62B); Trimming the dipole layer (64, 74); performing a treatment process (67, 78) on the dipole layer (64, 74) using nitrogen N2 and hydrogen H2; performing an annealing process (70, 82) on the dipole layer (64, 74) that has been treated; Removing the dipole layer (64, 74); Depositing a second high-k dielectric layer (62C) on the high-k dielectric layer (62B); and Forming a gate electrode (88) on the second high-k dielectric layer (62C). [17] The method (200) of claim 16, wherein the treatment process (67, 78) is performed by a plasma treatment process. [18] The method (200) of claim 16 or 17, wherein depositing the dipole layer (74) comprises depositing aluminum oxide. [19] The method (200) of any one of claims 16 to 18, wherein depositing the dipole layer comprises depositing lanthanum oxide (64).

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