DISPLAY DEVICE

Abstract

According to one aspect of the present disclosure, a display device comprises a display panel in which several subpixels are defined; a first light-emitting diode (LED) arranged in each of the several subpixels; a second LED connected in series with the first LED; a first control transistor connected in parallel with the first LED and switched on by a first control signal; and a second control transistor connected in parallel with the second LED and switched on by a second control signal. Accordingly, the first LED and the second LED can be controlled independently of each other using the first and second control transistors.

Description

[0001] The application claims priority from Korean Patent Application No. 10-2023-0125525, filed on September 20, 2023, in the Korean Intellectual Property Office. Area

[0002] The present disclosure relates to a display device, and more particularly to a display device using a light-emitting diode (LED) and a method of controlling the same. background

[0003] As display devices used for a computer monitor, a television, or a mobile phone, an organic light-emitting display device (OLED device) which is a self-emitting device, a liquid crystal display device (LCD device) which requires a separate light source, and the like are known.

[0004] An application field of the display device has expanded to personal digital assistants as well as computer and television monitors, and a display device with a large display area and reduced volume and weight is being investigated.

[0005] Furthermore, a light-emitting diode (LED) display device has recently attracted attention as a next-generation display device. Because the LED is made of an inorganic material rather than an organic material, its reliability is excellent, so its service life is longer than that of liquid crystal displays or organic light-emitting displays. Furthermore, the LED has a fast flashing speed, excellent luminous efficiency, and high shock resistance, so its stability is excellent and it can display a high-luminance image. SUMMARY

[0006] An object to be achieved by the present disclosure is to provide a display device in which a dark spot defect of a sub-pixel is reduced and a method for controlling the same.

[0007] Another object to be achieved by the present disclosure is to provide a display device in which a plurality of light-emitting diodes are arranged in a sub-pixel to reduce the failure of the sub-pixel, and a method for controlling the same.

[0008] Yet another object to be achieved by the present disclosure is to provide a display device in which a plurality of light-emitting diodes are arranged in a sub-pixel to display the image with a high resolution, and a method for controlling the same.

[0009] Yet another object to be achieved by the present disclosure is to provide a display device in which, even when an open-circuit defect or a short-circuit defect occurs in one light-emitting diode among a plurality of light-emitting diodes connected in series, the remaining light-emitting diodes are normally driven, and a method for controlling the same.

[0010] Yet another object to be achieved by the present disclosure is to provide a display device in which, when some light-emitting diodes are defective, a path is provided through which a drive current is diverted, and a method for controlling the same.

[0011] Yet another object to be achieved by the present disclosure is to provide a display device in which a minimum number of transistors is added to control a plurality of light-emitting diodes, and a method for controlling the same.

[0012] The objects of the present disclosure are not limited to the above-mentioned objects, and other objects not mentioned above will be clearly understood by those skilled in the art from the following descriptions. One or more of these objects are achieved by the features of the independent claims.

[0013] According to one aspect of the present disclosure, a display device includes a display panel in which a plurality of sub-pixels are defined; a first light-emitting diode arranged in each of the plurality of sub-pixels; a second light-emitting diode connected in series with the first light-emitting diode; a first control transistor connected in parallel with the first light-emitting diode and turned on by a first control signal; and a second control transistor connected in parallel with the second light-emitting diode and turned on by a second control signal. Accordingly, the first light-emitting diode and the second light-emitting diode can be controlled independently of each other by using the first control transistor and the second control transistor connected in parallel with the first light-emitting diode and the second light-emitting diode, respectively.

[0014] According to another aspect of the present disclosure, a method for controlling a display device is provided, the method comprising: receiving a first control signal and turning on a first control transistor based on the first control signal, wherein the first control transistor is connected in parallel with a first light-emitting diode; and receiving a second control signal and turning on a second control transistor based on the second control signal, wherein the second control transistor is connected in parallel with a second light-emitting diode, wherein the second light-emitting diode is connected in series with the first light-emitting diode, wherein the first light-emitting diode is arranged in each of a plurality of sub-pixels contributing to the display panel (PN).

[0015] The display device or the method for controlling it according to the aspect of the present disclosure may further comprise one or more of the following features:

[0016] The first LED and the second LED can emit light alternately.

[0017] While the first LED emits light, the first control transistor can be turned off and the second control transistor can be turned on.

[0018] While the first LED emits light, a drive current can flow from the first LED to the second control transistor.

[0019] While the second LED emits light, the first control transistor may be turned on and the second control transistor may be turned off.

[0020] While the second LED emits light, a drive current can flow from the first control transistor to the second LED.

[0021] The display device may further include a gate driver electrically connected to the display panel and outputting a first scanning signal to the plurality of sub-pixels. The gate driver may output the first control signal to the plurality of sub-pixels. The gate driver may output the second control signal to the plurality of sub-pixels.

[0022] The gate driver may have a plurality of first stages that generate the first sampling signal.

[0023] The gate driver may include a plurality of control signal generating circuits, each connected to an output terminal of a corresponding one of the plurality of first stages. Each of the plurality of control signal generating circuits may generate the first control signal and / or the second control signal to output the first control signal and / or the second control signal to a first control line and / or a second control line.

[0024] Each of the plurality of control signal generating circuits may include a first circuit capable of outputting the first control signal and / or the second control signal to the first control line and / or the second control line while the first light-emitting diode emits light.

[0025] Each of the plurality of control signal generating circuits may include a second circuit capable of outputting the first control signal and / or the second control signal to the first control line and / or the second control line while the second light-emitting diode emits light.

[0026] The first circuit may output the first sampling signal as the first control signal and a gate low voltage as the second control signal. The second circuit may output the gate low voltage as the first control signal and the first sampling signal as the second control signal.

[0027] The first circuit may comprise a first connecting transistor having a gate electrode connected to a first node (Q1), a source electrode and a drain electrode connected between the output terminal of a corresponding one of the plurality of first stages and the first control line.

[0028] The first circuit may include a second connection transistor having a gate electrode connected to the first node and a source electrode and a drain electrode connected between a gate low line and the second control line.

[0029] The first circuit may include a first auxiliary transistor capable of sending a first enable signal to the first node.

[0030] The second circuit may comprise a third connecting transistor having a gate electrode connected to a second node (Q2), a source electrode and a drain electrode connected between the output terminal of the corresponding one of the plurality of first stages and the second control line.

[0031] The second circuit may include a fourth connecting transistor having a gate electrode connected to the second node and a source electrode and a drain electrode connected between the gate low line and the first control line.

[0032] The second circuit may include a second auxiliary transistor capable of sending a second enable signal to the second node.

[0033] The first enable signal and / or the second enable signal may be signals with reversed phases.

[0034] A turn-on period of the first connecting transistor and a turn-on period of the second connecting transistor may be configured to alternate. A turn-on period of the third connecting transistor and a turn-on period of the fourth connecting transistor may be configured to alternate.

[0035] The first circuit may further include a first gain capacitor connected between the first node and the first control line. The second circuit may further include a second gain capacitor connected between the second node and the second control line.

[0036] The method according to the further aspect of the present disclosure may further comprise one or more of the following features:

[0037] Alternately emitting light by the first LED and the second LED.

[0038] Turning off the first control transistor and turning on the second control transistor while the first light-emitting diode emits light.

[0039] Supplying a drive current from the first light-emitting diode to the second control transistor while the first light-emitting diode emits light.

[0040] Turning off the second control transistor and turning on the first control transistor while the second LED emits light.

[0041] Supplying a drive current from the first control transistor to the second light-emitting diode while the second light-emitting diode emits light.

[0042] Generating a first sensing signal by a plurality of first stages of a gate driver. Generating the first control signal and the second control signal by a plurality of control signal generating circuits, each of which may be connected to an output terminal. Outputting the first control signal and the second control signal to a first control line and a second control line. Outputting the first sensing signal, the first control signal, and the second control signal by the gate driver to the plurality of subpixels.

[0043] According to another aspect of the present disclosure, a display device comprises: a substrate, an adhesive layer disposed on the substrate; a first light-emitting diode disposed on the adhesive layer and having a first anode and a first cathode; a second light-emitting diode disposed on the adhesive layer and having a second anode and a second cathode; and a plurality of reflective electrodes disposed between the substrate and the adhesive layer. The plurality of reflective electrodes includes a first reflective electrode electrically connected to the first anode; a second reflective electrode electrically connected to the first cathode and the second anode; and a third reflective electrode electrically connected to the second cathode. Accordingly, the first light-emitting diode and the second light-emitting diode may be connected in series using the plurality of reflective electrodes.

[0044] The display device according to the further aspect of the present disclosure may further comprise one or more of the following features:

[0045] A first control transistor that may be disposed between the substrate and the plurality of reflective electrodes. The first control transistor may have a first control source electrode electrically connected to a high-potential power line;

[0046] A second control transistor, which may be arranged between the substrate and the plurality of reflective electrodes. The second control transistor may have a second control source electrode electrically connected to a first control drain electrode of the first control transistor;

[0047] A drive transistor that may be arranged between the substrate and the plurality of reflective electrodes. The drive transistor may include a drive source electrode electrically connected to a second control drain electrode of the second control transistor. The first reflective electrode may be electrically connected to the first control source electrode. The first reflective electrode may be electrically connected to the high-potential power line. The second reflective electrode may be electrically connected to the first control drain electrode. The second reflective electrode may be electrically connected to the second control source electrode. The third reflective electrode may be electrically connected to the second control drain electrode. The third reflective electrode may be electrically connected to the drive source electrode;

[0048] A planarization layer that may cover the first light-emitting diode and / or the second light-emitting diode;

[0049] A plurality of connecting electrodes may be arranged on the planarization layer. The plurality of connecting electrodes may electrically connect the first light-emitting diode and / or the second light-emitting diode to the plurality of reflective electrodes through a contact hole in the planarization layer.

[0050] The plurality of connecting electrodes may include a first anode connecting electrode that can electrically connect the first anode and the first reflective electrode.

[0051] The plurality of connecting electrodes may include a first cathode connecting electrode that can electrically connect the first cathode and the second reflective electrode.

[0052] The plurality of connecting electrodes may include a second anode connecting electrode that can electrically connect the second anode and the second reflective electrode.

[0053] The plurality of connecting electrodes may include a second cathode connecting electrode that can electrically connect the second cathode and the third reflective electrode.

[0054] Further details of the exemplary embodiments are included in the detailed description and drawings.

[0055] According to the present disclosure, a dark spot defect of a sub-pixel is reduced to improve the reliability of the display device.

[0056] According to the present disclosure, a plurality of light-emitting diodes are arranged in the sub-pixel to display an image with a higher resolution.

[0057] According to the present disclosure, a plurality of light-emitting diodes are arranged in the sub-pixel, and when one light-emitting diode is defective, the remaining light-emitting diodes are used to normally drive the sub-pixel.

[0058] According to the present disclosure, even if some of the series-connected LEDs are defective, the remaining LEDs can be normally driven by a transistor through which a drive current is bypassed.

[0059] According to the present disclosure, a control transistor is connected in parallel with each of the light-emitting diodes to provide a path that allows a drive current to be bypassed when a light-emitting diode is defective.

[0060] According to the present disclosure, each of the light-emitting diodes is connected in parallel to control the light-emitting diodes individually.

[0061] According to the present disclosure, a minimum number of transistors are added to control the LEDs. In other words, the complexity of the display device is reduced by minimizing the number of transistors required to control the LEDs.

[0062] The effects according to the present disclosure are not limited to the above-exemplified content, and more diverse effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The above and other aspects, features and advantages of the present disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure; Fig. 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure; Fig. 2B is a perspective view of a tiled display device according to an exemplary embodiment of the present disclosure; Fig. 3 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure; Fig. 4A is a driving timing diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure when a first light-emitting diode emits light; Fig. 4B is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure for explaining a flow of a driving current when a first light-emitting diode emits light; Fig. 5A is a driving timing diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure when a second light-emitting diode emits light; Fig. 5B is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure for explaining a flow of a driving current when a second light-emitting diode emits light; Fig. 6 is a top view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure; Fig. 7 a cross-sectional view along lines VIIa-VIIa' and VIIb-VIIb' of Fig. 6; Fig. 8 is a diagram of a gate driver of a display device according to an exemplary embodiment of the present disclosure; Fig. 9 is a circuit diagram of a control signal generating circuit of a display device according to an exemplary embodiment of the present disclosure; and Fig. 10 is a drive timing diagram of a control signal generating circuit of a display device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENT

[0064] Advantages and features of the present disclosure, and a method for achieving the advantages and features, will become apparent when reference is made to the exemplary embodiments described in detail below, together with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but is implemented in various forms. The exemplary embodiments are provided only as examples so that those skilled in the art can fully understand the disclosures of the present disclosure and the scope of the present disclosure.

[0065] The shapes, sizes, ratios, angles, numbers, and the like illustrated in the accompanying drawings for describing exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Like reference numerals generally designate like elements throughout. Furthermore, in the following description of the present disclosure, detailed explanation of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. As used herein, terms such as "comprising," "having," and "consisting of" are generally intended to allow the addition of other components unless the terms are used with the term "only." All references to the singular may include the plural unless expressly stated otherwise.

[0066] Components are designed to include a normal error range, even if this is not explicitly stated.

[0067] When the positional relationship between two parts is described using terms such as "on", "above", "below" and "next to", one or more parts may be positioned between the two parts, provided the terms are not used with the term "immediate" or "direct".

[0068] When one element or layer is placed "on top of" another element or layer, another layer or element can be placed directly on top of the other element or between them.

[0069] Although the terms "first," "second," and the like are used to describe various components, these components are not limited to these terms. These terms are used merely to distinguish one component from the other components. Therefore, a first component mentioned below may be a second component in a technical concept of the present disclosure.

[0070] The same reference symbols generally designate the same elements throughout the application text.

[0071] The size and thickness of each component shown in the drawing are shown for convenience, and the present disclosure is not limited to the size and thickness of the component shown.

[0072] The features of various embodiments of the present disclosure may be partially or fully concatenated or combined with one another and may be interconnected and operated in technically different ways, and the embodiments may be practiced independently of one another or in conjunction with one another.

[0073] Hereinafter, the exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0074] Fig. 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Fig. 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Fig. 2B is a perspective view of a tiled display device according to an exemplary embodiment of the present disclosure. In Fig. 1, for the sake of simplicity, only a display panel PN, a gate driver GD, a data driver DD and a timing controller TC are shown among the various components of the display device 100.

[0075] With reference to Fig. 1, the display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD that supply various signals to the display panel PN, and a timing controller TC that controls the gate driver GD and the data driver DD.

[0076] The gate driver GD supplies multiple scanning signals to multiple scanning lines SL according to multiple gate control signals supplied from the timing controller TC. Although in Fig. 1 that a gate driver GD is arranged to be spaced from one side of the display panel PN, the number of the gate drivers GD and their placement are not limited thereto.

[0077] The data driver DD converts image data input from the timing controller TC into a data voltage Vdata using a reference gamma voltage according to a plurality of data control signals supplied from the timing controller TC. The data driver DD can supply the converted data voltage Vdata to the plurality of data lines DL.

[0078] The timing controller TC aligns externally input image data to supply the image data to the data driver DD. The timing controller TC can generate a gate control signal and a data control signal using externally input synchronization signals such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal. Furthermore, the timing controller TC supplies the generated gate control signal and the data control signal to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0079] The display panel PN is a configuration that displays images to the user and includes a plurality of sub-pixels SP. In the display panel PN, the plurality of scanning lines SL and the plurality of data lines DL intersect, and the plurality of sub-pixels SP are connected to the scanning lines SL and the data lines DL, respectively. Although not shown in the drawings, each of the plurality of sub-pixels SP may be connected to a high-potential power line VDD, a low-potential power line VSS, a reference line RL, and the like.

[0080] In the display board PN, an active area AA and a non-active area NA, which encloses the active area AA, can be defined.

[0081] The active area AA is an area where images are displayed in the display device 100. In the active area AA, a plurality of sub-pixels SP forming a plurality of pixels PX and a circuit for driving the plurality of sub-pixels SP may be arranged. The plurality of sub-pixels SP are a minimum unit forming the active area AA, and n sub-pixels SP form one pixel PX. In each of the plurality of sub-pixels SP, a light-emitting diode LED and a thin-film transistor for driving the light-emitting diode LED may be arranged. The plurality of light-emitting elements LED may be defined differently depending on the type of display panel PN. For example, if the display panel PN is an inorganic light-emitting display panel, the light-emitting diode LED may be a light-emitting diode (LED) or a micro-light-emitting diode (micro-LED).

[0082] In the active region AA, a plurality of wiring lines are arranged, which transmit various signals to the plurality of sub-pixels SP. The plurality of wiring lines may include, for example, a plurality of data lines DL that supply a data voltage Vdata to each of the plurality of sub-pixels SP, a plurality of scanning lines SL that supply a scanning signal to each of the plurality of sub-pixels SP, and the like. The plurality of scanning lines SL extend in one direction in the active region AA for connecting to the plurality of sub-pixels SP, and the plurality of data lines DL extend in a direction different from the one direction in the active region AA for connecting to the plurality of sub-pixels SP. In addition, a low-potential power line VSS, a high-potential power line VDD, etc. may be arranged in the active region AA, but are not limited thereto.

[0083] The non-active region NA is a region where no images are displayed, so the non-active region NA can be defined as a region extending from the active region AA. A link line that transmits a signal to the sub-pixel SP of the active region AA, a pad electrode, or a drive IC such as a gate driver IC or a data driver IC can be disposed in the non-active region NA.

[0084] However, the non-active area NA may be located on a rear surface of the display panel PN, ie, a surface on which the sub-pixels SP are not arranged or may be omitted, and is not limited to the illustration in the drawing.

[0085] Meanwhile, a driver such as a gate driver GD, a data driver DD, and a timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD can be mounted in the non-active region NA in a gate-in-panel (GIP) manner or between the multiple sub-pixels SP in the active region AA in a gate-in-active area (GIA) manner. For example, the data driver DD and the timing controller TC are formed in a separate flexible film and circuit board. The data driver DD and the timing controller TC are electrically connected to the display panel PN by bonding the flexible film and circuit board to the pad electrode formed in the non-active region NA of the display panel PN.

[0086] When the gate driver GD is mounted in the GIP manner, and the data driver DD and timing controller TC send a signal to the display panel PN via a pad electrode of the non-active region NA, an area of ​​the non-active region NA is required to arrange the gate driver GD and the pad electrode at a predetermined level or more. Accordingly, a bezel can be enlarged.

[0087] In contrast, when the gate driver GD is mounted in the active area AA in the GIA manner, and a side line SRL connecting the signal line on the front surface of the display panel PN to the pad electrode on a rear surface of the display panel PN is formed to connect the flexible film and the circuit board on a rear surface of the display panel PN, the non-active area NA on the front surface of the display panel PN can be minimized. That is, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN as described above, a zero bezel with essentially no bezel can be implemented.

[0088] In particular, with reference to Fig. 2A and Fig. 2B, in the non-active region NA of the display panel PN, a plurality of pad electrodes for transmitting various signals to the plurality of sub-pixels SP are arranged. For example, in a non-active region NA on the front surface of the display panel PN, a first pad electrode PAD1 is arranged, which transmits a signal to the plurality of sub-pixels SP. In a non-active region NA on the rear surface of the display panel PN, a second pad electrode PAD2 is arranged, which is electrically connected to a driving component such as a flexible film and the circuit board. That is, on the front surface of the display panel PN on which images are displayed, at least only one pad region of the non-active region NA in which the first pad electrode PAD1 is arranged can be formed.

[0089] In this case, although not shown in the drawing, various signal lines connected to the plurality of sub-pixels SP, such as a scanning line SL or a data line DL for electrically connecting to the first pad electrode PAD1, extend from the active area AA to the non-active area NA.

[0090] Furthermore, the side line SRL is arranged along a side surface of the display panel PN. The side line SRL can electrically connect the first pad electrode PAD1 on the front surface of the display panel PN and the second pad electrode PAD2 on the rear surface of the display panel PN. Therefore, a signal from a driving component on the rear surface of the display panel PN can be transmitted to the plurality of sub-pixels SP via the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Accordingly, a signal transmission path is formed from the front surface of the display panel PN to the side surface and to the rear surface to minimize an area of ​​the non-active region NA on the front surface of the display panel PN.

[0091] With reference to Fig. 2B, a tiled display device TD with a large screen size can be implemented by connecting multiple display devices 100. As shown in Fig. 2A, when the tiled display device TD is implemented using a display device 100 with a minimized bezel, a seam area in which an image is not displayed between the display devices 100 is minimized, so that display quality can be improved.

[0092] For example, the plurality of sub-pixels SP form one pixel PX, and a distance D1 between an outermost pixel PX of one display device 100 and an outermost pixel PX of another display device 100 adjacent to the one display device may be implemented to correspond to a distance D1 between pixels PX in one display device 100. Accordingly, a constant distance D1 between pixels PX between the display devices 100 is designed to minimize the seam area.

[0093] Fig. 2A and Fig. 2B are exemplary, so the display device 100 according to the exemplary embodiment of the present disclosure may be, but is not limited to, a general display device with a bezel.

[0094] Fig. 3 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Fig. 4A is a driving timing diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure when a first light-emitting diode emits light. Fig. 4B is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure for explaining a flow of a driving current when a first light-emitting diode emits light. Fig. 5A is a driving timing diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure when a second light-emitting diode emits light. Fig. 5B is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure for explaining a flow of a driving current when a second light-emitting diode emits light.

[0095] With reference to Fig. 3, a sub-pixel SP of a display device 100 according to the exemplary embodiment of the present disclosure may include a pixel circuit including a drive transistor DT, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first control transistor LET1, a second control transistor LET2, a first capacitor C1, a second capacitor C2, and a third capacitor C3, and a first light-emitting diode LED1 and a second light-emitting diode LED2 connected to the pixel circuit.

[0096] Each of the plurality of sub-pixels SP may be electrically connected to a first scanning line SL1, a second scanning line SL2, a data line DL, an emission control line EML, a reference line RL, a first control line LEL1, a second control line LEL2, a high-potential power line VDD, and a low-potential power line VSS.

[0097] Meanwhile, the plurality of transistors of the plurality of sub-pixels SP may be formed by different types of transistors. For example, one transistor among the plurality of transistors may be a transistor having an oxide semiconductor as an active layer. The oxide semiconductor material has a low off-state current, so the oxide semiconductor material is suitable for a switching transistor that maintains a short on-time and a long off-time. As another example, the other transistor among the plurality of transistors may be a transistor having low-temperature polysilicon (LTPS) as an active layer. The polysilicon material has high mobility, so it has low power consumption and excellent reliability and may be suitable for the driving transistor DT.

[0098] Furthermore, a plurality of transistors arranged in each of the plurality of sub-pixels SP may be an N-type transistor or a P-type transistor. In the N-type transistor, the carriers are electrons, so that electrons flow from the source electrode to the drain electrode, and currents flow from the drain electrode to the source electrode. In the P-type transistor, the carriers are holes, so that holes flow from the source electrode to the drain electrode, and currents flow from the source electrode to the drain electrode. For example, one of the plurality of transistors may be an N-type transistor, and the other of the plurality of transistors may be a P-type transistor.

[0099] Although it is assumed below that the plurality of transistors are P-type transistors, the plurality of transistors may also be N-type transistors or may include both the P-type transistor and the N-type transistor, but the present disclosure is not limited thereto.

[0100] The drive transistor DT can be a transistor that controls a drive current based on the data voltage Vdata. A drive gate electrode DGE of the drive transistor DT is connected to a second node N2, a drive source electrode DSE is connected to a third node N3, and a drive drain electrode DDE is connected to a fourth node N4. The drive transistor DT can control a drive current applied to the light-emitting diode LED according to a gate-source voltage Vgs.

[0101] The first transistor T1 may be a transistor that sends the data voltage Vdata to the sub-pixel SP. A first gate electrode GE1 of the first transistor T1 is connected to the first scan line SL1, a first source electrode SE1 is connected to the data line DL, and a first drain electrode DE1 is connected to the first node N1. The first transistor T1 may be turned on by a first scan signal SCAN1 to supply the data voltage Vdata from the data line DL to the first node N1.

[0102] The second transistor T2 may be a transistor that samples and compensates a threshold voltage of the drive transistor DT. A second gate electrode GE2 of the second transistor T2 is connected to the first scan line SL1, and a second source electrode SE2 and a second drain electrode DE2 are connected to the second node N2 and the fourth node N4, respectively. The second transistor T2 may be turned on by the first scan signal SCAN1 to connect the drive gate electrode DGE and the drive drain electrode DDE of the drive transistor DT. Therefore, when the second transistor T2 is turned on, the drive transistor DT may be in a diode connection state in which the drive gate electrode DGE and the drive drain electrode DDE are short-circuited to operate as a diode.

[0103] The third transistor T3 may be a transistor that initializes the first node N1 to a reference voltage. A third gate electrode GE3 of the third transistor T3 is connected to the emission control line EML, a third source electrode SE3 is connected to the reference line RL, and a third drain electrode DE3 is connected to the first node N1. The third transistor T3 may be turned on by the emission control signal EM to transmit the reference voltage to the first node N1.

[0104] The fourth transistor T4 may be a transistor that controls the flow of the drive current. A fourth gate electrode GE4 of the fourth transistor T4 is connected to the emission control line EML, a fourth source electrode SE4 is connected to the fourth node N4, and a fourth drain electrode DE4 is connected to the low-potential power line VSS. The fourth transistor T4 may be turned on by the emission control signal EM to connect the fourth node N4 and the low-potential power line VSS, and allows the flow of drive current from the high-potential power line VDD to the low-potential power line VSS.

[0105] The fifth transistor T5 may be a transistor that initializes the fourth node N4 to the reference voltage. A fifth gate electrode GE5 of the fifth transistor T5 is connected to the second scan line SL2, a fifth source electrode SE5 is connected to the reference line RL, and a fifth drain electrode DE5 is connected to the fourth node N4. The fifth transistor T5 may be turned on by the second scan signal SCAN2 to transmit the reference voltage to the fourth node N4. Accordingly, a voltage of the drive drain electrode DDE of the drive transistor DT may be initialized to the reference voltage by the fifth transistor T5.

[0106] The first control transistor LET1 may be a transistor that controls whether the first light-emitting diode LED1 emits light. A first control gate electrode EGE1 of the first control transistor LET1 is connected to a first control line LEL1, and a first control source electrode ESE1 is connected to a first anode AD1 of the first light-emitting diode LED1 and the high-potential power line VDD. A first control drain electrode EDE1 is connected to a first cathode CD1 of the first light-emitting diode LED1 and a fifth node N5. The first control transistor LET1 and the first light-emitting diode LED1 may be connected in parallel.

[0107] The first control transistor LET1 can be turned on by the first control signal LE1 of the first control line LEL1 to allow the drive current to flow to the first control transistor LET1 instead of to the first light-emitting diode LED1. That is, when the first control transistor LET1 is turned on, the drive current does not flow to the first light-emitting diode LED1, but is redirected to the turned-on first control transistor LET1. When the first control transistor LET1 is turned on, the drive current can be redirected from the first control source electrode ESE1 of the first control transistor LET1 to the first control drain electrode EDE1. In contrast, when the first control transistor LET1 is turned off, the drive current can flow from the first anode AD1 of the first light-emitting diode LED1 to the first cathode CD1. Accordingly, the first light-emitting diode LED1 can emit light only when the first control transistor LET1 is turned off.

[0108] The second control transistor LET2 may be a transistor that controls whether the second light-emitting diode LED2 emits light. A second control gate electrode EGE2 of the second control transistor LET2 is connected to a second control line LEL2, and a second control source electrode ESE2 is connected to a second anode AD2 of the second light-emitting diode LED2 and the fifth node N5. A second control drain electrode EDE2 is connected to a second cathode CD2 of the second light-emitting diode LED2 and the third node N3. The second control transistor LET2 and the second light-emitting diode LED2 may be connected in parallel.

[0109] The second control transistor LET2 can be turned on by the second control signal LE2 of the second control line LEL2 to allow the drive current to flow to the second control transistor LET2 instead of to the second light-emitting diode LED2. When the second control transistor LET2 is turned on, the drive current can be redirected from the second control source electrode ESE2 of the second control transistor LET2 to the second control drain electrode EDE2. When the second control transistor LET2 is turned off, the drive current can flow from the second anode AD2 of the second light-emitting diode LED2 to the second cathode CD2. Accordingly, the second light-emitting diode LED2 can only emit light when the second control transistor LET2 is turned off.

[0110] The first capacitor C1 is connected between the first node N1 and the second node N2. The first capacitor C1 includes a plurality of first capacitor electrodes. Some of the plurality of first capacitor electrodes are connected to the first node N1, and the others are connected to the second node N2. Further, the first capacitor C1 is charged with the data voltage Vdata, to which a threshold voltage of the drive transistor DT is reflected, to fix a voltage applied to the drive gate electrode DGE of the drive transistor DT while the first light-emitting diode LED1 or the second light-emitting diode LED2 emits light. In this way, a constant drive current can be supplied to the first light-emitting diode LED1 or the second light-emitting diode LED2 during one frame.

[0111] The second capacitor C2 is connected between the second node N2 and the third node N3. The second capacitor C2 includes a plurality of second capacitor electrodes. Some of the plurality of second capacitor electrodes are connected to the second node N2, and the others are connected to the third node N3. The second capacitor C2 can be connected between the drive gate electrode DGE and the drive source electrode DSE of the drive transistor DT.

[0112] Meanwhile, when a voltage in the first node N1 fluctuates, a voltage of the second node N2 may also fluctuate due to a coupling characteristic of the first capacitor C1. At this time, the second capacitor C2, which is connected in series with the first capacitor C1, is in a coupled state with the first capacitor C1, so that a transmission rate of a voltage of the first node N1 to the voltage of the second node N2 may vary according to a capacitance ratio of the first capacitor C1 and the second capacitor C2. Therefore, when the light-emitting diode (LED) is formed by a micro-LED having a large IV curve slope, the second capacitor C2 is connected to the first capacitor C1 to lower a transmission rate of the data voltage Vdata transmitted from the first node N1 to the second node N2. Furthermore, a finer grayscale level can be expressed.

[0113] The third capacitor C3 is a capacitor formed between the high-potential power line VDD and the third node N3 and may be a parasitic capacitor. The third capacitor C3 may be a capacitor formed between existing configurations without additionally forming a separate electrode. For example, at least a portion of a configuration connected to the high-potential power line VDD and at least a portion of a configuration connected to the third node N3 overlap to form the third capacitor C3. The third capacitor C3 increases an intrinsic capacitance in the light-emitting diode (LED) to enable the light-emitting diode (LED) to emit light with higher luminance.

[0114] The first light-emitting diode LED1 includes a first anode AD1 and a first cathode CD1. The first anode AD1 of the first light-emitting diode LED1 is connected to the high-potential power line VDD, and the first cathode CD1 is connected to the fifth node N5. The first light-emitting diode LED1 is supplied with a drive current, which is set by an on-state drive transistor DT in an off-state of the first control transistor LET1, to emit light.

[0115] The second light-emitting diode LED2 is connected in series with the first light-emitting diode LED1 and includes a second anode AD2 and a second cathode CD2. The second anode AD2 of the second light-emitting diode LED2 is connected to the fifth node N5, and the second cathode CD2 is connected to the third node N3. The second light-emitting diode LED2 is supplied with a drive current, which is set by an on-state drive transistor DT in an off-state of the second control transistor LET2, to emit light.

[0116] The first light-emitting diode LED1 and the second light-emitting diode LED2 can be controlled alternately. The first light-emitting diode LED1 and the second light-emitting diode LED2 can emit light in different frames or different horizontal periods. For example, the first light-emitting diode LED1 emits light in an nth frame, and the second light-emitting diode LED2 can emit light in an mth frame. For example, the first light-emitting diode LED1 can emit light in an nth horizontal period, and the second light-emitting diode LED2 can emit light in an mth horizontal period. In this case, the first control transistor LET1 and the second control transistor LET2 can also be turned on alternately.That is, the first control transistor LET1 and the second control transistor LET2 are turned on in different frames and control the first light-emitting diode LED1 and the second light-emitting diode LED2 to emit light in different periods.

[0117] Accordingly, in the display device 100 according to the exemplary embodiment of the present disclosure, the first light-emitting diode LED1 and the second light-emitting diode LED2 are connected in series to the plurality of sub-pixels SP, the first control transistor LET1 is connected in parallel to the first light-emitting diode LED1, and the second control transistor LET2 is connected in parallel to the second light-emitting diode LED2. Therefore, it can be seen that the sub-pixel SP is normally driven even when a defect occurs in the sub-pixel SP. For example, when an open-circuit defect or a short-circuit defect occurs, the drive current bypasses the first control transistor LET1 to be supplied to the second light-emitting diode LED2, and the second light-emitting diode LED2 can be normally driven.An open-circuit defect is a defect in which a portion of the first anode AD1 and the first cathode CD1 of the first light-emitting diode LED1 is not connected to the circuit. A short-circuit defect is a defect in which the first anode AD1 and the first cathode CD1 of the first light-emitting diode LED1 are electrically connected. Similarly, the second control transistor LET2 can form a current path between the drive transistor DT and the first light-emitting diode LED1 even if the open-circuit defect or short-circuit defect occurs in the second light-emitting diode LED2. This means that when the second light-emitting diode LED2 is defective, the drive current bypasses the second control transistor LET2, and the first light-emitting diode LED1 can be driven normally.Accordingly, in the display device 100 according to the exemplary embodiment of the present disclosure, even if one of the plurality of light-emitting diodes (LEDs) arranged in each of the plurality of sub-pixels SP is defective, the sub-pixel SP can be driven using the remaining light-emitting diodes (LEDs). Therefore, the dark spot defect can be minimized and the reliability of the display device 100 can be improved.

[0118] Furthermore, as described above, the first light-emitting diode LED1 and the second light-emitting diode LED2 can alternately emit light in units of frames or in units of horizontal periods. When the first light-emitting diode LED1 is defective so that the first light-emitting diode LED1 does not emit light, the second light-emitting diode LED2 emits light in a different frame or horizontal period, so that the sub-pixel SP does not look like a dark spot. In particular, when the display device 100 is driven at a high frequency, the length of a frame or the length of a horizontal period is very short, so it is difficult for a user to recognize a non-emission defect of the first light-emitting diode LED1 or the second light-emitting diode LED2. Accordingly, the first light-emitting diode LED1 and the second light-emitting diode LED2 alternately emit light.Even if one LED is defective and does not emit light, the remaining LED will emit light so that an image is displayed normally.

[0119] In the following, the driving process of the sub-pixel SP is described in detail, assuming that the first light-emitting diode LED1 and the second light-emitting diode LED2 alternately emit light in the unit of frames.

[0120] With joint reference to Fig. 4A and Fig. 4B, at time A, a low level of the second scanning signal SCAN2 is output to the second scanning line SL2. The fifth transistor T5 is turned on by the low level of the second scanning signal SCAN2, and the reference voltage is applied to the drive drain electrode DDE of the drive transistor DT, which is the fourth node N4. Accordingly, a voltage of the drive drain electrode DDE of the drive transistor DT at time A can be initialized to the reference voltage.

[0121] Next, in a period between time B and time C, a low level of the first scanning signal SCAN1 is output to the first scanning line SL1. The first transistor T1 is turned on by the low level of the first scanning signal SCAN1 to transmit the data voltage Vdata to the first node N1. Furthermore, the second transistor T2 is turned on by the low level of the first scanning signal SCAN1 to connect the drive gate electrode DGE and the drive drain electrode DDE of the drive transistor DT.

[0122] Furthermore, low levels of the first control signal LE1 and the second control signal LE2 are output to both the first control line LEL1 and the second control line LEL2 during a period between time B and time C. At time B, the high-potential power line VDD and the drive source electrode DSE of the drive transistor DT may be electrically connected. At time B, the high-potential power line VDD is connected through the second transistor T2 to the drive source electrode DSE of the drive transistor DT, which is in a diode connection state, so that the current flows through the drive transistor DT and the threshold voltage of the drive transistor DT can be sensed.Accordingly, the threshold voltage of the drive transistor DT is sampled to reflect it to the second node N2, and the data voltage Vdata to which the threshold voltage of the drive transistor DT is reflected can be charged to the first capacitor C1.

[0123] Next, the low level of the emission control signal EM is output to the emission control line EML at time D. The third transistor T3 is turned on by the low level of the emission control signal EM, and the reference voltage can be applied to the first node N1.

[0124] When the fourth transistor T4 is turned on by the low level of the emission control signal EM, the drive transistor DT and the low-potential power line VSS can be electrically connected and the drive current can flow to the first light-emitting diode LED1 or to the second light-emitting diode LED2.

[0125] With reference to Fig. 4A and Fig. 4B, when it is the turn of the first light-emitting diode LED1 among the first light-emitting diode LED1 and the second light-emitting diode LED2 to emit light, a high level of the first control signal LE1 is output to the first control line LEL1, and a low level of the second control signal LE2 is output to the second control line LEL2. That is, the first control signal LE1, which turns off the first control transistor LET1, is output to the first control line LEL1, and the second control signal LE2, which turns on the second control transistor LET2, is output to the second control line LEL2.

[0126] When the first control transistor LET1 is turned off, the drive current can flow to the first light-emitting diode LED1 connected in parallel to the first control transistor LET1. When the second control transistor LET2 is further turned on, the drive current can flow to the second control transistor LET2. Accordingly, the first control transistor LET1 is turned off between the high-potential power line VDD and the fifth node N5 to allow the drive current to flow to the first light-emitting diode LED1 connected in parallel to the first control transistor LET1. The second control transistor LET2 is turned on between the fifth node N5 and the third node N3 to allow the drive current to flow to the second control transistor LET2.Accordingly, when the first control transistor LET1 is turned off and the second control transistor LET2 is turned on, the first light-emitting diode LED1 emits light and the second light-emitting diode LED2 does not emit light.

[0127] Next, with reference to Fig. 5A and Fig. 5B, when it is the second LED2's turn to emit light among the first LED1 and the second LED2, a low level of the first control signal LE1 is output to the first control line LEL1, and a high level of the second control signal LE2 is output to the second control line LEL2. That is, the first control signal LE1, which turns on the first control transistor LET1, is output to the first control line LEL1, and the second control signal LE2, which turns off the second control transistor LET2, is output to the second control line LEL2.

[0128] When the first control transistor LET1 is turned on, the drive current is diverted to flow to the first control transistor LET1. When the second control transistor LET2 is turned off, the drive current can flow to the second light-emitting diode LED2. Accordingly, the first control transistor LET1 is turned on between the high-potential power line VDD and the fifth node N5 to allow the drive current to flow to the first control transistor LET1. The second control transistor LET2 is turned off between the fifth node N5 and the third node N3 to allow the drive current to flow to the second light-emitting diode LED2, which is connected in parallel to the second control transistor LET2. Accordingly, when the first control transistor LET1 is turned on and the second control transistor LET2 is turned off, the first light-emitting diode LED1 does not emit light, and the second light-emitting diode LED2 can emit light.

[0129] Accordingly, in the display device 100 according to the exemplary embodiment of the present disclosure, the first control transistor LET1 and the second control transistor LET2, which are connected in parallel with the first light-emitting diode LED1 and the second light-emitting diode LED2, respectively, are configured to easily control the first light-emitting diode LED1 and the second light-emitting diode LED2 to emit light. The first light-emitting diode LED1 and the first control transistor LET1 are connected in parallel, and when the first control transistor LET1 is off, the drive current flows to the first light-emitting diode LED1, so that the first light-emitting diode LED1 emits light. Conversely, when the first control transistor LET1 is on, the drive current is bypassed to the first control transistor LET1, so that the first light-emitting diode LED1 does not emit light.Only when the second control transistor LET2, which is connected in parallel with the second light-emitting diode LED2, is turned off does the second light-emitting diode LED2 emit light. Accordingly, the first light-emitting diode LED1 and the second light-emitting diode LED2 selectively emit light using the first control transistor LET1 and the second control transistor LET2, which are connected in parallel with the first light-emitting diode LED1 and the second light-emitting diode LED2, respectively. Furthermore, to independently control the first light-emitting diode LED1 and the second light-emitting diode LED2, only the first control transistor LET1 and the second control transistor LET2 are added instead of a complex circuit, so that the configuration of the sub-pixel SP can be simplified.

[0130] Furthermore, in the display device 100 according to the exemplary embodiment of the present disclosure, the first control transistor LET1 and the second control transistor LET2 are formed, which are connected in parallel with the first light-emitting diode LED1 and the second light-emitting diode LED2, respectively. Therefore, even if one light-emitting diode LED is defective, the remaining light-emitting diode LED can be driven normally. For example, if an open-circuit defect occurs in the first light-emitting diode LED1, it may be difficult to allow the drive current to flow to the second light-emitting diode LED2 between the first light-emitting diode LED1 and the second light-emitting diode LED2, which are connected in series.However, in the display device 100 according to the exemplary embodiment of the present disclosure, the first control transistor LET1 connected in parallel with the first light-emitting diode LED1 is turned on to form a path through which the drive current is bypassed, and the drive current is normally supplied to the second light-emitting diode LED2. Therefore, even if one light-emitting diode LED is defective, the drive current can be normally supplied to the remaining light-emitting diode LED using a control transistor connected in parallel with the light-emitting diode LED.

[0131] Furthermore, in the display device 100 according to the exemplary embodiment of the present disclosure, a plurality of light-emitting diodes (LEDs) are arranged in one sub-pixel SP, so that a high-resolution image can be easily displayed. For example, only one light-emitting diode (LED) is arranged in each of the plurality of sub-pixels SP, and the high-resolution image can be displayed by increasing the number of the plurality of sub-pixels SP. However, in this case, an area allocated to each of the plurality of sub-pixels SP is reduced, so that it is difficult to design the sub-pixel SP. In contrast, in the display device 100 according to the exemplary embodiment of the present disclosure, a plurality of light-emitting diodes (LEDs) are arranged in each of the plurality of sub-pixels SP, so that the high-resolution image can be displayed without increasing the number of the plurality of sub-pixels SP.That is, the number of LEDs is increased to achieve the same effect as increasing the number of sub-pixels SP. The number of sub-pixels SP remains the same, but only the number of LEDs is increased, ensuring a surface area for designing each of the sub-pixels SP, and simplifying the design of the sub-pixel SP.

[0132] However, with reference to Fig. 4A, when the first light-emitting diode LED1 emits light, the first control signal LE1 applied to the first control line LEL1 has the same waveform as the first scanning signal SCAN1. Further, with reference to Fig. 5A, the second light-emitting diode LED2 emits light, the second control signal LE2 applied to the second control line LEL2 may have the same waveform as the first scanning signal SCAN1. In the display device 100 according to the exemplary embodiment of the present disclosure, a control signal generation circuit LEC is connected to each of a plurality of first stages ST1 that generates the first scanning signal SCAN1 to output one of the first control signal LE1 and the second control signal LE2 to have the same waveform as the first scanning signal SCAN1. This will be explained below with reference to Fig. 8 to 10 are described in more detail.

[0133] Hereinafter, a structure of a sub-pixel SP of the display device 100 according to the exemplary embodiment of the present disclosure will be described with reference to Fig. 6 and Fig. 7 described.

[0134] Fig. 6 is a top view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Fig. Figure 7 is a cross-sectional view along lines VIIa-VIIa' and VIIb-VIIb' of Fig. 6. For the sake of clarity of description, Fig. 6 several reflective electrodes RE, a first light-emitting diode LED1, a second light-emitting diode LED2, several connecting electrodes CE and a bank BB not shown.

[0135] With reference to Fig. 6 and Fig. 7, the display device 100 according to the exemplary embodiment of the present disclosure includes a substrate 110, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113a, a second interlayer insulating layer 113b, a first passivation layer 114a, a second passivation layer 114b, a first planarization layer 115a, a second planarization layer 115b, a third planarization layer 115c, an adhesive layer 116, a bank BB, a protection layer 117, a light-shielding layer LS, a plurality of transistors, a plurality of capacitors, a plurality of wiring lines, a plurality of reflective electrodes RE, a plurality of connection electrodes CE, and a plurality of light-emitting diodes LED.

[0136] First, the substrate 110 is a component for supporting various components included in the display device 100 and may be formed from an insulating material. For example, the substrate 110 may be formed from glass or resin. Furthermore, the substrate 110 may be configured to contain polymers or plastics, or it may be formed from a flexible material.

[0137] The light-shielding layer LS is disposed in each of the plurality of sub-pixels SP on the substrate 110. The light-shielding layer LS blocks light incident on a drive active layer DACT of the drive transistor DT described below, located below the substrate 110. Light incident on the drive active layer DACT of the drive transistor DT is blocked by the light-shielding layer LS to minimize leakage current. The light-shielding layer LS may be made of an opaque conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0138] Buffer layer 111 is disposed on substrate 110 and light-shielding layer LS. Buffer layer 111 can reduce the penetration of moisture or contaminants through substrate 110. Buffer layer 111 can be made of, but is not limited to, a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx). However, buffer layer 111 can be omitted depending on the type of substrate 110 or the type of transistor, but is not limited to this.

[0139] The drive transistor DT is arranged on the buffer layer 111. The drive transistor DT includes a drive active layer DACT, a drive gate electrode DGE, a drive source electrode DSE, and a drive drain electrode DDE.

[0140] The drive active layer DACT is arranged on the buffer layer 111. The drive active layer DACT may be formed of a semiconductor material such as, but is not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0141] The gate insulating layer 112 is disposed on the drive active layer DACT. The gate insulating layer 112 is an insulating layer that electrically isolates the drive active layer DACT from the drive gate electrode DGE and may be formed by, but is not limited to, a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx).

[0142] The drive gate electrode DGE is disposed on the gate insulating layer 112. The drive gate electrode DGE may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0143] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are disposed on the drive gate electrode DGE. A contact hole is formed in the first interlayer insulating layer 113a and the second interlayer insulating layer 113b, through which the drive source electrode DSE and the drive drain electrode DDE are connected to the drive active layer DACT. The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are insulating layers that protect components below the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. Furthermore, the first interlayer insulating layer 113a and the second interlayer insulating layer 113b may be formed by a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but are not limited thereto.

[0144] The drive source electrode DSE and the drive drain electrode DDE, which are electrically connected to the drive active layer DACT, are arranged on the second interlayer insulating layer 113b. The drive source electrode DSE and the drive drain electrode DDE may be made of a conductive material such as, but are not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0145] The first transistor T1 is arranged on the buffer layer 111. The first transistor T1 comprises a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0146] The first active layer ACT1 is disposed on the buffer layer 111. The first active layer ACT1 may be made of a semiconductor material such as, but is not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0147] The gate insulating layer 112 is disposed on the first active layer ACT1, and the first gate electrode GE1 is disposed on the gate insulating layer 112. The first gate electrode GE1 is integrally formed with the first drive line SL1 so as to be electrically connected to the first drive line SL1. The first gate electrode GE1 may be made of a conductive material such as, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0148] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are disposed on the first gate electrode GE1. Furthermore, the first source electrode SE1 and the first drain electrode DE1, which are electrically connected to the first active layer ACT1, are disposed on the second interlayer insulating layer 113b. The first source electrode SE1 is integrally formed with the data line DL so as to be electrically connected to the data line DL. The first drain electrode DE1 may be electrically connected to a first-second capacitor electrode C1b of the first capacitor C1 described below through a contact hole of the second interlayer insulating layer 113b. The first source electrode SE1 and the first drain electrode DE1 may be formed of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0149] The second transistor T2 is arranged on the buffer layer 111. The second transistor T2 comprises a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0150] The second active layer ACT2 is disposed on the buffer layer 111. The second active layer ACT2 may be formed of a semiconductor material such as, but is not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0151] The gate insulating layer 112 is disposed on the second active layer ACT2, and the second gate electrode GE2 is disposed on the gate insulating layer 112. The second gate electrode GE2 is integrally formed with the first drive line SL1 so as to be electrically connected to the first drive line SL1. The second gate electrode GE2 may be made of a conductive material such as, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0152] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are disposed on the second gate electrode GE2. Further, the second source electrode SE2 and the second drain electrode DE2, which are electrically connected to the second active layer ACT2, are disposed on the second interlayer insulating layer 113b. The second source electrode SE2 is electrically connected to the drive gate electrode DGE, which is a first capacitor electrode C1a of the first capacitor C1. The second drain electrode DE2 is electrically connected to the fourth source electrode SE4 of the fourth transistor T4, the fifth drain electrode DE5 of the fifth transistor T5, and the drive drain electrode DDE of the drive transistor DT.The second source electrode SE2 and the second drain electrode DE2 may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0153] The third transistor T3 is arranged on the buffer layer 111. The third transistor T3 comprises a third active layer ACT3, a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3.

[0154] The third active layer ACT3 is disposed on the buffer layer 111. The third active layer ACT3 may be formed of a semiconductor material such as, but is not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0155] The gate insulating layer 112 is disposed on the third active layer ACT3, and the third gate electrode GE3 is disposed on the gate insulating layer 112. The third gate electrode GE3 is formed with the emission control line EML such that it is electrically connected to the emission control line EML. The third gate electrode GE3 may be made of a conductive material such as, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0156] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are disposed on the third gate electrode GE3. Further, the third source electrode SE3 and the third drain electrode DE3, which are electrically connected to the third active layer ACT3, are disposed on the second interlayer insulating layer 113b. The third source electrode SE3 is electrically connected to the fifth source electrode SE5 and the reference line RL. Further, the third drain electrode DE3 is electrically connected to the 1-2nd capacitor electrode C1b of the first capacitor C1 and the first drain electrode DE1 of the first transistor T1. The third source electrode SE3 and the third drain electrode DE3 may be made of a conductive material such as, but are not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0157] The fourth transistor T4 is arranged on the buffer layer 111. The fourth charging transistor T4 comprises a fourth active layer ACT4, a fourth gate electrode GE4, a fourth source electrode SE4, and a fourth drain electrode DE4.

[0158] The fourth active layer ACT4 is disposed on the buffer layer 111. The fourth active layer ACT4 may be formed of a semiconductor material such as, but is not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0159] The gate insulating layer 112 is disposed on the fourth active layer ACT4, and the fourth gate electrode GE4 is disposed on the gate insulating layer 112. The fourth gate electrode GE4 is integrally formed with the emission control line EML so as to be electrically connected to the emission control line EML. The fourth gate electrode GE4 may be made of a conductive material such as, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0160] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are disposed on the fourth gate electrode GE4. Furthermore, the fourth source electrode SE4 and the fourth drain electrode DE4, which are electrically connected to a fourth active layer ACT4, are disposed on the second interlayer insulating layer 113b. The fourth source electrode SE4 is electrically connected to the drive drain electrode DDE of the drive transistor DT, the fifth drain electrode DE5 of the fifth transistor T5, and the second drain electrode DE2 of the second transistor T2. Furthermore, the fourth drain electrode DE4 is electrically connected to the low-potential power line VSS. Here, the low-potential power line VSS and the fourth drain electrode DE4 are integrally formed on the same layer using the same material.The fourth source electrode SE4 and the fourth drain electrode DE4 may be made of a conductive material such as, but are not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof.

[0161] The fifth transistor T5 is arranged on the buffer layer 111. The fifth transistor T5 comprises a fifth active layer ACT5, a fifth gate electrode GE5, a fifth source electrode SE5, and a fifth drain electrode DE5.

[0162] The fifth active layer ACT5 is disposed on the buffer layer 111. The fifth active layer ACT5 may be formed of a semiconductor material such as, but is not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0163] The gate insulating layer 112 is disposed on the fifth active layer ACT5, and the fifth gate electrode GE5 is disposed on the gate insulating layer 112. The fifth gate electrode GE5 may be electrically connected to the second drive line SL2. The fifth gate electrode GE5 may be integrally formed with the second drive line SL2 on the same layer and with the same material. The fifth gate electrode GE5 may be formed of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0164] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are disposed on the fifth gate electrode GE5. Further, the fifth source electrode SE5 and the fifth drain electrode DE5, which are electrically connected to the fifth active layer ACT5, are disposed on the second interlayer insulating layer 113b. The fifth source electrode SE5 is electrically connected to the reference line RL and the third source electrode SE3. Further, the fifth drain electrode DE5 is connected to the drive drain electrode DDE, the fourth source electrode SE4, and the second drain electrode DE2. The fifth source electrode SE5 and the fifth drain electrode DE5 may be made of a conductive material such as, but are not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0165] The first control transistor LET1 is arranged on the buffer layer 111. The first control transistor LET1 includes a first active control layer EACT1, a first control gate electrode EGE1, a first control source electrode ESE1, and a first control drain electrode EDE1.

[0166] The first active control layer EACT1 is arranged on the buffer layer 111. The first active control layer EACT1 may be formed of a semiconductor material such as, but is not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0167] The gate insulating layer 112 is disposed on the first active control layer EACT1, and the first control gate electrode EGE1 is disposed on the gate insulating layer 112. The first control gate electrode EGE1 is integrally formed with the first control line LEL1 so as to be electrically connected to the first control line LEL1. The first control gate electrode EGE1 may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0168] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are disposed on the first control gate electrode EGE1. Further, the first control source electrode ESE1 and the first control drain electrode EDE1, which are electrically connected to the first active control layer EACT1, are disposed on the second interlayer insulating layer 113b. The first control source electrode ESE1 is electrically connected to the high-potential power line VDD, and the first control drain electrode EDE1 is electrically connected to the second control source electrode ESE2 of the second control transistor LET2. Further, the first control source electrode ESE1 and the first drain electrode DE1 may be connected in parallel to the first light-emitting diode LED1 via the first reflective electrode RE1 and the second reflective electrode RE2, which are described below.The first control source electrode ESE1 and the first control drain electrode EDE1 may be made of a conductive material such as, but are not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof.

[0169] The second control transistor LET2 is arranged on the buffer layer 111. The second control transistor LET2 includes a second active control layer EACT2, a second control gate electrode EGE2, a second control source electrode ESE2, and a second control drain electrode EDE2.

[0170] The second active control layer EACT2 is arranged on the buffer layer 111. The second active control layer EACT2 may be formed of a semiconductor material such as, but is not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0171] The gate insulating layer 112 is disposed on the second active control layer EACT2, and the second control gate electrode EGE2 is disposed on the gate insulating layer 112. The second control gate electrode EGE2 is integrally formed with the second control line LEL2 so as to be electrically connected to the second control line LEL2. The second control gate electrode EGE2 may be formed of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0172] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are disposed on the second control gate electrode EGE2. Further, the second control source electrode ESE2 and the second control drain electrode EDE2, which are electrically connected to the second control active layer EACT2, are disposed on the second interlayer insulating layer 113b. The second control source electrode ESE2 is integrally formed with the first control drain electrode EDE1 so as to be electrically connected to the first control drain electrode EDE1. The second control source electrode ESE2 can be electrically connected to the second anode AD2 of the second light-emitting diode LED2 through the second reflective electrode RE2, which will be described below. The second control drain electrode EDE2 extends from the second control active layer EACT2 to the drive active layer DACT so as to be connected to the drive active layer DACT.Furthermore, the second control drain electrode EDE2 can be electrically connected to the drive source electrode DSE via the active drive layer DACT. Furthermore, the second control drain electrode EDE2 can be electrically connected to the second cathode CD2 of the second light-emitting diode LED2 via the drive source electrode DSE and a third reflective electrode RE3. Accordingly, the second control source electrode ESE2 and the second control drain electrode EDE2 are connected in parallel to the second light-emitting diode LED2 via the second reflective electrode RE2 and the third reflective electrode RE3. The second control source electrode ESE2 and the second control drain electrode EDE2 can be made of a conductive material such as, but are not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0173] Next, the first capacitor C1 is disposed on the gate insulating layer 112. The first capacitor C1 includes a first capacitor electrode C1a and a second capacitor electrode C1b. The first capacitor electrode C1a and the second capacitor electrode C1b may be made of a conductive material such as, but are not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0174] The first capacitor electrode C1a is disposed on the gate insulating layer 112. The first capacitor electrode C1a is integrally formed with the drive gate electrode DGE. Accordingly, the first capacitor electrode C1a may be electrically connected to the drive gate electrode DGE, and the second source electrode SE2 may be electrically connected to the drive gate electrode DGE.

[0175] The 1-2nd capacitor electrode C1b is disposed on the first interlayer insulating layer 113a. The 1-2nd capacitor electrode C1b is arranged to overlap the 1-1st capacitor electrode C1a, with the first interlayer insulating layer 113a therebetween. Furthermore, the 1-2nd capacitor electrode C1b may be electrically connected to the first drain electrode DE1 and the third drain electrode DE3.

[0176] The second capacitor C2 is arranged on the substrate 110. The second capacitor C2 includes a 2-1st capacitor electrode C2a, a 2-2nd capacitor electrode C2b, and a 2-3rd capacitor electrode C2c. The 2-1st capacitor electrode C2a, the 2-2nd capacitor electrode C2b, and the 2-3rd capacitor electrode C2c may be made of a conductive material such as, but are not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0177] The 2-1st capacitor electrode C2a is arranged on the substrate 110. The 2-1st capacitor electrode C2a extends from the light-shielding layer LS and is formed integrally with the light-shielding layer LS. The 2-1st capacitor electrode C2a can be electrically connected to the drive source electrode DSE via an auxiliary electrode AE. The auxiliary electrode AE ​​is arranged on the gate insulating layer 112 to electrically connect the drive source electrode DSE and the 2-1st capacitor electrode C2a.

[0178] The 2-2nd capacitor electrode C2b is disposed on the buffer layer 111 and the gate insulating layer 112. The 2-2nd capacitor electrode C2b may be integrally formed with the drive gate electrode DGE and the 1-1st capacitor electrode C1a. Accordingly, the 2-1st capacitor electrode C2a may be electrically connected to the drive gate electrode DGE, the 1-1st capacitor electrode C1a, and the second source electrode SE2.

[0179] The 2-3rd capacitor electrode C2c is arranged on the first interlayer insulating layer 113a. The 2-3rd capacitor electrode C2c may be formed by a first electrode layer C2c1 and a second electrode layer C2c2. The first electrode layer C2c1 of the 2-3rd capacitor electrode C2c is on the same layer with the same material as the 1-2nd capacitor electrode C1b and is spaced from the 1-2nd capacitor electrode C1b to be formed in an island-shaped pattern. The first electrode layer C2c1 may be arranged to overlap the 2-1st capacitor electrode C2a and the 2-2nd capacitor electrode C2b with the first interlayer insulating layer 113a therebetween.

[0180] The second electrode layer C2c2 of the second-third capacitor electrode C2c is disposed on the second interlayer insulating layer 113b. The second electrode layer C2c2 may be integrally formed with the drive source electrode DSE. The second electrode layer C2c2 may be electrically connected to the first electrode layer C2c1 through a contact hole of the second interlayer insulating layer 113b.

[0181] Next, one of a plurality of wiring lines is arranged on the substrate 110. The plurality of wiring lines includes a first scan line SL1, a second scan line SL2, an emission control line EML, a first control line LEL1, a second control line LEL2, a reference line RL, a data line DL, a high-potential power line VDD, and a low-potential power line VSS.

[0182] First, the first scan line SL1, the second scan line SL2, the emission control line EML, the first control line LEL1, and the second control line LEL2 are arranged on the gate insulating layer 112. The first scan line SL1, the second scan line SL2, the emission control line EML, the first control line LEL1, and the second control line LEL2 extend in a row direction and may be electrically connected to other configurations of the sub-pixel SP. For example, the first scan line SL1 is connected to the first transistor T1 and the second transistor T2, and the second scan line SL2 may be connected to the fifth transistor T5. The emission control line EML is connected to the third transistor T3 and the fourth transistor T4, and the first control line LEL1 and the second control line LEL2 may be connected to the first control transistor LET1 and the second control transistor LET2.The first scanning line SL1, the second scanning line SL2, the emission control line EML, the first control line LEL1 and the second control line LEL2 are formed of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti) and chromium (Cr) or an alloy thereof.

[0183] Next, the reference line RL and the high-potential power line VDD are arranged on the first interlayer insulating film 113a. The reference line RL and the high-potential power line VDD extend in the row direction and may be electrically connected to the other configurations of the sub-pixel SP. For example, the reference line RL is connected to the fifth transistor T5, and the high-potential power line VDD may be connected to the first control transistor LET1. The reference line RL and the high-potential power line VDD may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0184] The data line DL and the low-potential power line VSS are arranged on the second interlayer insulating film 113b. The data line DL and the low-potential power line VSS extend in the column direction and may cross other wiring lines extending in the row direction. Furthermore, the data line DL and the low-potential power line VSS may be electrically connected to the other configurations of the sub-pixel SP. For example, the data line DL is connected to the first transistor T1, and the low-potential power line VSS may be connected to the fourth transistor T4. The data line DL and the low-potential power line VSS may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0185] Next, a first passivation layer 114a is disposed on the drive transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the first control transistor LET1, the second control transistor LET2, the first capacitor C1, and the second capacitor C2. The first passivation layer 114a is an insulating layer that protects components beneath the first passivation layer 114a and may be made of an inorganic material such as, but is not limited to, silicon oxide SiOx or silicon nitride SiNx.

[0186] A first planarization layer 115a is disposed on the first passivation layer 114a. The first planarization layer 115a may planarize an upper portion of the substrate 110, including the drive transistor DT. The first planarization layer 115a may consist of a single layer or a double layer and may be made of, for example, photoresist, benzocyclobutene, or an organic acrylic-based material, but is not limited thereto.

[0187] A plurality of reflective electrodes RE are arranged on the first planarization layer 115a. The plurality of reflective electrodes RE are configurations that reflect light emitted by the plurality of light-emitting diodes (LEDs) above the substrate 110 and can be arranged to cover the largest possible area of ​​the plurality of sub-pixels SP. Furthermore, the plurality of reflective electrodes RE reflect the light emitted by the LEDs and can also be used as an electrode that electrically connects the plurality of light-emitting diodes (LEDs) and the remaining configuration of the sub-pixel SP. The plurality of reflective electrodes RE can include various conductive layers, taking into account light reflection efficiency and resistance.For example, the reflective electrodes RE can be formed from an opaque conductive layer with high reflectivity, such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or an alloy thereof. Furthermore, the reflective electrode RE can comprise a transparent conductive layer, such as indium tin oxide (ITO), to improve resistance.

[0188] The plurality of reflective electrodes RE include a first reflective electrode RE1, a second reflective electrode RE2, and a third reflective electrode RE3.

[0189] The first reflective electrode RE1 is an electrode that electrically connects the first control source electrode ESE1 and the first light-emitting diode LED1. The first reflective electrode RE1 may be electrically connected to the first control source electrode ESE1 through a contact hole formed in the first planarization layer 115a and the first passivation layer 114a. The first reflective electrode RE1 may be electrically connected to the first anode AD1 of the first light-emitting diode LED1 through a first anode AD1 connection electrode CE to be described below. Accordingly, the first control source electrode ESE1 of the first control transistor LET1 and the first anode AD1 of the first light-emitting diode LED1 may be electrically connected to each other via the first reflective electrode RE1.

[0190] The second reflective electrode RE2 is an electrode that electrically connects the first control drain electrode EDE1 and the first light-emitting diode LED1, and simultaneously electrically connects the second control source electrode ESE2 and the second light-emitting diode LED2. The second reflective electrode RE2 may be electrically connected to the first control drain electrode EDE1 and the second control source electrode ESE2 via a contact hole formed in the first planarization layer 115a and the first passivation layer 114a. The second reflective electrode RE2 may be electrically connected to the first cathode CD1 of the first light-emitting diode LED1 via a first cathode CD1 connection electrode CE to be described below. Furthermore, the second reflective electrode RE2 may be electrically connected to the second anode AD2 of the second light-emitting diode LED2 via a second anode AD2 connection electrode CE to be described below.Accordingly, the first control drain electrode EDE1 of the first control transistor LET1 and the first cathode CD1 of the first light-emitting diode LED1 can be electrically connected to each other via the second reflective electrode RE2. Furthermore, the second control source electrode ESE2 of the second control transistor LET2 and the second anode AD2 of the second light-emitting diode LED2 can be electrically connected to each other via the second reflective electrode RE2.

[0191] The third reflective electrode RE3 is an electrode that electrically connects the second light-emitting diode LED2, the drive source electrode DSE, and the second control drain electrode EDE2. The third reflective electrode RE3 may be electrically connected to the drive source electrode DSE via a contact hole formed in the first planarization layer 115a and the first passivation layer 114a. Here, the drive source electrode DSE and the second control drain electrode EDE2 of the second control transistor LET2 are electrically connected to each other via the drive active layer DACT. Therefore, the third reflective electrode RE3 may also be electrically connected to the second control drain electrode EDE2. Furthermore, the third reflective electrode RE3 may be electrically connected to the second cathode CD2 of the second light-emitting diode LED2 via a second cathode CD2 connection electrode CE to be described below.Accordingly, the second control drain electrode EDE2 and the drive source electrode DSE as well as the second cathode CD2 of the second light-emitting diode LED2 can be electrically connected to each other via the third reflective electrode RE3.

[0192] Next, a second passivation layer 114b is disposed on the plurality of reflective electrodes RE. The second passivation layer 114b is an insulating layer that protects components beneath the second passivation layer 114b and may be formed by, but is not limited to, a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx.

[0193] The adhesive layer 116 is disposed on the second passivation layer 114b. The adhesive layer 116 is formed on the front surface of the substrate 110 to secure the plurality of light-emitting diodes (LEDs) disposed on the adhesive layer 116. The adhesive layer 116 may be formed from a photocurable adhesive that is cured by light. For example, the adhesive layer 116 may be formed from an acrylic-based material containing a photoresist, but is not limited thereto.

[0194] The plurality of light-emitting diodes (LEDs) are arranged on the adhesive layer 116. The plurality of light-emitting diodes (LEDs) are an element that emits light through a current and may be, for example, a light-emitting diode (LED) or a micro-LED. The plurality of light-emitting diodes (LEDs) include a red light-emitting diode (LED) that emits red light, a green light-emitting diode (LED) that emits green light, and a blue light-emitting diode (LED) that emits blue light, and generates light of various colors including white through a combination thereof. The first light-emitting diode (LED)1 and the second light-emitting diode (LED)2, which are arranged on the same sub-pixel SP so as to be connected in series, may be light-emitting diodes that emit light of the same color.

[0195] The first light-emitting diode LED1 and the second light-emitting diode LED2 may be formed with substantially the same structure. A first semiconductor layer NL, an emission layer EL, a second semiconductor layer PL, a first anode AD1, a first cathode CD1, and an encapsulation film PAS of the first light-emitting diode LED1 may have substantially the same configuration as a first semiconductor layer NL, an emission layer EL, a second semiconductor layer PL, a second anode AD2, a second cathode CD2, and an encapsulation film PAS of the second light-emitting diode LED2.

[0196] First, the first light-emitting diode LED1 comprises the first semiconductor layer NL, the emission layer EL, the second semiconductor layer PL, the first anode AD1, the first cathode CD1 and the encapsulation film PAS.

[0197] The first semiconductor layer NL is disposed on the adhesion layer 116, and the second semiconductor layer PL is disposed on the first semiconductor layer NL. The first semiconductor layer NL and the second semiconductor layer PL may be layers formed by doping n-type and p-type impurities into a specific material. For example, the first semiconductor layer NL and the second semiconductor layer PL may be layers doped with n-type and p-type impurities into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). The p-type impurity may be magnesium (Mg), zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium, tin (Sn), etc., but are not limited thereto.

[0198] The emission layer EL is arranged between the first semiconductor layer NL and the second semiconductor layer PL. The emission layer EL is supplied with holes and electrons from the first semiconductor layer NL and the second semiconductor layer PL to emit light. The emission layer EL can be formed by a single layer or a multiple quantum well (MQW) structure and can be made of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0199] The first cathode CD1 is disposed on the first semiconductor layer NL. The first cathode CD1 may be disposed on an upper surface of the first semiconductor layer NL exposed from the emission layer EL and the second semiconductor layer PL. In this case, the first semiconductor layer NL electrically connected to the first cathode CD1 may be a semiconductor layer doped with the n-type impurity. The first cathode CD1 may be electrically connected to the second anode AD2 of the second light-emitting diode LED2, the first control drain electrode EDE1 of the first control transistor LET1, and the second control source electrode ESE2 of the second control transistor LET2 via the first cathode CD1 connection electrode CE and the second reflective electrode RE2.The first cathode CD1 may be made of a conductive material such as, but not limited to, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof.

[0200] The first anode AD1 is disposed on the second semiconductor layer PL. The first anode AD1 may be disposed on an upper surface of the second semiconductor layer PL. The second semiconductor layer PL, which is electrically connected to the first anode AD1, is a semiconductor layer doped with a p-type impurity. The first anode AD1 may be electrically connected to the high-potential power line VDD and the first control source electrode ESE1 of the first control transistor LET1 via the first anode AD1 connection electrode CE and the first reflective electrode RE1. The first anode AD1 may be formed by a conductive material such as, but not limited to, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof.

[0201] Next, the encapsulation film PAS is disposed, which encloses the first semiconductor layer NL, the emission layer EL, the second semiconductor layer PL, the first anode AD1, and the first cathode CD1. The encapsulation film PAS is made of an insulating material for protecting the first semiconductor layer NL, the emission layer EL, and the second semiconductor layer PL. Furthermore, a contact hole is formed in the encapsulation film PAS through which the first anode AD1 and the first cathode CD1 are exposed, so that the first anode AD1 and the first cathode CD1 can be electrically connected to the first anode AD1 connection electrode CE and the first cathode CD1 connection electrode CE.

[0202] Meanwhile, a portion of the side surface of the first semiconductor layer NL may be exposed from the encapsulation film PAS. The light-emitting diode LED fabricated on the wafer is separated from the wafer to be transferred to the display panel PN. However, during the separation process of the light-emitting diode LED from the wafer, a portion of the encapsulation film PAS may be torn. For example, a portion of the encapsulation layer PAS adjacent to a lower edge of the first semiconductor layer NL of the light-emitting diode LED is torn during the separation process of the light-emitting diode LED from the wafer. Accordingly, a portion of a lower side surface of the first semiconductor layer NL may be exposed to the outside.However, although the lower portion of the light-emitting diode (LED) is exposed from the encapsulation film (PAS), the first anode AD1 connection electrode (CE) and the first cathode CD1 connection electrode (CE) are formed after the second planarization layer 115b and the third planarization layer 115c are formed, which cover the side surface of the first semiconductor layer NL. Accordingly, a short-circuit defect can be reduced.

[0203] Next, the second light-emitting diode LED2 includes the first semiconductor layer NL, the emission layer EL, the second semiconductor layer PL, the second anode AD2, the second cathode CD2, and the encapsulation film PAS. The first semiconductor layer NL, the emission layer EL, the second semiconductor layer PL, and the encapsulation film PAS of the second light-emitting diode LED2 are formed with substantially the same structure and material as the first semiconductor layer NL, the emission layer EL, the second semiconductor layer PL, and the encapsulation film PAS of the first light-emitting diode LED1.

[0204] Furthermore, the second cathode CD2 of the second light-emitting diode LED2, like the first cathode CD1 of the first light-emitting diode LED1, is arranged on the first semiconductor layer NL and can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof. Furthermore, the second cathode CD2 can be electrically connected to the drive source electrode DSE of the drive transistor DT and the second control drain electrode EDE2 of the second control transistor LET2 via the second cathode CD2 connection electrode CE and the third reflective electrode RE3.

[0205] The second anode AD2 of the second light-emitting diode LED2, like the first anode AD1 of the first light-emitting diode LED1, is arranged on the second semiconductor layer PL and can be formed from a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof. The second anode AD2 can be electrically connected to the first cathode CD1 of the first light-emitting diode LED1, the first control drain electrode EDE1 of the first control transistor LET1, and the second control source electrode ESE2 of the second control transistor LET2 via the second anode AD2 connection electrode CE and the second reflective electrode RE2.

[0206] Next, the second planarization layer 115b and the third planarization layer 115c are arranged on the adhesive layer 116 and the light-emitting diode LED.

[0207] The second planarization layer 115b overlaps a portion of the side surfaces of the plurality of light-emitting diodes (LEDs) to fix and protect the plurality of light-emitting diodes (LEDs). A torn portion of the encapsulation film (PAS) protecting the side surface of the first semiconductor layer (NL) of the light-emitting diode (LED) can be covered by the second planarization layer 115b. This can suppress contact and short-circuit defects between the connecting electrode (CE) and the first semiconductor layer (NL) thereafter.

[0208] The third planarization layer 115c is formed to cover upper portions of the second planarization layer 115b and the light-emitting diode LED. A contact hole may be formed in the third planarization layer 115c, through which the first anode AD1 and the first cathode CD1 of the first light-emitting diode LED1 and the second anode AD2 and the second cathode CD2 of the second light-emitting diode LED2 are exposed. The first anode AD1, the first cathode CD1, the second anode AD2, and the second cathode CD2 are exposed from the third planarization layer 115c. However, the third planarization layer 115c is partially disposed in a region between the first anode AD1 and the first cathode CD1 of the first light-emitting diode LED1 and a region between the second anode AD2 and the second cathode CD2 of the second light-emitting diode LED2 to reduce the short-circuit defect.The second planarization layer 115b and the third planarization layer 115c may be a single layer or a double layer and may be formed of, for example, but not limited to, photoresist, benzocyclobutene, or an organic acrylic-based material.

[0209] A plurality of connection electrodes CE are arranged on the third planarization layer 115c. The plurality of connection electrodes CE are electrodes that electrically connect the plurality of light-emitting diodes (LEDs) and the other configurations of the sub-pixel (SP). The plurality of connection electrodes CE include the first cathode CD1 connection electrode CE, the first anode AD1 connection electrode CE, the second cathode CD2 connection electrode CE, and the second anode AD2 connection electrode CE. The plurality of connection electrodes CE are formed of a transparent conductive material such as, but not limited to, indium tin oxide (ITO) or indium zinc oxide (IZO).

[0210] First, the first cathode CD1 connection electrode CE may be electrically connected to the second reflective electrode RE2 through a contact hole formed in the third planarization layer 115c, the second planarization layer 115b, and the second passivation layer 114b. Furthermore, the first cathode CD1 connection electrode CE may be electrically connected to the first cathode CD1 of the first light-emitting diode LED1 through a contact hole of the third planarization layer 115c. Accordingly, the first cathode CD1 and the second reflective electrode RE2 may be electrically connected through the first cathode CD1 connection electrode CE.

[0211] The first anode AD1 connection electrode CE may be electrically connected to the first reflective electrode RE1 through a contact hole formed in the third planarization layer 115c, the second planarization layer 115b, and the second passivation layer 114b. The first anode AD1 connection electrode CE may be electrically connected to the first anode AD1 of the first light-emitting diode LED1 through a contact hole in the third planarization layer 115c. Accordingly, the first anode AD1 and the first reflective electrode RE1 may be electrically connected through the first anode AD1 connection electrode CE.

[0212] The second cathode CD2 connection electrode CE may be electrically connected to the third reflective electrode RE3 through a contact hole formed in the third planarization layer 115c, the second planarization layer 115b, and the second passivation layer 114b. Furthermore, the second cathode CD2 connection electrode CE may be electrically connected to the second cathode CD2 of the second light-emitting diode LED2 through a contact hole of the third planarization layer 115c. Accordingly, the second cathode CD2 and the third reflective electrode RE3 may be electrically connected through the second cathode CD2 connection electrode CE.

[0213] The second anode AD2 connection electrode CE may be electrically connected to the second reflective electrode RE2 through a contact hole formed in the third planarization layer 115c, the second planarization layer 115b, and the second passivation layer 114b. The second anode AD2 connection electrode CE may be electrically connected to the second anode AD2 of the second light-emitting diode LED2 through a contact hole of the third planarization layer 115c. Accordingly, the second anode AD2 and the second reflective electrode RE2 may be electrically connected through the second anode AD2 connection electrode CE.

[0214] Meanwhile, both the first cathode CD1 connection electrode CE and the second anode AD2 connection electrode CE may be connected to the second reflective electrode RE2. Although the drawing shows that the first cathode CD1 connection electrode CE and the second anode AD2 connection electrode CE are spaced apart from each other on the second reflective electrode RE2, the first cathode CD1 connection electrode CE and the second anode AD2 connection electrode CE are connected to form an integral structure, but this is not limited to this.

[0215] Next, a bank BB is disposed on the second planarization layer 115b. The bank BB is arranged to be spaced a predetermined distance from the light-emitting diode LED and to at least partially overlap the plurality of reflective electrodes RE. Furthermore, the bank BB may be arranged to cover at least a portion of the plurality of connection electrodes CE. The bank BB may be formed of an opaque material to reduce color mixing between the plurality of sub-pixels SP, and may be formed of, for example, but is not limited to, black resin.

[0216] The protective layer 117 is disposed on the plurality of connection electrodes CE and the bank BB. The protective layer 117 is a layer for protecting configurations beneath the protective layer 117. The protective layer 117 may be formed from a single layer or a double layer and may be formed from, for example, but is not limited to, benzocyclobutene, a light-transmitting epoxy, a photoresist, or an acrylic-based organic material.

[0217] Meanwhile, the display device 100 according to the exemplary embodiment of the present disclosure includes a gate driver GD and a data driver DD as described above for driving the plurality of sub-pixels SP of the display panel PN. Here, the gate driver GD generates a first scanning signal SCAN1, a second scanning signal SCAN2, and an emission control signal EM to apply the signals to the first scanning line SL1, the second scanning line SL2, and the emission control line EML. Furthermore, the gate driver GD generates a first control signal LE1 and a second control signal LE2 to apply the signals to the first control line LEL1 and the second control line LEL2.In particular, each of the first control signal LE1 and the second control signal LE2 has the same waveform as the first scanning signal SCAN1, so that the first scanning signal SCAN1 generated in the gate driver GD can be used for each of the first control signal LE1 and the second control signal LE2. Accordingly, the display device 100 according to the exemplary embodiment of the present disclosure further includes a control signal generation circuit LEC that additionally generates the first control signal LE1 and the second control signal LE2 for the gate driver GD, which has a plurality of first stages ST1 that generate the first scanning signal SCAN1.

[0218] In the following, the control signal generating circuit LEC will be described with reference to Fig. 8 and Fig. 9 described in detail.

[0219] Fig. 8 is an illustration of a gate driver of a display device according to an exemplary embodiment of the present disclosure. Fig. 9 is a circuit diagram of a control signal generating circuit of a display device according to an exemplary embodiment of the present disclosure. Fig. 10 is a drive timing chart of a control signal generating circuit of a display device according to an exemplary embodiment of the present disclosure.

[0220] First, the gate driver GD includes a plurality of first stages ST1 for generating a first scanning signal SCAN1. The plurality of first stages ST1 are dependently connected and can generate the first scanning signal SCAN1 based on a start signal VST or a first scanning signal SCAN1 output from a first stage ST1 of a previous stage. For example, the first stage ST1, which is at the top, receives the start signal VST to output the first scanning signal SCAN1 to a first scanning line SL1, which is at the top. An n-th first stage ST1 receives a first scanning signal SCAN1 from an n-1-th first stage ST1 of a previous stage to output the first scanning signal SCAN1 to the n-th first scanning line SL1.

[0221] Furthermore, the control signal generating circuit LEC is connected to an output terminal of each of the plurality of first stages ST1. The control signal generating circuit LEC includes a first circuit LEC1 and a second circuit LEC2, and each of the first circuit LEC1 and the second circuit LEC2 receives the first scanning signal SCAN1 output from the first stage ST1 to generate a first control signal LE1 and a second control signal LE2.

[0222] With reference to Fig. 9, the first circuit LEC1 is a circuit that generates the first control signal LE1 and the second control signal LE2 when the first light-emitting diode LED1 emits light. The first circuit LEC1 can generate a first control signal LE1 having the same waveform as the first scanning signal SCAN1 and a turn-on level of the second control signal LE2. The first circuit LEC1 includes a first connecting transistor CT1, a second connecting transistor CT2, a first auxiliary transistor Tbv1, and a first amplifying capacitor Cb1.

[0223] First, the first connecting transistor CT1 is a transistor that selectively connects an output terminal of the first stage ST1 and a first control line LEL1. A gate electrode of the first connecting transistor CT1 is connected to a drain electrode of the first auxiliary transistor Tbv1 and a Q1 node Q1, a source electrode is connected to an output terminal of the first stage ST1, and a drain electrode may be connected to the first control line LEL1. The first connecting transistor CT1 can be turned on or off based on a first enable signal EN1 transmitted via the first auxiliary transistor Tbv1. The turned-on first connecting transistor CT1 can connect an output terminal of the first stage ST1 and the first control line LEL1, and the first scan signal SCAN1 from the first stage ST1 can be transmitted to the first control line LEL1 via the first connecting transistor CT1.Therefore, the first scanning signal SCAN1 is transmitted unchanged to the first control line LEL1, so that the first scanning signal SCAN1 and the first control signal LE1 can have the same waveform.

[0224] The second connecting transistor CT2 is a transistor that selectively connects a gate low line and the second control line LEL2. A gate electrode of the second connecting transistor CT2 is connected to a drain electrode of the first auxiliary transistor Tbv1 and a Q1 node Q1, a source electrode is connected to a gate low line, and a drain electrode may be connected to the second control line LEL2. The second connecting transistor CT2 can be turned on or off based on a first enable signal EN1 transmitted via the first auxiliary transistor Tbv1. The turned-on second connecting transistor CT2 can connect the gate low line and the second control line LEL2, and a gate low voltage VGL of the gate low line can be transmitted to the second control line LEL2 via the second connecting transistor CT2.Accordingly, the gate low voltage VGL serves as the low level of the second control signal LE2 to be output to the second control line LEL2.

[0225] The first auxiliary transistor Tbv1 is connected between the first enable line and the Q1 node Q1. A gate electrode of the first auxiliary transistor Tbv1 is connected to the gate low line, a source electrode is connected to a first enable line, and a drain electrode is connected to the Q1 node Q1. The first auxiliary transistor Tbv1, whose gate electrode is connected to the gate low line, is always on and can electrically connect the first enable line and the Q1 node Q1.

[0226] The first amplification capacitor Cb1 is connected between the Q1 node Q1 and the first control line LEL1. A voltage of the Q1 node Q1 can momentarily be lower than the first enable voltage, and the first connection transistor CT1 stably maintains an on state by bootstrapping the first amplification capacitor Cb1. Accordingly, the first amplification capacitor Cb1 can help the first scanning signal SCAN1 be output as the first control signal LE1 without distortion and delay.

[0227] Next, the second circuit LEC2 is a circuit that generates the first control signal LE1 and the second control signal LE2 when the second light-emitting diode LED2 emits light. The second circuit LEC2 can generate an on-level of the first control signal LE1 and a second control signal LE2 having the same waveform as the first scanning signal SCAN1. The second circuit LEC2 includes a third connecting transistor CT3, a fourth connecting transistor CT4, a second auxiliary transistor Tbv2, and a second boosting capacitor Cb2.

[0228] The third connecting transistor CT3 is a transistor that selectively connects the output terminal of the first stage ST1 and the second control line LEL2. A gate electrode of the third connecting transistor CT3 is connected to a drain electrode of the second auxiliary transistor Tbv2 and a Q2 node Q2, a source electrode is connected to an output terminal of the first stage ST1, and a drain electrode may be connected to the second control line LEL2. The third connecting transistor CT3 can be turned on or off based on a second enable signal EN2 transmitted via the second auxiliary transistor Tbv2. The turned-on third connecting transistor CT3 can connect an output terminal of the first stage ST1 and the second control line LEL2, and the first scan signal SCAN1 from the first stage ST1 can be transmitted to the second control line LEL2 via the third connecting transistor CT3.Therefore, the first scanning signal SCAN1 is transmitted unchanged to the second control line LEL2, so that the first scanning signal SCAN1 and the second control signal LE2 can have the same waveform.

[0229] The fourth connecting transistor CT4 is a transistor that selectively connects the gate low line and the first control line LEL1. A gate electrode of the fourth connecting transistor CT4 is connected to a drain electrode of the second auxiliary transistor Tbv2 and a Q2 node Q2, a source electrode is connected to the gate low line, and a drain electrode may be connected to the first control line LEL1. The fourth connecting transistor CT4 can be turned on or off based on a second enable signal EN2 transmitted via the second auxiliary transistor Tbv2. The turned-on fourth connecting transistor CT4 can connect the gate low line and the first control line LEL1, and a gate low voltage VGL of the gate low line can be transmitted to the first control line LEL1 via the fourth connecting transistor CT4.Accordingly, the gate low voltage VGL serves as the low level of the first control signal LE1 to be output to the first control line LEL1.

[0230] The second auxiliary transistor Tbv2 is connected between the second enable line and the Q2 node Q2. A gate electrode of the second auxiliary transistor Tbv2 is connected to the gate low line, a source electrode is connected to the second enable line, and a drain electrode is connected to the Q2 node Q2. The second auxiliary transistor Tbv2, whose gate electrode is connected to the gate low line, is always on and can electrically connect the second enable line and the Q2 node Q2.

[0231] The second amplification capacitor Cb2 is connected between the Q2 node Q2 and the second control line LEL2. A voltage of the Q2 node Q2 can be lower than the second enable voltage, and the third connection transistor CT3 maintains a stable on-state by bootstrapping the second amplification capacitor Cb2. Accordingly, the second amplification capacitor Cb2 can help output the first scanning signal SCAN1 as the second control signal LE2 without distortion and delay.

[0232] Next, with joint reference to Fig. 9 and Fig. 10 a period of time between time A and time B is a period of time in which the first light-emitting diode LED1 is controlled, and a period of time between time C and time D is a period of time in which the second light-emitting diode LED2 is controlled.

[0233] First, in the period between time A and time B, the first circuit LEC1 may generate and output the first control signal LE1 and the second control signal LE2 to allow only the first light-emitting diode LED1 to emit light.

[0234] In the period between time A and time B, a low level of the first enable signal EN1 is output to the first enable line, and a high level of the second enable signal EN2 is output to the second enable line. At this time, the first enable signal EN1 and the second enable signal EN2 are signals with reversed phases. For example, when the first enable signal EN1 is at a high level, the second enable signal EN2 may be at a low level, and when the first enable signal EN1 is at a low level, the second enable signal EN2 may be at a high level.Accordingly, a turn-on period of the first connecting transistor CT1 and the second connecting transistor CT2 in which the first enable signal EN1 is applied to the gate electrodes and a turn-on period of the third connecting transistor CT3 and the fourth connecting transistor CT4 in which the second enable signal EN2 is applied to the gate electrodes may be alternately designed.

[0235] Furthermore, in the first circuit LEC1, a low level of the first enable signal EN1 may be applied to the Q1 node Q1 via the first auxiliary transistor Tbv1. The first connecting transistor CT1 and the second connecting transistor CT2 may be turned on by the low level of the first enable signal EN1 applied to the Q1 node Q1. The turned-on first connecting transistor CT1 may connect an output terminal of the first stage ST1 and the first control line LEL1, and the first control signal LE1 having the same waveform as the first scan signal SCAN1 may be output to the first control line LEL1. The turned-on second connecting transistor CT2 may connect the gate low line and the second control line LEL2 and output a low level of the second control signal LE2 having the same voltage as the gate low voltage VGL.Accordingly, the first control signal LE1 having the same waveform as the first scanning signal SCAN1 is output to the first control line LEL1, and a low level of the second control signal LE2 can be output to the second control line LEL2. Therefore, the second control transistor LET2 remains in an on state during a period in which the first light-emitting diode LED1 is emitting light, so that the second light-emitting diode LED2 does not emit light.

[0236] Furthermore, in the period between time A and time B, a high level of the second enable signal EN2 output to the second enable line can be transmitted to the Q2 node Q2 of the second circuit LEC2. Therefore, the third connection transistor CT3 and the fourth connection transistor CT4 of the second circuit LEC2 can be turned off by the high level of the second enable signal EN2. Furthermore, the first scan signal SCAN1 is not output to the second control line LEL2, or the gate low voltage VGL is not output to the first control line LEL1.

[0237] Next, in the period between time C and time D, a high level of the first enable signal EN1 is output to the first enable line and a low level of the second enable signal EN2 is output to the second enable line.

[0238] In the first circuit LEC1, a high level of the first enable signal EN1 can be applied to the Q1 node Q1 via the first auxiliary transistor Tbv1. The first connecting transistor CT1 and the second connecting transistor CT2 can be turned off by the high level of the first enable signal EN1 applied to the Q1 node Q1. Accordingly, no signal may be output from the first circuit LEC1 to the first control line LEL1 and the second control line LEL2.

[0239] In the second circuit LEC2, a low level of the second enable signal EN2 can be applied to the Q2 node Q2 via the second auxiliary transistor Tbv2. The third connecting transistor CT3 and the fourth connecting transistor CT4 can be turned on by the low level of the second enable signal EN2 applied to the Q2 node Q2. The turned-on third connecting transistor CT3 can connect an output terminal of the first stage ST1 and the second control line LEL2, and the second control signal LE2 having the same waveform as the first scan signal SCAN1 can be output to the second control line LEL2. The turned-on fourth connecting transistor CT4 can connect the gate low line and the first control line LEL1 and output a low level of the first control signal LE1 having the same voltage as the gate low voltage VGL.Accordingly, a low level of the first control signal LE1 is output to the first control line LEL1, and the second control signal LE2 having the same waveform as the first scanning signal SCAN1 can be output to the second control line LEL2. Therefore, the first control transistor LET1 maintains an on state during a period in which the second light-emitting diode LED2 is emitting light, so that the first light-emitting diode LED1 does not emit light.

[0240] Accordingly, in the display device 100 according to the exemplary embodiment of the present disclosure, the control signal generation circuit LEC is connected to output terminals of the plurality of first stages ST1 of the gate driver GD to easily generate the first control signal LE1 and the second control signal LE2. First, the control signal generation circuit LEC includes a first circuit LEC1 and a second circuit LEC2. When the first light-emitting diode LED1 emits light, the first circuit LEC1 generates the first control signal LE1 having the same waveform as the first scanning signal SCAN1 to apply the first control signal to the first control line LEL1.When the first light-emitting diode LED1 emits light, the first circuit LEC1 generates an on-level of the second control signal LE2, which turns on the second control transistor LET2, so that the second light-emitting diode LED2 is not allowed to emit light, in order to apply the on-level of the second control signal to the second control line LEL2. For example, the first circuit LEC1 outputs the first scanning signal SCAN1 received from the first stage ST1 as the first control signal LE1 to the first control line LEL1 and can output a low level of the second control signal LE2 to the second control line LEL2. Accordingly, in one frame or one horizontal period in which the first light-emitting diode LED1 emits light, the first control signal LE1 and the second control signal LE2 can be generated using the first circuit LEC1.

[0241] When the second light-emitting diode LED2 emits light, the second circuit LEC2 further generates an on-level of the first control signal LE1, which turns on the first control transistor LET1 so that the first light-emitting diode LED1 is not allowed to emit light, to apply the on-level of the first control signal to the first control line LEL1. When the second light-emitting diode LED2 emits light, the second circuit LEC2 generates the second control signal LE2 with the same waveform as the first scanning signal SCAN1 to apply the second control signal to the second control line LEL2. For example, the second circuit LEC2 outputs the first scanning signal SCAN1 received from the first stage ST1 as the second control signal LE1 to the second control line LEL2 and can output a low level of the first control signal LE1 to the first control line LEL1.Accordingly, in one frame or one horizontal period in which the second light-emitting diode LED2 emits light, the first control signal LE1 and the second control signal LE2 can be generated using the second circuit LEC2. Therefore, the existing first scanning signal SCAN1 and the gate low voltage VGL are used as the first control signal LE1 and the second control signal LE2, so that the structure of the gate driver GD can be simplified.

[0242] The exemplary embodiments of the present disclosure may also be described as follows:

[0243] According to one aspect of the present disclosure, a display device includes a display panel in which a plurality of sub-pixels are defined, a first light-emitting diode arranged in each of the plurality of sub-pixels, a second light-emitting diode connected in series with the first light-emitting diode, a first control transistor connected in parallel with the first light-emitting diode and turned on by a first control signal, and a second control transistor connected in parallel with the second light-emitting diode and turned on by a second control signal.

[0244] The first LED and the second LED can emit light alternately.

[0245] While the first LED emits light, the first control transistor can be turned off and the second control transistor can be turned on.

[0246] While the first LED emits light, a drive current can flow from the first LED to the second control transistor.

[0247] While the second LED emits light, the first control transistor may be turned on and the second control transistor may be turned off.

[0248] While the second LED emits light, a drive current can flow from the first control transistor to the second LED.

[0249] The display device may further include a gate driver electrically connected to the display panel and outputting a first scanning signal, the first control signal, and the second control signal to the plurality of sub-pixels. The gate driver may include a plurality of first stages that generate the first scanning signal, and a plurality of control signal generating circuits connected to output terminals of the plurality of first stages and generating the first control signal and the second control signal, for outputting the first control signal and the second control signal to a first control line and a second control line.

[0250] Each of the plurality of control signal generation circuits may include a first circuit that outputs the first control signal and the second control signal to the first control line and the second control line while the first light-emitting diode emits light, and a second circuit that outputs the first control signal and the second control signal to the first control line and the second control line while the second light-emitting diode emits light, and the first circuit may output the first sensing signal as the first control signal and output a gate low voltage as the second control signal, and the second circuit may output the gate low voltage as the first control signal and output the first sensing signal as the second control signal.

[0251] The first circuit may include a first connecting transistor having a gate electrode connected to a Q1 node, a source electrode and a drain electrode connected between the output terminals of the plurality of first stages and the first control line, a second connecting transistor having a gate electrode connected to the Q1 node, and a source electrode and a drain electrode connected between a gate low line and the second control line, and a first auxiliary transistor transmitting a first enable signal to the Q1 node, and the second circuit may include a third connecting transistor having a gate electrode connected to a Q2 node, a source electrode and a drain electrode connected between the output terminals of the plurality of first stages and the second control line, a fourth connecting transistor,having a gate electrode connected to the Q2 node, and a source electrode and a drain electrode connected between the gate low line and the first control line, and a second auxiliary transistor transmitting a second enable signal to the Q2 node.

[0252] The first enable signal and the second enable signal may be signals with reversed phases.

[0253] A turn-on period of the first connecting transistor and the second connecting transistor and a turn-on period of the third connecting transistor and the fourth connecting transistor may be alternately configured.

[0254] According to another aspect of the present disclosure, a display device comprises a substrate, an adhesive layer disposed on the substrate, a first light-emitting diode disposed on the adhesive layer and having a first anode and a first cathode, a second light-emitting diode disposed on the adhesive layer and having a second anode and a second cathode, and a plurality of reflective electrodes disposed between the substrate and the adhesive layer. The plurality of reflective electrodes includes a first reflective electrode electrically connected to the first anode, a second reflective electrode electrically connected to the first cathode and the second anode, and a third reflective electrode electrically connected to the second cathode.

[0255] The display device may further include a first control transistor disposed between the substrate and the plurality of reflective electrodes and having a first control source electrode electrically connected to a high-potential power line, a second control transistor disposed between the substrate and the plurality of reflective electrodes and having a second control source electrode electrically connected to a first control drain electrode of the first control transistor, and a drive transistor disposed between the substrate and the plurality of reflective electrodes and having a drive source electrode electrically connected to a second control drain electrode of the second control transistor.The first reflective electrode may be electrically connected to the first control source electrode and the high-potential power line, the second reflective electrode is electrically connected to the first control drain electrode and the second control source electrode, and the third reflective electrode may be electrically connected to the second control drain electrode and the drive source electrode.

[0256] The display device may further include a planarization layer covering the first light-emitting diode and the second light-emitting diode, and a plurality of connection electrodes disposed on the planarization layer and electrically connecting the first light-emitting diode and the second light-emitting diode to the plurality of reflective electrodes through a contact hole of the planarization layer. The plurality of connection electrodes may include a first anode connection electrode electrically connecting the first anode and the first reflective electrode, a first cathode connection electrode electrically connecting the first cathode and the second reflective electrode, a second anode connection electrode electrically connecting the second anode and the second reflective electrode, and a second cathode connection electrode electrically connecting the second cathode and the third reflective electrode.

[0257] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the exemplary embodiments described above are illustrative in all aspects and do not limit the present disclosure. All technical concepts within the corresponding scope of the present disclosure should be construed as falling within the scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] KR 10-2023-0125525

[0001]

Claims

[1] Display device (100) comprising: a display panel (PN) in which several subpixels (SP) are defined; a first light-emitting diode (LED1) arranged in each of the plurality of sub-pixels (SP); a second light-emitting diode (LED2) connected in series with the first light-emitting diode (LED1); a first control transistor (LET1) connected in parallel with the first light-emitting diode (LED1) and switched on by a first control signal (LE1); and a second control transistor (LET2) which is connected in parallel with the second light-emitting diode (LED2) and is switched on by a second control signal (LE2). [2] The display device (100) according to claim 1, wherein the first light-emitting diode (LED1) and the second light-emitting diode (LED2) alternately emit light. [3] The display device (100) according to claim 2, wherein, while the first light-emitting diode (LED1) emits light, the first control transistor (LET1) is turned off and the second control transistor (LET2) is turned on. [4] The display device (100) according to claim 3, wherein, while the first light-emitting diode (LED1) emits light, a drive current flows from the first light-emitting diode (LED1) to the second control transistor (LET2). [5] The display device (100) according to any one of claims 2 to 4, wherein, while the second light-emitting diode (LED2) emits light, the first control transistor (LET1) is turned on and the second control transistor (LET2) is turned off. [6] The display device (100) according to claim 5, wherein, while the second light-emitting diode (LED2) emits light, a drive current flows from the first control transistor (LET1) to the second light-emitting diode (LED2). [7] Display device (100) according to any one of claims 2-6, further comprising: a gate driver (GD) electrically connected to the display panel (PN) and outputting a first scanning signal (SCAN1), the first control signal (LE1) and the second control signal (LE2) to the plurality of sub-pixels (SP), where the gate driver (GD) comprises: a plurality of first stages (ST1) generating the first scanning signal (SCAN1); and a plurality of control signal generating circuits (LEC), each connected to an output terminal of a corresponding one of the plurality of first stages (ST1) and generating the first control signal (LE1) and the second control signal (LE2) to output the first control signal (LE1) and the second control signal (LE2) to a first control line (LEL1) and a second control line (LEL2). [8] The display device (100) according to claim 7, wherein each of the plurality of control signal generating circuits (LEC) comprises: a first circuit (LEC1) that outputs the first control signal (LE1) and the second control signal (LE2) to the first control line (LEL1) and the second control line (LEL2) while the first light-emitting diode (LED1) emits light; and a second circuit (LEC2) which outputs the first control signal (LE1) and the second control signal (LE2) to the first control line (LEL1) and the second control line (LEL2) while the second light-emitting diode (LED2) emits light, and wherein the first circuit (LEC1) outputs the first scanning signal (SCAN1) as a first control signal (LE1) and outputs a gate low voltage (VGL) as a second control signal (LE2), and the second circuit (LEC2) outputs the gate low voltage (VGL) as a first control signal (LE1) and outputs the first scanning signal (SCAN1) as a second control signal (LE2). [9] The display device (100) of claim 8, wherein the first circuit (LEC1) comprises: a first connection transistor (CT1) having a gate electrode connected to a first node (Q1), a source electrode and a drain electrode connected between the output terminal of a corresponding one of the plurality of first stages (ST1) and the first control line (LEL1); a second connection transistor (CT2) having a gate electrode connected to the first node (Q1) and a source electrode and a drain electrode connected between a gate low line and the second control line (LEL2); and a first auxiliary transistor (Tbv1) transmitting a first enable signal (EN1) to the first node (Q1), and wherein the second circuit (LEC2) comprises: a third connection transistor (CT3) having a gate electrode connected to a second node (Q2), a source electrode and a drain electrode connected between the output terminal of the corresponding one of the plurality of first stages (ST1) and the second control line (LEL2); a fourth connection transistor (CT4) having a gate electrode connected to the second node (Q2) and a source electrode and a drain electrode connected between the gate low line and the first control line (LE1); and a second auxiliary transistor (Tbv2) transmitting a second enable signal (EN2) to the second node (Q2). [10] The display device (100) according to claim 9, wherein the first enable signal (EN1) and the second enable signal (EN2) are signals with reversed phases. [11] The display device (100) according to claim 10, wherein a turn-on period of the first connecting transistor (CT1) and the second connecting transistor (CT2) and a turn-on period of the third connecting transistor (CT3) and the fourth connecting transistor (CT4) are alternately designed. [12] Display device (100) according to one of claims 9-11, wherein the first circuit (LEC1) further comprises a first gain capacitor (Cb1) connected between the first node (Q1) and the first control line (LEL1); and the second circuit (LEC2) further comprises a second gain capacitor (Cb2) connected between the second node (Q2) and the second control line (LEL2). [13] Display device (100) comprising: a substrate (110); an adhesive layer (116) disposed on the substrate (110); a first light-emitting diode (LED1) arranged on the adhesive layer (116) and having a first anode (AD1) and a first cathode (CD1); a second light-emitting diode (LED2) arranged on the adhesive layer (116) and having a second anode (AD2) and a second cathode (CD2); and a plurality of reflective electrodes (RE) arranged between the substrate (110) and the adhesive layer (116), wherein the plurality of reflective electrodes (RE) comprise: a first reflective electrode (RE1) electrically connected to the first anode (AD1); a second reflective electrode (RE2) electrically connected to the first cathode (CD1) and the second anode (AD2); and a third reflective electrode (RE3) electrically connected to the second cathode (CD2). [14] The display device (100) of claim 13, further comprising: a first control transistor (LET1) arranged between the substrate (110) and the plurality of reflective electrodes (RE) and having a first control source electrode (ESE1) electrically connected to a high-potential power line (VDD); a second control transistor (LET2) arranged between the substrate (110) and the plurality of reflective electrodes (RE) and having a second control source electrode (ESE2) electrically connected to a first control drain electrode (EDE1) of the first control transistor (LET1); and a drive transistor (DT) arranged between the substrate (110) and the plurality of reflective electrodes (RE) and having a drive source electrode (DSE) electrically connected to a second control drain electrode (EDE2) of the second control transistor (LET2), wherein the first reflective electrode (RE1) is electrically connected to the first control source electrode (ESE1) and the high-potential power line (VDD), the second reflective electrode (RE2) is electrically connected to the first control drain electrode (EDE1) and the second control source electrode (ESE2), and the third reflective electrode (RE3) is electrically connected to the second control drain electrode (EDE2) and the drive source electrode (DSE). [15] The display device (100) of claim 14, further comprising: a planarization layer (115a, 115b, 115c) covering the first light-emitting diode (LED1) and the second light-emitting diode (LED2); and a plurality of connecting electrodes (CE) arranged on the planarization layer (115) and electrically connecting the first light-emitting diode (LED 1) and the second light-emitting diode (LED 2) to the plurality of reflective electrodes (RE) through a contact hole of the planarization layer (115a, 115b, 115c), wherein the plurality of connecting electrodes (CE) comprise: a first anode connection electrode electrically connecting the first anode (AD1) and the first reflective electrode (RE1); a first cathode connection electrode electrically connecting the first cathode (CD1) and the second reflective electrode (RE2); a second anode connection electrode electrically connecting the second anode (AD2) and the second reflective electrode (RE2); and a second cathode connection electrode electrically connecting the second cathode (CD2) and the third reflective electrode (RE3).

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